?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
ptrace: change signature of arch_ptrace()
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / arch / mips / kernel / traps.c
blobd053bf4759e417071760634656083151358ef23c
1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1994 - 1999, 2000, 01, 06 Ralf Baechle
7 * Copyright (C) 1995, 1996 Paul M. Antoine
8 * Copyright (C) 1998 Ulf Carlsson
9 * Copyright (C) 1999 Silicon Graphics, Inc.
10 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
11 * Copyright (C) 2000, 01 MIPS Technologies, Inc.
12 * Copyright (C) 2002, 2003, 2004, 2005, 2007 Maciej W. Rozycki
13 */
14 #include <linux/bug.h>
15 #include <linux/compiler.h>
16 #include <linux/init.h>
17 #include <linux/mm.h>
18 #include <linux/module.h>
19 #include <linux/sched.h>
20 #include <linux/smp.h>
21 #include <linux/spinlock.h>
22 #include <linux/kallsyms.h>
23 #include <linux/bootmem.h>
24 #include <linux/interrupt.h>
25 #include <linux/ptrace.h>
26 #include <linux/kgdb.h>
27 #include <linux/kdebug.h>
28 #include <linux/kprobes.h>
29 #include <linux/notifier.h>
30 #include <linux/kdb.h>
31 #include <linux/irq.h>
32
33 #include <asm/bootinfo.h>
34 #include <asm/branch.h>
35 #include <asm/break.h>
36 #include <asm/cop2.h>
37 #include <asm/cpu.h>
38 #include <asm/dsp.h>
39 #include <asm/fpu.h>
40 #include <asm/fpu_emulator.h>
41 #include <asm/mipsregs.h>
42 #include <asm/mipsmtregs.h>
43 #include <asm/module.h>
44 #include <asm/pgtable.h>
45 #include <asm/ptrace.h>
46 #include <asm/sections.h>
47 #include <asm/system.h>
48 #include <asm/tlbdebug.h>
49 #include <asm/traps.h>
50 #include <asm/uaccess.h>
51 #include <asm/watch.h>
52 #include <asm/mmu_context.h>
53 #include <asm/types.h>
54 #include <asm/stacktrace.h>
55 #include <asm/uasm.h>
56
57 extern void check_wait(void);
58 extern asmlinkage void r4k_wait(void);
59 extern asmlinkage void rollback_handle_int(void);
60 extern asmlinkage void handle_int(void);
61 extern asmlinkage void handle_tlbm(void);
62 extern asmlinkage void handle_tlbl(void);
63 extern asmlinkage void handle_tlbs(void);
64 extern asmlinkage void handle_adel(void);
65 extern asmlinkage void handle_ades(void);
66 extern asmlinkage void handle_ibe(void);
67 extern asmlinkage void handle_dbe(void);
68 extern asmlinkage void handle_sys(void);
69 extern asmlinkage void handle_bp(void);
70 extern asmlinkage void handle_ri(void);
71 extern asmlinkage void handle_ri_rdhwr_vivt(void);
72 extern asmlinkage void handle_ri_rdhwr(void);
73 extern asmlinkage void handle_cpu(void);
74 extern asmlinkage void handle_ov(void);
75 extern asmlinkage void handle_tr(void);
76 extern asmlinkage void handle_fpe(void);
77 extern asmlinkage void handle_mdmx(void);
78 extern asmlinkage void handle_watch(void);
79 extern asmlinkage void handle_mt(void);
80 extern asmlinkage void handle_dsp(void);
81 extern asmlinkage void handle_mcheck(void);
82 extern asmlinkage void handle_reserved(void);
83
84 extern int fpu_emulator_cop1Handler(struct pt_regs *xcp,
85 struct mips_fpu_struct *ctx, int has_fpu);
86
87 void (*board_be_init)(void);
88 int (*board_be_handler)(struct pt_regs *regs, int is_fixup);
89 void (*board_nmi_handler_setup)(void);
90 void (*board_ejtag_handler_setup)(void);
91 void (*board_bind_eic_interrupt)(int irq, int regset);
92
93
94 static void show_raw_backtrace(unsigned long reg29)
95 {
96 unsigned long *sp = (unsigned long *)(reg29 & ~3);
97 unsigned long addr;
98
99 printk("Call Trace:");
100 #ifdef CONFIG_KALLSYMS
101 printk("\n");
102 #endif
103 while (!kstack_end(sp)) {
104 unsigned long __user *p =
105 (unsigned long __user *)(unsigned long)sp++;
106 if (__get_user(addr, p)) {
107 printk(" (Bad stack address)");
108 break;
109 }
110 if (__kernel_text_address(addr))
111 print_ip_sym(addr);
112 }
113 printk("\n");
114 }
115
116 #ifdef CONFIG_KALLSYMS
117 int raw_show_trace;
118 static int __init set_raw_show_trace(char *str)
119 {
120 raw_show_trace = 1;
121 return 1;
122 }
123 __setup("raw_show_trace", set_raw_show_trace);
124 #endif
125
126 static void show_backtrace(struct task_struct *task, const struct pt_regs *regs)
127 {
128 unsigned long sp = regs->regs[29];
129 unsigned long ra = regs->regs[31];
130 unsigned long pc = regs->cp0_epc;
131
132 if (raw_show_trace || !__kernel_text_address(pc)) {
133 show_raw_backtrace(sp);
134 return;
135 }
136 printk("Call Trace:\n");
137 do {
138 print_ip_sym(pc);
139 pc = unwind_stack(task, &sp, pc, &ra);
140 } while (pc);
141 printk("\n");
142 }
143
144 /*
145 * This routine abuses get_user()/put_user() to reference pointers
146 * with at least a bit of error checking ...
147 */
148 static void show_stacktrace(struct task_struct *task,
149 const struct pt_regs *regs)
150 {
151 const int field = 2 * sizeof(unsigned long);
152 long stackdata;
153 int i;
154 unsigned long __user *sp = (unsigned long __user *)regs->regs[29];
155
156 printk("Stack :");
157 i = 0;
158 while ((unsigned long) sp & (PAGE_SIZE - 1)) {
159 if (i && ((i % (64 / field)) == 0))
160 printk("\n ");
161 if (i > 39) {
162 printk(" ...");
163 break;
164 }
165
166 if (__get_user(stackdata, sp++)) {
167 printk(" (Bad stack address)");
168 break;
169 }
170
171 printk(" %0*lx", field, stackdata);
172 i++;
173 }
174 printk("\n");
175 show_backtrace(task, regs);
176 }
177
178 void show_stack(struct task_struct *task, unsigned long *sp)
179 {
180 struct pt_regs regs;
181 if (sp) {
182 regs.regs[29] = (unsigned long)sp;
183 regs.regs[31] = 0;
184 regs.cp0_epc = 0;
185 } else {
186 if (task && task != current) {
187 regs.regs[29] = task->thread.reg29;
188 regs.regs[31] = 0;
189 regs.cp0_epc = task->thread.reg31;
190 #ifdef CONFIG_KGDB_KDB
191 } else if (atomic_read(&kgdb_active) != -1 &&
192 kdb_current_regs) {
193 memcpy(&regs, kdb_current_regs, sizeof(regs));
194 #endif /* CONFIG_KGDB_KDB */
195 } else {
196 prepare_frametrace(&regs);
197 }
198 }
199 show_stacktrace(task, &regs);
200 }
201
202 /*
203 * The architecture-independent dump_stack generator
204 */
205 void dump_stack(void)
206 {
207 struct pt_regs regs;
208
209 prepare_frametrace(&regs);
210 show_backtrace(current, &regs);
211 }
212
213 EXPORT_SYMBOL(dump_stack);
214
215 static void show_code(unsigned int __user *pc)
216 {
217 long i;
218 unsigned short __user *pc16 = NULL;
219
220 printk("\nCode:");
221
222 if ((unsigned long)pc & 1)
223 pc16 = (unsigned short __user *)((unsigned long)pc & ~1);
224 for(i = -3 ; i < 6 ; i++) {
225 unsigned int insn;
226 if (pc16 ? __get_user(insn, pc16 + i) : __get_user(insn, pc + i)) {
227 printk(" (Bad address in epc)\n");
228 break;
229 }
230 printk("%c%0*x%c", (i?' ':'<'), pc16 ? 4 : 8, insn, (i?' ':'>'));
231 }
232 }
233
234 static void __show_regs(const struct pt_regs *regs)
235 {
236 const int field = 2 * sizeof(unsigned long);
237 unsigned int cause = regs->cp0_cause;
238 int i;
239
240 printk("Cpu %d\n", smp_processor_id());
241
242 /*
243 * Saved main processor registers
244 */
245 for (i = 0; i < 32; ) {
246 if ((i % 4) == 0)
247 printk("$%2d :", i);
248 if (i == 0)
249 printk(" %0*lx", field, 0UL);
250 else if (i == 26 || i == 27)
251 printk(" %*s", field, "");
252 else
253 printk(" %0*lx", field, regs->regs[i]);
254
255 i++;
256 if ((i % 4) == 0)
257 printk("\n");
258 }
259
260 #ifdef CONFIG_CPU_HAS_SMARTMIPS
261 printk("Acx : %0*lx\n", field, regs->acx);
262 #endif
263 printk("Hi : %0*lx\n", field, regs->hi);
264 printk("Lo : %0*lx\n", field, regs->lo);
265
266 /*
267 * Saved cp0 registers
268 */
269 printk("epc : %0*lx %pS\n", field, regs->cp0_epc,
270 (void *) regs->cp0_epc);
271 printk(" %s\n", print_tainted());
272 printk("ra : %0*lx %pS\n", field, regs->regs[31],
273 (void *) regs->regs[31]);
274
275 printk("Status: %08x ", (uint32_t) regs->cp0_status);
276
277 if (current_cpu_data.isa_level == MIPS_CPU_ISA_I) {
278 if (regs->cp0_status & ST0_KUO)
279 printk("KUo ");
280 if (regs->cp0_status & ST0_IEO)
281 printk("IEo ");
282 if (regs->cp0_status & ST0_KUP)
283 printk("KUp ");
284 if (regs->cp0_status & ST0_IEP)
285 printk("IEp ");
286 if (regs->cp0_status & ST0_KUC)
287 printk("KUc ");
288 if (regs->cp0_status & ST0_IEC)
289 printk("IEc ");
290 } else {
291 if (regs->cp0_status & ST0_KX)
292 printk("KX ");
293 if (regs->cp0_status & ST0_SX)
294 printk("SX ");
295 if (regs->cp0_status & ST0_UX)
296 printk("UX ");
297 switch (regs->cp0_status & ST0_KSU) {
298 case KSU_USER:
299 printk("USER ");
300 break;
301 case KSU_SUPERVISOR:
302 printk("SUPERVISOR ");
303 break;
304 case KSU_KERNEL:
305 printk("KERNEL ");
306 break;
307 default:
308 printk("BAD_MODE ");
309 break;
310 }
311 if (regs->cp0_status & ST0_ERL)
312 printk("ERL ");
313 if (regs->cp0_status & ST0_EXL)
314 printk("EXL ");
315 if (regs->cp0_status & ST0_IE)
316 printk("IE ");
317 }
318 printk("\n");
319
320 printk("Cause : %08x\n", cause);
321
322 cause = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE;
323 if (1 <= cause && cause <= 5)
324 printk("BadVA : %0*lx\n", field, regs->cp0_badvaddr);
325
326 printk("PrId : %08x (%s)\n", read_c0_prid(),
327 cpu_name_string());
328 }
329
330 /*
331 * FIXME: really the generic show_regs should take a const pointer argument.
332 */
333 void show_regs(struct pt_regs *regs)
334 {
335 __show_regs((struct pt_regs *)regs);
336 }
337
338 void show_registers(struct pt_regs *regs)
339 {
340 const int field = 2 * sizeof(unsigned long);
341
342 __show_regs(regs);
343 print_modules();
344 printk("Process %s (pid: %d, threadinfo=%p, task=%p, tls=%0*lx)\n",
345 current->comm, current->pid, current_thread_info(), current,
346 field, current_thread_info()->tp_value);
347 if (cpu_has_userlocal) {
348 unsigned long tls;
349
350 tls = read_c0_userlocal();
351 if (tls != current_thread_info()->tp_value)
352 printk("*HwTLS: %0*lx\n", field, tls);
353 }
354
355 show_stacktrace(current, regs);
356 show_code((unsigned int __user *) regs->cp0_epc);
357 printk("\n");
358 }
359
360 static int regs_to_trapnr(struct pt_regs *regs)
361 {
362 return (regs->cp0_cause >> 2) & 0x1f;
363 }
364
365 static DEFINE_SPINLOCK(die_lock);
366
367 void __noreturn die(const char *str, struct pt_regs *regs)
368 {
369 static int die_counter;
370 int sig = SIGSEGV;
371 #ifdef CONFIG_MIPS_MT_SMTC
372 unsigned long dvpret = dvpe();
373 #endif /* CONFIG_MIPS_MT_SMTC */
374
375 notify_die(DIE_OOPS, str, regs, 0, regs_to_trapnr(regs), SIGSEGV);
376
377 console_verbose();
378 spin_lock_irq(&die_lock);
379 bust_spinlocks(1);
380 #ifdef CONFIG_MIPS_MT_SMTC
381 mips_mt_regdump(dvpret);
382 #endif /* CONFIG_MIPS_MT_SMTC */
383
384 if (notify_die(DIE_OOPS, str, regs, 0, regs_to_trapnr(regs), SIGSEGV) == NOTIFY_STOP)
385 sig = 0;
386
387 printk("%s[#%d]:\n", str, ++die_counter);
388 show_registers(regs);
389 add_taint(TAINT_DIE);
390 spin_unlock_irq(&die_lock);
391
392 if (in_interrupt())
393 panic("Fatal exception in interrupt");
394
395 if (panic_on_oops) {
396 printk(KERN_EMERG "Fatal exception: panic in 5 seconds\n");
397 ssleep(5);
398 panic("Fatal exception");
399 }
400
401 do_exit(sig);
402 }
403
404 extern struct exception_table_entry __start___dbe_table[];
405 extern struct exception_table_entry __stop___dbe_table[];
406
407 __asm__(
408 " .section __dbe_table, \"a\"\n"
409 " .previous \n");
410
411 /* Given an address, look for it in the exception tables. */
412 static const struct exception_table_entry *search_dbe_tables(unsigned long addr)
413 {
414 const struct exception_table_entry *e;
415
416 e = search_extable(__start___dbe_table, __stop___dbe_table - 1, addr);
417 if (!e)
418 e = search_module_dbetables(addr);
419 return e;
420 }
421
422 asmlinkage void do_be(struct pt_regs *regs)
423 {
424 const int field = 2 * sizeof(unsigned long);
425 const struct exception_table_entry *fixup = NULL;
426 int data = regs->cp0_cause & 4;
427 int action = MIPS_BE_FATAL;
428
429 /* XXX For now. Fixme, this searches the wrong table ... */
430 if (data && !user_mode(regs))
431 fixup = search_dbe_tables(exception_epc(regs));
432
433 if (fixup)
434 action = MIPS_BE_FIXUP;
435
436 if (board_be_handler)
437 action = board_be_handler(regs, fixup != NULL);
438
439 switch (action) {
440 case MIPS_BE_DISCARD:
441 return;
442 case MIPS_BE_FIXUP:
443 if (fixup) {
444 regs->cp0_epc = fixup->nextinsn;
445 return;
446 }
447 break;
448 default:
449 break;
450 }
451
452 /*
453 * Assume it would be too dangerous to continue ...
454 */
455 printk(KERN_ALERT "%s bus error, epc == %0*lx, ra == %0*lx\n",
456 data ? "Data" : "Instruction",
457 field, regs->cp0_epc, field, regs->regs[31]);
458 if (notify_die(DIE_OOPS, "bus error", regs, 0, regs_to_trapnr(regs), SIGBUS)
459 == NOTIFY_STOP)
460 return;
461
462 die_if_kernel("Oops", regs);
463 force_sig(SIGBUS, current);
464 }
465
466 /*
467 * ll/sc, rdhwr, sync emulation
468 */
469
470 #define OPCODE 0xfc000000
471 #define BASE 0x03e00000
472 #define RT 0x001f0000
473 #define OFFSET 0x0000ffff
474 #define LL 0xc0000000
475 #define SC 0xe0000000
476 #define SPEC0 0x00000000
477 #define SPEC3 0x7c000000
478 #define RD 0x0000f800
479 #define FUNC 0x0000003f
480 #define SYNC 0x0000000f
481 #define RDHWR 0x0000003b
482
483 /*
484 * The ll_bit is cleared by r*_switch.S
485 */
486
487 unsigned int ll_bit;
488 struct task_struct *ll_task;
489
490 static inline int simulate_ll(struct pt_regs *regs, unsigned int opcode)
491 {
492 unsigned long value, __user *vaddr;
493 long offset;
494
495 /*
496 * analyse the ll instruction that just caused a ri exception
497 * and put the referenced address to addr.
498 */
499
500 /* sign extend offset */
501 offset = opcode & OFFSET;
502 offset <<= 16;
503 offset >>= 16;
504
505 vaddr = (unsigned long __user *)
506 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
507
508 if ((unsigned long)vaddr & 3)
509 return SIGBUS;
510 if (get_user(value, vaddr))
511 return SIGSEGV;
512
513 preempt_disable();
514
515 if (ll_task == NULL || ll_task == current) {
516 ll_bit = 1;
517 } else {
518 ll_bit = 0;
519 }
520 ll_task = current;
521
522 preempt_enable();
523
524 regs->regs[(opcode & RT) >> 16] = value;
525
526 return 0;
527 }
528
529 static inline int simulate_sc(struct pt_regs *regs, unsigned int opcode)
530 {
531 unsigned long __user *vaddr;
532 unsigned long reg;
533 long offset;
534
535 /*
536 * analyse the sc instruction that just caused a ri exception
537 * and put the referenced address to addr.
538 */
539
540 /* sign extend offset */
541 offset = opcode & OFFSET;
542 offset <<= 16;
543 offset >>= 16;
544
545 vaddr = (unsigned long __user *)
546 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
547 reg = (opcode & RT) >> 16;
548
549 if ((unsigned long)vaddr & 3)
550 return SIGBUS;
551
552 preempt_disable();
553
554 if (ll_bit == 0 || ll_task != current) {
555 regs->regs[reg] = 0;
556 preempt_enable();
557 return 0;
558 }
559
560 preempt_enable();
561
562 if (put_user(regs->regs[reg], vaddr))
563 return SIGSEGV;
564
565 regs->regs[reg] = 1;
566
567 return 0;
568 }
569
570 /*
571 * ll uses the opcode of lwc0 and sc uses the opcode of swc0. That is both
572 * opcodes are supposed to result in coprocessor unusable exceptions if
573 * executed on ll/sc-less processors. That's the theory. In practice a
574 * few processors such as NEC's VR4100 throw reserved instruction exceptions
575 * instead, so we're doing the emulation thing in both exception handlers.
576 */
577 static int simulate_llsc(struct pt_regs *regs, unsigned int opcode)
578 {
579 if ((opcode & OPCODE) == LL)
580 return simulate_ll(regs, opcode);
581 if ((opcode & OPCODE) == SC)
582 return simulate_sc(regs, opcode);
583
584 return -1; /* Must be something else ... */
585 }
586
587 /*
588 * Simulate trapping 'rdhwr' instructions to provide user accessible
589 * registers not implemented in hardware.
590 */
591 static int simulate_rdhwr(struct pt_regs *regs, unsigned int opcode)
592 {
593 struct thread_info *ti = task_thread_info(current);
594
595 if ((opcode & OPCODE) == SPEC3 && (opcode & FUNC) == RDHWR) {
596 int rd = (opcode & RD) >> 11;
597 int rt = (opcode & RT) >> 16;
598 switch (rd) {
599 case 0: /* CPU number */
600 regs->regs[rt] = smp_processor_id();
601 return 0;
602 case 1: /* SYNCI length */
603 regs->regs[rt] = min(current_cpu_data.dcache.linesz,
604 current_cpu_data.icache.linesz);
605 return 0;
606 case 2: /* Read count register */
607 regs->regs[rt] = read_c0_count();
608 return 0;
609 case 3: /* Count register resolution */
610 switch (current_cpu_data.cputype) {
611 case CPU_20KC:
612 case CPU_25KF:
613 regs->regs[rt] = 1;
614 break;
615 default:
616 regs->regs[rt] = 2;
617 }
618 return 0;
619 case 29:
620 regs->regs[rt] = ti->tp_value;
621 return 0;
622 default:
623 return -1;
624 }
625 }
626
627 /* Not ours. */
628 return -1;
629 }
630
631 static int simulate_sync(struct pt_regs *regs, unsigned int opcode)
632 {
633 if ((opcode & OPCODE) == SPEC0 && (opcode & FUNC) == SYNC)
634 return 0;
635
636 return -1; /* Must be something else ... */
637 }
638
639 asmlinkage void do_ov(struct pt_regs *regs)
640 {
641 siginfo_t info;
642
643 die_if_kernel("Integer overflow", regs);
644
645 info.si_code = FPE_INTOVF;
646 info.si_signo = SIGFPE;
647 info.si_errno = 0;
648 info.si_addr = (void __user *) regs->cp0_epc;
649 force_sig_info(SIGFPE, &info, current);
650 }
651
652 /*
653 * XXX Delayed fp exceptions when doing a lazy ctx switch XXX
654 */
655 asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31)
656 {
657 siginfo_t info;
658
659 if (notify_die(DIE_FP, "FP exception", regs, 0, regs_to_trapnr(regs), SIGFPE)
660 == NOTIFY_STOP)
661 return;
662 die_if_kernel("FP exception in kernel code", regs);
663
664 if (fcr31 & FPU_CSR_UNI_X) {
665 int sig;
666
667 /*
668 * Unimplemented operation exception. If we've got the full
669 * software emulator on-board, let's use it...
670 *
671 * Force FPU to dump state into task/thread context. We're
672 * moving a lot of data here for what is probably a single
673 * instruction, but the alternative is to pre-decode the FP
674 * register operands before invoking the emulator, which seems
675 * a bit extreme for what should be an infrequent event.
676 */
677 /* Ensure 'resume' not overwrite saved fp context again. */
678 lose_fpu(1);
679
680 /* Run the emulator */
681 sig = fpu_emulator_cop1Handler(regs, &current->thread.fpu, 1);
682
683 /*
684 * We can't allow the emulated instruction to leave any of
685 * the cause bit set in $fcr31.
686 */
687 current->thread.fpu.fcr31 &= ~FPU_CSR_ALL_X;
688
689 /* Restore the hardware register state */
690 own_fpu(1); /* Using the FPU again. */
691
692 /* If something went wrong, signal */
693 if (sig)
694 force_sig(sig, current);
695
696 return;
697 } else if (fcr31 & FPU_CSR_INV_X)
698 info.si_code = FPE_FLTINV;
699 else if (fcr31 & FPU_CSR_DIV_X)
700 info.si_code = FPE_FLTDIV;
701 else if (fcr31 & FPU_CSR_OVF_X)
702 info.si_code = FPE_FLTOVF;
703 else if (fcr31 & FPU_CSR_UDF_X)
704 info.si_code = FPE_FLTUND;
705 else if (fcr31 & FPU_CSR_INE_X)
706 info.si_code = FPE_FLTRES;
707 else
708 info.si_code = __SI_FAULT;
709 info.si_signo = SIGFPE;
710 info.si_errno = 0;
711 info.si_addr = (void __user *) regs->cp0_epc;
712 force_sig_info(SIGFPE, &info, current);
713 }
714
715 static void do_trap_or_bp(struct pt_regs *regs, unsigned int code,
716 const char *str)
717 {
718 siginfo_t info;
719 char b[40];
720
721 #ifdef CONFIG_KGDB_LOW_LEVEL_TRAP
722 if (kgdb_ll_trap(DIE_TRAP, str, regs, code, regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP)
723 return;
724 #endif /* CONFIG_KGDB_LOW_LEVEL_TRAP */
725
726 if (notify_die(DIE_TRAP, str, regs, code, regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP)
727 return;
728
729 /*
730 * A short test says that IRIX 5.3 sends SIGTRAP for all trap
731 * insns, even for trap and break codes that indicate arithmetic
732 * failures. Weird ...
733 * But should we continue the brokenness??? --macro
734 */
735 switch (code) {
736 case BRK_OVERFLOW:
737 case BRK_DIVZERO:
738 scnprintf(b, sizeof(b), "%s instruction in kernel code", str);
739 die_if_kernel(b, regs);
740 if (code == BRK_DIVZERO)
741 info.si_code = FPE_INTDIV;
742 else
743 info.si_code = FPE_INTOVF;
744 info.si_signo = SIGFPE;
745 info.si_errno = 0;
746 info.si_addr = (void __user *) regs->cp0_epc;
747 force_sig_info(SIGFPE, &info, current);
748 break;
749 case BRK_BUG:
750 die_if_kernel("Kernel bug detected", regs);
751 force_sig(SIGTRAP, current);
752 break;
753 case BRK_MEMU:
754 /*
755 * Address errors may be deliberately induced by the FPU
756 * emulator to retake control of the CPU after executing the
757 * instruction in the delay slot of an emulated branch.
758 *
759 * Terminate if exception was recognized as a delay slot return
760 * otherwise handle as normal.
761 */
762 if (do_dsemulret(regs))
763 return;
764
765 die_if_kernel("Math emu break/trap", regs);
766 force_sig(SIGTRAP, current);
767 break;
768 default:
769 scnprintf(b, sizeof(b), "%s instruction in kernel code", str);
770 die_if_kernel(b, regs);
771 force_sig(SIGTRAP, current);
772 }
773 }
774
775 asmlinkage void do_bp(struct pt_regs *regs)
776 {
777 unsigned int opcode, bcode;
778
779 if (__get_user(opcode, (unsigned int __user *) exception_epc(regs)))
780 goto out_sigsegv;
781
782 /*
783 * There is the ancient bug in the MIPS assemblers that the break
784 * code starts left to bit 16 instead to bit 6 in the opcode.
785 * Gas is bug-compatible, but not always, grrr...
786 * We handle both cases with a simple heuristics. --macro
787 */
788 bcode = ((opcode >> 6) & ((1 << 20) - 1));
789 if (bcode >= (1 << 10))
790 bcode >>= 10;
791
792 /*
793 * notify the kprobe handlers, if instruction is likely to
794 * pertain to them.
795 */
796 switch (bcode) {
797 case BRK_KPROBE_BP:
798 if (notify_die(DIE_BREAK, "debug", regs, bcode, regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP)
799 return;
800 else
801 break;
802 case BRK_KPROBE_SSTEPBP:
803 if (notify_die(DIE_SSTEPBP, "single_step", regs, bcode, regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP)
804 return;
805 else
806 break;
807 default:
808 break;
809 }
810
811 do_trap_or_bp(regs, bcode, "Break");
812 return;
813
814 out_sigsegv:
815 force_sig(SIGSEGV, current);
816 }
817
818 asmlinkage void do_tr(struct pt_regs *regs)
819 {
820 unsigned int opcode, tcode = 0;
821
822 if (__get_user(opcode, (unsigned int __user *) exception_epc(regs)))
823 goto out_sigsegv;
824
825 /* Immediate versions don't provide a code. */
826 if (!(opcode & OPCODE))
827 tcode = ((opcode >> 6) & ((1 << 10) - 1));
828
829 do_trap_or_bp(regs, tcode, "Trap");
830 return;
831
832 out_sigsegv:
833 force_sig(SIGSEGV, current);
834 }
835
836 asmlinkage void do_ri(struct pt_regs *regs)
837 {
838 unsigned int __user *epc = (unsigned int __user *)exception_epc(regs);
839 unsigned long old_epc = regs->cp0_epc;
840 unsigned int opcode = 0;
841 int status = -1;
842
843 if (notify_die(DIE_RI, "RI Fault", regs, 0, regs_to_trapnr(regs), SIGILL)
844 == NOTIFY_STOP)
845 return;
846
847 die_if_kernel("Reserved instruction in kernel code", regs);
848
849 if (unlikely(compute_return_epc(regs) < 0))
850 return;
851
852 if (unlikely(get_user(opcode, epc) < 0))
853 status = SIGSEGV;
854
855 if (!cpu_has_llsc && status < 0)
856 status = simulate_llsc(regs, opcode);
857
858 if (status < 0)
859 status = simulate_rdhwr(regs, opcode);
860
861 if (status < 0)
862 status = simulate_sync(regs, opcode);
863
864 if (status < 0)
865 status = SIGILL;
866
867 if (unlikely(status > 0)) {
868 regs->cp0_epc = old_epc; /* Undo skip-over. */
869 force_sig(status, current);
870 }
871 }
872
873 /*
874 * MIPS MT processors may have fewer FPU contexts than CPU threads. If we've
875 * emulated more than some threshold number of instructions, force migration to
876 * a "CPU" that has FP support.
877 */
878 static void mt_ase_fp_affinity(void)
879 {
880 #ifdef CONFIG_MIPS_MT_FPAFF
881 if (mt_fpemul_threshold > 0 &&
882 ((current->thread.emulated_fp++ > mt_fpemul_threshold))) {
883 /*
884 * If there's no FPU present, or if the application has already
885 * restricted the allowed set to exclude any CPUs with FPUs,
886 * we'll skip the procedure.
887 */
888 if (cpus_intersects(current->cpus_allowed, mt_fpu_cpumask)) {
889 cpumask_t tmask;
890
891 current->thread.user_cpus_allowed
892 = current->cpus_allowed;
893 cpus_and(tmask, current->cpus_allowed,
894 mt_fpu_cpumask);
895 set_cpus_allowed_ptr(current, &tmask);
896 set_thread_flag(TIF_FPUBOUND);
897 }
898 }
899 #endif /* CONFIG_MIPS_MT_FPAFF */
900 }
901
902 /*
903 * No lock; only written during early bootup by CPU 0.
904 */
905 static RAW_NOTIFIER_HEAD(cu2_chain);
906
907 int __ref register_cu2_notifier(struct notifier_block *nb)
908 {
909 return raw_notifier_chain_register(&cu2_chain, nb);
910 }
911
912 int cu2_notifier_call_chain(unsigned long val, void *v)
913 {
914 return raw_notifier_call_chain(&cu2_chain, val, v);
915 }
916
917 static int default_cu2_call(struct notifier_block *nfb, unsigned long action,
918 void *data)
919 {
920 struct pt_regs *regs = data;
921
922 switch (action) {
923 default:
924 die_if_kernel("Unhandled kernel unaligned access or invalid "
925 "instruction", regs);
926 /* Fall through */
927
928 case CU2_EXCEPTION:
929 force_sig(SIGILL, current);
930 }
931
932 return NOTIFY_OK;
933 }
934
935 asmlinkage void do_cpu(struct pt_regs *regs)
936 {
937 unsigned int __user *epc;
938 unsigned long old_epc;
939 unsigned int opcode;
940 unsigned int cpid;
941 int status;
942 unsigned long __maybe_unused flags;
943
944 die_if_kernel("do_cpu invoked from kernel context!", regs);
945
946 cpid = (regs->cp0_cause >> CAUSEB_CE) & 3;
947
948 switch (cpid) {
949 case 0:
950 epc = (unsigned int __user *)exception_epc(regs);
951 old_epc = regs->cp0_epc;
952 opcode = 0;
953 status = -1;
954
955 if (unlikely(compute_return_epc(regs) < 0))
956 return;
957
958 if (unlikely(get_user(opcode, epc) < 0))
959 status = SIGSEGV;
960
961 if (!cpu_has_llsc && status < 0)
962 status = simulate_llsc(regs, opcode);
963
964 if (status < 0)
965 status = simulate_rdhwr(regs, opcode);
966
967 if (status < 0)
968 status = SIGILL;
969
970 if (unlikely(status > 0)) {
971 regs->cp0_epc = old_epc; /* Undo skip-over. */
972 force_sig(status, current);
973 }
974
975 return;
976
977 case 1:
978 if (used_math()) /* Using the FPU again. */
979 own_fpu(1);
980 else { /* First time FPU user. */
981 init_fpu();
982 set_used_math();
983 }
984
985 if (!raw_cpu_has_fpu) {
986 int sig;
987 sig = fpu_emulator_cop1Handler(regs,
988 &current->thread.fpu, 0);
989 if (sig)
990 force_sig(sig, current);
991 else
992 mt_ase_fp_affinity();
993 }
994
995 return;
996
997 case 2:
998 raw_notifier_call_chain(&cu2_chain, CU2_EXCEPTION, regs);
999 return;
1000
1001 case 3:
1002 break;
1003 }
1004
1005 force_sig(SIGILL, current);
1006 }
1007
1008 asmlinkage void do_mdmx(struct pt_regs *regs)
1009 {
1010 force_sig(SIGILL, current);
1011 }
1012
1013 /*
1014 * Called with interrupts disabled.
1015 */
1016 asmlinkage void do_watch(struct pt_regs *regs)
1017 {
1018 u32 cause;
1019
1020 /*
1021 * Clear WP (bit 22) bit of cause register so we don't loop
1022 * forever.
1023 */
1024 cause = read_c0_cause();
1025 cause &= ~(1 << 22);
1026 write_c0_cause(cause);
1027
1028 /*
1029 * If the current thread has the watch registers loaded, save
1030 * their values and send SIGTRAP. Otherwise another thread
1031 * left the registers set, clear them and continue.
1032 */
1033 if (test_tsk_thread_flag(current, TIF_LOAD_WATCH)) {
1034 mips_read_watch_registers();
1035 local_irq_enable();
1036 force_sig(SIGTRAP, current);
1037 } else {
1038 mips_clear_watch_registers();
1039 local_irq_enable();
1040 }
1041 }
1042
1043 asmlinkage void do_mcheck(struct pt_regs *regs)
1044 {
1045 const int field = 2 * sizeof(unsigned long);
1046 int multi_match = regs->cp0_status & ST0_TS;
1047
1048 show_regs(regs);
1049
1050 if (multi_match) {
1051 printk("Index : %0x\n", read_c0_index());
1052 printk("Pagemask: %0x\n", read_c0_pagemask());
1053 printk("EntryHi : %0*lx\n", field, read_c0_entryhi());
1054 printk("EntryLo0: %0*lx\n", field, read_c0_entrylo0());
1055 printk("EntryLo1: %0*lx\n", field, read_c0_entrylo1());
1056 printk("\n");
1057 dump_tlb_all();
1058 }
1059
1060 show_code((unsigned int __user *) regs->cp0_epc);
1061
1062 /*
1063 * Some chips may have other causes of machine check (e.g. SB1
1064 * graduation timer)
1065 */
1066 panic("Caught Machine Check exception - %scaused by multiple "
1067 "matching entries in the TLB.",
1068 (multi_match) ? "" : "not ");
1069 }
1070
1071 asmlinkage void do_mt(struct pt_regs *regs)
1072 {
1073 int subcode;
1074
1075 subcode = (read_vpe_c0_vpecontrol() & VPECONTROL_EXCPT)
1076 >> VPECONTROL_EXCPT_SHIFT;
1077 switch (subcode) {
1078 case 0:
1079 printk(KERN_DEBUG "Thread Underflow\n");
1080 break;
1081 case 1:
1082 printk(KERN_DEBUG "Thread Overflow\n");
1083 break;
1084 case 2:
1085 printk(KERN_DEBUG "Invalid YIELD Qualifier\n");
1086 break;
1087 case 3:
1088 printk(KERN_DEBUG "Gating Storage Exception\n");
1089 break;
1090 case 4:
1091 printk(KERN_DEBUG "YIELD Scheduler Exception\n");
1092 break;
1093 case 5:
1094 printk(KERN_DEBUG "Gating Storage Schedulier Exception\n");
1095 break;
1096 default:
1097 printk(KERN_DEBUG "*** UNKNOWN THREAD EXCEPTION %d ***\n",
1098 subcode);
1099 break;
1100 }
1101 die_if_kernel("MIPS MT Thread exception in kernel", regs);
1102
1103 force_sig(SIGILL, current);
1104 }
1105
1106
1107 asmlinkage void do_dsp(struct pt_regs *regs)
1108 {
1109 if (cpu_has_dsp)
1110 panic("Unexpected DSP exception\n");
1111
1112 force_sig(SIGILL, current);
1113 }
1114
1115 asmlinkage void do_reserved(struct pt_regs *regs)
1116 {
1117 /*
1118 * Game over - no way to handle this if it ever occurs. Most probably
1119 * caused by a new unknown cpu type or after another deadly
1120 * hard/software error.
1121 */
1122 show_regs(regs);
1123 panic("Caught reserved exception %ld - should not happen.",
1124 (regs->cp0_cause & 0x7f) >> 2);
1125 }
1126
1127 static int __initdata l1parity = 1;
1128 static int __init nol1parity(char *s)
1129 {
1130 l1parity = 0;
1131 return 1;
1132 }
1133 __setup("nol1par", nol1parity);
1134 static int __initdata l2parity = 1;
1135 static int __init nol2parity(char *s)
1136 {
1137 l2parity = 0;
1138 return 1;
1139 }
1140 __setup("nol2par", nol2parity);
1141
1142 /*
1143 * Some MIPS CPUs can enable/disable for cache parity detection, but do
1144 * it different ways.
1145 */
1146 static inline void parity_protection_init(void)
1147 {
1148 switch (current_cpu_type()) {
1149 case CPU_24K:
1150 case CPU_34K:
1151 case CPU_74K:
1152 case CPU_1004K:
1153 {
1154 #define ERRCTL_PE 0x80000000
1155 #define ERRCTL_L2P 0x00800000
1156 unsigned long errctl;
1157 unsigned int l1parity_present, l2parity_present;
1158
1159 errctl = read_c0_ecc();
1160 errctl &= ~(ERRCTL_PE|ERRCTL_L2P);
1161
1162 /* probe L1 parity support */
1163 write_c0_ecc(errctl | ERRCTL_PE);
1164 back_to_back_c0_hazard();
1165 l1parity_present = (read_c0_ecc() & ERRCTL_PE);
1166
1167 /* probe L2 parity support */
1168 write_c0_ecc(errctl|ERRCTL_L2P);
1169 back_to_back_c0_hazard();
1170 l2parity_present = (read_c0_ecc() & ERRCTL_L2P);
1171
1172 if (l1parity_present && l2parity_present) {
1173 if (l1parity)
1174 errctl |= ERRCTL_PE;
1175 if (l1parity ^ l2parity)
1176 errctl |= ERRCTL_L2P;
1177 } else if (l1parity_present) {
1178 if (l1parity)
1179 errctl |= ERRCTL_PE;
1180 } else if (l2parity_present) {
1181 if (l2parity)
1182 errctl |= ERRCTL_L2P;
1183 } else {
1184 /* No parity available */
1185 }
1186
1187 printk(KERN_INFO "Writing ErrCtl register=%08lx\n", errctl);
1188
1189 write_c0_ecc(errctl);
1190 back_to_back_c0_hazard();
1191 errctl = read_c0_ecc();
1192 printk(KERN_INFO "Readback ErrCtl register=%08lx\n", errctl);
1193
1194 if (l1parity_present)
1195 printk(KERN_INFO "Cache parity protection %sabled\n",
1196 (errctl & ERRCTL_PE) ? "en" : "dis");
1197
1198 if (l2parity_present) {
1199 if (l1parity_present && l1parity)
1200 errctl ^= ERRCTL_L2P;
1201 printk(KERN_INFO "L2 cache parity protection %sabled\n",
1202 (errctl & ERRCTL_L2P) ? "en" : "dis");
1203 }
1204 }
1205 break;
1206
1207 case CPU_5KC:
1208 write_c0_ecc(0x80000000);
1209 back_to_back_c0_hazard();
1210 /* Set the PE bit (bit 31) in the c0_errctl register. */
1211 printk(KERN_INFO "Cache parity protection %sabled\n",
1212 (read_c0_ecc() & 0x80000000) ? "en" : "dis");
1213 break;
1214 case CPU_20KC:
1215 case CPU_25KF:
1216 /* Clear the DE bit (bit 16) in the c0_status register. */
1217 printk(KERN_INFO "Enable cache parity protection for "
1218 "MIPS 20KC/25KF CPUs.\n");
1219 clear_c0_status(ST0_DE);
1220 break;
1221 default:
1222 break;
1223 }
1224 }
1225
1226 asmlinkage void cache_parity_error(void)
1227 {
1228 const int field = 2 * sizeof(unsigned long);
1229 unsigned int reg_val;
1230
1231 /* For the moment, report the problem and hang. */
1232 printk("Cache error exception:\n");
1233 printk("cp0_errorepc == %0*lx\n", field, read_c0_errorepc());
1234 reg_val = read_c0_cacheerr();
1235 printk("c0_cacheerr == %08x\n", reg_val);
1236
1237 printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n",
1238 reg_val & (1<<30) ? "secondary" : "primary",
1239 reg_val & (1<<31) ? "data" : "insn");
1240 printk("Error bits: %s%s%s%s%s%s%s\n",
1241 reg_val & (1<<29) ? "ED " : "",
1242 reg_val & (1<<28) ? "ET " : "",
1243 reg_val & (1<<26) ? "EE " : "",
1244 reg_val & (1<<25) ? "EB " : "",
1245 reg_val & (1<<24) ? "EI " : "",
1246 reg_val & (1<<23) ? "E1 " : "",
1247 reg_val & (1<<22) ? "E0 " : "");
1248 printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1));
1249
1250 #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
1251 if (reg_val & (1<<22))
1252 printk("DErrAddr0: 0x%0*lx\n", field, read_c0_derraddr0());
1253
1254 if (reg_val & (1<<23))
1255 printk("DErrAddr1: 0x%0*lx\n", field, read_c0_derraddr1());
1256 #endif
1257
1258 panic("Can't handle the cache error!");
1259 }
1260
1261 /*
1262 * SDBBP EJTAG debug exception handler.
1263 * We skip the instruction and return to the next instruction.
1264 */
1265 void ejtag_exception_handler(struct pt_regs *regs)
1266 {
1267 const int field = 2 * sizeof(unsigned long);
1268 unsigned long depc, old_epc;
1269 unsigned int debug;
1270
1271 printk(KERN_DEBUG "SDBBP EJTAG debug exception - not handled yet, just ignored!\n");
1272 depc = read_c0_depc();
1273 debug = read_c0_debug();
1274 printk(KERN_DEBUG "c0_depc = %0*lx, DEBUG = %08x\n", field, depc, debug);
1275 if (debug & 0x80000000) {
1276 /*
1277 * In branch delay slot.
1278 * We cheat a little bit here and use EPC to calculate the
1279 * debug return address (DEPC). EPC is restored after the
1280 * calculation.
1281 */
1282 old_epc = regs->cp0_epc;
1283 regs->cp0_epc = depc;
1284 __compute_return_epc(regs);
1285 depc = regs->cp0_epc;
1286 regs->cp0_epc = old_epc;
1287 } else
1288 depc += 4;
1289 write_c0_depc(depc);
1290
1291 #if 0
1292 printk(KERN_DEBUG "\n\n----- Enable EJTAG single stepping ----\n\n");
1293 write_c0_debug(debug | 0x100);
1294 #endif
1295 }
1296
1297 /*
1298 * NMI exception handler.
1299 */
1300 NORET_TYPE void ATTRIB_NORET nmi_exception_handler(struct pt_regs *regs)
1301 {
1302 bust_spinlocks(1);
1303 printk("NMI taken!!!!\n");
1304 die("NMI", regs);
1305 }
1306
1307 #define VECTORSPACING 0x100 /* for EI/VI mode */
1308
1309 unsigned long ebase;
1310 unsigned long exception_handlers[32];
1311 unsigned long vi_handlers[64];
1312
1313 void __init *set_except_vector(int n, void *addr)
1314 {
1315 unsigned long handler = (unsigned long) addr;
1316 unsigned long old_handler = exception_handlers[n];
1317
1318 exception_handlers[n] = handler;
1319 if (n == 0 && cpu_has_divec) {
1320 unsigned long jump_mask = ~((1 << 28) - 1);
1321 u32 *buf = (u32 *)(ebase + 0x200);
1322 unsigned int k0 = 26;
1323 if ((handler & jump_mask) == ((ebase + 0x200) & jump_mask)) {
1324 uasm_i_j(&buf, handler & ~jump_mask);
1325 uasm_i_nop(&buf);
1326 } else {
1327 UASM_i_LA(&buf, k0, handler);
1328 uasm_i_jr(&buf, k0);
1329 uasm_i_nop(&buf);
1330 }
1331 local_flush_icache_range(ebase + 0x200, (unsigned long)buf);
1332 }
1333 return (void *)old_handler;
1334 }
1335
1336 static asmlinkage void do_default_vi(void)
1337 {
1338 show_regs(get_irq_regs());
1339 panic("Caught unexpected vectored interrupt.");
1340 }
1341
1342 static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs)
1343 {
1344 unsigned long handler;
1345 unsigned long old_handler = vi_handlers[n];
1346 int srssets = current_cpu_data.srsets;
1347 u32 *w;
1348 unsigned char *b;
1349
1350 BUG_ON(!cpu_has_veic && !cpu_has_vint);
1351
1352 if (addr == NULL) {
1353 handler = (unsigned long) do_default_vi;
1354 srs = 0;
1355 } else
1356 handler = (unsigned long) addr;
1357 vi_handlers[n] = (unsigned long) addr;
1358
1359 b = (unsigned char *)(ebase + 0x200 + n*VECTORSPACING);
1360
1361 if (srs >= srssets)
1362 panic("Shadow register set %d not supported", srs);
1363
1364 if (cpu_has_veic) {
1365 if (board_bind_eic_interrupt)
1366 board_bind_eic_interrupt(n, srs);
1367 } else if (cpu_has_vint) {
1368 /* SRSMap is only defined if shadow sets are implemented */
1369 if (srssets > 1)
1370 change_c0_srsmap(0xf << n*4, srs << n*4);
1371 }
1372
1373 if (srs == 0) {
1374 /*
1375 * If no shadow set is selected then use the default handler
1376 * that does normal register saving and a standard interrupt exit
1377 */
1378
1379 extern char except_vec_vi, except_vec_vi_lui;
1380 extern char except_vec_vi_ori, except_vec_vi_end;
1381 extern char rollback_except_vec_vi;
1382 char *vec_start = (cpu_wait == r4k_wait) ?
1383 &rollback_except_vec_vi : &except_vec_vi;
1384 #ifdef CONFIG_MIPS_MT_SMTC
1385 /*
1386 * We need to provide the SMTC vectored interrupt handler
1387 * not only with the address of the handler, but with the
1388 * Status.IM bit to be masked before going there.
1389 */
1390 extern char except_vec_vi_mori;
1391 const int mori_offset = &except_vec_vi_mori - vec_start;
1392 #endif /* CONFIG_MIPS_MT_SMTC */
1393 const int handler_len = &except_vec_vi_end - vec_start;
1394 const int lui_offset = &except_vec_vi_lui - vec_start;
1395 const int ori_offset = &except_vec_vi_ori - vec_start;
1396
1397 if (handler_len > VECTORSPACING) {
1398 /*
1399 * Sigh... panicing won't help as the console
1400 * is probably not configured :(
1401 */
1402 panic("VECTORSPACING too small");
1403 }
1404
1405 memcpy(b, vec_start, handler_len);
1406 #ifdef CONFIG_MIPS_MT_SMTC
1407 BUG_ON(n > 7); /* Vector index %d exceeds SMTC maximum. */
1408
1409 w = (u32 *)(b + mori_offset);
1410 *w = (*w & 0xffff0000) | (0x100 << n);
1411 #endif /* CONFIG_MIPS_MT_SMTC */
1412 w = (u32 *)(b + lui_offset);
1413 *w = (*w & 0xffff0000) | (((u32)handler >> 16) & 0xffff);
1414 w = (u32 *)(b + ori_offset);
1415 *w = (*w & 0xffff0000) | ((u32)handler & 0xffff);
1416 local_flush_icache_range((unsigned long)b,
1417 (unsigned long)(b+handler_len));
1418 }
1419 else {
1420 /*
1421 * In other cases jump directly to the interrupt handler
1422 *
1423 * It is the handlers responsibility to save registers if required
1424 * (eg hi/lo) and return from the exception using "eret"
1425 */
1426 w = (u32 *)b;
1427 *w++ = 0x08000000 | (((u32)handler >> 2) & 0x03fffff); /* j handler */
1428 *w = 0;
1429 local_flush_icache_range((unsigned long)b,
1430 (unsigned long)(b+8));
1431 }
1432
1433 return (void *)old_handler;
1434 }
1435
1436 void *set_vi_handler(int n, vi_handler_t addr)
1437 {
1438 return set_vi_srs_handler(n, addr, 0);
1439 }
1440
1441 extern void cpu_cache_init(void);
1442 extern void tlb_init(void);
1443 extern void flush_tlb_handlers(void);
1444
1445 /*
1446 * Timer interrupt
1447 */
1448 int cp0_compare_irq;
1449 int cp0_compare_irq_shift;
1450
1451 /*
1452 * Performance counter IRQ or -1 if shared with timer
1453 */
1454 int cp0_perfcount_irq;
1455 EXPORT_SYMBOL_GPL(cp0_perfcount_irq);
1456
1457 static int __cpuinitdata noulri;
1458
1459 static int __init ulri_disable(char *s)
1460 {
1461 pr_info("Disabling ulri\n");
1462 noulri = 1;
1463
1464 return 1;
1465 }
1466 __setup("noulri", ulri_disable);
1467
1468 void __cpuinit per_cpu_trap_init(void)
1469 {
1470 unsigned int cpu = smp_processor_id();
1471 unsigned int status_set = ST0_CU0;
1472 #ifdef CONFIG_MIPS_MT_SMTC
1473 int secondaryTC = 0;
1474 int bootTC = (cpu == 0);
1475
1476 /*
1477 * Only do per_cpu_trap_init() for first TC of Each VPE.
1478 * Note that this hack assumes that the SMTC init code
1479 * assigns TCs consecutively and in ascending order.
1480 */
1481
1482 if (((read_c0_tcbind() & TCBIND_CURTC) != 0) &&
1483 ((read_c0_tcbind() & TCBIND_CURVPE) == cpu_data[cpu - 1].vpe_id))
1484 secondaryTC = 1;
1485 #endif /* CONFIG_MIPS_MT_SMTC */
1486
1487 /*
1488 * Disable coprocessors and select 32-bit or 64-bit addressing
1489 * and the 16/32 or 32/32 FPR register model. Reset the BEV
1490 * flag that some firmware may have left set and the TS bit (for
1491 * IP27). Set XX for ISA IV code to work.
1492 */
1493 #ifdef CONFIG_64BIT
1494 status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX;
1495 #endif
1496 if (current_cpu_data.isa_level == MIPS_CPU_ISA_IV)
1497 status_set |= ST0_XX;
1498 if (cpu_has_dsp)
1499 status_set |= ST0_MX;
1500
1501 change_c0_status(ST0_CU|ST0_MX|ST0_RE|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX,
1502 status_set);
1503
1504 if (cpu_has_mips_r2) {
1505 unsigned int enable = 0x0000000f | cpu_hwrena_impl_bits;
1506
1507 if (!noulri && cpu_has_userlocal)
1508 enable |= (1 << 29);
1509
1510 write_c0_hwrena(enable);
1511 }
1512
1513 #ifdef CONFIG_MIPS_MT_SMTC
1514 if (!secondaryTC) {
1515 #endif /* CONFIG_MIPS_MT_SMTC */
1516
1517 if (cpu_has_veic || cpu_has_vint) {
1518 unsigned long sr = set_c0_status(ST0_BEV);
1519 write_c0_ebase(ebase);
1520 write_c0_status(sr);
1521 /* Setting vector spacing enables EI/VI mode */
1522 change_c0_intctl(0x3e0, VECTORSPACING);
1523 }
1524 if (cpu_has_divec) {
1525 if (cpu_has_mipsmt) {
1526 unsigned int vpflags = dvpe();
1527 set_c0_cause(CAUSEF_IV);
1528 evpe(vpflags);
1529 } else
1530 set_c0_cause(CAUSEF_IV);
1531 }
1532
1533 /*
1534 * Before R2 both interrupt numbers were fixed to 7, so on R2 only:
1535 *
1536 * o read IntCtl.IPTI to determine the timer interrupt
1537 * o read IntCtl.IPPCI to determine the performance counter interrupt
1538 */
1539 if (cpu_has_mips_r2) {
1540 cp0_compare_irq_shift = CAUSEB_TI - CAUSEB_IP;
1541 cp0_compare_irq = (read_c0_intctl() >> INTCTLB_IPTI) & 7;
1542 cp0_perfcount_irq = (read_c0_intctl() >> INTCTLB_IPPCI) & 7;
1543 if (cp0_perfcount_irq == cp0_compare_irq)
1544 cp0_perfcount_irq = -1;
1545 } else {
1546 cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ;
1547 cp0_compare_irq_shift = cp0_compare_irq;
1548 cp0_perfcount_irq = -1;
1549 }
1550
1551 #ifdef CONFIG_MIPS_MT_SMTC
1552 }
1553 #endif /* CONFIG_MIPS_MT_SMTC */
1554
1555 cpu_data[cpu].asid_cache = ASID_FIRST_VERSION;
1556 TLBMISS_HANDLER_SETUP();
1557
1558 atomic_inc(&init_mm.mm_count);
1559 current->active_mm = &init_mm;
1560 BUG_ON(current->mm);
1561 enter_lazy_tlb(&init_mm, current);
1562
1563 #ifdef CONFIG_MIPS_MT_SMTC
1564 if (bootTC) {
1565 #endif /* CONFIG_MIPS_MT_SMTC */
1566 cpu_cache_init();
1567 tlb_init();
1568 #ifdef CONFIG_MIPS_MT_SMTC
1569 } else if (!secondaryTC) {
1570 /*
1571 * First TC in non-boot VPE must do subset of tlb_init()
1572 * for MMU countrol registers.
1573 */
1574 write_c0_pagemask(PM_DEFAULT_MASK);
1575 write_c0_wired(0);
1576 }
1577 #endif /* CONFIG_MIPS_MT_SMTC */
1578 }
1579
1580 /* Install CPU exception handler */
1581 void __init set_handler(unsigned long offset, void *addr, unsigned long size)
1582 {
1583 memcpy((void *)(ebase + offset), addr, size);
1584 local_flush_icache_range(ebase + offset, ebase + offset + size);
1585 }
1586
1587 static char panic_null_cerr[] __cpuinitdata =
1588 "Trying to set NULL cache error exception handler";
1589
1590 /*
1591 * Install uncached CPU exception handler.
1592 * This is suitable only for the cache error exception which is the only
1593 * exception handler that is being run uncached.
1594 */
1595 void __cpuinit set_uncached_handler(unsigned long offset, void *addr,
1596 unsigned long size)
1597 {
1598 unsigned long uncached_ebase = CKSEG1ADDR(ebase);
1599
1600 if (!addr)
1601 panic(panic_null_cerr);
1602
1603 memcpy((void *)(uncached_ebase + offset), addr, size);
1604 }
1605
1606 static int __initdata rdhwr_noopt;
1607 static int __init set_rdhwr_noopt(char *str)
1608 {
1609 rdhwr_noopt = 1;
1610 return 1;
1611 }
1612
1613 __setup("rdhwr_noopt", set_rdhwr_noopt);
1614
1615 void __init trap_init(void)
1616 {
1617 extern char except_vec3_generic, except_vec3_r4000;
1618 extern char except_vec4;
1619 unsigned long i;
1620 int rollback;
1621
1622 check_wait();
1623 rollback = (cpu_wait == r4k_wait);
1624
1625 #if defined(CONFIG_KGDB)
1626 if (kgdb_early_setup)
1627 return; /* Already done */
1628 #endif
1629
1630 if (cpu_has_veic || cpu_has_vint) {
1631 unsigned long size = 0x200 + VECTORSPACING*64;
1632 ebase = (unsigned long)
1633 __alloc_bootmem(size, 1 << fls(size), 0);
1634 } else {
1635 ebase = CKSEG0;
1636 if (cpu_has_mips_r2)
1637 ebase += (read_c0_ebase() & 0x3ffff000);
1638 }
1639
1640 per_cpu_trap_init();
1641
1642 /*
1643 * Copy the generic exception handlers to their final destination.
1644 * This will be overriden later as suitable for a particular
1645 * configuration.
1646 */
1647 set_handler(0x180, &except_vec3_generic, 0x80);
1648
1649 /*
1650 * Setup default vectors
1651 */
1652 for (i = 0; i <= 31; i++)
1653 set_except_vector(i, handle_reserved);
1654
1655 /*
1656 * Copy the EJTAG debug exception vector handler code to it's final
1657 * destination.
1658 */
1659 if (cpu_has_ejtag && board_ejtag_handler_setup)
1660 board_ejtag_handler_setup();
1661
1662 /*
1663 * Only some CPUs have the watch exceptions.
1664 */
1665 if (cpu_has_watch)
1666 set_except_vector(23, handle_watch);
1667
1668 /*
1669 * Initialise interrupt handlers
1670 */
1671 if (cpu_has_veic || cpu_has_vint) {
1672 int nvec = cpu_has_veic ? 64 : 8;
1673 for (i = 0; i < nvec; i++)
1674 set_vi_handler(i, NULL);
1675 }
1676 else if (cpu_has_divec)
1677 set_handler(0x200, &except_vec4, 0x8);
1678
1679 /*
1680 * Some CPUs can enable/disable for cache parity detection, but does
1681 * it different ways.
1682 */
1683 parity_protection_init();
1684
1685 /*
1686 * The Data Bus Errors / Instruction Bus Errors are signaled
1687 * by external hardware. Therefore these two exceptions
1688 * may have board specific handlers.
1689 */
1690 if (board_be_init)
1691 board_be_init();
1692
1693 set_except_vector(0, rollback ? rollback_handle_int : handle_int);
1694 set_except_vector(1, handle_tlbm);
1695 set_except_vector(2, handle_tlbl);
1696 set_except_vector(3, handle_tlbs);
1697
1698 set_except_vector(4, handle_adel);
1699 set_except_vector(5, handle_ades);
1700
1701 set_except_vector(6, handle_ibe);
1702 set_except_vector(7, handle_dbe);
1703
1704 set_except_vector(8, handle_sys);
1705 set_except_vector(9, handle_bp);
1706 set_except_vector(10, rdhwr_noopt ? handle_ri :
1707 (cpu_has_vtag_icache ?
1708 handle_ri_rdhwr_vivt : handle_ri_rdhwr));
1709 set_except_vector(11, handle_cpu);
1710 set_except_vector(12, handle_ov);
1711 set_except_vector(13, handle_tr);
1712
1713 if (current_cpu_type() == CPU_R6000 ||
1714 current_cpu_type() == CPU_R6000A) {
1715 /*
1716 * The R6000 is the only R-series CPU that features a machine
1717 * check exception (similar to the R4000 cache error) and
1718 * unaligned ldc1/sdc1 exception. The handlers have not been
1719 * written yet. Well, anyway there is no R6000 machine on the
1720 * current list of targets for Linux/MIPS.
1721 * (Duh, crap, there is someone with a triple R6k machine)
1722 */
1723 //set_except_vector(14, handle_mc);
1724 //set_except_vector(15, handle_ndc);
1725 }
1726
1727
1728 if (board_nmi_handler_setup)
1729 board_nmi_handler_setup();
1730
1731 if (cpu_has_fpu && !cpu_has_nofpuex)
1732 set_except_vector(15, handle_fpe);
1733
1734 set_except_vector(22, handle_mdmx);
1735
1736 if (cpu_has_mcheck)
1737 set_except_vector(24, handle_mcheck);
1738
1739 if (cpu_has_mipsmt)
1740 set_except_vector(25, handle_mt);
1741
1742 set_except_vector(26, handle_dsp);
1743
1744 if (cpu_has_vce)
1745 /* Special exception: R4[04]00 uses also the divec space. */
1746 memcpy((void *)(ebase + 0x180), &except_vec3_r4000, 0x100);
1747 else if (cpu_has_4kex)
1748 memcpy((void *)(ebase + 0x180), &except_vec3_generic, 0x80);
1749 else
1750 memcpy((void *)(ebase + 0x080), &except_vec3_generic, 0x80);
1751
1752 local_flush_icache_range(ebase, ebase + 0x400);
1753 flush_tlb_handlers();
1754
1755 sort_extable(__start___dbe_table, __stop___dbe_table);
1756
1757 cu2_notifier(default_cu2_call, 0x80000000); /* Run last */
1758 }
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree