arch/alpha/kernel/sys_sio.c

   1 /*
   2  *      linux/arch/alpha/kernel/sys_sio.c
   3  *
   4  *      Copyright (C) 1995 David A Rusling
   5  *      Copyright (C) 1996 Jay A Estabrook
   6  *      Copyright (C) 1998, 1999 Richard Henderson
   7  *
   8  * Code for all boards that route the PCI interrupts through the SIO
   9  * PCI/ISA bridge.  This includes Noname (AXPpci33), Multia (UDB),
  10  * Kenetics's Platform 2000, Avanti (AlphaStation), XL, and AlphaBook1.
  11  */
  12
  13 #include <linux/kernel.h>
  14 #include <linux/types.h>
  15 #include <linux/mm.h>
  16 #include <linux/sched.h>
  17 #include <linux/pci.h>
  18 #include <linux/init.h>
  19 #include <linux/screen_info.h>
  20
  21 #include <asm/compiler.h>
  22 #include <asm/ptrace.h>
  23 #include <asm/system.h>
  24 #include <asm/dma.h>
  25 #include <asm/irq.h>
  26 #include <asm/mmu_context.h>
  27 #include <asm/io.h>
  28 #include <asm/pgtable.h>
  29 #include <asm/core_apecs.h>
  30 #include <asm/core_lca.h>
  31 #include <asm/tlbflush.h>
  32
  33 #include "proto.h"
  34 #include "irq_impl.h"
  35 #include "pci_impl.h"
  36 #include "machvec_impl.h"
  37 #include "pc873xx.h"
  38
  39 #if defined(ALPHA_RESTORE_SRM_SETUP)
  40 /* Save LCA configuration data as the console had it set up.  */
  41 struct
  42 {
  43         unsigned int orig_route_tab; /* for SAVE/RESTORE */
  44 } saved_config __attribute((common));
  45 #endif
  46
  47
  48 static void __init
  49 sio_init_irq(void)
  50 {
  51         if (alpha_using_srm)
  52                 alpha_mv.device_interrupt = srm_device_interrupt;
  53
  54         init_i8259a_irqs();
  55         common_init_isa_dma();
  56 }
  57
  58 static inline void __init
  59 alphabook1_init_arch(void)
  60 {
  61         /* The AlphaBook1 has LCD video fixed at 800x600,
  62            37 rows and 100 cols. */
  63         screen_info.orig_y = 37;
  64         screen_info.orig_video_cols = 100;
  65         screen_info.orig_video_lines = 37;
  66
  67         lca_init_arch();
  68 }
  69
  70
  71 /*
  72  * sio_route_tab selects irq routing in PCI/ISA bridge so that:
  73  *              PIRQ0 -> irq 15
  74  *              PIRQ1 -> irq  9
  75  *              PIRQ2 -> irq 10
  76  *              PIRQ3 -> irq 11
  77  *
  78  * This probably ought to be configurable via MILO.  For
  79  * example, sound boards seem to like using IRQ 9.
  80  *
  81  * This is NOT how we should do it. PIRQ0-X should have
  82  * their own IRQs, the way intel uses the IO-APIC IRQs.
  83  */
  84
  85 static void __init
  86 sio_pci_route(void)
  87 {
  88         unsigned int orig_route_tab;
  89
  90         /* First, ALWAYS read and print the original setting. */
  91         pci_bus_read_config_dword(pci_isa_hose->bus, PCI_DEVFN(7, 0), 0x60,
  92                                   &orig_route_tab);
  93         printk("%s: PIRQ original 0x%x new 0x%x\n", __func__,
  94                orig_route_tab, alpha_mv.sys.sio.route_tab);
  95
  96 #if defined(ALPHA_RESTORE_SRM_SETUP)
  97         saved_config.orig_route_tab = orig_route_tab;
  98 #endif
  99
 100         /* Now override with desired setting. */
 101         pci_bus_write_config_dword(pci_isa_hose->bus, PCI_DEVFN(7, 0), 0x60,
 102                                    alpha_mv.sys.sio.route_tab);
 103 }
 104
 105 static unsigned int __init
 106 sio_collect_irq_levels(void)
 107 {
 108         unsigned int level_bits = 0;
 109         struct pci_dev *dev = NULL;
 110
 111         /* Iterate through the devices, collecting IRQ levels.  */
 112         for_each_pci_dev(dev) {
 113                 if ((dev->class >> 16 == PCI_BASE_CLASS_BRIDGE) &&
 114                     (dev->class >> 8 != PCI_CLASS_BRIDGE_PCMCIA))
 115                         continue;
 116
 117                 if (dev->irq)
 118                         level_bits |= (1 << dev->irq);
 119         }
 120         return level_bits;
 121 }
 122
 123 static void __init
 124 sio_fixup_irq_levels(unsigned int level_bits)
 125 {
 126         unsigned int old_level_bits;
 127
 128         /*
 129          * Now, make all PCI interrupts level sensitive.  Notice:
 130          * these registers must be accessed byte-wise.  inw()/outw()
 131          * don't work.
 132          *
 133          * Make sure to turn off any level bits set for IRQs 9,10,11,15,
 134          *  so that the only bits getting set are for devices actually found.
 135          * Note that we do preserve the remainder of the bits, which we hope
 136          *  will be set correctly by ARC/SRM.
 137          *
 138          * Note: we at least preserve any level-set bits on AlphaBook1
 139          */
 140         old_level_bits = inb(0x4d0) | (inb(0x4d1) << 8);
 141
 142         level_bits |= (old_level_bits & 0x71ff);
 143
 144         outb((level_bits >> 0) & 0xff, 0x4d0);
 145         outb((level_bits >> 8) & 0xff, 0x4d1);
 146 }
 147
 148 static inline int __init
 149 noname_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
 150 {
 151         /*
 152          * The Noname board has 5 PCI slots with each of the 4
 153          * interrupt pins routed to different pins on the PCI/ISA
 154          * bridge (PIRQ0-PIRQ3).  The table below is based on
 155          * information available at:
 156          *
 157          *   http://ftp.digital.com/pub/DEC/axppci/ref_interrupts.txt
 158          *
 159          * I have no information on the Avanti interrupt routing, but
 160          * the routing seems to be identical to the Noname except
 161          * that the Avanti has an additional slot whose routing I'm
 162          * unsure of.
 163          *
 164          * pirq_tab[0] is a fake entry to deal with old PCI boards
 165          * that have the interrupt pin number hardwired to 0 (meaning
 166          * that they use the default INTA line, if they are interrupt
 167          * driven at all).
 168          */
 169         static char irq_tab[][5] __initdata = {
 170                 /*INT A   B   C   D */
 171                 { 3,  3,  3,  3,  3}, /* idsel  6 (53c810) */
 172                 {-1, -1, -1, -1, -1}, /* idsel  7 (SIO: PCI/ISA bridge) */
 173                 { 2,  2, -1, -1, -1}, /* idsel  8 (Hack: slot closest ISA) */
 174                 {-1, -1, -1, -1, -1}, /* idsel  9 (unused) */
 175                 {-1, -1, -1, -1, -1}, /* idsel 10 (unused) */
 176                 { 0,  0,  2,  1,  0}, /* idsel 11 KN25_PCI_SLOT0 */
 177                 { 1,  1,  0,  2,  1}, /* idsel 12 KN25_PCI_SLOT1 */
 178                 { 2,  2,  1,  0,  2}, /* idsel 13 KN25_PCI_SLOT2 */
 179                 { 0,  0,  0,  0,  0}, /* idsel 14 AS255 TULIP */
 180         };
 181         const long min_idsel = 6, max_idsel = 14, irqs_per_slot = 5;
 182         int irq = COMMON_TABLE_LOOKUP, tmp;
 183         tmp = __kernel_extbl(alpha_mv.sys.sio.route_tab, irq);
 184         return irq >= 0 ? tmp : -1;
 185 }
 186
 187 static inline int __init
 188 p2k_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
 189 {
 190         static char irq_tab[][5] __initdata = {
 191                 /*INT A   B   C   D */
 192                 { 0,  0, -1, -1, -1}, /* idsel  6 (53c810) */
 193                 {-1, -1, -1, -1, -1}, /* idsel  7 (SIO: PCI/ISA bridge) */
 194                 { 1,  1,  2,  3,  0}, /* idsel  8 (slot A) */
 195                 { 2,  2,  3,  0,  1}, /* idsel  9 (slot B) */
 196                 {-1, -1, -1, -1, -1}, /* idsel 10 (unused) */
 197                 {-1, -1, -1, -1, -1}, /* idsel 11 (unused) */
 198                 { 3,  3, -1, -1, -1}, /* idsel 12 (CMD0646) */
 199         };
 200         const long min_idsel = 6, max_idsel = 12, irqs_per_slot = 5;
 201         int irq = COMMON_TABLE_LOOKUP, tmp;
 202         tmp = __kernel_extbl(alpha_mv.sys.sio.route_tab, irq);
 203         return irq >= 0 ? tmp : -1;
 204 }
 205
 206 static inline void __init
 207 noname_init_pci(void)
 208 {
 209         common_init_pci();
 210         sio_pci_route();
 211         sio_fixup_irq_levels(sio_collect_irq_levels());
 212
 213         if (pc873xx_probe() == -1) {
 214                 printk(KERN_ERR "Probing for PC873xx Super IO chip failed.\n");
 215         } else {
 216                 printk(KERN_INFO "Found %s Super IO chip at 0x%x\n",
 217                         pc873xx_get_model(), pc873xx_get_base());
 218
 219                 /* Enabling things in the Super IO chip doesn't actually
 220                  * configure and enable things, the legacy drivers still
 221                  * need to do the actual configuration and enabling.
 222                  * This only unblocks them.
 223                  */
 224
 225 #if !defined(CONFIG_ALPHA_AVANTI)
 226                 /* Don't bother on the Avanti family.
 227                  * None of them had on-board IDE.
 228                  */
 229                 pc873xx_enable_ide();
 230 #endif
 231                 pc873xx_enable_epp19();
 232         }
 233 }
 234
 235 static inline void __init
 236 alphabook1_init_pci(void)
 237 {
 238         struct pci_dev *dev;
 239         unsigned char orig, config;
 240
 241         common_init_pci();
 242         sio_pci_route();
 243
 244         /*
 245          * On the AlphaBook1, the PCMCIA chip (Cirrus 6729)
 246          * is sensitive to PCI bus bursts, so we must DISABLE
 247          * burst mode for the NCR 8xx SCSI... :-(
 248          *
 249          * Note that the NCR810 SCSI driver must preserve the
 250          * setting of the bit in order for this to work.  At the
 251          * moment (2.0.29), ncr53c8xx.c does NOT do this, but
 252          * 53c7,8xx.c DOES.
 253          */
 254
 255         dev = NULL;
 256         while ((dev = pci_get_device(PCI_VENDOR_ID_NCR, PCI_ANY_ID, dev))) {
 257                 if (dev->device == PCI_DEVICE_ID_NCR_53C810
 258                     || dev->device == PCI_DEVICE_ID_NCR_53C815
 259                     || dev->device == PCI_DEVICE_ID_NCR_53C820
 260                     || dev->device == PCI_DEVICE_ID_NCR_53C825) {
 261                         unsigned long io_port;
 262                         unsigned char ctest4;
 263
 264                         io_port = dev->resource[0].start;
 265                         ctest4 = inb(io_port+0x21);
 266                         if (!(ctest4 & 0x80)) {
 267                                 printk("AlphaBook1 NCR init: setting"
 268                                        " burst disable\n");
 269                                 outb(ctest4 | 0x80, io_port+0x21);
 270                         }
 271                 }
 272         }
 273
 274         /* Do not set *ANY* level triggers for AlphaBook1. */
 275         sio_fixup_irq_levels(0);
 276
 277         /* Make sure that register PR1 indicates 1Mb mem */
 278         outb(0x0f, 0x3ce); orig = inb(0x3cf);   /* read PR5  */
 279         outb(0x0f, 0x3ce); outb(0x05, 0x3cf);   /* unlock PR0-4 */
 280         outb(0x0b, 0x3ce); config = inb(0x3cf); /* read PR1 */
 281         if ((config & 0xc0) != 0xc0) {
 282                 printk("AlphaBook1 VGA init: setting 1Mb memory\n");
 283                 config |= 0xc0;
 284                 outb(0x0b, 0x3ce); outb(config, 0x3cf); /* write PR1 */
 285         }
 286         outb(0x0f, 0x3ce); outb(orig, 0x3cf); /* (re)lock PR0-4 */
 287 }
 288
 289 void
 290 sio_kill_arch(int mode)
 291 {
 292 #if defined(ALPHA_RESTORE_SRM_SETUP)
 293         /* Since we cannot read the PCI DMA Window CSRs, we
 294          * cannot restore them here.
 295          *
 296          * However, we CAN read the PIRQ route register, so restore it
 297          * now...
 298          */
 299         pci_bus_write_config_dword(pci_isa_hose->bus, PCI_DEVFN(7, 0), 0x60,
 300                                    saved_config.orig_route_tab);
 301 #endif
 302 }
 303
 304
 305 /*
 306  * The System Vectors
 307  */
 308
 309 #if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_BOOK1)
 310 struct alpha_machine_vector alphabook1_mv __initmv = {
 311         .vector_name            = "AlphaBook1",
 312         DO_EV4_MMU,
 313         DO_DEFAULT_RTC,
 314         DO_LCA_IO,
 315         .machine_check          = lca_machine_check,
 316         .max_isa_dma_address    = ALPHA_MAX_ISA_DMA_ADDRESS,
 317         .min_io_address         = DEFAULT_IO_BASE,
 318         .min_mem_address        = APECS_AND_LCA_DEFAULT_MEM_BASE,
 319
 320         .nr_irqs                = 16,
 321         .device_interrupt       = isa_device_interrupt,
 322
 323         .init_arch              = alphabook1_init_arch,
 324         .init_irq               = sio_init_irq,
 325         .init_rtc               = common_init_rtc,
 326         .init_pci               = alphabook1_init_pci,
 327         .kill_arch              = sio_kill_arch,
 328         .pci_map_irq            = noname_map_irq,
 329         .pci_swizzle            = common_swizzle,
 330
 331         .sys = { .sio = {
 332                 /* NCR810 SCSI is 14, PCMCIA controller is 15.  */
 333                 .route_tab      = 0x0e0f0a0a,
 334         }}
 335 };
 336 ALIAS_MV(alphabook1)
 337 #endif
 338
 339 #if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_AVANTI)
 340 struct alpha_machine_vector avanti_mv __initmv = {
 341         .vector_name            = "Avanti",
 342         DO_EV4_MMU,
 343         DO_DEFAULT_RTC,
 344         DO_APECS_IO,
 345         .machine_check          = apecs_machine_check,
 346         .max_isa_dma_address    = ALPHA_MAX_ISA_DMA_ADDRESS,
 347         .min_io_address         = DEFAULT_IO_BASE,
 348         .min_mem_address        = APECS_AND_LCA_DEFAULT_MEM_BASE,
 349
 350         .nr_irqs                = 16,
 351         .device_interrupt       = isa_device_interrupt,
 352
 353         .init_arch              = apecs_init_arch,
 354         .init_irq               = sio_init_irq,
 355         .init_rtc               = common_init_rtc,
 356         .init_pci               = noname_init_pci,
 357         .kill_arch              = sio_kill_arch,
 358         .pci_map_irq            = noname_map_irq,
 359         .pci_swizzle            = common_swizzle,
 360
 361         .sys = { .sio = {
 362                 .route_tab      = 0x0b0a050f, /* leave 14 for IDE, 9 for SND */
 363         }}
 364 };
 365 ALIAS_MV(avanti)
 366 #endif
 367
 368 #if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_NONAME)
 369 struct alpha_machine_vector noname_mv __initmv = {
 370         .vector_name            = "Noname",
 371         DO_EV4_MMU,
 372         DO_DEFAULT_RTC,
 373         DO_LCA_IO,
 374         .machine_check          = lca_machine_check,
 375         .max_isa_dma_address    = ALPHA_MAX_ISA_DMA_ADDRESS,
 376         .min_io_address         = DEFAULT_IO_BASE,
 377         .min_mem_address        = APECS_AND_LCA_DEFAULT_MEM_BASE,
 378
 379         .nr_irqs                = 16,
 380         .device_interrupt       = srm_device_interrupt,
 381
 382         .init_arch              = lca_init_arch,
 383         .init_irq               = sio_init_irq,
 384         .init_rtc               = common_init_rtc,
 385         .init_pci               = noname_init_pci,
 386         .kill_arch              = sio_kill_arch,
 387         .pci_map_irq            = noname_map_irq,
 388         .pci_swizzle            = common_swizzle,
 389
 390         .sys = { .sio = {
 391                 /* For UDB, the only available PCI slot must not map to IRQ 9,
 392                    since that's the builtin MSS sound chip. That PCI slot
 393                    will map to PIRQ1 (for INTA at least), so we give it IRQ 15
 394                    instead.
 395
 396                    Unfortunately we have to do this for NONAME as well, since
 397                    they are co-indicated when the platform type "Noname" is
 398                    selected... :-(  */
 399
 400                 .route_tab      = 0x0b0a0f0d,
 401         }}
 402 };
 403 ALIAS_MV(noname)
 404 #endif
 405
 406 #if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_P2K)
 407 struct alpha_machine_vector p2k_mv __initmv = {
 408         .vector_name            = "Platform2000",
 409         DO_EV4_MMU,
 410         DO_DEFAULT_RTC,
 411         DO_LCA_IO,
 412         .machine_check          = lca_machine_check,
 413         .max_isa_dma_address    = ALPHA_MAX_ISA_DMA_ADDRESS,
 414         .min_io_address         = DEFAULT_IO_BASE,
 415         .min_mem_address        = APECS_AND_LCA_DEFAULT_MEM_BASE,
 416
 417         .nr_irqs                = 16,
 418         .device_interrupt       = srm_device_interrupt,
 419
 420         .init_arch              = lca_init_arch,
 421         .init_irq               = sio_init_irq,
 422         .init_rtc               = common_init_rtc,
 423         .init_pci               = noname_init_pci,
 424         .kill_arch              = sio_kill_arch,
 425         .pci_map_irq            = p2k_map_irq,
 426         .pci_swizzle            = common_swizzle,
 427
 428         .sys = { .sio = {
 429                 .route_tab      = 0x0b0a090f,
 430         }}
 431 };
 432 ALIAS_MV(p2k)
 433 #endif
 434
 435 #if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_XL)
 436 struct alpha_machine_vector xl_mv __initmv = {
 437         .vector_name            = "XL",
 438         DO_EV4_MMU,
 439         DO_DEFAULT_RTC,
 440         DO_APECS_IO,
 441         .machine_check          = apecs_machine_check,
 442         .max_isa_dma_address    = ALPHA_XL_MAX_ISA_DMA_ADDRESS,
 443         .min_io_address         = DEFAULT_IO_BASE,
 444         .min_mem_address        = XL_DEFAULT_MEM_BASE,
 445
 446         .nr_irqs                = 16,
 447         .device_interrupt       = isa_device_interrupt,
 448
 449         .init_arch              = apecs_init_arch,
 450         .init_irq               = sio_init_irq,
 451         .init_rtc               = common_init_rtc,
 452         .init_pci               = noname_init_pci,
 453         .kill_arch              = sio_kill_arch,
 454         .pci_map_irq            = noname_map_irq,
 455         .pci_swizzle            = common_swizzle,
 456
 457         .sys = { .sio = {
 458                 .route_tab      = 0x0b0a090f,
 459         }}
 460 };
 461 ALIAS_MV(xl)
 462 #endif