2 * ata_piix.c - Intel PATA/SATA controllers
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
9 * Copyright 2003-2005 Red Hat Inc
10 * Copyright 2003-2005 Jeff Garzik
13 * Copyright header from piix.c:
15 * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
16 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
17 * Copyright (C) 2003 Red Hat Inc <alan@redhat.com>
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2, or (at your option)
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
30 * You should have received a copy of the GNU General Public License
31 * along with this program; see the file COPYING. If not, write to
32 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
35 * libata documentation is available via 'make {ps|pdf}docs',
36 * as Documentation/DocBook/libata.*
38 * Hardware documentation available at http://developer.intel.com/
41 * Publically available from Intel web site. Errata documentation
42 * is also publically available. As an aide to anyone hacking on this
43 * driver the list of errata that are relevant is below, going back to
44 * PIIX4. Older device documentation is now a bit tricky to find.
46 * The chipsets all follow very much the same design. The orginal Triton
47 * series chipsets do _not_ support independant device timings, but this
48 * is fixed in Triton II. With the odd mobile exception the chips then
49 * change little except in gaining more modes until SATA arrives. This
50 * driver supports only the chips with independant timing (that is those
51 * with SITRE and the 0x44 timing register). See pata_oldpiix and pata_mpiix
52 * for the early chip drivers.
57 * PIIX4 errata #9 - Only on ultra obscure hw
58 * ICH3 errata #13 - Not observed to affect real hw
61 * Things we must deal with
62 * PIIX4 errata #10 - BM IDE hang with non UDMA
63 * (must stop/start dma to recover)
64 * 440MX errata #15 - As PIIX4 errata #10
65 * PIIX4 errata #15 - Must not read control registers
66 * during a PIO transfer
67 * 440MX errata #13 - As PIIX4 errata #15
68 * ICH2 errata #21 - DMA mode 0 doesn't work right
69 * ICH0/1 errata #55 - As ICH2 errata #21
70 * ICH2 spec c #9 - Extra operations needed to handle
71 * drive hotswap [NOT YET SUPPORTED]
72 * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary
73 * and must be dword aligned
74 * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3
76 * Should have been BIOS fixed:
77 * 450NX: errata #19 - DMA hangs on old 450NX
78 * 450NX: errata #20 - DMA hangs on old 450NX
79 * 450NX: errata #25 - Corruption with DMA on old 450NX
80 * ICH3 errata #15 - IDE deadlock under high load
81 * (BIOS must set dev 31 fn 0 bit 23)
82 * ICH3 errata #18 - Don't use native mode
85 #include <linux/kernel.h>
86 #include <linux/module.h>
87 #include <linux/pci.h>
88 #include <linux/init.h>
89 #include <linux/blkdev.h>
90 #include <linux/delay.h>
91 #include <linux/device.h>
92 #include <scsi/scsi_host.h>
93 #include <linux/libata.h>
94 #include <linux/dmi.h>
96 #define DRV_NAME "ata_piix"
97 #define DRV_VERSION "2.12"
100 PIIX_IOCFG
= 0x54, /* IDE I/O configuration register */
101 ICH5_PMR
= 0x90, /* port mapping register */
102 ICH5_PCS
= 0x92, /* port control and status */
103 PIIX_SCC
= 0x0A, /* sub-class code register */
105 PIIX_FLAG_SCR
= (1 << 26), /* SCR available */
106 PIIX_FLAG_AHCI
= (1 << 27), /* AHCI possible */
107 PIIX_FLAG_CHECKINTR
= (1 << 28), /* make sure PCI INTx enabled */
109 PIIX_PATA_FLAGS
= ATA_FLAG_SLAVE_POSS
,
110 PIIX_SATA_FLAGS
= ATA_FLAG_SATA
| PIIX_FLAG_CHECKINTR
,
112 /* combined mode. if set, PATA is channel 0.
113 * if clear, PATA is channel 1.
115 PIIX_PORT_ENABLED
= (1 << 0),
116 PIIX_PORT_PRESENT
= (1 << 4),
118 PIIX_80C_PRI
= (1 << 5) | (1 << 4),
119 PIIX_80C_SEC
= (1 << 7) | (1 << 6),
122 piix_pata_mwdma
= 0, /* PIIX3 MWDMA only */
123 piix_pata_33
, /* PIIX4 at 33Mhz */
124 ich_pata_33
, /* ICH up to UDMA 33 only */
125 ich_pata_66
, /* ICH up to 66 Mhz */
126 ich_pata_100
, /* ICH up to UDMA 100 */
133 ich8m_apple_sata_ahci
, /* locks up on second port enable */
136 /* constants for mapping table */
142 NA
= -2, /* not avaliable */
143 RV
= -3, /* reserved */
145 PIIX_AHCI_DEVICE
= 6,
147 /* host->flags bits */
148 PIIX_HOST_BROKEN_SUSPEND
= (1 << 24),
153 const u16 port_enable
;
157 struct piix_host_priv
{
161 static int piix_init_one(struct pci_dev
*pdev
,
162 const struct pci_device_id
*ent
);
163 static void piix_pata_error_handler(struct ata_port
*ap
);
164 static void piix_set_piomode(struct ata_port
*ap
, struct ata_device
*adev
);
165 static void piix_set_dmamode(struct ata_port
*ap
, struct ata_device
*adev
);
166 static void ich_set_dmamode(struct ata_port
*ap
, struct ata_device
*adev
);
167 static int ich_pata_cable_detect(struct ata_port
*ap
);
169 static int piix_pci_device_suspend(struct pci_dev
*pdev
, pm_message_t mesg
);
170 static int piix_pci_device_resume(struct pci_dev
*pdev
);
173 static unsigned int in_module_init
= 1;
175 static const struct pci_device_id piix_pci_tbl
[] = {
176 /* Intel PIIX3 for the 430HX etc */
177 { 0x8086, 0x7010, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, piix_pata_mwdma
},
178 /* Intel PIIX4 for the 430TX/440BX/MX chipset: UDMA 33 */
179 /* Also PIIX4E (fn3 rev 2) and PIIX4M (fn3 rev 3) */
180 { 0x8086, 0x7111, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, piix_pata_33
},
182 { 0x8086, 0x7199, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, piix_pata_33
},
184 { 0x8086, 0x7601, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, piix_pata_33
},
186 { 0x8086, 0x84CA, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, piix_pata_33
},
187 /* Intel ICH (i810, i815, i840) UDMA 66*/
188 { 0x8086, 0x2411, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich_pata_66
},
189 /* Intel ICH0 : UDMA 33*/
190 { 0x8086, 0x2421, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich_pata_33
},
192 { 0x8086, 0x244A, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich_pata_100
},
193 /* Intel ICH2 (i810E2, i845, 850, 860) UDMA 100 */
194 { 0x8086, 0x244B, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich_pata_100
},
196 { 0x8086, 0x248A, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich_pata_100
},
197 /* Intel ICH3 (E7500/1) UDMA 100 */
198 { 0x8086, 0x248B, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich_pata_100
},
199 /* Intel ICH4 (i845GV, i845E, i852, i855) UDMA 100 */
200 { 0x8086, 0x24CA, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich_pata_100
},
201 { 0x8086, 0x24CB, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich_pata_100
},
203 { 0x8086, 0x24DB, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich_pata_100
},
205 { 0x8086, 0x245B, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich_pata_100
},
206 /* ESB (855GME/875P + 6300ESB) UDMA 100 */
207 { 0x8086, 0x25A2, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich_pata_100
},
208 /* ICH6 (and 6) (i915) UDMA 100 */
209 { 0x8086, 0x266F, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich_pata_100
},
210 /* ICH7/7-R (i945, i975) UDMA 100*/
211 { 0x8086, 0x27DF, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich_pata_100
},
212 { 0x8086, 0x269E, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich_pata_100
},
213 /* ICH8 Mobile PATA Controller */
214 { 0x8086, 0x2850, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich_pata_100
},
216 /* NOTE: The following PCI ids must be kept in sync with the
217 * list in drivers/pci/quirks.c.
221 { 0x8086, 0x24d1, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich5_sata
},
223 { 0x8086, 0x24df, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich5_sata
},
224 /* 6300ESB (ICH5 variant with broken PCS present bits) */
225 { 0x8086, 0x25a3, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich5_sata
},
226 /* 6300ESB pretending RAID */
227 { 0x8086, 0x25b0, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich5_sata
},
228 /* 82801FB/FW (ICH6/ICH6W) */
229 { 0x8086, 0x2651, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich6_sata
},
230 /* 82801FR/FRW (ICH6R/ICH6RW) */
231 { 0x8086, 0x2652, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich6_sata_ahci
},
232 /* 82801FBM ICH6M (ICH6R with only port 0 and 2 implemented) */
233 { 0x8086, 0x2653, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich6m_sata_ahci
},
234 /* 82801GB/GR/GH (ICH7, identical to ICH6) */
235 { 0x8086, 0x27c0, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich6_sata_ahci
},
236 /* 2801GBM/GHM (ICH7M, identical to ICH6M) */
237 { 0x8086, 0x27c4, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich6m_sata_ahci
},
238 /* Enterprise Southbridge 2 (631xESB/632xESB) */
239 { 0x8086, 0x2680, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich6_sata_ahci
},
240 /* SATA Controller 1 IDE (ICH8) */
241 { 0x8086, 0x2820, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich8_sata_ahci
},
242 /* SATA Controller 2 IDE (ICH8) */
243 { 0x8086, 0x2825, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich8_2port_sata
},
244 /* Mobile SATA Controller IDE (ICH8M) */
245 { 0x8086, 0x2828, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich8_sata_ahci
},
246 /* Mobile SATA Controller IDE (ICH8M), Apple */
247 { 0x8086, 0x2828, 0x106b, 0x00a0, 0, 0, ich8m_apple_sata_ahci
},
248 /* SATA Controller IDE (ICH9) */
249 { 0x8086, 0x2920, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich8_sata_ahci
},
250 /* SATA Controller IDE (ICH9) */
251 { 0x8086, 0x2921, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich8_2port_sata
},
252 /* SATA Controller IDE (ICH9) */
253 { 0x8086, 0x2926, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich8_2port_sata
},
254 /* SATA Controller IDE (ICH9M) */
255 { 0x8086, 0x2928, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich8_2port_sata
},
256 /* SATA Controller IDE (ICH9M) */
257 { 0x8086, 0x292d, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich8_2port_sata
},
258 /* SATA Controller IDE (ICH9M) */
259 { 0x8086, 0x292e, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich8_sata_ahci
},
260 /* SATA Controller IDE (Tolapai) */
261 { 0x8086, 0x5028, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, tolapai_sata_ahci
},
263 { } /* terminate list */
266 static struct pci_driver piix_pci_driver
= {
268 .id_table
= piix_pci_tbl
,
269 .probe
= piix_init_one
,
270 .remove
= ata_pci_remove_one
,
272 .suspend
= piix_pci_device_suspend
,
273 .resume
= piix_pci_device_resume
,
277 static struct scsi_host_template piix_sht
= {
278 .module
= THIS_MODULE
,
280 .ioctl
= ata_scsi_ioctl
,
281 .queuecommand
= ata_scsi_queuecmd
,
282 .can_queue
= ATA_DEF_QUEUE
,
283 .this_id
= ATA_SHT_THIS_ID
,
284 .sg_tablesize
= LIBATA_MAX_PRD
,
285 .cmd_per_lun
= ATA_SHT_CMD_PER_LUN
,
286 .emulated
= ATA_SHT_EMULATED
,
287 .use_clustering
= ATA_SHT_USE_CLUSTERING
,
288 .proc_name
= DRV_NAME
,
289 .dma_boundary
= ATA_DMA_BOUNDARY
,
290 .slave_configure
= ata_scsi_slave_config
,
291 .slave_destroy
= ata_scsi_slave_destroy
,
292 .bios_param
= ata_std_bios_param
,
295 static const struct ata_port_operations piix_pata_ops
= {
296 .set_piomode
= piix_set_piomode
,
297 .set_dmamode
= piix_set_dmamode
,
298 .mode_filter
= ata_pci_default_filter
,
300 .tf_load
= ata_tf_load
,
301 .tf_read
= ata_tf_read
,
302 .check_status
= ata_check_status
,
303 .exec_command
= ata_exec_command
,
304 .dev_select
= ata_std_dev_select
,
306 .bmdma_setup
= ata_bmdma_setup
,
307 .bmdma_start
= ata_bmdma_start
,
308 .bmdma_stop
= ata_bmdma_stop
,
309 .bmdma_status
= ata_bmdma_status
,
310 .qc_prep
= ata_qc_prep
,
311 .qc_issue
= ata_qc_issue_prot
,
312 .data_xfer
= ata_data_xfer
,
314 .freeze
= ata_bmdma_freeze
,
315 .thaw
= ata_bmdma_thaw
,
316 .error_handler
= piix_pata_error_handler
,
317 .post_internal_cmd
= ata_bmdma_post_internal_cmd
,
318 .cable_detect
= ata_cable_40wire
,
320 .irq_handler
= ata_interrupt
,
321 .irq_clear
= ata_bmdma_irq_clear
,
322 .irq_on
= ata_irq_on
,
324 .port_start
= ata_port_start
,
327 static const struct ata_port_operations ich_pata_ops
= {
328 .set_piomode
= piix_set_piomode
,
329 .set_dmamode
= ich_set_dmamode
,
330 .mode_filter
= ata_pci_default_filter
,
332 .tf_load
= ata_tf_load
,
333 .tf_read
= ata_tf_read
,
334 .check_status
= ata_check_status
,
335 .exec_command
= ata_exec_command
,
336 .dev_select
= ata_std_dev_select
,
338 .bmdma_setup
= ata_bmdma_setup
,
339 .bmdma_start
= ata_bmdma_start
,
340 .bmdma_stop
= ata_bmdma_stop
,
341 .bmdma_status
= ata_bmdma_status
,
342 .qc_prep
= ata_qc_prep
,
343 .qc_issue
= ata_qc_issue_prot
,
344 .data_xfer
= ata_data_xfer
,
346 .freeze
= ata_bmdma_freeze
,
347 .thaw
= ata_bmdma_thaw
,
348 .error_handler
= piix_pata_error_handler
,
349 .post_internal_cmd
= ata_bmdma_post_internal_cmd
,
350 .cable_detect
= ich_pata_cable_detect
,
352 .irq_handler
= ata_interrupt
,
353 .irq_clear
= ata_bmdma_irq_clear
,
354 .irq_on
= ata_irq_on
,
356 .port_start
= ata_port_start
,
359 static const struct ata_port_operations piix_sata_ops
= {
360 .tf_load
= ata_tf_load
,
361 .tf_read
= ata_tf_read
,
362 .check_status
= ata_check_status
,
363 .exec_command
= ata_exec_command
,
364 .dev_select
= ata_std_dev_select
,
366 .bmdma_setup
= ata_bmdma_setup
,
367 .bmdma_start
= ata_bmdma_start
,
368 .bmdma_stop
= ata_bmdma_stop
,
369 .bmdma_status
= ata_bmdma_status
,
370 .qc_prep
= ata_qc_prep
,
371 .qc_issue
= ata_qc_issue_prot
,
372 .data_xfer
= ata_data_xfer
,
374 .freeze
= ata_bmdma_freeze
,
375 .thaw
= ata_bmdma_thaw
,
376 .error_handler
= ata_bmdma_error_handler
,
377 .post_internal_cmd
= ata_bmdma_post_internal_cmd
,
379 .irq_handler
= ata_interrupt
,
380 .irq_clear
= ata_bmdma_irq_clear
,
381 .irq_on
= ata_irq_on
,
383 .port_start
= ata_port_start
,
386 static const struct piix_map_db ich5_map_db
= {
390 /* PM PS SM SS MAP */
391 { P0
, NA
, P1
, NA
}, /* 000b */
392 { P1
, NA
, P0
, NA
}, /* 001b */
395 { P0
, P1
, IDE
, IDE
}, /* 100b */
396 { P1
, P0
, IDE
, IDE
}, /* 101b */
397 { IDE
, IDE
, P0
, P1
}, /* 110b */
398 { IDE
, IDE
, P1
, P0
}, /* 111b */
402 static const struct piix_map_db ich6_map_db
= {
406 /* PM PS SM SS MAP */
407 { P0
, P2
, P1
, P3
}, /* 00b */
408 { IDE
, IDE
, P1
, P3
}, /* 01b */
409 { P0
, P2
, IDE
, IDE
}, /* 10b */
414 static const struct piix_map_db ich6m_map_db
= {
418 /* Map 01b isn't specified in the doc but some notebooks use
419 * it anyway. MAP 01b have been spotted on both ICH6M and
423 /* PM PS SM SS MAP */
424 { P0
, P2
, NA
, NA
}, /* 00b */
425 { IDE
, IDE
, P1
, P3
}, /* 01b */
426 { P0
, P2
, IDE
, IDE
}, /* 10b */
431 static const struct piix_map_db ich8_map_db
= {
435 /* PM PS SM SS MAP */
436 { P0
, P2
, P1
, P3
}, /* 00b (hardwired when in AHCI) */
438 { P0
, P2
, IDE
, IDE
}, /* 10b (IDE mode) */
443 static const struct piix_map_db ich8_2port_map_db
= {
447 /* PM PS SM SS MAP */
448 { P0
, NA
, P1
, NA
}, /* 00b */
449 { RV
, RV
, RV
, RV
}, /* 01b */
450 { RV
, RV
, RV
, RV
}, /* 10b */
455 static const struct piix_map_db ich8m_apple_map_db
= {
459 /* PM PS SM SS MAP */
460 { P0
, NA
, NA
, NA
}, /* 00b */
462 { P0
, P2
, IDE
, IDE
}, /* 10b */
467 static const struct piix_map_db tolapai_map_db
= {
471 /* PM PS SM SS MAP */
472 { P0
, NA
, P1
, NA
}, /* 00b */
473 { RV
, RV
, RV
, RV
}, /* 01b */
474 { RV
, RV
, RV
, RV
}, /* 10b */
479 static const struct piix_map_db
*piix_map_db_table
[] = {
480 [ich5_sata
] = &ich5_map_db
,
481 [ich6_sata
] = &ich6_map_db
,
482 [ich6_sata_ahci
] = &ich6_map_db
,
483 [ich6m_sata_ahci
] = &ich6m_map_db
,
484 [ich8_sata_ahci
] = &ich8_map_db
,
485 [ich8_2port_sata
] = &ich8_2port_map_db
,
486 [ich8m_apple_sata_ahci
] = &ich8m_apple_map_db
,
487 [tolapai_sata_ahci
] = &tolapai_map_db
,
490 static struct ata_port_info piix_port_info
[] = {
491 [piix_pata_mwdma
] = /* PIIX3 MWDMA only */
494 .flags
= PIIX_PATA_FLAGS
,
495 .pio_mask
= 0x1f, /* pio0-4 */
496 .mwdma_mask
= 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
497 .port_ops
= &piix_pata_ops
,
500 [piix_pata_33
] = /* PIIX4 at 33MHz */
503 .flags
= PIIX_PATA_FLAGS
,
504 .pio_mask
= 0x1f, /* pio0-4 */
505 .mwdma_mask
= 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
506 .udma_mask
= ATA_UDMA_MASK_40C
,
507 .port_ops
= &piix_pata_ops
,
510 [ich_pata_33
] = /* ICH0 - ICH at 33Mhz*/
513 .flags
= PIIX_PATA_FLAGS
,
514 .pio_mask
= 0x1f, /* pio 0-4 */
515 .mwdma_mask
= 0x06, /* Check: maybe 0x07 */
516 .udma_mask
= ATA_UDMA2
, /* UDMA33 */
517 .port_ops
= &ich_pata_ops
,
520 [ich_pata_66
] = /* ICH controllers up to 66MHz */
523 .flags
= PIIX_PATA_FLAGS
,
524 .pio_mask
= 0x1f, /* pio 0-4 */
525 .mwdma_mask
= 0x06, /* MWDMA0 is broken on chip */
526 .udma_mask
= ATA_UDMA4
,
527 .port_ops
= &ich_pata_ops
,
533 .flags
= PIIX_PATA_FLAGS
| PIIX_FLAG_CHECKINTR
,
534 .pio_mask
= 0x1f, /* pio0-4 */
535 .mwdma_mask
= 0x06, /* mwdma1-2 */
536 .udma_mask
= ATA_UDMA5
, /* udma0-5 */
537 .port_ops
= &ich_pata_ops
,
543 .flags
= PIIX_SATA_FLAGS
,
544 .pio_mask
= 0x1f, /* pio0-4 */
545 .mwdma_mask
= 0x07, /* mwdma0-2 */
546 .udma_mask
= ATA_UDMA6
,
547 .port_ops
= &piix_sata_ops
,
553 .flags
= PIIX_SATA_FLAGS
| PIIX_FLAG_SCR
,
554 .pio_mask
= 0x1f, /* pio0-4 */
555 .mwdma_mask
= 0x07, /* mwdma0-2 */
556 .udma_mask
= ATA_UDMA6
,
557 .port_ops
= &piix_sata_ops
,
563 .flags
= PIIX_SATA_FLAGS
| PIIX_FLAG_SCR
|
565 .pio_mask
= 0x1f, /* pio0-4 */
566 .mwdma_mask
= 0x07, /* mwdma0-2 */
567 .udma_mask
= ATA_UDMA6
,
568 .port_ops
= &piix_sata_ops
,
574 .flags
= PIIX_SATA_FLAGS
| PIIX_FLAG_SCR
|
576 .pio_mask
= 0x1f, /* pio0-4 */
577 .mwdma_mask
= 0x07, /* mwdma0-2 */
578 .udma_mask
= ATA_UDMA6
,
579 .port_ops
= &piix_sata_ops
,
585 .flags
= PIIX_SATA_FLAGS
| PIIX_FLAG_SCR
|
587 .pio_mask
= 0x1f, /* pio0-4 */
588 .mwdma_mask
= 0x07, /* mwdma0-2 */
589 .udma_mask
= ATA_UDMA6
,
590 .port_ops
= &piix_sata_ops
,
596 .flags
= PIIX_SATA_FLAGS
| PIIX_FLAG_SCR
|
598 .pio_mask
= 0x1f, /* pio0-4 */
599 .mwdma_mask
= 0x07, /* mwdma0-2 */
600 .udma_mask
= ATA_UDMA6
,
601 .port_ops
= &piix_sata_ops
,
604 [tolapai_sata_ahci
] =
607 .flags
= PIIX_SATA_FLAGS
| PIIX_FLAG_SCR
|
609 .pio_mask
= 0x1f, /* pio0-4 */
610 .mwdma_mask
= 0x07, /* mwdma0-2 */
611 .udma_mask
= ATA_UDMA6
,
612 .port_ops
= &piix_sata_ops
,
615 [ich8m_apple_sata_ahci
] =
618 .flags
= PIIX_SATA_FLAGS
| PIIX_FLAG_SCR
|
620 .pio_mask
= 0x1f, /* pio0-4 */
621 .mwdma_mask
= 0x07, /* mwdma0-2 */
622 .udma_mask
= ATA_UDMA6
,
623 .port_ops
= &piix_sata_ops
,
628 static struct pci_bits piix_enable_bits
[] = {
629 { 0x41U
, 1U, 0x80UL
, 0x80UL
}, /* port 0 */
630 { 0x43U
, 1U, 0x80UL
, 0x80UL
}, /* port 1 */
633 MODULE_AUTHOR("Andre Hedrick, Alan Cox, Andrzej Krzysztofowicz, Jeff Garzik");
634 MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers");
635 MODULE_LICENSE("GPL");
636 MODULE_DEVICE_TABLE(pci
, piix_pci_tbl
);
637 MODULE_VERSION(DRV_VERSION
);
646 * List of laptops that use short cables rather than 80 wire
649 static const struct ich_laptop ich_laptop
[] = {
650 /* devid, subvendor, subdev */
651 { 0x27DF, 0x0005, 0x0280 }, /* ICH7 on Acer 5602WLMi */
652 { 0x27DF, 0x1025, 0x0102 }, /* ICH7 on Acer 5602aWLMi */
653 { 0x27DF, 0x1025, 0x0110 }, /* ICH7 on Acer 3682WLMi */
654 { 0x27DF, 0x1043, 0x1267 }, /* ICH7 on Asus W5F */
655 { 0x27DF, 0x103C, 0x30A1 }, /* ICH7 on HP Compaq nc2400 */
656 { 0x24CA, 0x1025, 0x0061 }, /* ICH4 on ACER Aspire 2023WLMi */
662 * ich_pata_cable_detect - Probe host controller cable detect info
663 * @ap: Port for which cable detect info is desired
665 * Read 80c cable indicator from ATA PCI device's PCI config
666 * register. This register is normally set by firmware (BIOS).
669 * None (inherited from caller).
672 static int ich_pata_cable_detect(struct ata_port
*ap
)
674 struct pci_dev
*pdev
= to_pci_dev(ap
->host
->dev
);
675 const struct ich_laptop
*lap
= &ich_laptop
[0];
678 /* Check for specials - Acer Aspire 5602WLMi */
679 while (lap
->device
) {
680 if (lap
->device
== pdev
->device
&&
681 lap
->subvendor
== pdev
->subsystem_vendor
&&
682 lap
->subdevice
== pdev
->subsystem_device
)
683 return ATA_CBL_PATA40_SHORT
;
688 /* check BIOS cable detect results */
689 mask
= ap
->port_no
== 0 ? PIIX_80C_PRI
: PIIX_80C_SEC
;
690 pci_read_config_byte(pdev
, PIIX_IOCFG
, &tmp
);
691 if ((tmp
& mask
) == 0)
692 return ATA_CBL_PATA40
;
693 return ATA_CBL_PATA80
;
697 * piix_pata_prereset - prereset for PATA host controller
699 * @deadline: deadline jiffies for the operation
702 * None (inherited from caller).
704 static int piix_pata_prereset(struct ata_link
*link
, unsigned long deadline
)
706 struct ata_port
*ap
= link
->ap
;
707 struct pci_dev
*pdev
= to_pci_dev(ap
->host
->dev
);
709 if (!pci_test_config_bits(pdev
, &piix_enable_bits
[ap
->port_no
]))
711 return ata_std_prereset(link
, deadline
);
714 static void piix_pata_error_handler(struct ata_port
*ap
)
716 ata_bmdma_drive_eh(ap
, piix_pata_prereset
, ata_std_softreset
, NULL
,
721 * piix_set_piomode - Initialize host controller PATA PIO timings
722 * @ap: Port whose timings we are configuring
725 * Set PIO mode for device, in host controller PCI config space.
728 * None (inherited from caller).
731 static void piix_set_piomode(struct ata_port
*ap
, struct ata_device
*adev
)
733 unsigned int pio
= adev
->pio_mode
- XFER_PIO_0
;
734 struct pci_dev
*dev
= to_pci_dev(ap
->host
->dev
);
735 unsigned int is_slave
= (adev
->devno
!= 0);
736 unsigned int master_port
= ap
->port_no
? 0x42 : 0x40;
737 unsigned int slave_port
= 0x44;
744 * See Intel Document 298600-004 for the timing programing rules
745 * for ICH controllers.
748 static const /* ISP RTC */
749 u8 timings
[][2] = { { 0, 0 },
756 control
|= 1; /* TIME1 enable */
757 if (ata_pio_need_iordy(adev
))
758 control
|= 2; /* IE enable */
760 /* Intel specifies that the PPE functionality is for disk only */
761 if (adev
->class == ATA_DEV_ATA
)
762 control
|= 4; /* PPE enable */
764 /* PIO configuration clears DTE unconditionally. It will be
765 * programmed in set_dmamode which is guaranteed to be called
766 * after set_piomode if any DMA mode is available.
768 pci_read_config_word(dev
, master_port
, &master_data
);
770 /* clear TIME1|IE1|PPE1|DTE1 */
771 master_data
&= 0xff0f;
772 /* Enable SITRE (seperate slave timing register) */
773 master_data
|= 0x4000;
774 /* enable PPE1, IE1 and TIME1 as needed */
775 master_data
|= (control
<< 4);
776 pci_read_config_byte(dev
, slave_port
, &slave_data
);
777 slave_data
&= (ap
->port_no
? 0x0f : 0xf0);
778 /* Load the timing nibble for this slave */
779 slave_data
|= ((timings
[pio
][0] << 2) | timings
[pio
][1])
780 << (ap
->port_no
? 4 : 0);
782 /* clear ISP|RCT|TIME0|IE0|PPE0|DTE0 */
783 master_data
&= 0xccf0;
784 /* Enable PPE, IE and TIME as appropriate */
785 master_data
|= control
;
786 /* load ISP and RCT */
788 (timings
[pio
][0] << 12) |
789 (timings
[pio
][1] << 8);
791 pci_write_config_word(dev
, master_port
, master_data
);
793 pci_write_config_byte(dev
, slave_port
, slave_data
);
795 /* Ensure the UDMA bit is off - it will be turned back on if
799 pci_read_config_byte(dev
, 0x48, &udma_enable
);
800 udma_enable
&= ~(1 << (2 * ap
->port_no
+ adev
->devno
));
801 pci_write_config_byte(dev
, 0x48, udma_enable
);
806 * do_pata_set_dmamode - Initialize host controller PATA PIO timings
807 * @ap: Port whose timings we are configuring
808 * @adev: Drive in question
809 * @udma: udma mode, 0 - 6
810 * @isich: set if the chip is an ICH device
812 * Set UDMA mode for device, in host controller PCI config space.
815 * None (inherited from caller).
818 static void do_pata_set_dmamode(struct ata_port
*ap
, struct ata_device
*adev
, int isich
)
820 struct pci_dev
*dev
= to_pci_dev(ap
->host
->dev
);
821 u8 master_port
= ap
->port_no
? 0x42 : 0x40;
823 u8 speed
= adev
->dma_mode
;
824 int devid
= adev
->devno
+ 2 * ap
->port_no
;
827 static const /* ISP RTC */
828 u8 timings
[][2] = { { 0, 0 },
834 pci_read_config_word(dev
, master_port
, &master_data
);
836 pci_read_config_byte(dev
, 0x48, &udma_enable
);
838 if (speed
>= XFER_UDMA_0
) {
839 unsigned int udma
= adev
->dma_mode
- XFER_UDMA_0
;
842 int u_clock
, u_speed
;
845 * UDMA is handled by a combination of clock switching and
846 * selection of dividers
848 * Handy rule: Odd modes are UDMATIMx 01, even are 02
849 * except UDMA0 which is 00
851 u_speed
= min(2 - (udma
& 1), udma
);
853 u_clock
= 0x1000; /* 100Mhz */
855 u_clock
= 1; /* 66Mhz */
857 u_clock
= 0; /* 33Mhz */
859 udma_enable
|= (1 << devid
);
861 /* Load the CT/RP selection */
862 pci_read_config_word(dev
, 0x4A, &udma_timing
);
863 udma_timing
&= ~(3 << (4 * devid
));
864 udma_timing
|= u_speed
<< (4 * devid
);
865 pci_write_config_word(dev
, 0x4A, udma_timing
);
868 /* Select a 33/66/100Mhz clock */
869 pci_read_config_word(dev
, 0x54, &ideconf
);
870 ideconf
&= ~(0x1001 << devid
);
871 ideconf
|= u_clock
<< devid
;
872 /* For ICH or later we should set bit 10 for better
873 performance (WR_PingPong_En) */
874 pci_write_config_word(dev
, 0x54, ideconf
);
878 * MWDMA is driven by the PIO timings. We must also enable
879 * IORDY unconditionally along with TIME1. PPE has already
880 * been set when the PIO timing was set.
882 unsigned int mwdma
= adev
->dma_mode
- XFER_MW_DMA_0
;
883 unsigned int control
;
885 const unsigned int needed_pio
[3] = {
886 XFER_PIO_0
, XFER_PIO_3
, XFER_PIO_4
888 int pio
= needed_pio
[mwdma
] - XFER_PIO_0
;
890 control
= 3; /* IORDY|TIME1 */
892 /* If the drive MWDMA is faster than it can do PIO then
893 we must force PIO into PIO0 */
895 if (adev
->pio_mode
< needed_pio
[mwdma
])
896 /* Enable DMA timing only */
897 control
|= 8; /* PIO cycles in PIO0 */
899 if (adev
->devno
) { /* Slave */
900 master_data
&= 0xFF4F; /* Mask out IORDY|TIME1|DMAONLY */
901 master_data
|= control
<< 4;
902 pci_read_config_byte(dev
, 0x44, &slave_data
);
903 slave_data
&= (ap
->port_no
? 0x0f : 0xf0);
904 /* Load the matching timing */
905 slave_data
|= ((timings
[pio
][0] << 2) | timings
[pio
][1]) << (ap
->port_no
? 4 : 0);
906 pci_write_config_byte(dev
, 0x44, slave_data
);
907 } else { /* Master */
908 master_data
&= 0xCCF4; /* Mask out IORDY|TIME1|DMAONLY
909 and master timing bits */
910 master_data
|= control
;
912 (timings
[pio
][0] << 12) |
913 (timings
[pio
][1] << 8);
917 udma_enable
&= ~(1 << devid
);
918 pci_write_config_word(dev
, master_port
, master_data
);
921 /* Don't scribble on 0x48 if the controller does not support UDMA */
923 pci_write_config_byte(dev
, 0x48, udma_enable
);
927 * piix_set_dmamode - Initialize host controller PATA DMA timings
928 * @ap: Port whose timings we are configuring
931 * Set MW/UDMA mode for device, in host controller PCI config space.
934 * None (inherited from caller).
937 static void piix_set_dmamode(struct ata_port
*ap
, struct ata_device
*adev
)
939 do_pata_set_dmamode(ap
, adev
, 0);
943 * ich_set_dmamode - Initialize host controller PATA DMA timings
944 * @ap: Port whose timings we are configuring
947 * Set MW/UDMA mode for device, in host controller PCI config space.
950 * None (inherited from caller).
953 static void ich_set_dmamode(struct ata_port
*ap
, struct ata_device
*adev
)
955 do_pata_set_dmamode(ap
, adev
, 1);
959 static int piix_broken_suspend(void)
961 static const struct dmi_system_id sysids
[] = {
965 DMI_MATCH(DMI_SYS_VENDOR
, "TOSHIBA"),
966 DMI_MATCH(DMI_PRODUCT_NAME
, "TECRA M3"),
972 DMI_MATCH(DMI_SYS_VENDOR
, "TOSHIBA"),
973 DMI_MATCH(DMI_PRODUCT_NAME
, "Tecra M3"),
979 DMI_MATCH(DMI_SYS_VENDOR
, "TOSHIBA"),
980 DMI_MATCH(DMI_PRODUCT_NAME
, "Tecra M4"),
986 DMI_MATCH(DMI_SYS_VENDOR
, "TOSHIBA"),
987 DMI_MATCH(DMI_PRODUCT_NAME
, "TECRA M5"),
993 DMI_MATCH(DMI_SYS_VENDOR
, "TOSHIBA"),
994 DMI_MATCH(DMI_PRODUCT_NAME
, "TECRA M7"),
1000 DMI_MATCH(DMI_SYS_VENDOR
, "TOSHIBA"),
1001 DMI_MATCH(DMI_PRODUCT_NAME
, "TECRA A8"),
1005 .ident
= "Satellite R25",
1007 DMI_MATCH(DMI_SYS_VENDOR
, "TOSHIBA"),
1008 DMI_MATCH(DMI_PRODUCT_NAME
, "Satellite R25"),
1012 .ident
= "Satellite U200",
1014 DMI_MATCH(DMI_SYS_VENDOR
, "TOSHIBA"),
1015 DMI_MATCH(DMI_PRODUCT_NAME
, "Satellite U200"),
1019 .ident
= "Satellite U200",
1021 DMI_MATCH(DMI_SYS_VENDOR
, "TOSHIBA"),
1022 DMI_MATCH(DMI_PRODUCT_NAME
, "SATELLITE U200"),
1026 .ident
= "Satellite Pro U200",
1028 DMI_MATCH(DMI_SYS_VENDOR
, "TOSHIBA"),
1029 DMI_MATCH(DMI_PRODUCT_NAME
, "SATELLITE PRO U200"),
1033 .ident
= "Satellite U205",
1035 DMI_MATCH(DMI_SYS_VENDOR
, "TOSHIBA"),
1036 DMI_MATCH(DMI_PRODUCT_NAME
, "Satellite U205"),
1040 .ident
= "SATELLITE U205",
1042 DMI_MATCH(DMI_SYS_VENDOR
, "TOSHIBA"),
1043 DMI_MATCH(DMI_PRODUCT_NAME
, "SATELLITE U205"),
1047 .ident
= "Portege M500",
1049 DMI_MATCH(DMI_SYS_VENDOR
, "TOSHIBA"),
1050 DMI_MATCH(DMI_PRODUCT_NAME
, "PORTEGE M500"),
1054 { } /* terminate list */
1056 static const char *oemstrs
[] = {
1061 if (dmi_check_system(sysids
))
1064 for (i
= 0; i
< ARRAY_SIZE(oemstrs
); i
++)
1065 if (dmi_find_device(DMI_DEV_TYPE_OEM_STRING
, oemstrs
[i
], NULL
))
1071 static int piix_pci_device_suspend(struct pci_dev
*pdev
, pm_message_t mesg
)
1073 struct ata_host
*host
= dev_get_drvdata(&pdev
->dev
);
1074 unsigned long flags
;
1077 rc
= ata_host_suspend(host
, mesg
);
1081 /* Some braindamaged ACPI suspend implementations expect the
1082 * controller to be awake on entry; otherwise, it burns cpu
1083 * cycles and power trying to do something to the sleeping
1086 if (piix_broken_suspend() && mesg
.event
== PM_EVENT_SUSPEND
) {
1087 pci_save_state(pdev
);
1089 /* mark its power state as "unknown", since we don't
1090 * know if e.g. the BIOS will change its device state
1093 if (pdev
->current_state
== PCI_D0
)
1094 pdev
->current_state
= PCI_UNKNOWN
;
1096 /* tell resume that it's waking up from broken suspend */
1097 spin_lock_irqsave(&host
->lock
, flags
);
1098 host
->flags
|= PIIX_HOST_BROKEN_SUSPEND
;
1099 spin_unlock_irqrestore(&host
->lock
, flags
);
1101 ata_pci_device_do_suspend(pdev
, mesg
);
1106 static int piix_pci_device_resume(struct pci_dev
*pdev
)
1108 struct ata_host
*host
= dev_get_drvdata(&pdev
->dev
);
1109 unsigned long flags
;
1112 if (host
->flags
& PIIX_HOST_BROKEN_SUSPEND
) {
1113 spin_lock_irqsave(&host
->lock
, flags
);
1114 host
->flags
&= ~PIIX_HOST_BROKEN_SUSPEND
;
1115 spin_unlock_irqrestore(&host
->lock
, flags
);
1117 pci_set_power_state(pdev
, PCI_D0
);
1118 pci_restore_state(pdev
);
1120 /* PCI device wasn't disabled during suspend. Use
1121 * pci_reenable_device() to avoid affecting the enable
1124 rc
= pci_reenable_device(pdev
);
1126 dev_printk(KERN_ERR
, &pdev
->dev
, "failed to enable "
1127 "device after resume (%d)\n", rc
);
1129 rc
= ata_pci_device_do_resume(pdev
);
1132 ata_host_resume(host
);
1138 #define AHCI_PCI_BAR 5
1139 #define AHCI_GLOBAL_CTL 0x04
1140 #define AHCI_ENABLE (1 << 31)
1141 static int piix_disable_ahci(struct pci_dev
*pdev
)
1147 /* BUG: pci_enable_device has not yet been called. This
1148 * works because this device is usually set up by BIOS.
1151 if (!pci_resource_start(pdev
, AHCI_PCI_BAR
) ||
1152 !pci_resource_len(pdev
, AHCI_PCI_BAR
))
1155 mmio
= pci_iomap(pdev
, AHCI_PCI_BAR
, 64);
1159 tmp
= ioread32(mmio
+ AHCI_GLOBAL_CTL
);
1160 if (tmp
& AHCI_ENABLE
) {
1161 tmp
&= ~AHCI_ENABLE
;
1162 iowrite32(tmp
, mmio
+ AHCI_GLOBAL_CTL
);
1164 tmp
= ioread32(mmio
+ AHCI_GLOBAL_CTL
);
1165 if (tmp
& AHCI_ENABLE
)
1169 pci_iounmap(pdev
, mmio
);
1174 * piix_check_450nx_errata - Check for problem 450NX setup
1175 * @ata_dev: the PCI device to check
1177 * Check for the present of 450NX errata #19 and errata #25. If
1178 * they are found return an error code so we can turn off DMA
1181 static int __devinit
piix_check_450nx_errata(struct pci_dev
*ata_dev
)
1183 struct pci_dev
*pdev
= NULL
;
1185 int no_piix_dma
= 0;
1187 while ((pdev
= pci_get_device(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82454NX
, pdev
)) != NULL
) {
1188 /* Look for 450NX PXB. Check for problem configurations
1189 A PCI quirk checks bit 6 already */
1190 pci_read_config_word(pdev
, 0x41, &cfg
);
1191 /* Only on the original revision: IDE DMA can hang */
1192 if (pdev
->revision
== 0x00)
1194 /* On all revisions below 5 PXB bus lock must be disabled for IDE */
1195 else if (cfg
& (1<<14) && pdev
->revision
< 5)
1199 dev_printk(KERN_WARNING
, &ata_dev
->dev
, "450NX errata present, disabling IDE DMA.\n");
1200 if (no_piix_dma
== 2)
1201 dev_printk(KERN_WARNING
, &ata_dev
->dev
, "A BIOS update may resolve this.\n");
1205 static void __devinit
piix_init_pcs(struct pci_dev
*pdev
,
1206 struct ata_port_info
*pinfo
,
1207 const struct piix_map_db
*map_db
)
1211 pci_read_config_word(pdev
, ICH5_PCS
, &pcs
);
1213 new_pcs
= pcs
| map_db
->port_enable
;
1215 if (new_pcs
!= pcs
) {
1216 DPRINTK("updating PCS from 0x%x to 0x%x\n", pcs
, new_pcs
);
1217 pci_write_config_word(pdev
, ICH5_PCS
, new_pcs
);
1222 static void __devinit
piix_init_sata_map(struct pci_dev
*pdev
,
1223 struct ata_port_info
*pinfo
,
1224 const struct piix_map_db
*map_db
)
1226 struct piix_host_priv
*hpriv
= pinfo
[0].private_data
;
1228 int i
, invalid_map
= 0;
1231 pci_read_config_byte(pdev
, ICH5_PMR
, &map_value
);
1233 map
= map_db
->map
[map_value
& map_db
->mask
];
1235 dev_printk(KERN_INFO
, &pdev
->dev
, "MAP [");
1236 for (i
= 0; i
< 4; i
++) {
1248 WARN_ON((i
& 1) || map
[i
+ 1] != IDE
);
1249 pinfo
[i
/ 2] = piix_port_info
[ich_pata_100
];
1250 pinfo
[i
/ 2].private_data
= hpriv
;
1256 printk(" P%d", map
[i
]);
1258 pinfo
[i
/ 2].flags
|= ATA_FLAG_SLAVE_POSS
;
1265 dev_printk(KERN_ERR
, &pdev
->dev
,
1266 "invalid MAP value %u\n", map_value
);
1271 static void piix_iocfg_bit18_quirk(struct pci_dev
*pdev
)
1273 static const struct dmi_system_id sysids
[] = {
1275 /* Clevo M570U sets IOCFG bit 18 if the cdrom
1276 * isn't used to boot the system which
1277 * disables the channel.
1281 DMI_MATCH(DMI_SYS_VENDOR
, "Clevo Co."),
1282 DMI_MATCH(DMI_PRODUCT_NAME
, "M570U"),
1286 { } /* terminate list */
1290 if (!dmi_check_system(sysids
))
1293 /* The datasheet says that bit 18 is NOOP but certain systems
1294 * seem to use it to disable a channel. Clear the bit on the
1297 pci_read_config_dword(pdev
, PIIX_IOCFG
, &iocfg
);
1298 if (iocfg
& (1 << 18)) {
1299 dev_printk(KERN_INFO
, &pdev
->dev
,
1300 "applying IOCFG bit18 quirk\n");
1301 iocfg
&= ~(1 << 18);
1302 pci_write_config_dword(pdev
, PIIX_IOCFG
, iocfg
);
1307 * piix_init_one - Register PIIX ATA PCI device with kernel services
1308 * @pdev: PCI device to register
1309 * @ent: Entry in piix_pci_tbl matching with @pdev
1311 * Called from kernel PCI layer. We probe for combined mode (sigh),
1312 * and then hand over control to libata, for it to do the rest.
1315 * Inherited from PCI layer (may sleep).
1318 * Zero on success, or -ERRNO value.
1321 static int piix_init_one(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
1323 static int printed_version
;
1324 struct device
*dev
= &pdev
->dev
;
1325 struct ata_port_info port_info
[2];
1326 const struct ata_port_info
*ppi
[] = { &port_info
[0], &port_info
[1] };
1327 struct piix_host_priv
*hpriv
;
1328 unsigned long port_flags
;
1330 if (!printed_version
++)
1331 dev_printk(KERN_DEBUG
, &pdev
->dev
,
1332 "version " DRV_VERSION
"\n");
1334 /* no hotplugging support (FIXME) */
1335 if (!in_module_init
)
1338 hpriv
= devm_kzalloc(dev
, sizeof(*hpriv
), GFP_KERNEL
);
1342 port_info
[0] = piix_port_info
[ent
->driver_data
];
1343 port_info
[1] = piix_port_info
[ent
->driver_data
];
1344 port_info
[0].private_data
= hpriv
;
1345 port_info
[1].private_data
= hpriv
;
1347 port_flags
= port_info
[0].flags
;
1349 if (port_flags
& PIIX_FLAG_AHCI
) {
1351 pci_read_config_byte(pdev
, PIIX_SCC
, &tmp
);
1352 if (tmp
== PIIX_AHCI_DEVICE
) {
1353 int rc
= piix_disable_ahci(pdev
);
1359 /* Initialize SATA map */
1360 if (port_flags
& ATA_FLAG_SATA
) {
1361 piix_init_sata_map(pdev
, port_info
,
1362 piix_map_db_table
[ent
->driver_data
]);
1363 piix_init_pcs(pdev
, port_info
,
1364 piix_map_db_table
[ent
->driver_data
]);
1367 /* apply IOCFG bit18 quirk */
1368 piix_iocfg_bit18_quirk(pdev
);
1370 /* On ICH5, some BIOSen disable the interrupt using the
1371 * PCI_COMMAND_INTX_DISABLE bit added in PCI 2.3.
1372 * On ICH6, this bit has the same effect, but only when
1373 * MSI is disabled (and it is disabled, as we don't use
1374 * message-signalled interrupts currently).
1376 if (port_flags
& PIIX_FLAG_CHECKINTR
)
1379 if (piix_check_450nx_errata(pdev
)) {
1380 /* This writes into the master table but it does not
1381 really matter for this errata as we will apply it to
1382 all the PIIX devices on the board */
1383 port_info
[0].mwdma_mask
= 0;
1384 port_info
[0].udma_mask
= 0;
1385 port_info
[1].mwdma_mask
= 0;
1386 port_info
[1].udma_mask
= 0;
1388 return ata_pci_init_one(pdev
, ppi
);
1391 static int __init
piix_init(void)
1395 DPRINTK("pci_register_driver\n");
1396 rc
= pci_register_driver(&piix_pci_driver
);
1406 static void __exit
piix_exit(void)
1408 pci_unregister_driver(&piix_pci_driver
);
1411 module_init(piix_init
);
1412 module_exit(piix_exit
);