2 * Copyright (C) 2005-2006 Atmel Corporation
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
9 #include <linux/init.h>
10 #include <linux/platform_device.h>
11 #include <linux/spi/spi.h>
15 #include <asm/arch/at32ap7000.h>
16 #include <asm/arch/board.h>
17 #include <asm/arch/portmux.h>
18 #include <asm/arch/sm.h>
27 .end = base + 0x3ff, \
28 .flags = IORESOURCE_MEM, \
34 .flags = IORESOURCE_IRQ, \
36 #define NAMED_IRQ(num, _name) \
41 .flags = IORESOURCE_IRQ, \
44 #define DEFINE_DEV(_name, _id) \
45 static struct platform_device _name##_id##_device = { \
48 .resource = _name##_id##_resource, \
49 .num_resources = ARRAY_SIZE(_name##_id##_resource), \
51 #define DEFINE_DEV_DATA(_name, _id) \
52 static struct platform_device _name##_id##_device = { \
56 .platform_data = &_name##_id##_data, \
58 .resource = _name##_id##_resource, \
59 .num_resources = ARRAY_SIZE(_name##_id##_resource), \
62 #define select_peripheral(pin, periph, flags) \
63 at32_select_periph(GPIO_PIN_##pin, GPIO_##periph, flags)
65 #define DEV_CLK(_name, devname, bus, _index) \
66 static struct clk devname##_##_name = { \
68 .dev = &devname##_device.dev, \
69 .parent = &bus##_clk, \
70 .mode = bus##_clk_mode, \
71 .get_rate = bus##_clk_get_rate, \
75 unsigned long at32ap7000_osc_rates
[3] = {
77 /* FIXME: these are ATSTK1002-specific */
82 static unsigned long osc_get_rate(struct clk
*clk
)
84 return at32ap7000_osc_rates
[clk
->index
];
87 static unsigned long pll_get_rate(struct clk
*clk
, unsigned long control
)
89 unsigned long div
, mul
, rate
;
91 if (!(control
& SM_BIT(PLLEN
)))
94 div
= SM_BFEXT(PLLDIV
, control
) + 1;
95 mul
= SM_BFEXT(PLLMUL
, control
) + 1;
97 rate
= clk
->parent
->get_rate(clk
->parent
);
98 rate
= (rate
+ div
/ 2) / div
;
104 static unsigned long pll0_get_rate(struct clk
*clk
)
108 control
= sm_readl(&system_manager
, PM_PLL0
);
110 return pll_get_rate(clk
, control
);
113 static unsigned long pll1_get_rate(struct clk
*clk
)
117 control
= sm_readl(&system_manager
, PM_PLL1
);
119 return pll_get_rate(clk
, control
);
123 * The AT32AP7000 has five primary clock sources: One 32kHz
124 * oscillator, two crystal oscillators and two PLLs.
126 static struct clk osc32k
= {
128 .get_rate
= osc_get_rate
,
132 static struct clk osc0
= {
134 .get_rate
= osc_get_rate
,
138 static struct clk osc1
= {
140 .get_rate
= osc_get_rate
,
143 static struct clk pll0
= {
145 .get_rate
= pll0_get_rate
,
148 static struct clk pll1
= {
150 .get_rate
= pll1_get_rate
,
155 * The main clock can be either osc0 or pll0. The boot loader may
156 * have chosen one for us, so we don't really know which one until we
157 * have a look at the SM.
159 static struct clk
*main_clock
;
162 * Synchronous clocks are generated from the main clock. The clocks
163 * must satisfy the constraint
164 * fCPU >= fHSB >= fPB
165 * i.e. each clock must not be faster than its parent.
167 static unsigned long bus_clk_get_rate(struct clk
*clk
, unsigned int shift
)
169 return main_clock
->get_rate(main_clock
) >> shift
;
172 static void cpu_clk_mode(struct clk
*clk
, int enabled
)
174 struct at32_sm
*sm
= &system_manager
;
178 spin_lock_irqsave(&sm
->lock
, flags
);
179 mask
= sm_readl(sm
, PM_CPU_MASK
);
181 mask
|= 1 << clk
->index
;
183 mask
&= ~(1 << clk
->index
);
184 sm_writel(sm
, PM_CPU_MASK
, mask
);
185 spin_unlock_irqrestore(&sm
->lock
, flags
);
188 static unsigned long cpu_clk_get_rate(struct clk
*clk
)
190 unsigned long cksel
, shift
= 0;
192 cksel
= sm_readl(&system_manager
, PM_CKSEL
);
193 if (cksel
& SM_BIT(CPUDIV
))
194 shift
= SM_BFEXT(CPUSEL
, cksel
) + 1;
196 return bus_clk_get_rate(clk
, shift
);
199 static void hsb_clk_mode(struct clk
*clk
, int enabled
)
201 struct at32_sm
*sm
= &system_manager
;
205 spin_lock_irqsave(&sm
->lock
, flags
);
206 mask
= sm_readl(sm
, PM_HSB_MASK
);
208 mask
|= 1 << clk
->index
;
210 mask
&= ~(1 << clk
->index
);
211 sm_writel(sm
, PM_HSB_MASK
, mask
);
212 spin_unlock_irqrestore(&sm
->lock
, flags
);
215 static unsigned long hsb_clk_get_rate(struct clk
*clk
)
217 unsigned long cksel
, shift
= 0;
219 cksel
= sm_readl(&system_manager
, PM_CKSEL
);
220 if (cksel
& SM_BIT(HSBDIV
))
221 shift
= SM_BFEXT(HSBSEL
, cksel
) + 1;
223 return bus_clk_get_rate(clk
, shift
);
226 static void pba_clk_mode(struct clk
*clk
, int enabled
)
228 struct at32_sm
*sm
= &system_manager
;
232 spin_lock_irqsave(&sm
->lock
, flags
);
233 mask
= sm_readl(sm
, PM_PBA_MASK
);
235 mask
|= 1 << clk
->index
;
237 mask
&= ~(1 << clk
->index
);
238 sm_writel(sm
, PM_PBA_MASK
, mask
);
239 spin_unlock_irqrestore(&sm
->lock
, flags
);
242 static unsigned long pba_clk_get_rate(struct clk
*clk
)
244 unsigned long cksel
, shift
= 0;
246 cksel
= sm_readl(&system_manager
, PM_CKSEL
);
247 if (cksel
& SM_BIT(PBADIV
))
248 shift
= SM_BFEXT(PBASEL
, cksel
) + 1;
250 return bus_clk_get_rate(clk
, shift
);
253 static void pbb_clk_mode(struct clk
*clk
, int enabled
)
255 struct at32_sm
*sm
= &system_manager
;
259 spin_lock_irqsave(&sm
->lock
, flags
);
260 mask
= sm_readl(sm
, PM_PBB_MASK
);
262 mask
|= 1 << clk
->index
;
264 mask
&= ~(1 << clk
->index
);
265 sm_writel(sm
, PM_PBB_MASK
, mask
);
266 spin_unlock_irqrestore(&sm
->lock
, flags
);
269 static unsigned long pbb_clk_get_rate(struct clk
*clk
)
271 unsigned long cksel
, shift
= 0;
273 cksel
= sm_readl(&system_manager
, PM_CKSEL
);
274 if (cksel
& SM_BIT(PBBDIV
))
275 shift
= SM_BFEXT(PBBSEL
, cksel
) + 1;
277 return bus_clk_get_rate(clk
, shift
);
280 static struct clk cpu_clk
= {
282 .get_rate
= cpu_clk_get_rate
,
285 static struct clk hsb_clk
= {
288 .get_rate
= hsb_clk_get_rate
,
290 static struct clk pba_clk
= {
293 .mode
= hsb_clk_mode
,
294 .get_rate
= pba_clk_get_rate
,
297 static struct clk pbb_clk
= {
300 .mode
= hsb_clk_mode
,
301 .get_rate
= pbb_clk_get_rate
,
306 /* --------------------------------------------------------------------
307 * Generic Clock operations
308 * -------------------------------------------------------------------- */
310 static void genclk_mode(struct clk
*clk
, int enabled
)
314 control
= sm_readl(&system_manager
, PM_GCCTRL
+ 4 * clk
->index
);
316 control
|= SM_BIT(CEN
);
318 control
&= ~SM_BIT(CEN
);
319 sm_writel(&system_manager
, PM_GCCTRL
+ 4 * clk
->index
, control
);
322 static unsigned long genclk_get_rate(struct clk
*clk
)
325 unsigned long div
= 1;
327 control
= sm_readl(&system_manager
, PM_GCCTRL
+ 4 * clk
->index
);
328 if (control
& SM_BIT(DIVEN
))
329 div
= 2 * (SM_BFEXT(DIV
, control
) + 1);
331 return clk
->parent
->get_rate(clk
->parent
) / div
;
334 static long genclk_set_rate(struct clk
*clk
, unsigned long rate
, int apply
)
337 unsigned long parent_rate
, actual_rate
, div
;
339 parent_rate
= clk
->parent
->get_rate(clk
->parent
);
340 control
= sm_readl(&system_manager
, PM_GCCTRL
+ 4 * clk
->index
);
342 if (rate
> 3 * parent_rate
/ 4) {
343 actual_rate
= parent_rate
;
344 control
&= ~SM_BIT(DIVEN
);
346 div
= (parent_rate
+ rate
) / (2 * rate
) - 1;
347 control
= SM_BFINS(DIV
, div
, control
) | SM_BIT(DIVEN
);
348 actual_rate
= parent_rate
/ (2 * (div
+ 1));
351 printk("clk %s: new rate %lu (actual rate %lu)\n",
352 clk
->name
, rate
, actual_rate
);
355 sm_writel(&system_manager
, PM_GCCTRL
+ 4 * clk
->index
,
361 int genclk_set_parent(struct clk
*clk
, struct clk
*parent
)
365 printk("clk %s: new parent %s (was %s)\n",
366 clk
->name
, parent
->name
, clk
->parent
->name
);
368 control
= sm_readl(&system_manager
, PM_GCCTRL
+ 4 * clk
->index
);
370 if (parent
== &osc1
|| parent
== &pll1
)
371 control
|= SM_BIT(OSCSEL
);
372 else if (parent
== &osc0
|| parent
== &pll0
)
373 control
&= ~SM_BIT(OSCSEL
);
377 if (parent
== &pll0
|| parent
== &pll1
)
378 control
|= SM_BIT(PLLSEL
);
380 control
&= ~SM_BIT(PLLSEL
);
382 sm_writel(&system_manager
, PM_GCCTRL
+ 4 * clk
->index
, control
);
383 clk
->parent
= parent
;
388 static void __init
genclk_init_parent(struct clk
*clk
)
393 BUG_ON(clk
->index
> 7);
395 control
= sm_readl(&system_manager
, PM_GCCTRL
+ 4 * clk
->index
);
396 if (control
& SM_BIT(OSCSEL
))
397 parent
= (control
& SM_BIT(PLLSEL
)) ? &pll1
: &osc1
;
399 parent
= (control
& SM_BIT(PLLSEL
)) ? &pll0
: &osc0
;
401 clk
->parent
= parent
;
404 /* --------------------------------------------------------------------
406 * -------------------------------------------------------------------- */
407 static struct resource sm_resource
[] = {
409 NAMED_IRQ(19, "eim"),
411 NAMED_IRQ(21, "rtc"),
413 struct platform_device at32_sm_device
= {
416 .resource
= sm_resource
,
417 .num_resources
= ARRAY_SIZE(sm_resource
),
419 DEV_CLK(pclk
, at32_sm
, pbb
, 0);
421 static struct resource intc0_resource
[] = {
424 struct platform_device at32_intc0_device
= {
427 .resource
= intc0_resource
,
428 .num_resources
= ARRAY_SIZE(intc0_resource
),
430 DEV_CLK(pclk
, at32_intc0
, pbb
, 1);
432 static struct clk ebi_clk
= {
435 .mode
= hsb_clk_mode
,
436 .get_rate
= hsb_clk_get_rate
,
439 static struct clk hramc_clk
= {
442 .mode
= hsb_clk_mode
,
443 .get_rate
= hsb_clk_get_rate
,
447 static struct resource smc0_resource
[] = {
451 DEV_CLK(pclk
, smc0
, pbb
, 13);
452 DEV_CLK(mck
, smc0
, hsb
, 0);
454 static struct platform_device pdc_device
= {
458 DEV_CLK(hclk
, pdc
, hsb
, 4);
459 DEV_CLK(pclk
, pdc
, pba
, 16);
461 static struct clk pico_clk
= {
464 .mode
= cpu_clk_mode
,
465 .get_rate
= cpu_clk_get_rate
,
469 /* --------------------------------------------------------------------
471 * -------------------------------------------------------------------- */
473 static struct resource pio0_resource
[] = {
478 DEV_CLK(mck
, pio0
, pba
, 10);
480 static struct resource pio1_resource
[] = {
485 DEV_CLK(mck
, pio1
, pba
, 11);
487 static struct resource pio2_resource
[] = {
492 DEV_CLK(mck
, pio2
, pba
, 12);
494 static struct resource pio3_resource
[] = {
499 DEV_CLK(mck
, pio3
, pba
, 13);
501 static struct resource pio4_resource
[] = {
506 DEV_CLK(mck
, pio4
, pba
, 14);
508 void __init
at32_add_system_devices(void)
510 system_manager
.eim_first_irq
= EIM_IRQ_BASE
;
512 platform_device_register(&at32_sm_device
);
513 platform_device_register(&at32_intc0_device
);
514 platform_device_register(&smc0_device
);
515 platform_device_register(&pdc_device
);
517 platform_device_register(&pio0_device
);
518 platform_device_register(&pio1_device
);
519 platform_device_register(&pio2_device
);
520 platform_device_register(&pio3_device
);
521 platform_device_register(&pio4_device
);
524 /* --------------------------------------------------------------------
526 * -------------------------------------------------------------------- */
528 static struct atmel_uart_data atmel_usart0_data
= {
532 static struct resource atmel_usart0_resource
[] = {
536 DEFINE_DEV_DATA(atmel_usart
, 0);
537 DEV_CLK(usart
, atmel_usart0
, pba
, 4);
539 static struct atmel_uart_data atmel_usart1_data
= {
543 static struct resource atmel_usart1_resource
[] = {
547 DEFINE_DEV_DATA(atmel_usart
, 1);
548 DEV_CLK(usart
, atmel_usart1
, pba
, 4);
550 static struct atmel_uart_data atmel_usart2_data
= {
554 static struct resource atmel_usart2_resource
[] = {
558 DEFINE_DEV_DATA(atmel_usart
, 2);
559 DEV_CLK(usart
, atmel_usart2
, pba
, 5);
561 static struct atmel_uart_data atmel_usart3_data
= {
565 static struct resource atmel_usart3_resource
[] = {
569 DEFINE_DEV_DATA(atmel_usart
, 3);
570 DEV_CLK(usart
, atmel_usart3
, pba
, 6);
572 static inline void configure_usart0_pins(void)
574 select_peripheral(PA(8), PERIPH_B
, 0); /* RXD */
575 select_peripheral(PA(9), PERIPH_B
, 0); /* TXD */
578 static inline void configure_usart1_pins(void)
580 select_peripheral(PA(17), PERIPH_A
, 0); /* RXD */
581 select_peripheral(PA(18), PERIPH_A
, 0); /* TXD */
584 static inline void configure_usart2_pins(void)
586 select_peripheral(PB(26), PERIPH_B
, 0); /* RXD */
587 select_peripheral(PB(27), PERIPH_B
, 0); /* TXD */
590 static inline void configure_usart3_pins(void)
592 select_peripheral(PB(18), PERIPH_B
, 0); /* RXD */
593 select_peripheral(PB(17), PERIPH_B
, 0); /* TXD */
596 static struct platform_device
*__initdata at32_usarts
[4];
598 void __init
at32_map_usart(unsigned int hw_id
, unsigned int line
)
600 struct platform_device
*pdev
;
604 pdev
= &atmel_usart0_device
;
605 configure_usart0_pins();
608 pdev
= &atmel_usart1_device
;
609 configure_usart1_pins();
612 pdev
= &atmel_usart2_device
;
613 configure_usart2_pins();
616 pdev
= &atmel_usart3_device
;
617 configure_usart3_pins();
623 if (PXSEG(pdev
->resource
[0].start
) == P4SEG
) {
624 /* Addresses in the P4 segment are permanently mapped 1:1 */
625 struct atmel_uart_data
*data
= pdev
->dev
.platform_data
;
626 data
->regs
= (void __iomem
*)pdev
->resource
[0].start
;
630 at32_usarts
[line
] = pdev
;
633 struct platform_device
*__init
at32_add_device_usart(unsigned int id
)
635 platform_device_register(at32_usarts
[id
]);
636 return at32_usarts
[id
];
639 struct platform_device
*atmel_default_console_device
;
641 void __init
at32_setup_serial_console(unsigned int usart_id
)
643 atmel_default_console_device
= at32_usarts
[usart_id
];
646 /* --------------------------------------------------------------------
648 * -------------------------------------------------------------------- */
650 static struct eth_platform_data macb0_data
;
651 static struct resource macb0_resource
[] = {
655 DEFINE_DEV_DATA(macb
, 0);
656 DEV_CLK(hclk
, macb0
, hsb
, 8);
657 DEV_CLK(pclk
, macb0
, pbb
, 6);
659 static struct eth_platform_data macb1_data
;
660 static struct resource macb1_resource
[] = {
664 DEFINE_DEV_DATA(macb
, 1);
665 DEV_CLK(hclk
, macb1
, hsb
, 9);
666 DEV_CLK(pclk
, macb1
, pbb
, 7);
668 struct platform_device
*__init
669 at32_add_device_eth(unsigned int id
, struct eth_platform_data
*data
)
671 struct platform_device
*pdev
;
675 pdev
= &macb0_device
;
677 select_peripheral(PC(3), PERIPH_A
, 0); /* TXD0 */
678 select_peripheral(PC(4), PERIPH_A
, 0); /* TXD1 */
679 select_peripheral(PC(7), PERIPH_A
, 0); /* TXEN */
680 select_peripheral(PC(8), PERIPH_A
, 0); /* TXCK */
681 select_peripheral(PC(9), PERIPH_A
, 0); /* RXD0 */
682 select_peripheral(PC(10), PERIPH_A
, 0); /* RXD1 */
683 select_peripheral(PC(13), PERIPH_A
, 0); /* RXER */
684 select_peripheral(PC(15), PERIPH_A
, 0); /* RXDV */
685 select_peripheral(PC(16), PERIPH_A
, 0); /* MDC */
686 select_peripheral(PC(17), PERIPH_A
, 0); /* MDIO */
688 if (!data
->is_rmii
) {
689 select_peripheral(PC(0), PERIPH_A
, 0); /* COL */
690 select_peripheral(PC(1), PERIPH_A
, 0); /* CRS */
691 select_peripheral(PC(2), PERIPH_A
, 0); /* TXER */
692 select_peripheral(PC(5), PERIPH_A
, 0); /* TXD2 */
693 select_peripheral(PC(6), PERIPH_A
, 0); /* TXD3 */
694 select_peripheral(PC(11), PERIPH_A
, 0); /* RXD2 */
695 select_peripheral(PC(12), PERIPH_A
, 0); /* RXD3 */
696 select_peripheral(PC(14), PERIPH_A
, 0); /* RXCK */
697 select_peripheral(PC(18), PERIPH_A
, 0); /* SPD */
702 pdev
= &macb1_device
;
704 select_peripheral(PD(13), PERIPH_B
, 0); /* TXD0 */
705 select_peripheral(PD(14), PERIPH_B
, 0); /* TXD1 */
706 select_peripheral(PD(11), PERIPH_B
, 0); /* TXEN */
707 select_peripheral(PD(12), PERIPH_B
, 0); /* TXCK */
708 select_peripheral(PD(10), PERIPH_B
, 0); /* RXD0 */
709 select_peripheral(PD(6), PERIPH_B
, 0); /* RXD1 */
710 select_peripheral(PD(5), PERIPH_B
, 0); /* RXER */
711 select_peripheral(PD(4), PERIPH_B
, 0); /* RXDV */
712 select_peripheral(PD(3), PERIPH_B
, 0); /* MDC */
713 select_peripheral(PD(2), PERIPH_B
, 0); /* MDIO */
715 if (!data
->is_rmii
) {
716 select_peripheral(PC(19), PERIPH_B
, 0); /* COL */
717 select_peripheral(PC(23), PERIPH_B
, 0); /* CRS */
718 select_peripheral(PC(26), PERIPH_B
, 0); /* TXER */
719 select_peripheral(PC(27), PERIPH_B
, 0); /* TXD2 */
720 select_peripheral(PC(28), PERIPH_B
, 0); /* TXD3 */
721 select_peripheral(PC(29), PERIPH_B
, 0); /* RXD2 */
722 select_peripheral(PC(30), PERIPH_B
, 0); /* RXD3 */
723 select_peripheral(PC(24), PERIPH_B
, 0); /* RXCK */
724 select_peripheral(PD(15), PERIPH_B
, 0); /* SPD */
732 memcpy(pdev
->dev
.platform_data
, data
, sizeof(struct eth_platform_data
));
733 platform_device_register(pdev
);
738 /* --------------------------------------------------------------------
740 * -------------------------------------------------------------------- */
741 static struct resource atmel_spi0_resource
[] = {
745 DEFINE_DEV(atmel_spi
, 0);
746 DEV_CLK(spi_clk
, atmel_spi0
, pba
, 0);
748 static struct resource atmel_spi1_resource
[] = {
752 DEFINE_DEV(atmel_spi
, 1);
753 DEV_CLK(spi_clk
, atmel_spi1
, pba
, 1);
756 at32_spi_setup_slaves(unsigned int bus_num
, struct spi_board_info
*b
,
757 unsigned int n
, const u8
*pins
)
759 unsigned int pin
, mode
;
761 for (; n
; n
--, b
++) {
762 b
->bus_num
= bus_num
;
763 if (b
->chip_select
>= 4)
765 pin
= (unsigned)b
->controller_data
;
767 pin
= pins
[b
->chip_select
];
768 b
->controller_data
= (void *)pin
;
770 mode
= AT32_GPIOF_OUTPUT
;
771 if (!(b
->mode
& SPI_CS_HIGH
))
772 mode
|= AT32_GPIOF_HIGH
;
773 at32_select_gpio(pin
, mode
);
777 struct platform_device
*__init
778 at32_add_device_spi(unsigned int id
, struct spi_board_info
*b
, unsigned int n
)
781 * Manage the chipselects as GPIOs, normally using the same pins
782 * the SPI controller expects; but boards can use other pins.
784 static u8 __initdata spi0_pins
[] =
785 { GPIO_PIN_PA(3), GPIO_PIN_PA(4),
786 GPIO_PIN_PA(5), GPIO_PIN_PA(20), };
787 static u8 __initdata spi1_pins
[] =
788 { GPIO_PIN_PB(2), GPIO_PIN_PB(3),
789 GPIO_PIN_PB(4), GPIO_PIN_PA(27), };
790 struct platform_device
*pdev
;
794 pdev
= &atmel_spi0_device
;
795 select_peripheral(PA(0), PERIPH_A
, 0); /* MISO */
796 select_peripheral(PA(1), PERIPH_A
, 0); /* MOSI */
797 select_peripheral(PA(2), PERIPH_A
, 0); /* SCK */
798 at32_spi_setup_slaves(0, b
, n
, spi0_pins
);
802 pdev
= &atmel_spi1_device
;
803 select_peripheral(PB(0), PERIPH_B
, 0); /* MISO */
804 select_peripheral(PB(1), PERIPH_B
, 0); /* MOSI */
805 select_peripheral(PB(5), PERIPH_B
, 0); /* SCK */
806 at32_spi_setup_slaves(1, b
, n
, spi1_pins
);
813 spi_register_board_info(b
, n
);
814 platform_device_register(pdev
);
818 /* --------------------------------------------------------------------
820 * -------------------------------------------------------------------- */
821 static struct lcdc_platform_data lcdc0_data
;
822 static struct resource lcdc0_resource
[] = {
826 .flags
= IORESOURCE_MEM
,
830 DEFINE_DEV_DATA(lcdc
, 0);
831 DEV_CLK(hclk
, lcdc0
, hsb
, 7);
832 static struct clk lcdc0_pixclk
= {
834 .dev
= &lcdc0_device
.dev
,
836 .get_rate
= genclk_get_rate
,
837 .set_rate
= genclk_set_rate
,
838 .set_parent
= genclk_set_parent
,
842 struct platform_device
*__init
843 at32_add_device_lcdc(unsigned int id
, struct lcdc_platform_data
*data
)
845 struct platform_device
*pdev
;
849 pdev
= &lcdc0_device
;
850 select_peripheral(PC(19), PERIPH_A
, 0); /* CC */
851 select_peripheral(PC(20), PERIPH_A
, 0); /* HSYNC */
852 select_peripheral(PC(21), PERIPH_A
, 0); /* PCLK */
853 select_peripheral(PC(22), PERIPH_A
, 0); /* VSYNC */
854 select_peripheral(PC(23), PERIPH_A
, 0); /* DVAL */
855 select_peripheral(PC(24), PERIPH_A
, 0); /* MODE */
856 select_peripheral(PC(25), PERIPH_A
, 0); /* PWR */
857 select_peripheral(PC(26), PERIPH_A
, 0); /* DATA0 */
858 select_peripheral(PC(27), PERIPH_A
, 0); /* DATA1 */
859 select_peripheral(PC(28), PERIPH_A
, 0); /* DATA2 */
860 select_peripheral(PC(29), PERIPH_A
, 0); /* DATA3 */
861 select_peripheral(PC(30), PERIPH_A
, 0); /* DATA4 */
862 select_peripheral(PC(31), PERIPH_A
, 0); /* DATA5 */
863 select_peripheral(PD(0), PERIPH_A
, 0); /* DATA6 */
864 select_peripheral(PD(1), PERIPH_A
, 0); /* DATA7 */
865 select_peripheral(PD(2), PERIPH_A
, 0); /* DATA8 */
866 select_peripheral(PD(3), PERIPH_A
, 0); /* DATA9 */
867 select_peripheral(PD(4), PERIPH_A
, 0); /* DATA10 */
868 select_peripheral(PD(5), PERIPH_A
, 0); /* DATA11 */
869 select_peripheral(PD(6), PERIPH_A
, 0); /* DATA12 */
870 select_peripheral(PD(7), PERIPH_A
, 0); /* DATA13 */
871 select_peripheral(PD(8), PERIPH_A
, 0); /* DATA14 */
872 select_peripheral(PD(9), PERIPH_A
, 0); /* DATA15 */
873 select_peripheral(PD(10), PERIPH_A
, 0); /* DATA16 */
874 select_peripheral(PD(11), PERIPH_A
, 0); /* DATA17 */
875 select_peripheral(PD(12), PERIPH_A
, 0); /* DATA18 */
876 select_peripheral(PD(13), PERIPH_A
, 0); /* DATA19 */
877 select_peripheral(PD(14), PERIPH_A
, 0); /* DATA20 */
878 select_peripheral(PD(15), PERIPH_A
, 0); /* DATA21 */
879 select_peripheral(PD(16), PERIPH_A
, 0); /* DATA22 */
880 select_peripheral(PD(17), PERIPH_A
, 0); /* DATA23 */
882 clk_set_parent(&lcdc0_pixclk
, &pll0
);
883 clk_set_rate(&lcdc0_pixclk
, clk_get_rate(&pll0
));
890 memcpy(pdev
->dev
.platform_data
, data
,
891 sizeof(struct lcdc_platform_data
));
893 platform_device_register(pdev
);
897 /* --------------------------------------------------------------------
899 * -------------------------------------------------------------------- */
900 static struct clk gclk0
= {
903 .get_rate
= genclk_get_rate
,
904 .set_rate
= genclk_set_rate
,
905 .set_parent
= genclk_set_parent
,
908 static struct clk gclk1
= {
911 .get_rate
= genclk_get_rate
,
912 .set_rate
= genclk_set_rate
,
913 .set_parent
= genclk_set_parent
,
916 static struct clk gclk2
= {
919 .get_rate
= genclk_get_rate
,
920 .set_rate
= genclk_set_rate
,
921 .set_parent
= genclk_set_parent
,
924 static struct clk gclk3
= {
927 .get_rate
= genclk_get_rate
,
928 .set_rate
= genclk_set_rate
,
929 .set_parent
= genclk_set_parent
,
932 static struct clk gclk4
= {
935 .get_rate
= genclk_get_rate
,
936 .set_rate
= genclk_set_rate
,
937 .set_parent
= genclk_set_parent
,
941 struct clk
*at32_clock_list
[] = {
983 unsigned int at32_nr_clocks
= ARRAY_SIZE(at32_clock_list
);
985 void __init
at32_portmux_init(void)
987 at32_init_pio(&pio0_device
);
988 at32_init_pio(&pio1_device
);
989 at32_init_pio(&pio2_device
);
990 at32_init_pio(&pio3_device
);
991 at32_init_pio(&pio4_device
);
994 void __init
at32_clock_init(void)
996 struct at32_sm
*sm
= &system_manager
;
997 u32 cpu_mask
= 0, hsb_mask
= 0, pba_mask
= 0, pbb_mask
= 0;
1000 if (sm_readl(sm
, PM_MCCTRL
) & SM_BIT(PLLSEL
))
1005 if (sm_readl(sm
, PM_PLL0
) & SM_BIT(PLLOSC
))
1006 pll0
.parent
= &osc1
;
1007 if (sm_readl(sm
, PM_PLL1
) & SM_BIT(PLLOSC
))
1008 pll1
.parent
= &osc1
;
1010 genclk_init_parent(&gclk0
);
1011 genclk_init_parent(&gclk1
);
1012 genclk_init_parent(&gclk2
);
1013 genclk_init_parent(&gclk3
);
1014 genclk_init_parent(&gclk4
);
1015 genclk_init_parent(&lcdc0_pixclk
);
1018 * Turn on all clocks that have at least one user already, and
1019 * turn off everything else. We only do this for module
1020 * clocks, and even though it isn't particularly pretty to
1021 * check the address of the mode function, it should do the
1024 for (i
= 0; i
< ARRAY_SIZE(at32_clock_list
); i
++) {
1025 struct clk
*clk
= at32_clock_list
[i
];
1027 if (clk
->mode
== &cpu_clk_mode
)
1028 cpu_mask
|= 1 << clk
->index
;
1029 else if (clk
->mode
== &hsb_clk_mode
)
1030 hsb_mask
|= 1 << clk
->index
;
1031 else if (clk
->mode
== &pba_clk_mode
)
1032 pba_mask
|= 1 << clk
->index
;
1033 else if (clk
->mode
== &pbb_clk_mode
)
1034 pbb_mask
|= 1 << clk
->index
;
1037 sm_writel(sm
, PM_CPU_MASK
, cpu_mask
);
1038 sm_writel(sm
, PM_HSB_MASK
, hsb_mask
);
1039 sm_writel(sm
, PM_PBA_MASK
, pba_mask
);
1040 sm_writel(sm
, PM_PBB_MASK
, pbb_mask
);