2 * Copyright (c) 2008-2009 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include <linux/nl80211.h>
20 #define ATH_PCI_VERSION "0.1"
22 static char *dev_info
= "ath9k";
24 MODULE_AUTHOR("Atheros Communications");
25 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
26 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
27 MODULE_LICENSE("Dual BSD/GPL");
29 static int modparam_nohwcrypt
;
30 module_param_named(nohwcrypt
, modparam_nohwcrypt
, int, 0444);
31 MODULE_PARM_DESC(nohwcrypt
, "Disable hardware encryption");
33 /* We use the hw_value as an index into our private channel structure */
35 #define CHAN2G(_freq, _idx) { \
36 .center_freq = (_freq), \
41 #define CHAN5G(_freq, _idx) { \
42 .band = IEEE80211_BAND_5GHZ, \
43 .center_freq = (_freq), \
48 /* Some 2 GHz radios are actually tunable on 2312-2732
49 * on 5 MHz steps, we support the channels which we know
50 * we have calibration data for all cards though to make
52 static struct ieee80211_channel ath9k_2ghz_chantable
[] = {
53 CHAN2G(2412, 0), /* Channel 1 */
54 CHAN2G(2417, 1), /* Channel 2 */
55 CHAN2G(2422, 2), /* Channel 3 */
56 CHAN2G(2427, 3), /* Channel 4 */
57 CHAN2G(2432, 4), /* Channel 5 */
58 CHAN2G(2437, 5), /* Channel 6 */
59 CHAN2G(2442, 6), /* Channel 7 */
60 CHAN2G(2447, 7), /* Channel 8 */
61 CHAN2G(2452, 8), /* Channel 9 */
62 CHAN2G(2457, 9), /* Channel 10 */
63 CHAN2G(2462, 10), /* Channel 11 */
64 CHAN2G(2467, 11), /* Channel 12 */
65 CHAN2G(2472, 12), /* Channel 13 */
66 CHAN2G(2484, 13), /* Channel 14 */
69 /* Some 5 GHz radios are actually tunable on XXXX-YYYY
70 * on 5 MHz steps, we support the channels which we know
71 * we have calibration data for all cards though to make
73 static struct ieee80211_channel ath9k_5ghz_chantable
[] = {
74 /* _We_ call this UNII 1 */
75 CHAN5G(5180, 14), /* Channel 36 */
76 CHAN5G(5200, 15), /* Channel 40 */
77 CHAN5G(5220, 16), /* Channel 44 */
78 CHAN5G(5240, 17), /* Channel 48 */
79 /* _We_ call this UNII 2 */
80 CHAN5G(5260, 18), /* Channel 52 */
81 CHAN5G(5280, 19), /* Channel 56 */
82 CHAN5G(5300, 20), /* Channel 60 */
83 CHAN5G(5320, 21), /* Channel 64 */
84 /* _We_ call this "Middle band" */
85 CHAN5G(5500, 22), /* Channel 100 */
86 CHAN5G(5520, 23), /* Channel 104 */
87 CHAN5G(5540, 24), /* Channel 108 */
88 CHAN5G(5560, 25), /* Channel 112 */
89 CHAN5G(5580, 26), /* Channel 116 */
90 CHAN5G(5600, 27), /* Channel 120 */
91 CHAN5G(5620, 28), /* Channel 124 */
92 CHAN5G(5640, 29), /* Channel 128 */
93 CHAN5G(5660, 30), /* Channel 132 */
94 CHAN5G(5680, 31), /* Channel 136 */
95 CHAN5G(5700, 32), /* Channel 140 */
96 /* _We_ call this UNII 3 */
97 CHAN5G(5745, 33), /* Channel 149 */
98 CHAN5G(5765, 34), /* Channel 153 */
99 CHAN5G(5785, 35), /* Channel 157 */
100 CHAN5G(5805, 36), /* Channel 161 */
101 CHAN5G(5825, 37), /* Channel 165 */
104 static void ath_cache_conf_rate(struct ath_softc
*sc
,
105 struct ieee80211_conf
*conf
)
107 switch (conf
->channel
->band
) {
108 case IEEE80211_BAND_2GHZ
:
109 if (conf_is_ht20(conf
))
111 sc
->hw_rate_table
[ATH9K_MODE_11NG_HT20
];
112 else if (conf_is_ht40_minus(conf
))
114 sc
->hw_rate_table
[ATH9K_MODE_11NG_HT40MINUS
];
115 else if (conf_is_ht40_plus(conf
))
117 sc
->hw_rate_table
[ATH9K_MODE_11NG_HT40PLUS
];
120 sc
->hw_rate_table
[ATH9K_MODE_11G
];
122 case IEEE80211_BAND_5GHZ
:
123 if (conf_is_ht20(conf
))
125 sc
->hw_rate_table
[ATH9K_MODE_11NA_HT20
];
126 else if (conf_is_ht40_minus(conf
))
128 sc
->hw_rate_table
[ATH9K_MODE_11NA_HT40MINUS
];
129 else if (conf_is_ht40_plus(conf
))
131 sc
->hw_rate_table
[ATH9K_MODE_11NA_HT40PLUS
];
134 sc
->hw_rate_table
[ATH9K_MODE_11A
];
142 static void ath_update_txpow(struct ath_softc
*sc
)
144 struct ath_hw
*ah
= sc
->sc_ah
;
147 if (sc
->curtxpow
!= sc
->config
.txpowlimit
) {
148 ath9k_hw_set_txpowerlimit(ah
, sc
->config
.txpowlimit
);
149 /* read back in case value is clamped */
150 ath9k_hw_getcapability(ah
, ATH9K_CAP_TXPOW
, 1, &txpow
);
151 sc
->curtxpow
= txpow
;
155 static u8
parse_mpdudensity(u8 mpdudensity
)
158 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
159 * 0 for no restriction
168 switch (mpdudensity
) {
174 /* Our lower layer calculations limit our precision to
190 static void ath_setup_rates(struct ath_softc
*sc
, enum ieee80211_band band
)
192 const struct ath_rate_table
*rate_table
= NULL
;
193 struct ieee80211_supported_band
*sband
;
194 struct ieee80211_rate
*rate
;
198 case IEEE80211_BAND_2GHZ
:
199 rate_table
= sc
->hw_rate_table
[ATH9K_MODE_11G
];
201 case IEEE80211_BAND_5GHZ
:
202 rate_table
= sc
->hw_rate_table
[ATH9K_MODE_11A
];
208 if (rate_table
== NULL
)
211 sband
= &sc
->sbands
[band
];
212 rate
= sc
->rates
[band
];
214 if (rate_table
->rate_cnt
> ATH_RATE_MAX
)
215 maxrates
= ATH_RATE_MAX
;
217 maxrates
= rate_table
->rate_cnt
;
219 for (i
= 0; i
< maxrates
; i
++) {
220 rate
[i
].bitrate
= rate_table
->info
[i
].ratekbps
/ 100;
221 rate
[i
].hw_value
= rate_table
->info
[i
].ratecode
;
222 if (rate_table
->info
[i
].short_preamble
) {
223 rate
[i
].hw_value_short
= rate_table
->info
[i
].ratecode
|
224 rate_table
->info
[i
].short_preamble
;
225 rate
[i
].flags
= IEEE80211_RATE_SHORT_PREAMBLE
;
229 DPRINTF(sc
, ATH_DBG_CONFIG
, "Rate: %2dMbps, ratecode: %2d\n",
230 rate
[i
].bitrate
/ 10, rate
[i
].hw_value
);
235 * Set/change channels. If the channel is really being changed, it's done
236 * by reseting the chip. To accomplish this we must first cleanup any pending
237 * DMA, then restart stuff.
239 int ath_set_channel(struct ath_softc
*sc
, struct ieee80211_hw
*hw
,
240 struct ath9k_channel
*hchan
)
242 struct ath_hw
*ah
= sc
->sc_ah
;
243 bool fastcc
= true, stopped
;
244 struct ieee80211_channel
*channel
= hw
->conf
.channel
;
247 if (sc
->sc_flags
& SC_OP_INVALID
)
253 * This is only performed if the channel settings have
256 * To switch channels clear any pending DMA operations;
257 * wait long enough for the RX fifo to drain, reset the
258 * hardware at the new frequency, and then re-enable
259 * the relevant bits of the h/w.
261 ath9k_hw_set_interrupts(ah
, 0);
262 ath_drain_all_txq(sc
, false);
263 stopped
= ath_stoprecv(sc
);
265 /* XXX: do not flush receive queue here. We don't want
266 * to flush data frames already in queue because of
267 * changing channel. */
269 if (!stopped
|| (sc
->sc_flags
& SC_OP_FULL_RESET
))
272 DPRINTF(sc
, ATH_DBG_CONFIG
,
273 "(%u MHz) -> (%u MHz), chanwidth: %d\n",
274 sc
->sc_ah
->curchan
->channel
,
275 channel
->center_freq
, sc
->tx_chan_width
);
277 spin_lock_bh(&sc
->sc_resetlock
);
279 r
= ath9k_hw_reset(ah
, hchan
, fastcc
);
281 DPRINTF(sc
, ATH_DBG_FATAL
,
282 "Unable to reset channel (%u Mhz) "
284 channel
->center_freq
, r
);
285 spin_unlock_bh(&sc
->sc_resetlock
);
288 spin_unlock_bh(&sc
->sc_resetlock
);
290 sc
->sc_flags
&= ~SC_OP_FULL_RESET
;
292 if (ath_startrecv(sc
) != 0) {
293 DPRINTF(sc
, ATH_DBG_FATAL
,
294 "Unable to restart recv logic\n");
298 ath_cache_conf_rate(sc
, &hw
->conf
);
299 ath_update_txpow(sc
);
300 ath9k_hw_set_interrupts(ah
, sc
->imask
);
301 ath9k_ps_restore(sc
);
306 * This routine performs the periodic noise floor calibration function
307 * that is used to adjust and optimize the chip performance. This
308 * takes environmental changes (location, temperature) into account.
309 * When the task is complete, it reschedules itself depending on the
310 * appropriate interval that was calculated.
312 static void ath_ani_calibrate(unsigned long data
)
314 struct ath_softc
*sc
= (struct ath_softc
*)data
;
315 struct ath_hw
*ah
= sc
->sc_ah
;
316 bool longcal
= false;
317 bool shortcal
= false;
318 bool aniflag
= false;
319 unsigned int timestamp
= jiffies_to_msecs(jiffies
);
320 u32 cal_interval
, short_cal_interval
;
322 short_cal_interval
= (ah
->opmode
== NL80211_IFTYPE_AP
) ?
323 ATH_AP_SHORT_CALINTERVAL
: ATH_STA_SHORT_CALINTERVAL
;
326 * don't calibrate when we're scanning.
327 * we are most likely not on our home channel.
329 if (sc
->sc_flags
& SC_OP_SCANNING
)
332 /* Long calibration runs independently of short calibration. */
333 if ((timestamp
- sc
->ani
.longcal_timer
) >= ATH_LONG_CALINTERVAL
) {
335 DPRINTF(sc
, ATH_DBG_ANI
, "longcal @%lu\n", jiffies
);
336 sc
->ani
.longcal_timer
= timestamp
;
339 /* Short calibration applies only while caldone is false */
340 if (!sc
->ani
.caldone
) {
341 if ((timestamp
- sc
->ani
.shortcal_timer
) >= short_cal_interval
) {
343 DPRINTF(sc
, ATH_DBG_ANI
, "shortcal @%lu\n", jiffies
);
344 sc
->ani
.shortcal_timer
= timestamp
;
345 sc
->ani
.resetcal_timer
= timestamp
;
348 if ((timestamp
- sc
->ani
.resetcal_timer
) >=
349 ATH_RESTART_CALINTERVAL
) {
350 sc
->ani
.caldone
= ath9k_hw_reset_calvalid(ah
);
352 sc
->ani
.resetcal_timer
= timestamp
;
356 /* Verify whether we must check ANI */
357 if ((timestamp
- sc
->ani
.checkani_timer
) >= ATH_ANI_POLLINTERVAL
) {
359 sc
->ani
.checkani_timer
= timestamp
;
362 /* Skip all processing if there's nothing to do. */
363 if (longcal
|| shortcal
|| aniflag
) {
364 /* Call ANI routine if necessary */
366 ath9k_hw_ani_monitor(ah
, &sc
->nodestats
, ah
->curchan
);
368 /* Perform calibration if necessary */
369 if (longcal
|| shortcal
) {
370 sc
->ani
.caldone
= ath9k_hw_calibrate(ah
, ah
->curchan
,
371 sc
->rx_chainmask
, longcal
);
374 sc
->ani
.noise_floor
= ath9k_hw_getchan_noise(ah
,
377 DPRINTF(sc
, ATH_DBG_ANI
," calibrate chan %u/%x nf: %d\n",
378 ah
->curchan
->channel
, ah
->curchan
->channelFlags
,
379 sc
->ani
.noise_floor
);
385 * Set timer interval based on previous results.
386 * The interval must be the shortest necessary to satisfy ANI,
387 * short calibration and long calibration.
389 cal_interval
= ATH_LONG_CALINTERVAL
;
390 if (sc
->sc_ah
->config
.enable_ani
)
391 cal_interval
= min(cal_interval
, (u32
)ATH_ANI_POLLINTERVAL
);
392 if (!sc
->ani
.caldone
)
393 cal_interval
= min(cal_interval
, (u32
)short_cal_interval
);
395 mod_timer(&sc
->ani
.timer
, jiffies
+ msecs_to_jiffies(cal_interval
));
398 static void ath_start_ani(struct ath_softc
*sc
)
400 unsigned long timestamp
= jiffies_to_msecs(jiffies
);
402 sc
->ani
.longcal_timer
= timestamp
;
403 sc
->ani
.shortcal_timer
= timestamp
;
404 sc
->ani
.checkani_timer
= timestamp
;
406 mod_timer(&sc
->ani
.timer
,
407 jiffies
+ msecs_to_jiffies(ATH_ANI_POLLINTERVAL
));
411 * Update tx/rx chainmask. For legacy association,
412 * hard code chainmask to 1x1, for 11n association, use
413 * the chainmask configuration, for bt coexistence, use
414 * the chainmask configuration even in legacy mode.
416 void ath_update_chainmask(struct ath_softc
*sc
, int is_ht
)
419 (sc
->sc_ah
->caps
.hw_caps
& ATH9K_HW_CAP_BT_COEX
)) {
420 sc
->tx_chainmask
= sc
->sc_ah
->caps
.tx_chainmask
;
421 sc
->rx_chainmask
= sc
->sc_ah
->caps
.rx_chainmask
;
423 sc
->tx_chainmask
= 1;
424 sc
->rx_chainmask
= 1;
427 DPRINTF(sc
, ATH_DBG_CONFIG
, "tx chmask: %d, rx chmask: %d\n",
428 sc
->tx_chainmask
, sc
->rx_chainmask
);
431 static void ath_node_attach(struct ath_softc
*sc
, struct ieee80211_sta
*sta
)
435 an
= (struct ath_node
*)sta
->drv_priv
;
437 if (sc
->sc_flags
& SC_OP_TXAGGR
) {
438 ath_tx_node_init(sc
, an
);
439 an
->maxampdu
= 1 << (IEEE80211_HTCAP_MAXRXAMPDU_FACTOR
+
440 sta
->ht_cap
.ampdu_factor
);
441 an
->mpdudensity
= parse_mpdudensity(sta
->ht_cap
.ampdu_density
);
445 static void ath_node_detach(struct ath_softc
*sc
, struct ieee80211_sta
*sta
)
447 struct ath_node
*an
= (struct ath_node
*)sta
->drv_priv
;
449 if (sc
->sc_flags
& SC_OP_TXAGGR
)
450 ath_tx_node_cleanup(sc
, an
);
453 static void ath9k_tasklet(unsigned long data
)
455 struct ath_softc
*sc
= (struct ath_softc
*)data
;
456 u32 status
= sc
->intrstatus
;
460 if (status
& ATH9K_INT_FATAL
) {
461 ath_reset(sc
, false);
462 ath9k_ps_restore(sc
);
466 if (status
& (ATH9K_INT_RX
| ATH9K_INT_RXEOL
| ATH9K_INT_RXORN
)) {
467 spin_lock_bh(&sc
->rx
.rxflushlock
);
468 ath_rx_tasklet(sc
, 0);
469 spin_unlock_bh(&sc
->rx
.rxflushlock
);
472 if (status
& ATH9K_INT_TX
)
475 /* re-enable hardware interrupt */
476 ath9k_hw_set_interrupts(sc
->sc_ah
, sc
->imask
);
477 ath9k_ps_restore(sc
);
480 irqreturn_t
ath_isr(int irq
, void *dev
)
482 #define SCHED_INTR ( \
492 struct ath_softc
*sc
= dev
;
493 struct ath_hw
*ah
= sc
->sc_ah
;
494 enum ath9k_int status
;
498 * The hardware is not ready/present, don't
499 * touch anything. Note this can happen early
500 * on if the IRQ is shared.
502 if (sc
->sc_flags
& SC_OP_INVALID
)
506 /* shared irq, not for us */
508 if (!ath9k_hw_intrpend(ah
))
512 * Figure out the reason(s) for the interrupt. Note
513 * that the hal returns a pseudo-ISR that may include
514 * bits we haven't explicitly enabled so we mask the
515 * value to insure we only process bits we requested.
517 ath9k_hw_getisr(ah
, &status
); /* NB: clears ISR too */
518 status
&= sc
->imask
; /* discard unasked-for bits */
521 * If there are no status bits set, then this interrupt was not
522 * for me (should have been caught above).
527 /* Cache the status */
528 sc
->intrstatus
= status
;
530 if (status
& SCHED_INTR
)
534 * If a FATAL or RXORN interrupt is received, we have to reset the
537 if (status
& (ATH9K_INT_FATAL
| ATH9K_INT_RXORN
))
540 if (status
& ATH9K_INT_SWBA
)
541 tasklet_schedule(&sc
->bcon_tasklet
);
543 if (status
& ATH9K_INT_TXURN
)
544 ath9k_hw_updatetxtriglevel(ah
, true);
546 if (status
& ATH9K_INT_MIB
) {
548 * Disable interrupts until we service the MIB
549 * interrupt; otherwise it will continue to
552 ath9k_hw_set_interrupts(ah
, 0);
554 * Let the hal handle the event. We assume
555 * it will clear whatever condition caused
558 ath9k_hw_procmibevent(ah
, &sc
->nodestats
);
559 ath9k_hw_set_interrupts(ah
, sc
->imask
);
562 if (!(ah
->caps
.hw_caps
& ATH9K_HW_CAP_AUTOSLEEP
))
563 if (status
& ATH9K_INT_TIM_TIMER
) {
564 /* Clear RxAbort bit so that we can
566 ath9k_hw_setpower(ah
, ATH9K_PM_AWAKE
);
567 ath9k_hw_setrxabort(sc
->sc_ah
, 0);
568 sc
->sc_flags
|= SC_OP_WAIT_FOR_BEACON
;
573 ath_debug_stat_interrupt(sc
, status
);
576 /* turn off every interrupt except SWBA */
577 ath9k_hw_set_interrupts(ah
, (sc
->imask
& ATH9K_INT_SWBA
));
578 tasklet_schedule(&sc
->intr_tq
);
586 static u32
ath_get_extchanmode(struct ath_softc
*sc
,
587 struct ieee80211_channel
*chan
,
588 enum nl80211_channel_type channel_type
)
592 switch (chan
->band
) {
593 case IEEE80211_BAND_2GHZ
:
594 switch(channel_type
) {
595 case NL80211_CHAN_NO_HT
:
596 case NL80211_CHAN_HT20
:
597 chanmode
= CHANNEL_G_HT20
;
599 case NL80211_CHAN_HT40PLUS
:
600 chanmode
= CHANNEL_G_HT40PLUS
;
602 case NL80211_CHAN_HT40MINUS
:
603 chanmode
= CHANNEL_G_HT40MINUS
;
607 case IEEE80211_BAND_5GHZ
:
608 switch(channel_type
) {
609 case NL80211_CHAN_NO_HT
:
610 case NL80211_CHAN_HT20
:
611 chanmode
= CHANNEL_A_HT20
;
613 case NL80211_CHAN_HT40PLUS
:
614 chanmode
= CHANNEL_A_HT40PLUS
;
616 case NL80211_CHAN_HT40MINUS
:
617 chanmode
= CHANNEL_A_HT40MINUS
;
628 static int ath_setkey_tkip(struct ath_softc
*sc
, u16 keyix
, const u8
*key
,
629 struct ath9k_keyval
*hk
, const u8
*addr
,
635 key_txmic
= key
+ NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY
;
636 key_rxmic
= key
+ NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY
;
640 * Group key installation - only two key cache entries are used
641 * regardless of splitmic capability since group key is only
642 * used either for TX or RX.
645 memcpy(hk
->kv_mic
, key_txmic
, sizeof(hk
->kv_mic
));
646 memcpy(hk
->kv_txmic
, key_txmic
, sizeof(hk
->kv_mic
));
648 memcpy(hk
->kv_mic
, key_rxmic
, sizeof(hk
->kv_mic
));
649 memcpy(hk
->kv_txmic
, key_rxmic
, sizeof(hk
->kv_mic
));
651 return ath9k_hw_set_keycache_entry(sc
->sc_ah
, keyix
, hk
, addr
);
654 /* TX and RX keys share the same key cache entry. */
655 memcpy(hk
->kv_mic
, key_rxmic
, sizeof(hk
->kv_mic
));
656 memcpy(hk
->kv_txmic
, key_txmic
, sizeof(hk
->kv_txmic
));
657 return ath9k_hw_set_keycache_entry(sc
->sc_ah
, keyix
, hk
, addr
);
660 /* Separate key cache entries for TX and RX */
662 /* TX key goes at first index, RX key at +32. */
663 memcpy(hk
->kv_mic
, key_txmic
, sizeof(hk
->kv_mic
));
664 if (!ath9k_hw_set_keycache_entry(sc
->sc_ah
, keyix
, hk
, NULL
)) {
665 /* TX MIC entry failed. No need to proceed further */
666 DPRINTF(sc
, ATH_DBG_FATAL
,
667 "Setting TX MIC Key Failed\n");
671 memcpy(hk
->kv_mic
, key_rxmic
, sizeof(hk
->kv_mic
));
672 /* XXX delete tx key on failure? */
673 return ath9k_hw_set_keycache_entry(sc
->sc_ah
, keyix
+ 32, hk
, addr
);
676 static int ath_reserve_key_cache_slot_tkip(struct ath_softc
*sc
)
680 for (i
= IEEE80211_WEP_NKID
; i
< sc
->keymax
/ 2; i
++) {
681 if (test_bit(i
, sc
->keymap
) ||
682 test_bit(i
+ 64, sc
->keymap
))
683 continue; /* At least one part of TKIP key allocated */
685 (test_bit(i
+ 32, sc
->keymap
) ||
686 test_bit(i
+ 64 + 32, sc
->keymap
)))
687 continue; /* At least one part of TKIP key allocated */
689 /* Found a free slot for a TKIP key */
695 static int ath_reserve_key_cache_slot(struct ath_softc
*sc
)
699 /* First, try to find slots that would not be available for TKIP. */
701 for (i
= IEEE80211_WEP_NKID
; i
< sc
->keymax
/ 4; i
++) {
702 if (!test_bit(i
, sc
->keymap
) &&
703 (test_bit(i
+ 32, sc
->keymap
) ||
704 test_bit(i
+ 64, sc
->keymap
) ||
705 test_bit(i
+ 64 + 32, sc
->keymap
)))
707 if (!test_bit(i
+ 32, sc
->keymap
) &&
708 (test_bit(i
, sc
->keymap
) ||
709 test_bit(i
+ 64, sc
->keymap
) ||
710 test_bit(i
+ 64 + 32, sc
->keymap
)))
712 if (!test_bit(i
+ 64, sc
->keymap
) &&
713 (test_bit(i
, sc
->keymap
) ||
714 test_bit(i
+ 32, sc
->keymap
) ||
715 test_bit(i
+ 64 + 32, sc
->keymap
)))
717 if (!test_bit(i
+ 64 + 32, sc
->keymap
) &&
718 (test_bit(i
, sc
->keymap
) ||
719 test_bit(i
+ 32, sc
->keymap
) ||
720 test_bit(i
+ 64, sc
->keymap
)))
724 for (i
= IEEE80211_WEP_NKID
; i
< sc
->keymax
/ 2; i
++) {
725 if (!test_bit(i
, sc
->keymap
) &&
726 test_bit(i
+ 64, sc
->keymap
))
728 if (test_bit(i
, sc
->keymap
) &&
729 !test_bit(i
+ 64, sc
->keymap
))
734 /* No partially used TKIP slots, pick any available slot */
735 for (i
= IEEE80211_WEP_NKID
; i
< sc
->keymax
; i
++) {
736 /* Do not allow slots that could be needed for TKIP group keys
737 * to be used. This limitation could be removed if we know that
738 * TKIP will not be used. */
739 if (i
>= 64 && i
< 64 + IEEE80211_WEP_NKID
)
742 if (i
>= 32 && i
< 32 + IEEE80211_WEP_NKID
)
744 if (i
>= 64 + 32 && i
< 64 + 32 + IEEE80211_WEP_NKID
)
748 if (!test_bit(i
, sc
->keymap
))
749 return i
; /* Found a free slot for a key */
752 /* No free slot found */
756 static int ath_key_config(struct ath_softc
*sc
,
757 struct ieee80211_vif
*vif
,
758 struct ieee80211_sta
*sta
,
759 struct ieee80211_key_conf
*key
)
761 struct ath9k_keyval hk
;
762 const u8
*mac
= NULL
;
766 memset(&hk
, 0, sizeof(hk
));
770 hk
.kv_type
= ATH9K_CIPHER_WEP
;
773 hk
.kv_type
= ATH9K_CIPHER_TKIP
;
776 hk
.kv_type
= ATH9K_CIPHER_AES_CCM
;
782 hk
.kv_len
= key
->keylen
;
783 memcpy(hk
.kv_val
, key
->key
, key
->keylen
);
785 if (!(key
->flags
& IEEE80211_KEY_FLAG_PAIRWISE
)) {
786 /* For now, use the default keys for broadcast keys. This may
787 * need to change with virtual interfaces. */
789 } else if (key
->keyidx
) {
794 if (vif
->type
!= NL80211_IFTYPE_AP
) {
795 /* Only keyidx 0 should be used with unicast key, but
796 * allow this for client mode for now. */
805 if (key
->alg
== ALG_TKIP
)
806 idx
= ath_reserve_key_cache_slot_tkip(sc
);
808 idx
= ath_reserve_key_cache_slot(sc
);
810 return -ENOSPC
; /* no free key cache entries */
813 if (key
->alg
== ALG_TKIP
)
814 ret
= ath_setkey_tkip(sc
, idx
, key
->key
, &hk
, mac
,
815 vif
->type
== NL80211_IFTYPE_AP
);
817 ret
= ath9k_hw_set_keycache_entry(sc
->sc_ah
, idx
, &hk
, mac
);
822 set_bit(idx
, sc
->keymap
);
823 if (key
->alg
== ALG_TKIP
) {
824 set_bit(idx
+ 64, sc
->keymap
);
826 set_bit(idx
+ 32, sc
->keymap
);
827 set_bit(idx
+ 64 + 32, sc
->keymap
);
834 static void ath_key_delete(struct ath_softc
*sc
, struct ieee80211_key_conf
*key
)
836 ath9k_hw_keyreset(sc
->sc_ah
, key
->hw_key_idx
);
837 if (key
->hw_key_idx
< IEEE80211_WEP_NKID
)
840 clear_bit(key
->hw_key_idx
, sc
->keymap
);
841 if (key
->alg
!= ALG_TKIP
)
844 clear_bit(key
->hw_key_idx
+ 64, sc
->keymap
);
846 clear_bit(key
->hw_key_idx
+ 32, sc
->keymap
);
847 clear_bit(key
->hw_key_idx
+ 64 + 32, sc
->keymap
);
851 static void setup_ht_cap(struct ath_softc
*sc
,
852 struct ieee80211_sta_ht_cap
*ht_info
)
854 #define ATH9K_HT_CAP_MAXRXAMPDU_65536 0x3 /* 2 ^ 16 */
855 #define ATH9K_HT_CAP_MPDUDENSITY_8 0x6 /* 8 usec */
857 ht_info
->ht_supported
= true;
858 ht_info
->cap
= IEEE80211_HT_CAP_SUP_WIDTH_20_40
|
859 IEEE80211_HT_CAP_SM_PS
|
860 IEEE80211_HT_CAP_SGI_40
|
861 IEEE80211_HT_CAP_DSSSCCK40
;
863 ht_info
->ampdu_factor
= ATH9K_HT_CAP_MAXRXAMPDU_65536
;
864 ht_info
->ampdu_density
= ATH9K_HT_CAP_MPDUDENSITY_8
;
866 /* set up supported mcs set */
867 memset(&ht_info
->mcs
, 0, sizeof(ht_info
->mcs
));
869 switch(sc
->rx_chainmask
) {
871 ht_info
->mcs
.rx_mask
[0] = 0xff;
877 ht_info
->mcs
.rx_mask
[0] = 0xff;
878 ht_info
->mcs
.rx_mask
[1] = 0xff;
882 ht_info
->mcs
.tx_params
= IEEE80211_HT_MCS_TX_DEFINED
;
885 static void ath9k_bss_assoc_info(struct ath_softc
*sc
,
886 struct ieee80211_vif
*vif
,
887 struct ieee80211_bss_conf
*bss_conf
)
889 struct ath_vif
*avp
= (void *)vif
->drv_priv
;
891 if (bss_conf
->assoc
) {
892 DPRINTF(sc
, ATH_DBG_CONFIG
, "Bss Info ASSOC %d, bssid: %pM\n",
893 bss_conf
->aid
, sc
->curbssid
);
895 /* New association, store aid */
896 if (avp
->av_opmode
== NL80211_IFTYPE_STATION
) {
897 sc
->curaid
= bss_conf
->aid
;
898 ath9k_hw_write_associd(sc
);
901 /* Configure the beacon */
902 ath_beacon_config(sc
, vif
);
904 /* Reset rssi stats */
905 sc
->nodestats
.ns_avgbrssi
= ATH_RSSI_DUMMY_MARKER
;
906 sc
->nodestats
.ns_avgrssi
= ATH_RSSI_DUMMY_MARKER
;
907 sc
->nodestats
.ns_avgtxrssi
= ATH_RSSI_DUMMY_MARKER
;
908 sc
->nodestats
.ns_avgtxrate
= ATH_RATE_DUMMY_MARKER
;
912 DPRINTF(sc
, ATH_DBG_CONFIG
, "Bss Info DISASSOC\n");
917 /********************************/
919 /********************************/
921 static void ath_led_blink_work(struct work_struct
*work
)
923 struct ath_softc
*sc
= container_of(work
, struct ath_softc
,
924 ath_led_blink_work
.work
);
926 if (!(sc
->sc_flags
& SC_OP_LED_ASSOCIATED
))
929 if ((sc
->led_on_duration
== ATH_LED_ON_DURATION_IDLE
) ||
930 (sc
->led_off_duration
== ATH_LED_OFF_DURATION_IDLE
))
931 ath9k_hw_set_gpio(sc
->sc_ah
, ATH_LED_PIN
, 0);
933 ath9k_hw_set_gpio(sc
->sc_ah
, ATH_LED_PIN
,
934 (sc
->sc_flags
& SC_OP_LED_ON
) ? 1 : 0);
936 queue_delayed_work(sc
->hw
->workqueue
, &sc
->ath_led_blink_work
,
937 (sc
->sc_flags
& SC_OP_LED_ON
) ?
938 msecs_to_jiffies(sc
->led_off_duration
) :
939 msecs_to_jiffies(sc
->led_on_duration
));
941 sc
->led_on_duration
= sc
->led_on_cnt
?
942 max((ATH_LED_ON_DURATION_IDLE
- sc
->led_on_cnt
), 25) :
943 ATH_LED_ON_DURATION_IDLE
;
944 sc
->led_off_duration
= sc
->led_off_cnt
?
945 max((ATH_LED_OFF_DURATION_IDLE
- sc
->led_off_cnt
), 10) :
946 ATH_LED_OFF_DURATION_IDLE
;
947 sc
->led_on_cnt
= sc
->led_off_cnt
= 0;
948 if (sc
->sc_flags
& SC_OP_LED_ON
)
949 sc
->sc_flags
&= ~SC_OP_LED_ON
;
951 sc
->sc_flags
|= SC_OP_LED_ON
;
954 static void ath_led_brightness(struct led_classdev
*led_cdev
,
955 enum led_brightness brightness
)
957 struct ath_led
*led
= container_of(led_cdev
, struct ath_led
, led_cdev
);
958 struct ath_softc
*sc
= led
->sc
;
960 switch (brightness
) {
962 if (led
->led_type
== ATH_LED_ASSOC
||
963 led
->led_type
== ATH_LED_RADIO
) {
964 ath9k_hw_set_gpio(sc
->sc_ah
, ATH_LED_PIN
,
965 (led
->led_type
== ATH_LED_RADIO
));
966 sc
->sc_flags
&= ~SC_OP_LED_ASSOCIATED
;
967 if (led
->led_type
== ATH_LED_RADIO
)
968 sc
->sc_flags
&= ~SC_OP_LED_ON
;
974 if (led
->led_type
== ATH_LED_ASSOC
) {
975 sc
->sc_flags
|= SC_OP_LED_ASSOCIATED
;
976 queue_delayed_work(sc
->hw
->workqueue
,
977 &sc
->ath_led_blink_work
, 0);
978 } else if (led
->led_type
== ATH_LED_RADIO
) {
979 ath9k_hw_set_gpio(sc
->sc_ah
, ATH_LED_PIN
, 0);
980 sc
->sc_flags
|= SC_OP_LED_ON
;
990 static int ath_register_led(struct ath_softc
*sc
, struct ath_led
*led
,
996 led
->led_cdev
.name
= led
->name
;
997 led
->led_cdev
.default_trigger
= trigger
;
998 led
->led_cdev
.brightness_set
= ath_led_brightness
;
1000 ret
= led_classdev_register(wiphy_dev(sc
->hw
->wiphy
), &led
->led_cdev
);
1002 DPRINTF(sc
, ATH_DBG_FATAL
,
1003 "Failed to register led:%s", led
->name
);
1005 led
->registered
= 1;
1009 static void ath_unregister_led(struct ath_led
*led
)
1011 if (led
->registered
) {
1012 led_classdev_unregister(&led
->led_cdev
);
1013 led
->registered
= 0;
1017 static void ath_deinit_leds(struct ath_softc
*sc
)
1019 cancel_delayed_work_sync(&sc
->ath_led_blink_work
);
1020 ath_unregister_led(&sc
->assoc_led
);
1021 sc
->sc_flags
&= ~SC_OP_LED_ASSOCIATED
;
1022 ath_unregister_led(&sc
->tx_led
);
1023 ath_unregister_led(&sc
->rx_led
);
1024 ath_unregister_led(&sc
->radio_led
);
1025 ath9k_hw_set_gpio(sc
->sc_ah
, ATH_LED_PIN
, 1);
1028 static void ath_init_leds(struct ath_softc
*sc
)
1033 /* Configure gpio 1 for output */
1034 ath9k_hw_cfg_output(sc
->sc_ah
, ATH_LED_PIN
,
1035 AR_GPIO_OUTPUT_MUX_AS_OUTPUT
);
1036 /* LED off, active low */
1037 ath9k_hw_set_gpio(sc
->sc_ah
, ATH_LED_PIN
, 1);
1039 INIT_DELAYED_WORK(&sc
->ath_led_blink_work
, ath_led_blink_work
);
1041 trigger
= ieee80211_get_radio_led_name(sc
->hw
);
1042 snprintf(sc
->radio_led
.name
, sizeof(sc
->radio_led
.name
),
1043 "ath9k-%s::radio", wiphy_name(sc
->hw
->wiphy
));
1044 ret
= ath_register_led(sc
, &sc
->radio_led
, trigger
);
1045 sc
->radio_led
.led_type
= ATH_LED_RADIO
;
1049 trigger
= ieee80211_get_assoc_led_name(sc
->hw
);
1050 snprintf(sc
->assoc_led
.name
, sizeof(sc
->assoc_led
.name
),
1051 "ath9k-%s::assoc", wiphy_name(sc
->hw
->wiphy
));
1052 ret
= ath_register_led(sc
, &sc
->assoc_led
, trigger
);
1053 sc
->assoc_led
.led_type
= ATH_LED_ASSOC
;
1057 trigger
= ieee80211_get_tx_led_name(sc
->hw
);
1058 snprintf(sc
->tx_led
.name
, sizeof(sc
->tx_led
.name
),
1059 "ath9k-%s::tx", wiphy_name(sc
->hw
->wiphy
));
1060 ret
= ath_register_led(sc
, &sc
->tx_led
, trigger
);
1061 sc
->tx_led
.led_type
= ATH_LED_TX
;
1065 trigger
= ieee80211_get_rx_led_name(sc
->hw
);
1066 snprintf(sc
->rx_led
.name
, sizeof(sc
->rx_led
.name
),
1067 "ath9k-%s::rx", wiphy_name(sc
->hw
->wiphy
));
1068 ret
= ath_register_led(sc
, &sc
->rx_led
, trigger
);
1069 sc
->rx_led
.led_type
= ATH_LED_RX
;
1076 ath_deinit_leds(sc
);
1079 void ath_radio_enable(struct ath_softc
*sc
)
1081 struct ath_hw
*ah
= sc
->sc_ah
;
1082 struct ieee80211_channel
*channel
= sc
->hw
->conf
.channel
;
1085 ath9k_ps_wakeup(sc
);
1086 ath9k_hw_configpcipowersave(ah
, 0);
1088 spin_lock_bh(&sc
->sc_resetlock
);
1089 r
= ath9k_hw_reset(ah
, ah
->curchan
, false);
1091 DPRINTF(sc
, ATH_DBG_FATAL
,
1092 "Unable to reset channel %u (%uMhz) ",
1093 "reset status %d\n",
1094 channel
->center_freq
, r
);
1096 spin_unlock_bh(&sc
->sc_resetlock
);
1098 ath_update_txpow(sc
);
1099 if (ath_startrecv(sc
) != 0) {
1100 DPRINTF(sc
, ATH_DBG_FATAL
,
1101 "Unable to restart recv logic\n");
1105 if (sc
->sc_flags
& SC_OP_BEACONS
)
1106 ath_beacon_config(sc
, NULL
); /* restart beacons */
1108 /* Re-Enable interrupts */
1109 ath9k_hw_set_interrupts(ah
, sc
->imask
);
1112 ath9k_hw_cfg_output(ah
, ATH_LED_PIN
,
1113 AR_GPIO_OUTPUT_MUX_AS_OUTPUT
);
1114 ath9k_hw_set_gpio(ah
, ATH_LED_PIN
, 0);
1116 ieee80211_wake_queues(sc
->hw
);
1117 ath9k_ps_restore(sc
);
1120 void ath_radio_disable(struct ath_softc
*sc
)
1122 struct ath_hw
*ah
= sc
->sc_ah
;
1123 struct ieee80211_channel
*channel
= sc
->hw
->conf
.channel
;
1126 ath9k_ps_wakeup(sc
);
1127 ieee80211_stop_queues(sc
->hw
);
1130 ath9k_hw_set_gpio(ah
, ATH_LED_PIN
, 1);
1131 ath9k_hw_cfg_gpio_input(ah
, ATH_LED_PIN
);
1133 /* Disable interrupts */
1134 ath9k_hw_set_interrupts(ah
, 0);
1136 ath_drain_all_txq(sc
, false); /* clear pending tx frames */
1137 ath_stoprecv(sc
); /* turn off frame recv */
1138 ath_flushrecv(sc
); /* flush recv queue */
1140 spin_lock_bh(&sc
->sc_resetlock
);
1141 r
= ath9k_hw_reset(ah
, ah
->curchan
, false);
1143 DPRINTF(sc
, ATH_DBG_FATAL
,
1144 "Unable to reset channel %u (%uMhz) "
1145 "reset status %d\n",
1146 channel
->center_freq
, r
);
1148 spin_unlock_bh(&sc
->sc_resetlock
);
1150 ath9k_hw_phy_disable(ah
);
1151 ath9k_hw_configpcipowersave(ah
, 1);
1152 ath9k_hw_setpower(ah
, ATH9K_PM_FULL_SLEEP
);
1153 ath9k_ps_restore(sc
);
1156 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1158 /*******************/
1160 /*******************/
1162 static bool ath_is_rfkill_set(struct ath_softc
*sc
)
1164 struct ath_hw
*ah
= sc
->sc_ah
;
1166 return ath9k_hw_gpio_get(ah
, ah
->rfkill_gpio
) ==
1167 ah
->rfkill_polarity
;
1170 /* h/w rfkill poll function */
1171 static void ath_rfkill_poll(struct work_struct
*work
)
1173 struct ath_softc
*sc
= container_of(work
, struct ath_softc
,
1174 rf_kill
.rfkill_poll
.work
);
1177 if (sc
->sc_flags
& SC_OP_INVALID
)
1180 radio_on
= !ath_is_rfkill_set(sc
);
1183 * enable/disable radio only when there is a
1184 * state change in RF switch
1186 if (radio_on
== !!(sc
->sc_flags
& SC_OP_RFKILL_HW_BLOCKED
)) {
1187 enum rfkill_state state
;
1189 if (sc
->sc_flags
& SC_OP_RFKILL_SW_BLOCKED
) {
1190 state
= radio_on
? RFKILL_STATE_SOFT_BLOCKED
1191 : RFKILL_STATE_HARD_BLOCKED
;
1192 } else if (radio_on
) {
1193 ath_radio_enable(sc
);
1194 state
= RFKILL_STATE_UNBLOCKED
;
1196 ath_radio_disable(sc
);
1197 state
= RFKILL_STATE_HARD_BLOCKED
;
1200 if (state
== RFKILL_STATE_HARD_BLOCKED
)
1201 sc
->sc_flags
|= SC_OP_RFKILL_HW_BLOCKED
;
1203 sc
->sc_flags
&= ~SC_OP_RFKILL_HW_BLOCKED
;
1205 rfkill_force_state(sc
->rf_kill
.rfkill
, state
);
1208 queue_delayed_work(sc
->hw
->workqueue
, &sc
->rf_kill
.rfkill_poll
,
1209 msecs_to_jiffies(ATH_RFKILL_POLL_INTERVAL
));
1212 /* s/w rfkill handler */
1213 static int ath_sw_toggle_radio(void *data
, enum rfkill_state state
)
1215 struct ath_softc
*sc
= data
;
1218 case RFKILL_STATE_SOFT_BLOCKED
:
1219 if (!(sc
->sc_flags
& (SC_OP_RFKILL_HW_BLOCKED
|
1220 SC_OP_RFKILL_SW_BLOCKED
)))
1221 ath_radio_disable(sc
);
1222 sc
->sc_flags
|= SC_OP_RFKILL_SW_BLOCKED
;
1224 case RFKILL_STATE_UNBLOCKED
:
1225 if ((sc
->sc_flags
& SC_OP_RFKILL_SW_BLOCKED
)) {
1226 sc
->sc_flags
&= ~SC_OP_RFKILL_SW_BLOCKED
;
1227 if (sc
->sc_flags
& SC_OP_RFKILL_HW_BLOCKED
) {
1228 DPRINTF(sc
, ATH_DBG_FATAL
, "Can't turn on the"
1229 "radio as it is disabled by h/w\n");
1232 ath_radio_enable(sc
);
1240 /* Init s/w rfkill */
1241 static int ath_init_sw_rfkill(struct ath_softc
*sc
)
1243 sc
->rf_kill
.rfkill
= rfkill_allocate(wiphy_dev(sc
->hw
->wiphy
),
1245 if (!sc
->rf_kill
.rfkill
) {
1246 DPRINTF(sc
, ATH_DBG_FATAL
, "Failed to allocate rfkill\n");
1250 snprintf(sc
->rf_kill
.rfkill_name
, sizeof(sc
->rf_kill
.rfkill_name
),
1251 "ath9k-%s::rfkill", wiphy_name(sc
->hw
->wiphy
));
1252 sc
->rf_kill
.rfkill
->name
= sc
->rf_kill
.rfkill_name
;
1253 sc
->rf_kill
.rfkill
->data
= sc
;
1254 sc
->rf_kill
.rfkill
->toggle_radio
= ath_sw_toggle_radio
;
1255 sc
->rf_kill
.rfkill
->state
= RFKILL_STATE_UNBLOCKED
;
1260 /* Deinitialize rfkill */
1261 static void ath_deinit_rfkill(struct ath_softc
*sc
)
1263 if (sc
->sc_ah
->caps
.hw_caps
& ATH9K_HW_CAP_RFSILENT
)
1264 cancel_delayed_work_sync(&sc
->rf_kill
.rfkill_poll
);
1266 if (sc
->sc_flags
& SC_OP_RFKILL_REGISTERED
) {
1267 rfkill_unregister(sc
->rf_kill
.rfkill
);
1268 sc
->sc_flags
&= ~SC_OP_RFKILL_REGISTERED
;
1269 sc
->rf_kill
.rfkill
= NULL
;
1273 static int ath_start_rfkill_poll(struct ath_softc
*sc
)
1275 if (sc
->sc_ah
->caps
.hw_caps
& ATH9K_HW_CAP_RFSILENT
)
1276 queue_delayed_work(sc
->hw
->workqueue
,
1277 &sc
->rf_kill
.rfkill_poll
, 0);
1279 if (!(sc
->sc_flags
& SC_OP_RFKILL_REGISTERED
)) {
1280 if (rfkill_register(sc
->rf_kill
.rfkill
)) {
1281 DPRINTF(sc
, ATH_DBG_FATAL
,
1282 "Unable to register rfkill\n");
1283 rfkill_free(sc
->rf_kill
.rfkill
);
1285 /* Deinitialize the device */
1289 sc
->sc_flags
|= SC_OP_RFKILL_REGISTERED
;
1295 #endif /* CONFIG_RFKILL */
1297 void ath_cleanup(struct ath_softc
*sc
)
1300 free_irq(sc
->irq
, sc
);
1301 ath_bus_cleanup(sc
);
1302 kfree(sc
->sec_wiphy
);
1303 ieee80211_free_hw(sc
->hw
);
1306 void ath_detach(struct ath_softc
*sc
)
1308 struct ieee80211_hw
*hw
= sc
->hw
;
1311 ath9k_ps_wakeup(sc
);
1313 DPRINTF(sc
, ATH_DBG_CONFIG
, "Detach ATH hw\n");
1315 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1316 ath_deinit_rfkill(sc
);
1318 ath_deinit_leds(sc
);
1319 cancel_work_sync(&sc
->chan_work
);
1320 cancel_delayed_work_sync(&sc
->wiphy_work
);
1322 for (i
= 0; i
< sc
->num_sec_wiphy
; i
++) {
1323 struct ath_wiphy
*aphy
= sc
->sec_wiphy
[i
];
1326 sc
->sec_wiphy
[i
] = NULL
;
1327 ieee80211_unregister_hw(aphy
->hw
);
1328 ieee80211_free_hw(aphy
->hw
);
1330 ieee80211_unregister_hw(hw
);
1334 tasklet_kill(&sc
->intr_tq
);
1335 tasklet_kill(&sc
->bcon_tasklet
);
1337 if (!(sc
->sc_flags
& SC_OP_INVALID
))
1338 ath9k_hw_setpower(sc
->sc_ah
, ATH9K_PM_AWAKE
);
1340 /* cleanup tx queues */
1341 for (i
= 0; i
< ATH9K_NUM_TX_QUEUES
; i
++)
1342 if (ATH_TXQ_SETUP(sc
, i
))
1343 ath_tx_cleanupq(sc
, &sc
->tx
.txq
[i
]);
1345 ath9k_hw_detach(sc
->sc_ah
);
1346 ath9k_exit_debug(sc
);
1347 ath9k_ps_restore(sc
);
1350 static int ath9k_reg_notifier(struct wiphy
*wiphy
,
1351 struct regulatory_request
*request
)
1353 struct ieee80211_hw
*hw
= wiphy_to_ieee80211_hw(wiphy
);
1354 struct ath_wiphy
*aphy
= hw
->priv
;
1355 struct ath_softc
*sc
= aphy
->sc
;
1356 struct ath_regulatory
*reg
= &sc
->sc_ah
->regulatory
;
1358 return ath_reg_notifier_apply(wiphy
, request
, reg
);
1361 static int ath_init(u16 devid
, struct ath_softc
*sc
)
1363 struct ath_hw
*ah
= NULL
;
1368 /* XXX: hardware will not be ready until ath_open() being called */
1369 sc
->sc_flags
|= SC_OP_INVALID
;
1371 if (ath9k_init_debug(sc
) < 0)
1372 printk(KERN_ERR
"Unable to create debugfs files\n");
1374 spin_lock_init(&sc
->wiphy_lock
);
1375 spin_lock_init(&sc
->sc_resetlock
);
1376 spin_lock_init(&sc
->sc_serial_rw
);
1377 mutex_init(&sc
->mutex
);
1378 tasklet_init(&sc
->intr_tq
, ath9k_tasklet
, (unsigned long)sc
);
1379 tasklet_init(&sc
->bcon_tasklet
, ath_beacon_tasklet
,
1383 * Cache line size is used to size and align various
1384 * structures used to communicate with the hardware.
1386 ath_read_cachesize(sc
, &csz
);
1387 /* XXX assert csz is non-zero */
1388 sc
->cachelsz
= csz
<< 2; /* convert to bytes */
1390 ah
= ath9k_hw_attach(devid
, sc
, &status
);
1392 DPRINTF(sc
, ATH_DBG_FATAL
,
1393 "Unable to attach hardware; HAL status %d\n", status
);
1399 /* Get the hardware key cache size. */
1400 sc
->keymax
= ah
->caps
.keycache_size
;
1401 if (sc
->keymax
> ATH_KEYMAX
) {
1402 DPRINTF(sc
, ATH_DBG_ANY
,
1403 "Warning, using only %u entries in %u key cache\n",
1404 ATH_KEYMAX
, sc
->keymax
);
1405 sc
->keymax
= ATH_KEYMAX
;
1409 * Reset the key cache since some parts do not
1410 * reset the contents on initial power up.
1412 for (i
= 0; i
< sc
->keymax
; i
++)
1413 ath9k_hw_keyreset(ah
, (u16
) i
);
1415 error
= ath_regd_init(&sc
->sc_ah
->regulatory
, sc
->hw
->wiphy
,
1416 ath9k_reg_notifier
);
1420 /* default to MONITOR mode */
1421 sc
->sc_ah
->opmode
= NL80211_IFTYPE_MONITOR
;
1423 /* Setup rate tables */
1425 ath_rate_attach(sc
);
1426 ath_setup_rates(sc
, IEEE80211_BAND_2GHZ
);
1427 ath_setup_rates(sc
, IEEE80211_BAND_5GHZ
);
1430 * Allocate hardware transmit queues: one queue for
1431 * beacon frames and one data queue for each QoS
1432 * priority. Note that the hal handles reseting
1433 * these queues at the needed time.
1435 sc
->beacon
.beaconq
= ath_beaconq_setup(ah
);
1436 if (sc
->beacon
.beaconq
== -1) {
1437 DPRINTF(sc
, ATH_DBG_FATAL
,
1438 "Unable to setup a beacon xmit queue\n");
1442 sc
->beacon
.cabq
= ath_txq_setup(sc
, ATH9K_TX_QUEUE_CAB
, 0);
1443 if (sc
->beacon
.cabq
== NULL
) {
1444 DPRINTF(sc
, ATH_DBG_FATAL
,
1445 "Unable to setup CAB xmit queue\n");
1450 sc
->config
.cabqReadytime
= ATH_CABQ_READY_TIME
;
1451 ath_cabq_update(sc
);
1453 for (i
= 0; i
< ARRAY_SIZE(sc
->tx
.hwq_map
); i
++)
1454 sc
->tx
.hwq_map
[i
] = -1;
1456 /* Setup data queues */
1457 /* NB: ensure BK queue is the lowest priority h/w queue */
1458 if (!ath_tx_setup(sc
, ATH9K_WME_AC_BK
)) {
1459 DPRINTF(sc
, ATH_DBG_FATAL
,
1460 "Unable to setup xmit queue for BK traffic\n");
1465 if (!ath_tx_setup(sc
, ATH9K_WME_AC_BE
)) {
1466 DPRINTF(sc
, ATH_DBG_FATAL
,
1467 "Unable to setup xmit queue for BE traffic\n");
1471 if (!ath_tx_setup(sc
, ATH9K_WME_AC_VI
)) {
1472 DPRINTF(sc
, ATH_DBG_FATAL
,
1473 "Unable to setup xmit queue for VI traffic\n");
1477 if (!ath_tx_setup(sc
, ATH9K_WME_AC_VO
)) {
1478 DPRINTF(sc
, ATH_DBG_FATAL
,
1479 "Unable to setup xmit queue for VO traffic\n");
1484 /* Initializes the noise floor to a reasonable default value.
1485 * Later on this will be updated during ANI processing. */
1487 sc
->ani
.noise_floor
= ATH_DEFAULT_NOISE_FLOOR
;
1488 setup_timer(&sc
->ani
.timer
, ath_ani_calibrate
, (unsigned long)sc
);
1490 if (ath9k_hw_getcapability(ah
, ATH9K_CAP_CIPHER
,
1491 ATH9K_CIPHER_TKIP
, NULL
)) {
1493 * Whether we should enable h/w TKIP MIC.
1494 * XXX: if we don't support WME TKIP MIC, then we wouldn't
1495 * report WMM capable, so it's always safe to turn on
1496 * TKIP MIC in this case.
1498 ath9k_hw_setcapability(sc
->sc_ah
, ATH9K_CAP_TKIP_MIC
,
1503 * Check whether the separate key cache entries
1504 * are required to handle both tx+rx MIC keys.
1505 * With split mic keys the number of stations is limited
1506 * to 27 otherwise 59.
1508 if (ath9k_hw_getcapability(ah
, ATH9K_CAP_CIPHER
,
1509 ATH9K_CIPHER_TKIP
, NULL
)
1510 && ath9k_hw_getcapability(ah
, ATH9K_CAP_CIPHER
,
1511 ATH9K_CIPHER_MIC
, NULL
)
1512 && ath9k_hw_getcapability(ah
, ATH9K_CAP_TKIP_SPLIT
,
1516 /* turn on mcast key search if possible */
1517 if (!ath9k_hw_getcapability(ah
, ATH9K_CAP_MCAST_KEYSRCH
, 0, NULL
))
1518 (void)ath9k_hw_setcapability(ah
, ATH9K_CAP_MCAST_KEYSRCH
, 1,
1521 sc
->config
.txpowlimit
= ATH_TXPOWER_MAX
;
1523 /* 11n Capabilities */
1524 if (ah
->caps
.hw_caps
& ATH9K_HW_CAP_HT
) {
1525 sc
->sc_flags
|= SC_OP_TXAGGR
;
1526 sc
->sc_flags
|= SC_OP_RXAGGR
;
1529 sc
->tx_chainmask
= ah
->caps
.tx_chainmask
;
1530 sc
->rx_chainmask
= ah
->caps
.rx_chainmask
;
1532 ath9k_hw_setcapability(ah
, ATH9K_CAP_DIVERSITY
, 1, true, NULL
);
1533 sc
->rx
.defant
= ath9k_hw_getdefantenna(ah
);
1535 if (ah
->caps
.hw_caps
& ATH9K_HW_CAP_BSSIDMASK
)
1536 memcpy(sc
->bssidmask
, ath_bcast_mac
, ETH_ALEN
);
1538 sc
->beacon
.slottime
= ATH9K_SLOT_TIME_9
; /* default to short slot time */
1540 /* initialize beacon slots */
1541 for (i
= 0; i
< ARRAY_SIZE(sc
->beacon
.bslot
); i
++) {
1542 sc
->beacon
.bslot
[i
] = NULL
;
1543 sc
->beacon
.bslot_aphy
[i
] = NULL
;
1546 /* setup channels and rates */
1548 sc
->sbands
[IEEE80211_BAND_2GHZ
].channels
= ath9k_2ghz_chantable
;
1549 sc
->sbands
[IEEE80211_BAND_2GHZ
].bitrates
=
1550 sc
->rates
[IEEE80211_BAND_2GHZ
];
1551 sc
->sbands
[IEEE80211_BAND_2GHZ
].band
= IEEE80211_BAND_2GHZ
;
1552 sc
->sbands
[IEEE80211_BAND_2GHZ
].n_channels
=
1553 ARRAY_SIZE(ath9k_2ghz_chantable
);
1555 if (test_bit(ATH9K_MODE_11A
, sc
->sc_ah
->caps
.wireless_modes
)) {
1556 sc
->sbands
[IEEE80211_BAND_5GHZ
].channels
= ath9k_5ghz_chantable
;
1557 sc
->sbands
[IEEE80211_BAND_5GHZ
].bitrates
=
1558 sc
->rates
[IEEE80211_BAND_5GHZ
];
1559 sc
->sbands
[IEEE80211_BAND_5GHZ
].band
= IEEE80211_BAND_5GHZ
;
1560 sc
->sbands
[IEEE80211_BAND_5GHZ
].n_channels
=
1561 ARRAY_SIZE(ath9k_5ghz_chantable
);
1564 if (sc
->sc_ah
->caps
.hw_caps
& ATH9K_HW_CAP_BT_COEX
)
1565 ath9k_hw_btcoex_enable(sc
->sc_ah
);
1569 /* cleanup tx queues */
1570 for (i
= 0; i
< ATH9K_NUM_TX_QUEUES
; i
++)
1571 if (ATH_TXQ_SETUP(sc
, i
))
1572 ath_tx_cleanupq(sc
, &sc
->tx
.txq
[i
]);
1575 ath9k_hw_detach(ah
);
1576 ath9k_exit_debug(sc
);
1581 void ath_set_hw_capab(struct ath_softc
*sc
, struct ieee80211_hw
*hw
)
1583 hw
->flags
= IEEE80211_HW_RX_INCLUDES_FCS
|
1584 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING
|
1585 IEEE80211_HW_SIGNAL_DBM
|
1586 IEEE80211_HW_AMPDU_AGGREGATION
|
1587 IEEE80211_HW_SUPPORTS_PS
|
1588 IEEE80211_HW_PS_NULLFUNC_STACK
|
1589 IEEE80211_HW_SPECTRUM_MGMT
;
1591 if (AR_SREV_9160_10_OR_LATER(sc
->sc_ah
) || modparam_nohwcrypt
)
1592 hw
->flags
|= IEEE80211_HW_MFP_CAPABLE
;
1594 hw
->wiphy
->interface_modes
=
1595 BIT(NL80211_IFTYPE_AP
) |
1596 BIT(NL80211_IFTYPE_STATION
) |
1597 BIT(NL80211_IFTYPE_ADHOC
) |
1598 BIT(NL80211_IFTYPE_MESH_POINT
);
1602 hw
->channel_change_time
= 5000;
1603 hw
->max_listen_interval
= 10;
1604 hw
->max_rate_tries
= ATH_11N_TXMAXTRY
;
1605 hw
->sta_data_size
= sizeof(struct ath_node
);
1606 hw
->vif_data_size
= sizeof(struct ath_vif
);
1608 hw
->rate_control_algorithm
= "ath9k_rate_control";
1610 hw
->wiphy
->bands
[IEEE80211_BAND_2GHZ
] =
1611 &sc
->sbands
[IEEE80211_BAND_2GHZ
];
1612 if (test_bit(ATH9K_MODE_11A
, sc
->sc_ah
->caps
.wireless_modes
))
1613 hw
->wiphy
->bands
[IEEE80211_BAND_5GHZ
] =
1614 &sc
->sbands
[IEEE80211_BAND_5GHZ
];
1617 int ath_attach(u16 devid
, struct ath_softc
*sc
)
1619 struct ieee80211_hw
*hw
= sc
->hw
;
1621 struct ath_regulatory
*reg
;
1623 DPRINTF(sc
, ATH_DBG_CONFIG
, "Attach ATH hw\n");
1625 error
= ath_init(devid
, sc
);
1629 reg
= &sc
->sc_ah
->regulatory
;
1631 /* get mac address from hardware and set in mac80211 */
1633 SET_IEEE80211_PERM_ADDR(hw
, sc
->sc_ah
->macaddr
);
1635 ath_set_hw_capab(sc
, hw
);
1637 if (sc
->sc_ah
->caps
.hw_caps
& ATH9K_HW_CAP_HT
) {
1638 setup_ht_cap(sc
, &sc
->sbands
[IEEE80211_BAND_2GHZ
].ht_cap
);
1639 if (test_bit(ATH9K_MODE_11A
, sc
->sc_ah
->caps
.wireless_modes
))
1640 setup_ht_cap(sc
, &sc
->sbands
[IEEE80211_BAND_5GHZ
].ht_cap
);
1643 /* initialize tx/rx engine */
1644 error
= ath_tx_init(sc
, ATH_TXBUF
);
1648 error
= ath_rx_init(sc
, ATH_RXBUF
);
1652 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1653 /* Initialze h/w Rfkill */
1654 if (sc
->sc_ah
->caps
.hw_caps
& ATH9K_HW_CAP_RFSILENT
)
1655 INIT_DELAYED_WORK(&sc
->rf_kill
.rfkill_poll
, ath_rfkill_poll
);
1657 /* Initialize s/w rfkill */
1658 error
= ath_init_sw_rfkill(sc
);
1663 INIT_WORK(&sc
->chan_work
, ath9k_wiphy_chan_work
);
1664 INIT_DELAYED_WORK(&sc
->wiphy_work
, ath9k_wiphy_work
);
1665 sc
->wiphy_scheduler_int
= msecs_to_jiffies(500);
1667 error
= ieee80211_register_hw(hw
);
1669 if (!ath_is_world_regd(reg
)) {
1670 error
= regulatory_hint(hw
->wiphy
, reg
->alpha2
);
1675 /* Initialize LED control */
1682 /* cleanup tx queues */
1683 for (i
= 0; i
< ATH9K_NUM_TX_QUEUES
; i
++)
1684 if (ATH_TXQ_SETUP(sc
, i
))
1685 ath_tx_cleanupq(sc
, &sc
->tx
.txq
[i
]);
1687 ath9k_hw_detach(sc
->sc_ah
);
1688 ath9k_exit_debug(sc
);
1693 int ath_reset(struct ath_softc
*sc
, bool retry_tx
)
1695 struct ath_hw
*ah
= sc
->sc_ah
;
1696 struct ieee80211_hw
*hw
= sc
->hw
;
1699 ath9k_hw_set_interrupts(ah
, 0);
1700 ath_drain_all_txq(sc
, retry_tx
);
1704 spin_lock_bh(&sc
->sc_resetlock
);
1705 r
= ath9k_hw_reset(ah
, sc
->sc_ah
->curchan
, false);
1707 DPRINTF(sc
, ATH_DBG_FATAL
,
1708 "Unable to reset hardware; reset status %d\n", r
);
1709 spin_unlock_bh(&sc
->sc_resetlock
);
1711 if (ath_startrecv(sc
) != 0)
1712 DPRINTF(sc
, ATH_DBG_FATAL
, "Unable to start recv logic\n");
1715 * We may be doing a reset in response to a request
1716 * that changes the channel so update any state that
1717 * might change as a result.
1719 ath_cache_conf_rate(sc
, &hw
->conf
);
1721 ath_update_txpow(sc
);
1723 if (sc
->sc_flags
& SC_OP_BEACONS
)
1724 ath_beacon_config(sc
, NULL
); /* restart beacons */
1726 ath9k_hw_set_interrupts(ah
, sc
->imask
);
1730 for (i
= 0; i
< ATH9K_NUM_TX_QUEUES
; i
++) {
1731 if (ATH_TXQ_SETUP(sc
, i
)) {
1732 spin_lock_bh(&sc
->tx
.txq
[i
].axq_lock
);
1733 ath_txq_schedule(sc
, &sc
->tx
.txq
[i
]);
1734 spin_unlock_bh(&sc
->tx
.txq
[i
].axq_lock
);
1743 * This function will allocate both the DMA descriptor structure, and the
1744 * buffers it contains. These are used to contain the descriptors used
1747 int ath_descdma_setup(struct ath_softc
*sc
, struct ath_descdma
*dd
,
1748 struct list_head
*head
, const char *name
,
1749 int nbuf
, int ndesc
)
1751 #define DS2PHYS(_dd, _ds) \
1752 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
1753 #define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
1754 #define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
1756 struct ath_desc
*ds
;
1758 int i
, bsize
, error
;
1760 DPRINTF(sc
, ATH_DBG_CONFIG
, "%s DMA: %u buffers %u desc/buf\n",
1763 INIT_LIST_HEAD(head
);
1764 /* ath_desc must be a multiple of DWORDs */
1765 if ((sizeof(struct ath_desc
) % 4) != 0) {
1766 DPRINTF(sc
, ATH_DBG_FATAL
, "ath_desc not DWORD aligned\n");
1767 ASSERT((sizeof(struct ath_desc
) % 4) == 0);
1772 dd
->dd_desc_len
= sizeof(struct ath_desc
) * nbuf
* ndesc
;
1775 * Need additional DMA memory because we can't use
1776 * descriptors that cross the 4K page boundary. Assume
1777 * one skipped descriptor per 4K page.
1779 if (!(sc
->sc_ah
->caps
.hw_caps
& ATH9K_HW_CAP_4KB_SPLITTRANS
)) {
1781 ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd
->dd_desc_len
);
1784 while (ndesc_skipped
) {
1785 dma_len
= ndesc_skipped
* sizeof(struct ath_desc
);
1786 dd
->dd_desc_len
+= dma_len
;
1788 ndesc_skipped
= ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len
);
1792 /* allocate descriptors */
1793 dd
->dd_desc
= dma_alloc_coherent(sc
->dev
, dd
->dd_desc_len
,
1794 &dd
->dd_desc_paddr
, GFP_KERNEL
);
1795 if (dd
->dd_desc
== NULL
) {
1800 DPRINTF(sc
, ATH_DBG_CONFIG
, "%s DMA map: %p (%u) -> %llx (%u)\n",
1801 name
, ds
, (u32
) dd
->dd_desc_len
,
1802 ito64(dd
->dd_desc_paddr
), /*XXX*/(u32
) dd
->dd_desc_len
);
1804 /* allocate buffers */
1805 bsize
= sizeof(struct ath_buf
) * nbuf
;
1806 bf
= kzalloc(bsize
, GFP_KERNEL
);
1813 for (i
= 0; i
< nbuf
; i
++, bf
++, ds
+= ndesc
) {
1815 bf
->bf_daddr
= DS2PHYS(dd
, ds
);
1817 if (!(sc
->sc_ah
->caps
.hw_caps
&
1818 ATH9K_HW_CAP_4KB_SPLITTRANS
)) {
1820 * Skip descriptor addresses which can cause 4KB
1821 * boundary crossing (addr + length) with a 32 dword
1824 while (ATH_DESC_4KB_BOUND_CHECK(bf
->bf_daddr
)) {
1825 ASSERT((caddr_t
) bf
->bf_desc
<
1826 ((caddr_t
) dd
->dd_desc
+
1831 bf
->bf_daddr
= DS2PHYS(dd
, ds
);
1834 list_add_tail(&bf
->list
, head
);
1838 dma_free_coherent(sc
->dev
, dd
->dd_desc_len
, dd
->dd_desc
,
1841 memset(dd
, 0, sizeof(*dd
));
1843 #undef ATH_DESC_4KB_BOUND_CHECK
1844 #undef ATH_DESC_4KB_BOUND_NUM_SKIPPED
1848 void ath_descdma_cleanup(struct ath_softc
*sc
,
1849 struct ath_descdma
*dd
,
1850 struct list_head
*head
)
1852 dma_free_coherent(sc
->dev
, dd
->dd_desc_len
, dd
->dd_desc
,
1855 INIT_LIST_HEAD(head
);
1856 kfree(dd
->dd_bufptr
);
1857 memset(dd
, 0, sizeof(*dd
));
1860 int ath_get_hal_qnum(u16 queue
, struct ath_softc
*sc
)
1866 qnum
= sc
->tx
.hwq_map
[ATH9K_WME_AC_VO
];
1869 qnum
= sc
->tx
.hwq_map
[ATH9K_WME_AC_VI
];
1872 qnum
= sc
->tx
.hwq_map
[ATH9K_WME_AC_BE
];
1875 qnum
= sc
->tx
.hwq_map
[ATH9K_WME_AC_BK
];
1878 qnum
= sc
->tx
.hwq_map
[ATH9K_WME_AC_BE
];
1885 int ath_get_mac80211_qnum(u32 queue
, struct ath_softc
*sc
)
1890 case ATH9K_WME_AC_VO
:
1893 case ATH9K_WME_AC_VI
:
1896 case ATH9K_WME_AC_BE
:
1899 case ATH9K_WME_AC_BK
:
1910 /* XXX: Remove me once we don't depend on ath9k_channel for all
1911 * this redundant data */
1912 void ath9k_update_ichannel(struct ath_softc
*sc
, struct ieee80211_hw
*hw
,
1913 struct ath9k_channel
*ichan
)
1915 struct ieee80211_channel
*chan
= hw
->conf
.channel
;
1916 struct ieee80211_conf
*conf
= &hw
->conf
;
1918 ichan
->channel
= chan
->center_freq
;
1921 if (chan
->band
== IEEE80211_BAND_2GHZ
) {
1922 ichan
->chanmode
= CHANNEL_G
;
1923 ichan
->channelFlags
= CHANNEL_2GHZ
| CHANNEL_OFDM
;
1925 ichan
->chanmode
= CHANNEL_A
;
1926 ichan
->channelFlags
= CHANNEL_5GHZ
| CHANNEL_OFDM
;
1929 sc
->tx_chan_width
= ATH9K_HT_MACMODE_20
;
1931 if (conf_is_ht(conf
)) {
1932 if (conf_is_ht40(conf
))
1933 sc
->tx_chan_width
= ATH9K_HT_MACMODE_2040
;
1935 ichan
->chanmode
= ath_get_extchanmode(sc
, chan
,
1936 conf
->channel_type
);
1940 /**********************/
1941 /* mac80211 callbacks */
1942 /**********************/
1944 static int ath9k_start(struct ieee80211_hw
*hw
)
1946 struct ath_wiphy
*aphy
= hw
->priv
;
1947 struct ath_softc
*sc
= aphy
->sc
;
1948 struct ieee80211_channel
*curchan
= hw
->conf
.channel
;
1949 struct ath9k_channel
*init_channel
;
1952 DPRINTF(sc
, ATH_DBG_CONFIG
, "Starting driver with "
1953 "initial channel: %d MHz\n", curchan
->center_freq
);
1955 mutex_lock(&sc
->mutex
);
1957 if (ath9k_wiphy_started(sc
)) {
1958 if (sc
->chan_idx
== curchan
->hw_value
) {
1960 * Already on the operational channel, the new wiphy
1961 * can be marked active.
1963 aphy
->state
= ATH_WIPHY_ACTIVE
;
1964 ieee80211_wake_queues(hw
);
1967 * Another wiphy is on another channel, start the new
1968 * wiphy in paused state.
1970 aphy
->state
= ATH_WIPHY_PAUSED
;
1971 ieee80211_stop_queues(hw
);
1973 mutex_unlock(&sc
->mutex
);
1976 aphy
->state
= ATH_WIPHY_ACTIVE
;
1978 /* setup initial channel */
1980 pos
= curchan
->hw_value
;
1983 init_channel
= &sc
->sc_ah
->channels
[pos
];
1984 ath9k_update_ichannel(sc
, hw
, init_channel
);
1986 /* Reset SERDES registers */
1987 ath9k_hw_configpcipowersave(sc
->sc_ah
, 0);
1990 * The basic interface to setting the hardware in a good
1991 * state is ``reset''. On return the hardware is known to
1992 * be powered up and with interrupts disabled. This must
1993 * be followed by initialization of the appropriate bits
1994 * and then setup of the interrupt mask.
1996 spin_lock_bh(&sc
->sc_resetlock
);
1997 r
= ath9k_hw_reset(sc
->sc_ah
, init_channel
, false);
1999 DPRINTF(sc
, ATH_DBG_FATAL
,
2000 "Unable to reset hardware; reset status %d "
2001 "(freq %u MHz)\n", r
,
2002 curchan
->center_freq
);
2003 spin_unlock_bh(&sc
->sc_resetlock
);
2006 spin_unlock_bh(&sc
->sc_resetlock
);
2009 * This is needed only to setup initial state
2010 * but it's best done after a reset.
2012 ath_update_txpow(sc
);
2015 * Setup the hardware after reset:
2016 * The receive engine is set going.
2017 * Frame transmit is handled entirely
2018 * in the frame output path; there's nothing to do
2019 * here except setup the interrupt mask.
2021 if (ath_startrecv(sc
) != 0) {
2022 DPRINTF(sc
, ATH_DBG_FATAL
, "Unable to start recv logic\n");
2027 /* Setup our intr mask. */
2028 sc
->imask
= ATH9K_INT_RX
| ATH9K_INT_TX
2029 | ATH9K_INT_RXEOL
| ATH9K_INT_RXORN
2030 | ATH9K_INT_FATAL
| ATH9K_INT_GLOBAL
;
2032 if (sc
->sc_ah
->caps
.hw_caps
& ATH9K_HW_CAP_GTT
)
2033 sc
->imask
|= ATH9K_INT_GTT
;
2035 if (sc
->sc_ah
->caps
.hw_caps
& ATH9K_HW_CAP_HT
)
2036 sc
->imask
|= ATH9K_INT_CST
;
2038 ath_cache_conf_rate(sc
, &hw
->conf
);
2040 sc
->sc_flags
&= ~SC_OP_INVALID
;
2042 /* Disable BMISS interrupt when we're not associated */
2043 sc
->imask
&= ~(ATH9K_INT_SWBA
| ATH9K_INT_BMISS
);
2044 ath9k_hw_set_interrupts(sc
->sc_ah
, sc
->imask
);
2046 ieee80211_wake_queues(hw
);
2048 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2049 r
= ath_start_rfkill_poll(sc
);
2053 mutex_unlock(&sc
->mutex
);
2058 static int ath9k_tx(struct ieee80211_hw
*hw
,
2059 struct sk_buff
*skb
)
2061 struct ieee80211_tx_info
*info
= IEEE80211_SKB_CB(skb
);
2062 struct ath_wiphy
*aphy
= hw
->priv
;
2063 struct ath_softc
*sc
= aphy
->sc
;
2064 struct ath_tx_control txctl
;
2065 int hdrlen
, padsize
;
2067 if (aphy
->state
!= ATH_WIPHY_ACTIVE
&& aphy
->state
!= ATH_WIPHY_SCAN
) {
2068 printk(KERN_DEBUG
"ath9k: %s: TX in unexpected wiphy state "
2069 "%d\n", wiphy_name(hw
->wiphy
), aphy
->state
);
2073 if (unlikely(sc
->sc_ah
->power_mode
!= ATH9K_PM_AWAKE
)) {
2075 * We are using PS-Poll and mac80211 can request TX while in
2076 * power save mode. Need to wake up hardware for the TX to be
2077 * completed and if needed, also for RX of buffered frames.
2079 struct ieee80211_hdr
*hdr
= (struct ieee80211_hdr
*) skb
->data
;
2080 ath9k_ps_wakeup(sc
);
2081 ath9k_hw_setrxabort(sc
->sc_ah
, 0);
2082 if (ieee80211_is_pspoll(hdr
->frame_control
)) {
2083 DPRINTF(sc
, ATH_DBG_PS
, "Sending PS-Poll to pick a "
2084 "buffered frame\n");
2085 sc
->sc_flags
|= SC_OP_WAIT_FOR_PSPOLL_DATA
;
2087 DPRINTF(sc
, ATH_DBG_PS
, "Wake up to complete TX\n");
2088 sc
->sc_flags
|= SC_OP_WAIT_FOR_TX_ACK
;
2091 * The actual restore operation will happen only after
2092 * the sc_flags bit is cleared. We are just dropping
2093 * the ps_usecount here.
2095 ath9k_ps_restore(sc
);
2098 memset(&txctl
, 0, sizeof(struct ath_tx_control
));
2101 * As a temporary workaround, assign seq# here; this will likely need
2102 * to be cleaned up to work better with Beacon transmission and virtual
2105 if (info
->flags
& IEEE80211_TX_CTL_ASSIGN_SEQ
) {
2106 struct ieee80211_hdr
*hdr
= (struct ieee80211_hdr
*) skb
->data
;
2107 if (info
->flags
& IEEE80211_TX_CTL_FIRST_FRAGMENT
)
2108 sc
->tx
.seq_no
+= 0x10;
2109 hdr
->seq_ctrl
&= cpu_to_le16(IEEE80211_SCTL_FRAG
);
2110 hdr
->seq_ctrl
|= cpu_to_le16(sc
->tx
.seq_no
);
2113 /* Add the padding after the header if this is not already done */
2114 hdrlen
= ieee80211_get_hdrlen_from_skb(skb
);
2116 padsize
= hdrlen
% 4;
2117 if (skb_headroom(skb
) < padsize
)
2119 skb_push(skb
, padsize
);
2120 memmove(skb
->data
, skb
->data
+ padsize
, hdrlen
);
2123 /* Check if a tx queue is available */
2125 txctl
.txq
= ath_test_get_txq(sc
, skb
);
2129 DPRINTF(sc
, ATH_DBG_XMIT
, "transmitting packet, skb: %p\n", skb
);
2131 if (ath_tx_start(hw
, skb
, &txctl
) != 0) {
2132 DPRINTF(sc
, ATH_DBG_XMIT
, "TX failed\n");
2138 dev_kfree_skb_any(skb
);
2142 static void ath9k_stop(struct ieee80211_hw
*hw
)
2144 struct ath_wiphy
*aphy
= hw
->priv
;
2145 struct ath_softc
*sc
= aphy
->sc
;
2147 aphy
->state
= ATH_WIPHY_INACTIVE
;
2149 if (sc
->sc_flags
& SC_OP_INVALID
) {
2150 DPRINTF(sc
, ATH_DBG_ANY
, "Device not present\n");
2154 mutex_lock(&sc
->mutex
);
2156 ieee80211_stop_queues(hw
);
2158 if (ath9k_wiphy_started(sc
)) {
2159 mutex_unlock(&sc
->mutex
);
2160 return; /* another wiphy still in use */
2163 /* make sure h/w will not generate any interrupt
2164 * before setting the invalid flag. */
2165 ath9k_hw_set_interrupts(sc
->sc_ah
, 0);
2167 if (!(sc
->sc_flags
& SC_OP_INVALID
)) {
2168 ath_drain_all_txq(sc
, false);
2170 ath9k_hw_phy_disable(sc
->sc_ah
);
2172 sc
->rx
.rxlink
= NULL
;
2174 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2175 if (sc
->sc_ah
->caps
.hw_caps
& ATH9K_HW_CAP_RFSILENT
)
2176 cancel_delayed_work_sync(&sc
->rf_kill
.rfkill_poll
);
2178 /* disable HAL and put h/w to sleep */
2179 ath9k_hw_disable(sc
->sc_ah
);
2180 ath9k_hw_configpcipowersave(sc
->sc_ah
, 1);
2182 sc
->sc_flags
|= SC_OP_INVALID
;
2184 mutex_unlock(&sc
->mutex
);
2186 DPRINTF(sc
, ATH_DBG_CONFIG
, "Driver halt\n");
2189 static int ath9k_add_interface(struct ieee80211_hw
*hw
,
2190 struct ieee80211_if_init_conf
*conf
)
2192 struct ath_wiphy
*aphy
= hw
->priv
;
2193 struct ath_softc
*sc
= aphy
->sc
;
2194 struct ath_vif
*avp
= (void *)conf
->vif
->drv_priv
;
2195 enum nl80211_iftype ic_opmode
= NL80211_IFTYPE_UNSPECIFIED
;
2198 mutex_lock(&sc
->mutex
);
2200 if (!(sc
->sc_ah
->caps
.hw_caps
& ATH9K_HW_CAP_BSSIDMASK
) &&
2206 switch (conf
->type
) {
2207 case NL80211_IFTYPE_STATION
:
2208 ic_opmode
= NL80211_IFTYPE_STATION
;
2210 case NL80211_IFTYPE_ADHOC
:
2211 case NL80211_IFTYPE_AP
:
2212 case NL80211_IFTYPE_MESH_POINT
:
2213 if (sc
->nbcnvifs
>= ATH_BCBUF
) {
2217 ic_opmode
= conf
->type
;
2220 DPRINTF(sc
, ATH_DBG_FATAL
,
2221 "Interface type %d not yet supported\n", conf
->type
);
2226 DPRINTF(sc
, ATH_DBG_CONFIG
, "Attach a VIF of type: %d\n", ic_opmode
);
2228 /* Set the VIF opmode */
2229 avp
->av_opmode
= ic_opmode
;
2234 if (sc
->sc_ah
->caps
.hw_caps
& ATH9K_HW_CAP_BSSIDMASK
)
2235 ath9k_set_bssid_mask(hw
);
2238 goto out
; /* skip global settings for secondary vif */
2240 if (ic_opmode
== NL80211_IFTYPE_AP
) {
2241 ath9k_hw_set_tsfadjust(sc
->sc_ah
, 1);
2242 sc
->sc_flags
|= SC_OP_TSF_RESET
;
2245 /* Set the device opmode */
2246 sc
->sc_ah
->opmode
= ic_opmode
;
2249 * Enable MIB interrupts when there are hardware phy counters.
2250 * Note we only do this (at the moment) for station mode.
2252 if ((conf
->type
== NL80211_IFTYPE_STATION
) ||
2253 (conf
->type
== NL80211_IFTYPE_ADHOC
) ||
2254 (conf
->type
== NL80211_IFTYPE_MESH_POINT
)) {
2255 if (ath9k_hw_phycounters(sc
->sc_ah
))
2256 sc
->imask
|= ATH9K_INT_MIB
;
2257 sc
->imask
|= ATH9K_INT_TSFOOR
;
2260 ath9k_hw_set_interrupts(sc
->sc_ah
, sc
->imask
);
2262 if (conf
->type
== NL80211_IFTYPE_AP
)
2266 mutex_unlock(&sc
->mutex
);
2270 static void ath9k_remove_interface(struct ieee80211_hw
*hw
,
2271 struct ieee80211_if_init_conf
*conf
)
2273 struct ath_wiphy
*aphy
= hw
->priv
;
2274 struct ath_softc
*sc
= aphy
->sc
;
2275 struct ath_vif
*avp
= (void *)conf
->vif
->drv_priv
;
2278 DPRINTF(sc
, ATH_DBG_CONFIG
, "Detach Interface\n");
2280 mutex_lock(&sc
->mutex
);
2283 del_timer_sync(&sc
->ani
.timer
);
2285 /* Reclaim beacon resources */
2286 if ((sc
->sc_ah
->opmode
== NL80211_IFTYPE_AP
) ||
2287 (sc
->sc_ah
->opmode
== NL80211_IFTYPE_ADHOC
) ||
2288 (sc
->sc_ah
->opmode
== NL80211_IFTYPE_MESH_POINT
)) {
2289 ath9k_hw_stoptxdma(sc
->sc_ah
, sc
->beacon
.beaconq
);
2290 ath_beacon_return(sc
, avp
);
2293 sc
->sc_flags
&= ~SC_OP_BEACONS
;
2295 for (i
= 0; i
< ARRAY_SIZE(sc
->beacon
.bslot
); i
++) {
2296 if (sc
->beacon
.bslot
[i
] == conf
->vif
) {
2297 printk(KERN_DEBUG
"%s: vif had allocated beacon "
2298 "slot\n", __func__
);
2299 sc
->beacon
.bslot
[i
] = NULL
;
2300 sc
->beacon
.bslot_aphy
[i
] = NULL
;
2306 mutex_unlock(&sc
->mutex
);
2309 static int ath9k_config(struct ieee80211_hw
*hw
, u32 changed
)
2311 struct ath_wiphy
*aphy
= hw
->priv
;
2312 struct ath_softc
*sc
= aphy
->sc
;
2313 struct ieee80211_conf
*conf
= &hw
->conf
;
2314 struct ath_hw
*ah
= sc
->sc_ah
;
2316 mutex_lock(&sc
->mutex
);
2318 if (changed
& IEEE80211_CONF_CHANGE_PS
) {
2319 if (conf
->flags
& IEEE80211_CONF_PS
) {
2320 if (!(ah
->caps
.hw_caps
&
2321 ATH9K_HW_CAP_AUTOSLEEP
)) {
2322 if ((sc
->imask
& ATH9K_INT_TIM_TIMER
) == 0) {
2323 sc
->imask
|= ATH9K_INT_TIM_TIMER
;
2324 ath9k_hw_set_interrupts(sc
->sc_ah
,
2327 ath9k_hw_setrxabort(sc
->sc_ah
, 1);
2329 ath9k_hw_setpower(sc
->sc_ah
, ATH9K_PM_NETWORK_SLEEP
);
2331 ath9k_hw_setpower(sc
->sc_ah
, ATH9K_PM_AWAKE
);
2332 if (!(ah
->caps
.hw_caps
&
2333 ATH9K_HW_CAP_AUTOSLEEP
)) {
2334 ath9k_hw_setrxabort(sc
->sc_ah
, 0);
2335 sc
->sc_flags
&= ~(SC_OP_WAIT_FOR_BEACON
|
2336 SC_OP_WAIT_FOR_CAB
|
2337 SC_OP_WAIT_FOR_PSPOLL_DATA
|
2338 SC_OP_WAIT_FOR_TX_ACK
);
2339 if (sc
->imask
& ATH9K_INT_TIM_TIMER
) {
2340 sc
->imask
&= ~ATH9K_INT_TIM_TIMER
;
2341 ath9k_hw_set_interrupts(sc
->sc_ah
,
2348 if (changed
& IEEE80211_CONF_CHANGE_CHANNEL
) {
2349 struct ieee80211_channel
*curchan
= hw
->conf
.channel
;
2350 int pos
= curchan
->hw_value
;
2352 aphy
->chan_idx
= pos
;
2353 aphy
->chan_is_ht
= conf_is_ht(conf
);
2355 if (aphy
->state
== ATH_WIPHY_SCAN
||
2356 aphy
->state
== ATH_WIPHY_ACTIVE
)
2357 ath9k_wiphy_pause_all_forced(sc
, aphy
);
2360 * Do not change operational channel based on a paused
2363 goto skip_chan_change
;
2366 DPRINTF(sc
, ATH_DBG_CONFIG
, "Set channel: %d MHz\n",
2367 curchan
->center_freq
);
2369 /* XXX: remove me eventualy */
2370 ath9k_update_ichannel(sc
, hw
, &sc
->sc_ah
->channels
[pos
]);
2372 ath_update_chainmask(sc
, conf_is_ht(conf
));
2374 if (ath_set_channel(sc
, hw
, &sc
->sc_ah
->channels
[pos
]) < 0) {
2375 DPRINTF(sc
, ATH_DBG_FATAL
, "Unable to set channel\n");
2376 mutex_unlock(&sc
->mutex
);
2382 if (changed
& IEEE80211_CONF_CHANGE_POWER
)
2383 sc
->config
.txpowlimit
= 2 * conf
->power_level
;
2385 mutex_unlock(&sc
->mutex
);
2390 #define SUPPORTED_FILTERS \
2391 (FIF_PROMISC_IN_BSS | \
2395 FIF_BCN_PRBRESP_PROMISC | \
2398 /* FIXME: sc->sc_full_reset ? */
2399 static void ath9k_configure_filter(struct ieee80211_hw
*hw
,
2400 unsigned int changed_flags
,
2401 unsigned int *total_flags
,
2403 struct dev_mc_list
*mclist
)
2405 struct ath_wiphy
*aphy
= hw
->priv
;
2406 struct ath_softc
*sc
= aphy
->sc
;
2409 changed_flags
&= SUPPORTED_FILTERS
;
2410 *total_flags
&= SUPPORTED_FILTERS
;
2412 sc
->rx
.rxfilter
= *total_flags
;
2413 rfilt
= ath_calcrxfilter(sc
);
2414 ath9k_hw_setrxfilter(sc
->sc_ah
, rfilt
);
2416 DPRINTF(sc
, ATH_DBG_CONFIG
, "Set HW RX filter: 0x%x\n", sc
->rx
.rxfilter
);
2419 static void ath9k_sta_notify(struct ieee80211_hw
*hw
,
2420 struct ieee80211_vif
*vif
,
2421 enum sta_notify_cmd cmd
,
2422 struct ieee80211_sta
*sta
)
2424 struct ath_wiphy
*aphy
= hw
->priv
;
2425 struct ath_softc
*sc
= aphy
->sc
;
2428 case STA_NOTIFY_ADD
:
2429 ath_node_attach(sc
, sta
);
2431 case STA_NOTIFY_REMOVE
:
2432 ath_node_detach(sc
, sta
);
2439 static int ath9k_conf_tx(struct ieee80211_hw
*hw
, u16 queue
,
2440 const struct ieee80211_tx_queue_params
*params
)
2442 struct ath_wiphy
*aphy
= hw
->priv
;
2443 struct ath_softc
*sc
= aphy
->sc
;
2444 struct ath9k_tx_queue_info qi
;
2447 if (queue
>= WME_NUM_AC
)
2450 mutex_lock(&sc
->mutex
);
2452 memset(&qi
, 0, sizeof(struct ath9k_tx_queue_info
));
2454 qi
.tqi_aifs
= params
->aifs
;
2455 qi
.tqi_cwmin
= params
->cw_min
;
2456 qi
.tqi_cwmax
= params
->cw_max
;
2457 qi
.tqi_burstTime
= params
->txop
;
2458 qnum
= ath_get_hal_qnum(queue
, sc
);
2460 DPRINTF(sc
, ATH_DBG_CONFIG
,
2461 "Configure tx [queue/halq] [%d/%d], "
2462 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
2463 queue
, qnum
, params
->aifs
, params
->cw_min
,
2464 params
->cw_max
, params
->txop
);
2466 ret
= ath_txq_update(sc
, qnum
, &qi
);
2468 DPRINTF(sc
, ATH_DBG_FATAL
, "TXQ Update failed\n");
2470 mutex_unlock(&sc
->mutex
);
2475 static int ath9k_set_key(struct ieee80211_hw
*hw
,
2476 enum set_key_cmd cmd
,
2477 struct ieee80211_vif
*vif
,
2478 struct ieee80211_sta
*sta
,
2479 struct ieee80211_key_conf
*key
)
2481 struct ath_wiphy
*aphy
= hw
->priv
;
2482 struct ath_softc
*sc
= aphy
->sc
;
2485 if (modparam_nohwcrypt
)
2488 mutex_lock(&sc
->mutex
);
2489 ath9k_ps_wakeup(sc
);
2490 DPRINTF(sc
, ATH_DBG_CONFIG
, "Set HW Key\n");
2494 ret
= ath_key_config(sc
, vif
, sta
, key
);
2496 key
->hw_key_idx
= ret
;
2497 /* push IV and Michael MIC generation to stack */
2498 key
->flags
|= IEEE80211_KEY_FLAG_GENERATE_IV
;
2499 if (key
->alg
== ALG_TKIP
)
2500 key
->flags
|= IEEE80211_KEY_FLAG_GENERATE_MMIC
;
2501 if (sc
->sc_ah
->sw_mgmt_crypto
&& key
->alg
== ALG_CCMP
)
2502 key
->flags
|= IEEE80211_KEY_FLAG_SW_MGMT
;
2507 ath_key_delete(sc
, key
);
2513 ath9k_ps_restore(sc
);
2514 mutex_unlock(&sc
->mutex
);
2519 static void ath9k_bss_info_changed(struct ieee80211_hw
*hw
,
2520 struct ieee80211_vif
*vif
,
2521 struct ieee80211_bss_conf
*bss_conf
,
2524 struct ath_wiphy
*aphy
= hw
->priv
;
2525 struct ath_softc
*sc
= aphy
->sc
;
2526 struct ath_hw
*ah
= sc
->sc_ah
;
2527 struct ath_vif
*avp
= (void *)vif
->drv_priv
;
2531 mutex_lock(&sc
->mutex
);
2534 * TODO: Need to decide which hw opmode to use for
2535 * multi-interface cases
2536 * XXX: This belongs into add_interface!
2538 if (vif
->type
== NL80211_IFTYPE_AP
&&
2539 ah
->opmode
!= NL80211_IFTYPE_AP
) {
2540 ah
->opmode
= NL80211_IFTYPE_STATION
;
2541 ath9k_hw_setopmode(ah
);
2542 memcpy(sc
->curbssid
, sc
->sc_ah
->macaddr
, ETH_ALEN
);
2544 ath9k_hw_write_associd(sc
);
2545 /* Request full reset to get hw opmode changed properly */
2546 sc
->sc_flags
|= SC_OP_FULL_RESET
;
2549 if ((changed
& BSS_CHANGED_BSSID
) &&
2550 !is_zero_ether_addr(bss_conf
->bssid
)) {
2551 switch (vif
->type
) {
2552 case NL80211_IFTYPE_STATION
:
2553 case NL80211_IFTYPE_ADHOC
:
2554 case NL80211_IFTYPE_MESH_POINT
:
2556 memcpy(sc
->curbssid
, bss_conf
->bssid
, ETH_ALEN
);
2557 memcpy(avp
->bssid
, bss_conf
->bssid
, ETH_ALEN
);
2559 ath9k_hw_write_associd(sc
);
2561 /* Set aggregation protection mode parameters */
2562 sc
->config
.ath_aggr_prot
= 0;
2564 DPRINTF(sc
, ATH_DBG_CONFIG
,
2565 "RX filter 0x%x bssid %pM aid 0x%x\n",
2566 rfilt
, sc
->curbssid
, sc
->curaid
);
2568 /* need to reconfigure the beacon */
2569 sc
->sc_flags
&= ~SC_OP_BEACONS
;
2577 if ((vif
->type
== NL80211_IFTYPE_ADHOC
) ||
2578 (vif
->type
== NL80211_IFTYPE_AP
) ||
2579 (vif
->type
== NL80211_IFTYPE_MESH_POINT
)) {
2580 if ((changed
& BSS_CHANGED_BEACON
) ||
2581 (changed
& BSS_CHANGED_BEACON_ENABLED
&&
2582 bss_conf
->enable_beacon
)) {
2584 * Allocate and setup the beacon frame.
2586 * Stop any previous beacon DMA. This may be
2587 * necessary, for example, when an ibss merge
2588 * causes reconfiguration; we may be called
2589 * with beacon transmission active.
2591 ath9k_hw_stoptxdma(sc
->sc_ah
, sc
->beacon
.beaconq
);
2593 error
= ath_beacon_alloc(aphy
, vif
);
2595 ath_beacon_config(sc
, vif
);
2599 /* Check for WLAN_CAPABILITY_PRIVACY ? */
2600 if ((avp
->av_opmode
!= NL80211_IFTYPE_STATION
)) {
2601 for (i
= 0; i
< IEEE80211_WEP_NKID
; i
++)
2602 if (ath9k_hw_keyisvalid(sc
->sc_ah
, (u16
)i
))
2603 ath9k_hw_keysetmac(sc
->sc_ah
,
2608 /* Only legacy IBSS for now */
2609 if (vif
->type
== NL80211_IFTYPE_ADHOC
)
2610 ath_update_chainmask(sc
, 0);
2612 if (changed
& BSS_CHANGED_ERP_PREAMBLE
) {
2613 DPRINTF(sc
, ATH_DBG_CONFIG
, "BSS Changed PREAMBLE %d\n",
2614 bss_conf
->use_short_preamble
);
2615 if (bss_conf
->use_short_preamble
)
2616 sc
->sc_flags
|= SC_OP_PREAMBLE_SHORT
;
2618 sc
->sc_flags
&= ~SC_OP_PREAMBLE_SHORT
;
2621 if (changed
& BSS_CHANGED_ERP_CTS_PROT
) {
2622 DPRINTF(sc
, ATH_DBG_CONFIG
, "BSS Changed CTS PROT %d\n",
2623 bss_conf
->use_cts_prot
);
2624 if (bss_conf
->use_cts_prot
&&
2625 hw
->conf
.channel
->band
!= IEEE80211_BAND_5GHZ
)
2626 sc
->sc_flags
|= SC_OP_PROTECT_ENABLE
;
2628 sc
->sc_flags
&= ~SC_OP_PROTECT_ENABLE
;
2631 if (changed
& BSS_CHANGED_ASSOC
) {
2632 DPRINTF(sc
, ATH_DBG_CONFIG
, "BSS Changed ASSOC %d\n",
2634 ath9k_bss_assoc_info(sc
, vif
, bss_conf
);
2638 * The HW TSF has to be reset when the beacon interval changes.
2639 * We set the flag here, and ath_beacon_config_ap() would take this
2640 * into account when it gets called through the subsequent
2641 * config_interface() call - with IFCC_BEACON in the changed field.
2644 if (changed
& BSS_CHANGED_BEACON_INT
) {
2645 sc
->sc_flags
|= SC_OP_TSF_RESET
;
2646 sc
->beacon_interval
= bss_conf
->beacon_int
;
2649 mutex_unlock(&sc
->mutex
);
2652 static u64
ath9k_get_tsf(struct ieee80211_hw
*hw
)
2655 struct ath_wiphy
*aphy
= hw
->priv
;
2656 struct ath_softc
*sc
= aphy
->sc
;
2658 mutex_lock(&sc
->mutex
);
2659 tsf
= ath9k_hw_gettsf64(sc
->sc_ah
);
2660 mutex_unlock(&sc
->mutex
);
2665 static void ath9k_set_tsf(struct ieee80211_hw
*hw
, u64 tsf
)
2667 struct ath_wiphy
*aphy
= hw
->priv
;
2668 struct ath_softc
*sc
= aphy
->sc
;
2670 mutex_lock(&sc
->mutex
);
2671 ath9k_hw_settsf64(sc
->sc_ah
, tsf
);
2672 mutex_unlock(&sc
->mutex
);
2675 static void ath9k_reset_tsf(struct ieee80211_hw
*hw
)
2677 struct ath_wiphy
*aphy
= hw
->priv
;
2678 struct ath_softc
*sc
= aphy
->sc
;
2680 mutex_lock(&sc
->mutex
);
2681 ath9k_hw_reset_tsf(sc
->sc_ah
);
2682 mutex_unlock(&sc
->mutex
);
2685 static int ath9k_ampdu_action(struct ieee80211_hw
*hw
,
2686 enum ieee80211_ampdu_mlme_action action
,
2687 struct ieee80211_sta
*sta
,
2690 struct ath_wiphy
*aphy
= hw
->priv
;
2691 struct ath_softc
*sc
= aphy
->sc
;
2695 case IEEE80211_AMPDU_RX_START
:
2696 if (!(sc
->sc_flags
& SC_OP_RXAGGR
))
2699 case IEEE80211_AMPDU_RX_STOP
:
2701 case IEEE80211_AMPDU_TX_START
:
2702 ret
= ath_tx_aggr_start(sc
, sta
, tid
, ssn
);
2704 DPRINTF(sc
, ATH_DBG_FATAL
,
2705 "Unable to start TX aggregation\n");
2707 ieee80211_start_tx_ba_cb_irqsafe(hw
, sta
->addr
, tid
);
2709 case IEEE80211_AMPDU_TX_STOP
:
2710 ret
= ath_tx_aggr_stop(sc
, sta
, tid
);
2712 DPRINTF(sc
, ATH_DBG_FATAL
,
2713 "Unable to stop TX aggregation\n");
2715 ieee80211_stop_tx_ba_cb_irqsafe(hw
, sta
->addr
, tid
);
2717 case IEEE80211_AMPDU_TX_OPERATIONAL
:
2718 ath_tx_aggr_resume(sc
, sta
, tid
);
2721 DPRINTF(sc
, ATH_DBG_FATAL
, "Unknown AMPDU action\n");
2727 static void ath9k_sw_scan_start(struct ieee80211_hw
*hw
)
2729 struct ath_wiphy
*aphy
= hw
->priv
;
2730 struct ath_softc
*sc
= aphy
->sc
;
2732 if (ath9k_wiphy_scanning(sc
)) {
2733 printk(KERN_DEBUG
"ath9k: Two wiphys trying to scan at the "
2736 * Do not allow the concurrent scanning state for now. This
2737 * could be improved with scanning control moved into ath9k.
2742 aphy
->state
= ATH_WIPHY_SCAN
;
2743 ath9k_wiphy_pause_all_forced(sc
, aphy
);
2745 mutex_lock(&sc
->mutex
);
2746 sc
->sc_flags
|= SC_OP_SCANNING
;
2747 mutex_unlock(&sc
->mutex
);
2750 static void ath9k_sw_scan_complete(struct ieee80211_hw
*hw
)
2752 struct ath_wiphy
*aphy
= hw
->priv
;
2753 struct ath_softc
*sc
= aphy
->sc
;
2755 mutex_lock(&sc
->mutex
);
2756 aphy
->state
= ATH_WIPHY_ACTIVE
;
2757 sc
->sc_flags
&= ~SC_OP_SCANNING
;
2758 sc
->sc_flags
|= SC_OP_FULL_RESET
;
2759 mutex_unlock(&sc
->mutex
);
2762 struct ieee80211_ops ath9k_ops
= {
2764 .start
= ath9k_start
,
2766 .add_interface
= ath9k_add_interface
,
2767 .remove_interface
= ath9k_remove_interface
,
2768 .config
= ath9k_config
,
2769 .configure_filter
= ath9k_configure_filter
,
2770 .sta_notify
= ath9k_sta_notify
,
2771 .conf_tx
= ath9k_conf_tx
,
2772 .bss_info_changed
= ath9k_bss_info_changed
,
2773 .set_key
= ath9k_set_key
,
2774 .get_tsf
= ath9k_get_tsf
,
2775 .set_tsf
= ath9k_set_tsf
,
2776 .reset_tsf
= ath9k_reset_tsf
,
2777 .ampdu_action
= ath9k_ampdu_action
,
2778 .sw_scan_start
= ath9k_sw_scan_start
,
2779 .sw_scan_complete
= ath9k_sw_scan_complete
,
2785 } ath_mac_bb_names
[] = {
2786 { AR_SREV_VERSION_5416_PCI
, "5416" },
2787 { AR_SREV_VERSION_5416_PCIE
, "5418" },
2788 { AR_SREV_VERSION_9100
, "9100" },
2789 { AR_SREV_VERSION_9160
, "9160" },
2790 { AR_SREV_VERSION_9280
, "9280" },
2791 { AR_SREV_VERSION_9285
, "9285" }
2797 } ath_rf_names
[] = {
2799 { AR_RAD5133_SREV_MAJOR
, "5133" },
2800 { AR_RAD5122_SREV_MAJOR
, "5122" },
2801 { AR_RAD2133_SREV_MAJOR
, "2133" },
2802 { AR_RAD2122_SREV_MAJOR
, "2122" }
2806 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2809 ath_mac_bb_name(u32 mac_bb_version
)
2813 for (i
=0; i
<ARRAY_SIZE(ath_mac_bb_names
); i
++) {
2814 if (ath_mac_bb_names
[i
].version
== mac_bb_version
) {
2815 return ath_mac_bb_names
[i
].name
;
2823 * Return the RF name. "????" is returned if the RF is unknown.
2826 ath_rf_name(u16 rf_version
)
2830 for (i
=0; i
<ARRAY_SIZE(ath_rf_names
); i
++) {
2831 if (ath_rf_names
[i
].version
== rf_version
) {
2832 return ath_rf_names
[i
].name
;
2839 static int __init
ath9k_init(void)
2843 /* Register rate control algorithm */
2844 error
= ath_rate_control_register();
2847 "ath9k: Unable to register rate control "
2853 error
= ath9k_debug_create_root();
2856 "ath9k: Unable to create debugfs root: %d\n",
2858 goto err_rate_unregister
;
2861 error
= ath_pci_init();
2864 "ath9k: No PCI devices found, driver not installed.\n");
2866 goto err_remove_root
;
2869 error
= ath_ahb_init();
2881 ath9k_debug_remove_root();
2882 err_rate_unregister
:
2883 ath_rate_control_unregister();
2887 module_init(ath9k_init
);
2889 static void __exit
ath9k_exit(void)
2893 ath9k_debug_remove_root();
2894 ath_rate_control_unregister();
2895 printk(KERN_INFO
"%s: Driver unloaded\n", dev_info
);
2897 module_exit(ath9k_exit
);