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[MTD] NAND Signal that a bitflip was corrected by ECC
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / video / virgefb.c
blob5ea2345dab993e8cb3aa3c28d6451f426d277737
1 /*
2 * linux/drivers/video/virgefb.c -- CyberVision64/3D frame buffer device
3 *
4 * Copyright (C) 1997 André Heynatz
5 *
6 *
7 * This file is based on the CyberVision frame buffer device (cyberfb.c):
8 *
9 * Copyright (C) 1996 Martin Apel
10 * Geert Uytterhoeven
11 *
12 * Zorro II additions :
13 *
14 * Copyright (C) 1998-2000 Christian T. Steigies
15 *
16 * Initialization additions :
17 *
18 * Copyright (C) 1998-2000 Ken Tyler
19 *
20 * Parts of the Initialization code are based on Cyberfb.c by Allan Bair,
21 * and on the NetBSD CyberVision64 frame buffer driver by Michael Teske who gave
22 * permission for its use.
23 *
24 * Many thanks to Frank Mariak for his assistance with ZORRO 2 access and other
25 * mysteries.
26 *
27 *
28 *
29 * This file is subject to the terms and conditions of the GNU General Public
30 * License. See the file COPYING in the main directory of this archive
31 * for more details.
32 */
33
34 #undef VIRGEFBDEBUG
35 #undef VIRGEFBDUMP
36
37 #include <linux/module.h>
38 #include <linux/kernel.h>
39 #include <linux/errno.h>
40 #include <linux/string.h>
41 #include <linux/mm.h>
42 #include <linux/tty.h>
43 #include <linux/slab.h>
44 #include <linux/delay.h>
45 #include <linux/zorro.h>
46 #include <linux/fb.h>
47 #include <linux/init.h>
48 #include <asm/uaccess.h>
49 #include <asm/system.h>
50 #include <asm/amigahw.h>
51 #include <asm/io.h>
52 #include <asm/irq.h>
53 #include <video/fbcon.h>
54 #include <video/fbcon-cfb8.h>
55 #include <video/fbcon-cfb16.h>
56 #include <video/fbcon-cfb32.h>
57
58 #include "virgefb.h"
59
60 #ifdef VIRGEFBDEBUG
61 #define DPRINTK(fmt, args...) printk(KERN_DEBUG "%s: " fmt, __FUNCTION__ , ## args)
62 #else
63 #define DPRINTK(fmt, args...)
64 #endif
65
66 #ifdef VIRGEFBDUMP
67 static void cv64_dump(void);
68 #define DUMP cv64_dump()
69 #else
70 #define DUMP
71 #endif
72
73 /*
74 * Macros for register access and zorro control
75 */
76
77 static inline void mb_inline(void) { mb(); } /* for use in comma expressions */
78
79 /* Set zorro 2 map */
80
81 #define SelectIO \
82 mb(); \
83 if (on_zorro2) { \
84 (*(volatile u16 *)((u8 *)(vcode_switch_base + 0x04)) = 0x01); \
85 mb(); \
86 }
87
88 #define SelectMMIO \
89 mb(); \
90 if (on_zorro2) { \
91 (*(volatile u16 *)((u8 *)(vcode_switch_base + 0x04)) = 0x02); \
92 mb(); \
93 }
94
95 #define SelectCFG \
96 mb(); \
97 if (on_zorro2) { \
98 (*(volatile u16 *)((u8 *)(vcode_switch_base + 0x04)) = 0x03); \
99 mb(); \
100 }
101
102 /* Set pass through, 0 = amiga, !=0 = cv64/3d */
103
104 #define SetVSwitch(x) \
105 mb(); \
106 (*(volatile u16 *)((u8 *)(vcode_switch_base)) = \
107 (u16)(x ? 0 : 1)); \
108 mb();
109
110 /* Zorro2 endian 'aperture' */
111
112 #define ENDIAN_BYTE 2
113 #define ENDIAN_WORD 1
114 #define ENDIAN_LONG 0
115
116 #define Select_Zorro2_FrameBuffer(x) \
117 do { \
118 if (on_zorro2) { \
119 mb(); \
120 (*(volatile u16 *)((u8 *)(vcode_switch_base + 0x08)) = \
121 (x * 0x40)); \
122 mb(); \
123 } \
124 } while (0)
125
126 /* SetPortVal - only used for interrupt enable (not yet implemented) */
127
128 #if 0
129 #define SetPortVal(x) \
130 mb(); \
131 (*(volatile u16 *)((u8 *)(vcode_switch_base + 0x0c)) = \
132 (u16)x); \
133 mb();
134 #endif
135
136 /* IO access */
137
138 #define byte_access_io(x) (((x) & 0x3ffc) | (((x) & 3)^3) | (((x) & 3) <<14))
139 #define byte_access_mmio(x) (((x) & 0xfffc) | (((x) & 3)^3))
140
141 /* Write 8 bit VGA register - used once for chip wakeup */
142
143 #define wb_vgaio(reg, dat) \
144 SelectIO; \
145 (*(volatile u8 *)(vgaio_regs + ((u32)byte_access_io(reg) & 0xffff)) = \
146 (dat & 0xff)); \
147 SelectMMIO;
148
149 /* Read 8 bit VGA register - only used in dump (SelectIO not needed on read ?) */
150
151 #ifdef VIRGEFBDUMP
152 #define rb_vgaio(reg) \
153 ({ \
154 u8 __zzyzx; \
155 SelectIO; \
156 __zzyzx = (*(volatile u8 *)((vgaio_regs)+(u32)byte_access_io(reg))); \
157 SelectMMIO; \
158 __zzyzx; \
159 })
160 #endif
161
162 /* MMIO access */
163
164 /* Read 8 bit MMIO register */
165
166 #define rb_mmio(reg) \
167 (mb_inline(), \
168 (*(volatile u8 *)(mmio_regs + 0x8000 + (u32)byte_access_mmio(reg))))
169
170 /* Write 8 bit MMIO register */
171
172 #define wb_mmio(reg,dat) \
173 mb(); \
174 (*(volatile u8 *)(mmio_regs + 0x8000 + (byte_access_mmio((reg) & 0xffff))) = \
175 (dat & 0xff)); \
176 mb();
177
178 /* Read 32 bit MMIO register */
179
180 #define rl_mmio(reg) \
181 (mb_inline(), \
182 (*((volatile u32 *)((u8 *)((mmio_regs + (on_zorro2 ? 0x20000 : 0)) + (reg))))))
183
184 /* Write 32 bit MMIO register */
185
186 #define wl_mmio(reg,dat) \
187 mb(); \
188 ((*(volatile u32 *)((u8 *)((mmio_regs + (on_zorro2 ? 0x20000 : 0)) + (reg)))) = \
189 (u32)(dat)); \
190 mb();
191
192 /* Write to virge graphics register */
193
194 #define wgfx(reg, dat) do { wb_mmio(GCT_ADDRESS, (reg)); wb_mmio(GCT_ADDRESS_W, (dat)); } while (0)
195
196 /* Write to virge sequencer register */
197
198 #define wseq(reg, dat) do { wb_mmio(SEQ_ADDRESS, (reg)); wb_mmio(SEQ_ADDRESS_W, (dat)); } while (0)
199
200 /* Write to virge CRT controller register */
201
202 #define wcrt(reg, dat) do { wb_mmio(CRT_ADDRESS, (reg)); wb_mmio(CRT_ADDRESS_W, (dat)); } while (0)
203
204 /* Write to virge attribute register */
205
206 #define watr(reg, dat) \
207 do { \
208 volatile unsigned char watr_tmp; \
209 watr_tmp = rb_mmio(ACT_ADDRESS_RESET); \
210 wb_mmio(ACT_ADDRESS_W, (reg)); \
211 wb_mmio(ACT_ADDRESS_W, (dat)); \
212 udelay(10); \
213 } while (0)
214
215 /* end of macros */
216
217 struct virgefb_par {
218 struct fb_var_screeninfo var;
219 __u32 type;
220 __u32 type_aux;
221 __u32 visual;
222 __u32 line_length;
223 };
224
225 static struct virgefb_par current_par;
226
227 static int current_par_valid = 0;
228
229 static struct display disp;
230 static struct fb_info fb_info;
231
232 static union {
233 #ifdef FBCON_HAS_CFB16
234 u16 cfb16[16];
235 #endif
236 #ifdef FBCON_HAS_CFB32
237 u32 cfb32[16];
238 #endif
239 } fbcon_cmap;
240
241 /*
242 * Switch for Chipset Independency
243 */
244
245 static struct fb_hwswitch {
246
247 /* Initialisation */
248
249 int (*init)(void);
250
251 /* Display Control */
252
253 int (*encode_fix)(struct fb_fix_screeninfo *fix, struct virgefb_par *par);
254 int (*decode_var)(struct fb_var_screeninfo *var, struct virgefb_par *par);
255 int (*encode_var)(struct fb_var_screeninfo *var, struct virgefb_par *par);
256 int (*getcolreg)(u_int regno, u_int *red, u_int *green, u_int *blue,
257 u_int *transp, struct fb_info *info);
258 void (*blank)(int blank);
259 } *fbhw;
260
261 static unsigned char blit_maybe_busy = 0;
262
263 /*
264 * Frame Buffer Name
265 */
266
267 static char virgefb_name[16] = "CyberVision/3D";
268
269 /*
270 * CyberVision64/3d Graphics Board
271 */
272
273 static unsigned char virgefb_colour_table [256][3];
274 static unsigned long v_ram;
275 static unsigned long v_ram_size;
276 static volatile unsigned char *mmio_regs;
277 static volatile unsigned char *vgaio_regs;
278
279 static unsigned long v_ram_phys;
280 static unsigned long mmio_regs_phys;
281 static unsigned long vcode_switch_base;
282 static unsigned char on_zorro2;
283
284 /*
285 * Offsets from start of video ram to appropriate ZIII aperture
286 */
287
288 #ifdef FBCON_HAS_CFB8
289 #define CYBMEM_OFFSET_8 0x800000 /* BGRX */
290 #endif
291 #ifdef FBCON_HAS_CFB16
292 #define CYBMEM_OFFSET_16 0x400000 /* GBXR */
293 #endif
294 #ifdef FBCON_HAS_CFB32
295 #define CYBMEM_OFFSET_32 0x000000 /* XRGB */
296 #endif
297
298 /*
299 * MEMCLOCK was 32MHz, 64MHz works, 72MHz doesn't (on my board)
300 */
301
302 #define MEMCLOCK 50000000
303
304 /*
305 * Predefined Video Modes
306 */
307
308 static struct {
309 const char *name;
310 struct fb_var_screeninfo var;
311 } virgefb_predefined[] __initdata = {
312 #ifdef FBCON_HAS_CFB8
313 {
314 "640x480-8", { /* Cybervision 8 bpp */
315 640, 480, 640, 480, 0, 0, 8, 0,
316 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
317 0, 0, -1, -1, FB_ACCELF_TEXT, 31250, 160, 136, 82, 61, 88, 2,
318 0, FB_VMODE_NONINTERLACED
319 }
320 }, {
321 "768x576-8", { /* Cybervision 8 bpp */
322 768, 576, 768, 576, 0, 0, 8, 0,
323 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
324 0, 0, -1, -1, FB_ACCELF_TEXT, 29411, 144, 112, 32, 15, 64, 2,
325 0, FB_VMODE_NONINTERLACED
326 }
327 }, {
328 "800x600-8", { /* Cybervision 8 bpp */
329 800, 600, 800, 600, 0, 0, 8, 0,
330 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
331 0, 0, -1, -1, FB_ACCELF_TEXT, 28571, 168, 104, 22, 1, 48, 2,
332 0, FB_VMODE_NONINTERLACED
333 }
334 }, {
335 #if 0
336 "1024x768-8", { /* Cybervision 8 bpp */
337 1024, 768, 1024, 768, 0, 0, 8, 0,
338 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
339 0, 0, -1, -1, FB_ACCELF_TEXT, 20833, 272, 168, 39, 2, 72, 1,
340 0, FB_VMODE_NONINTERLACED
341 }
342 #else
343 "1024x768-8", {
344 1024, 768, 1024, 768, 0, 0, 8, 0,
345 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
346 #if 0
347 0, 0, -1, -1, FB_ACCELF_TEXT, 12500, 184, 40, 40, 2, 96, 1,
348 FB_SYNC_COMP_HIGH_ACT|FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED
349 }
350 #else
351 0, 0, -1, -1, FB_ACCELF_TEXT, 12699, 176, 16, 28, 1, 96, 3,
352 FB_SYNC_COMP_HIGH_ACT|FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED
353 }
354 #endif
355 #endif
356 }, {
357 "1152x886-8", { /* Cybervision 8 bpp */
358 1152, 886, 1152, 886, 0, 0, 8, 0,
359 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
360 0, 0, -1, -1, FB_ACCELF_TEXT, 19230, 280, 168, 45, 1, 64, 10,
361 0, FB_VMODE_NONINTERLACED
362 }
363 }, {
364 "1280x1024-8", { /* Cybervision 8 bpp */
365 1280, 1024, 1280, 1024, 0, 0, 8, 0,
366 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
367 #if 0
368 0, 0, -1, -1, FB_ACCELF_TEXT, 17857, 232, 232, 71, 15, 176, 12,
369 }
370 #else
371 0, 0, -1, -1, FB_ACCELF_TEXT, 7414, 232, 64, 38, 1, 112, 3,
372 FB_SYNC_COMP_HIGH_ACT|FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED
373 }
374 #endif
375 }, {
376 "1600x1200-8", { /* Cybervision 8 bpp */
377 1600, 1200, 1600, 1200, 0, 0, 8, 0,
378 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
379 #if 0
380 0, 0, -1, -1, FB_ACCELF_TEXT, 13698, 336, 224, 77, 15, 176, 12,
381 0, FB_VMODE_NONINTERLACED
382 }
383 #else
384 0, 0, -1, -1, FB_ACCELF_TEXT, 6411, 256, 32, 52, 10, 160, 8,
385 FB_SYNC_COMP_HIGH_ACT|FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED
386 }
387 #endif
388 },
389 #endif
390
391 #ifdef FBCON_HAS_CFB16
392 {
393 "640x480-16", { /* Cybervision 16 bpp */
394 640, 480, 640, 480, 0, 0, 16, 0,
395 {11, 5, 0}, {5, 6, 0}, {0, 5, 0}, {0, 0, 0},
396 0, 0, -1, -1, FB_ACCELF_TEXT, 31250, 152, 144, 82, 61, 88, 2,
397 0, FB_VMODE_NONINTERLACED
398 }
399 }, {
400 "768x576-16", { /* Cybervision 16 bpp */
401 768, 576, 768, 576, 0, 0, 16, 0,
402 {11, 5, 0}, {5, 6, 0}, {0, 5, 0}, {0, 0, 0},
403 0, 0, -1, -1, FB_ACCELF_TEXT, 29411, 144, 112, 32, 15, 64, 2,
404 0, FB_VMODE_NONINTERLACED
405 }
406 }, {
407 "800x600-16", { /* Cybervision 16 bpp */
408 800, 600, 800, 600, 0, 0, 16, 0,
409 {11, 5, 0}, {5, 6, 0}, {0, 5, 0}, {0, 0, 0},
410 0, 0, -1, -1, FB_ACCELF_TEXT, 28571, 168, 104, 22, 1, 48, 2,
411 0, FB_VMODE_NONINTERLACED
412 }
413 }, {
414 #if 0
415 "1024x768-16", { /* Cybervision 16 bpp */
416 1024, 768, 1024, 768, 0, 0, 16, 0,
417 {11, 5, 0}, {5, 6, 0}, {0, 5, 0}, {0, 0, 0},
418 0, 0, -1, -1, FB_ACCELF_TEXT, 20833, 272, 168, 39, 2, 72, 1,
419 0, FB_VMODE_NONINTERLACED
420 }
421 #else
422 "1024x768-16", {
423 1024, 768, 1024, 768, 0, 0, 16, 0,
424 {11, 5, 0}, {5, 6, 0}, {0, 5, 0}, {0, 0, 0},
425 0, 0, -1, -1, FB_ACCELF_TEXT, 12500, 184, 40, 40, 2, 96, 1,
426 FB_SYNC_COMP_HIGH_ACT|FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED
427 }
428 #endif
429 }, {
430 "1152x886-16", { /* Cybervision 16 bpp */
431 1152, 886, 1152, 886, 0, 0, 16, 0,
432 {11, 5, 0}, {5, 6, 0}, {0, 5, 0}, {0, 0, 0},
433 0, 0, -1, -1, FB_ACCELF_TEXT, 19230, 280, 168, 45, 1, 64, 10,
434 0, FB_VMODE_NONINTERLACED
435 }
436 }, {
437 "1280x1024-16", { /* Cybervision 16 bpp */
438 1280, 1024, 1280, 1024, 0, 0, 16, 0,
439 {11, 5, 0}, {5, 6, 0}, {0, 5, 0}, {0, 0, 0},
440 0, 0, -1, -1, FB_ACCELF_TEXT, 17857, 232, 232, 71, 15, 176, 12,
441 0, FB_VMODE_NONINTERLACED
442 }
443 }, {
444 "1600x1200-16", { /* Cybervision 16 bpp */
445 1600, 1200, 1600, 1200, 0, 0, 16, 0,
446 {11, 5, 0}, {5, 6, 0}, {0, 5, 0}, {0, 0, 0},
447 0, 0, -1, -1, FB_ACCELF_TEXT, 13698, 336, 224, 77, 15, 176, 12,
448 0, FB_VMODE_NONINTERLACED
449 }
450 },
451 #endif
452
453 #ifdef FBCON_HAS_CFB32
454 {
455 "640x480-32", { /* Cybervision 32 bpp */
456 640, 480, 640, 480, 0, 0, 32, 0,
457 {16, 8, 0}, {8, 8, 0}, {0, 8, 0}, {24, 0, 0},
458 0, 0, -1, -1, FB_ACCELF_TEXT, 31250, 160, 136, 82, 61, 88, 2,
459 0, FB_VMODE_NONINTERLACED
460 }
461 }, {
462 "768x576-32", { /* Cybervision 32 bpp */
463 768, 576, 768, 576, 0, 0, 32, 0,
464 {16, 8, 0}, {8, 8, 0}, {0, 8, 0}, {24, 0, 0},
465 0, 0, -1, -1, FB_ACCELF_TEXT, 29411, 144, 112, 32, 15, 64, 2,
466 0, FB_VMODE_NONINTERLACED
467 }
468 }, {
469 "800x600-32", { /* Cybervision 32 bpp */
470 800, 600, 800, 600, 0, 0, 32, 0,
471 {16, 8, 0}, {8, 8, 0}, {0, 8, 0}, {24, 0, 0},
472 0, 0, -1, -1, FB_ACCELF_TEXT, 28571, 168, 104, 22, 1, 48, 2,
473 0, FB_VMODE_NONINTERLACED
474 }
475 }, {
476 "1024x768-32", { /* Cybervision 32 bpp */
477 1024, 768, 1024, 768, 0, 0, 32, 0,
478 {16, 8, 0}, {8, 8, 0}, {0, 8, 0}, {24, 0, 0},
479 0, 0, -1, -1, FB_ACCELF_TEXT, 20833, 272, 168, 39, 2, 72, 1,
480 0, FB_VMODE_NONINTERLACED
481 }
482 }, {
483 "1152x886-32", { /* Cybervision 32 bpp */
484 1152, 886, 1152, 886, 0, 0, 32, 0,
485 {16, 8, 0}, {8, 8, 0}, {0, 8, 0}, {24, 0, 0},
486 0, 0, -1, -1, FB_ACCELF_TEXT, 19230, 280, 168, 45, 1, 64, 10,
487 0, FB_VMODE_NONINTERLACED
488 }
489 }, {
490 "1280x1024-32", { /* Cybervision 32 bpp */
491 1280, 1024, 1280, 1024, 0, 0, 32, 0,
492 {16, 8, 0}, {8, 8, 0}, {0, 8, 0}, {24, 0, 0},
493 0, 0, -1, -1, FB_ACCELF_TEXT, 17857, 232, 232, 71, 15, 176, 12,
494 0, FB_VMODE_NONINTERLACED
495 }
496 }, {
497 "1600x1200-32", { /* Cybervision 32 bpp */
498 1600, 1200, 1600, 1200, 0, 0, 32, 0,
499 {16, 8, 0}, {8, 8, 0}, {0, 8, 0}, {24, 0, 0},
500 0, 0, -1, -1, FB_ACCELF_TEXT, 13698, 336, 224, 77, 15, 176, 12,
501 0, FB_VMODE_NONINTERLACED
502 }
503 },
504 #endif
505
506 /* interlaced modes */
507
508 #ifdef FBCON_HAS_CFB8
509 {
510 "1024x768-8i", { /* Cybervision 8 bpp */
511 1024, 768, 1024, 768, 0, 0, 8, 0,
512 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
513 0, 0, -1, -1, FB_ACCELF_TEXT, 20833, 272, 168, 39, 2, 72, 1,
514 0, FB_VMODE_INTERLACED
515 }
516 }, {
517 "1280x1024-8i", { /* Cybervision 8 bpp */
518 1280, 1024, 1280, 1024, 0, 0, 8, 0,
519 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
520 0, 0, -1, -1, FB_ACCELF_TEXT, 17857, 232, 232, 71, 15, 176, 12,
521 0, FB_VMODE_INTERLACED
522 }
523 }, {
524 "1600x1200-8i", { /* Cybervision 8 bpp */
525 1600, 1200, 1600, 1200, 0, 0, 8, 0,
526 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
527 0, 0, -1, -1, FB_ACCELF_TEXT, 13698, 336, 224, 77, 15, 176, 12,
528 0, FB_VMODE_INTERLACED
529 }
530 },
531 #endif
532
533 #ifdef FBCON_HAS_CFB16
534 {
535 "1024x768-16i", { /* Cybervision 16 bpp */
536 1024, 768, 1024, 768, 0, 0, 16, 0,
537 {11, 5, 0}, {5, 6, 0}, {0, 5, 0}, {0, 0, 0},
538 0, 0, -1, -1, FB_ACCELF_TEXT, 20833, 272, 168, 39, 2, 72, 1,
539 0, FB_VMODE_INTERLACED
540 }
541 }, {
542 "1280x1024-16i", { /* Cybervision 16 bpp */
543 1280, 1024, 1280, 1024, 0, 0, 16, 0,
544 {11, 5, 0}, {5, 6, 0}, {0, 5, 0}, {0, 0, 0},
545 0, 0, -1, -1, FB_ACCELF_TEXT, 17857, 232, 232, 71, 15, 176, 12,
546 0, FB_VMODE_INTERLACED
547 }
548 }, {
549 "1600x1200-16i", { /* Cybervision 16 bpp */
550 1600, 1200, 1600, 1200, 0, 0, 16, 0,
551 {11, 5, 0}, {5, 6, 0}, {0, 5, 0}, {0, 0, 0},
552 0, 0, -1, -1, FB_ACCELF_TEXT, 13698, 336, 224, 77, 15, 176, 12,
553 0, FB_VMODE_INTERLACED
554 }
555 },
556 #endif
557
558 #ifdef FBCON_HAS_CFB32
559 {
560 "1024x768-32i", { /* Cybervision 32 bpp */
561 1024, 768, 1024, 768, 0, 0, 32, 0,
562 {16, 8, 0}, {8, 8, 0}, {0, 8, 0}, {24, 0, 0},
563 0, 0, -1, -1, FB_ACCELF_TEXT, 22222, 216, 144, 39, 2, 72, 1,
564 0, FB_VMODE_INTERLACED
565 }
566 }, {
567 "1280x1024-32i", { /* Cybervision 32 bpp */
568 1280, 1024, 1280, 1024, 0, 0, 32, 0,
569 {16, 8, 0}, {8, 8, 0}, {0, 8, 0}, {23, 0, 0},
570 0, 0, -1, -1, FB_ACCELF_TEXT, 17857, 232, 232, 71, 15, 176, 12,
571 0, FB_VMODE_INTERLACED
572 }
573 }, {
574 "1600x1200-32i", { /* Cybervision 32 bpp */
575 1600, 1200, 1600, 1200, 0, 0, 32, 0,
576 {16, 8, 0}, {8, 8, 0}, {0, 8, 0}, {24, 0, 0},
577 0, 0, -1, -1, FB_ACCELF_TEXT, 13698, 336, 224, 77, 15, 176, 12,
578 0, FB_VMODE_INTERLACED
579 }
580 },
581 #endif
582
583 /* doublescan modes */
584
585 #ifdef FBCON_HAS_CFB8
586 {
587 "320x240-8d", { /* Cybervision 8 bpp */
588 320, 240, 320, 240, 0, 0, 8, 0,
589 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
590 0, 0, -1, -1, FB_ACCELF_TEXT, 59259, 80, 80, 45, 26, 32, 1,
591 0, FB_VMODE_DOUBLE
592 }
593 },
594 #endif
595
596 #ifdef FBCON_HAS_CFB16
597 {
598 "320x240-16d", { /* Cybervision 16 bpp */
599 320, 240, 320, 240, 0, 0, 16, 0,
600 {11, 5, 0}, {5, 6, 0}, {0, 5, 0}, {0, 0, 0},
601 0, 0, -1, -1, FB_ACCELF_TEXT, 59259, 80, 80, 45, 26, 32, 1,
602 0, FB_VMODE_DOUBLE
603 }
604 },
605 #endif
606
607 #ifdef FBCON_HAS_CFB32
608 {
609 "320x240-32d", { /* Cybervision 32 bpp */
610 320, 240, 320, 240, 0, 0, 32, 0,
611 {16, 8, 0}, {8, 8, 0}, {0, 8, 0}, {24, 0, 0},
612 0, 0, -1, -1, FB_ACCELF_TEXT, 59259, 80, 80, 45, 26, 32, 1,
613 0, FB_VMODE_DOUBLE
614 }
615 },
616 #endif
617 };
618
619 #define NUM_TOTAL_MODES ARRAY_SIZE(virgefb_predefined)
620
621 /*
622 * Default to 800x600 for video=virge8:, virge16: or virge32:
623 */
624
625 #ifdef FBCON_HAS_CFB8
626 #define VIRGE8_DEFMODE (2)
627 #endif
628
629 #ifdef FBCON_HAS_CFB16
630 #define VIRGE16_DEFMODE (9)
631 #endif
632
633 #ifdef FBCON_HAS_CFB32
634 #define VIRGE32_DEFMODE (16)
635 #endif
636
637 static struct fb_var_screeninfo virgefb_default;
638 static int virgefb_inverse = 0;
639
640 /*
641 * Interface used by the world
642 */
643
644 int virgefb_setup(char*);
645 static int virgefb_get_fix(struct fb_fix_screeninfo *fix, int con,
646 struct fb_info *info);
647 static int virgefb_get_var(struct fb_var_screeninfo *var, int con,
648 struct fb_info *info);
649 static int virgefb_set_var(struct fb_var_screeninfo *var, int con,
650 struct fb_info *info);
651 static int virgefb_get_cmap(struct fb_cmap *cmap, int kspc, int con,
652 struct fb_info *info);
653 static int virgefb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
654 u_int transp, struct fb_info *info);
655 static int virgefb_blank(int blank, struct fb_info *info);
656
657 /*
658 * Interface to the low level console driver
659 */
660
661 int virgefb_init(void);
662 static int virgefb_switch(int con, struct fb_info *info);
663 static int virgefb_updatevar(int con, struct fb_info *info);
664
665 /*
666 * Text console acceleration
667 */
668
669 #ifdef FBCON_HAS_CFB8
670 static struct display_switch fbcon_virge8;
671 #endif
672
673 #ifdef FBCON_HAS_CFB16
674 static struct display_switch fbcon_virge16;
675 #endif
676
677 #ifdef FBCON_HAS_CFB32
678 static struct display_switch fbcon_virge32;
679 #endif
680
681 /*
682 * Hardware Specific Routines
683 */
684
685 static int virge_init(void);
686 static int virgefb_encode_fix(struct fb_fix_screeninfo *fix,
687 struct virgefb_par *par);
688 static int virgefb_decode_var(struct fb_var_screeninfo *var,
689 struct virgefb_par *par);
690 static int virgefb_encode_var(struct fb_var_screeninfo *var,
691 struct virgefb_par *par);
692 static int virgefb_getcolreg(u_int regno, u_int *red, u_int *green, u_int *blue,
693 u_int *transp, struct fb_info *info);
694 static void virgefb_gfx_on_off(int blank);
695 static inline void virgefb_wait_for_idle(void);
696 static void virgefb_BitBLT(u_short curx, u_short cury, u_short destx, u_short desty,
697 u_short width, u_short height, u_short stride, u_short depth);
698 static void virgefb_RectFill(u_short x, u_short y, u_short width, u_short height,
699 u_short color, u_short stride, u_short depth);
700
701 /*
702 * Internal routines
703 */
704
705 static void virgefb_get_par(struct virgefb_par *par);
706 static void virgefb_set_par(struct virgefb_par *par);
707 static int virgefb_do_fb_set_var(struct fb_var_screeninfo *var, int isactive);
708 static void virgefb_set_disp(int con, struct fb_info *info);
709 static int virgefb_get_video_mode(const char *name);
710 static void virgefb_set_video(struct fb_var_screeninfo *var);
711
712 /*
713 * Additions for Initialization
714 */
715
716 static void virgefb_load_video_mode(struct fb_var_screeninfo *video_mode);
717 static int cv3d_has_4mb(void);
718 static unsigned short virgefb_compute_clock(unsigned long freq);
719 static inline unsigned char rattr(short);
720 static inline unsigned char rseq(short);
721 static inline unsigned char rcrt(short);
722 static inline unsigned char rgfx(short);
723 static inline void gfx_on_off(int toggle);
724 static void virgefb_pci_init(void);
725
726 /* -------------------- Hardware specific routines ------------------------- */
727
728 /*
729 * Functions for register access
730 */
731
732 /* Read attribute controller register */
733
734 static inline unsigned char rattr(short idx)
735 {
736 volatile unsigned char rattr_tmp;
737
738 rattr_tmp = rb_mmio(ACT_ADDRESS_RESET);
739 wb_mmio(ACT_ADDRESS_W, idx);
740 return (rb_mmio(ACT_ADDRESS_R));
741 }
742
743 /* Read sequencer register */
744
745 static inline unsigned char rseq(short idx)
746 {
747 wb_mmio(SEQ_ADDRESS, idx);
748 return (rb_mmio(SEQ_ADDRESS_R));
749 }
750
751 /* Read CRT controller register */
752
753 static inline unsigned char rcrt(short idx)
754 {
755 wb_mmio(CRT_ADDRESS, idx);
756 return (rb_mmio(CRT_ADDRESS_R));
757 }
758
759 /* Read graphics controller register */
760
761 static inline unsigned char rgfx(short idx)
762 {
763 wb_mmio(GCT_ADDRESS, idx);
764 return (rb_mmio(GCT_ADDRESS_R));
765 }
766
767
768 /*
769 * Initialization
770 */
771
772 /* PCI init */
773
774 void virgefb_pci_init(void) {
775
776 DPRINTK("ENTER\n");
777
778 SelectCFG;
779
780 if (on_zorro2) {
781 *((short *)(vgaio_regs + 0x00000010)) = 0;
782 *((long *)(vgaio_regs + 0x00000004)) = 0x02000003;
783 } else {
784 *((short *)(vgaio_regs + 0x000e0010)) = 0;
785 *((long *)(vgaio_regs + 0x000e0004)) = 0x02000003;
786 }
787
788 /* SelectIO is in wb_vgaio macro */
789 wb_vgaio(SREG_VIDEO_SUBS_ENABLE, 0x01);
790 /* SelectMMIO is in wb_vgaio macro */
791
792 DPRINTK("EXIT\n");
793
794 return;
795 }
796
797 /*
798 * Initalize all mode independent regs, find mem size and clear mem
799 */
800
801 static int virge_init(void)
802 {
803 int i;
804 unsigned char tmp;
805
806 DPRINTK("ENTER\n");
807
808 virgefb_pci_init();
809
810 wb_mmio(GREG_MISC_OUTPUT_W, 0x07); /* colour, ram enable, clk sel */
811
812 wseq(SEQ_ID_UNLOCK_EXT, 0x06); /* unlock extensions */
813 tmp = rb_mmio(GREG_MISC_OUTPUT_R);
814 wcrt(CRT_ID_REGISTER_LOCK_1, 0x48); /* unlock CR2D to CR3F */
815
816 wcrt(CRT_ID_BACKWAD_COMP_1, 0x00); /* irq disable */
817
818 wcrt(CRT_ID_REGISTER_LOCK_2, 0xa5); /* unlock CR40 to CRFF and more */
819 wcrt(CRT_ID_REGISTER_LOCK,0x00); /* unlock h and v timing */
820 wcrt(CRT_ID_SYSTEM_CONFIG, 0x01); /* unlock enhanced programming registers */
821
822 wb_mmio(GREG_FEATURE_CONTROL_W, 0x00);
823
824 wcrt(CRT_ID_EXT_MISC_CNTL, 0x00); /* b2 = 0 to allow VDAC mmio access */
825 #if 0
826 /* write strap options ... ? */
827 wcrt(CRT_ID_CONFIG_1, 0x08);
828 wcrt(CRT_ID_CONFIG_2, 0xff); /* 0x0x2 bit needs to be set ?? */
829 wcrt(CRT_ID_CONFIG_3, 0x0f);
830 wcrt(CRT_ID_CONFIG_4, 0x1a);
831 #endif
832 wcrt(CRT_ID_EXT_MISC_CNTL_1, 0x82); /* PCI DE and software reset S3D engine */
833 /* EXT_MISC_CNTL_1, CR66 bit 0 should be the same as bit 0 MR_ADVANCED_FUNCTION_CONTROL - check */
834 wl_mmio(MR_ADVANCED_FUNCTION_CONTROL, 0x00000011); /* enhanced mode, linear addressing */
835
836 /* crtc registers */
837
838 wcrt(CRT_ID_PRESET_ROW_SCAN, 0x00);
839
840 /* Disable h/w cursor */
841
842 wcrt(CRT_ID_CURSOR_START, 0x00);
843 wcrt(CRT_ID_CURSOR_END, 0x00);
844 wcrt(CRT_ID_START_ADDR_HIGH, 0x00);
845 wcrt(CRT_ID_START_ADDR_LOW, 0x00);
846 wcrt(CRT_ID_CURSOR_LOC_HIGH, 0x00);
847 wcrt(CRT_ID_CURSOR_LOC_LOW, 0x00);
848 wcrt(CRT_ID_EXT_MODE, 0x00);
849 wcrt(CRT_ID_HWGC_MODE, 0x00);
850 wcrt(CRT_ID_HWGC_ORIGIN_X_HI, 0x00);
851 wcrt(CRT_ID_HWGC_ORIGIN_X_LO, 0x00);
852 wcrt(CRT_ID_HWGC_ORIGIN_Y_HI, 0x00);
853 wcrt(CRT_ID_HWGC_ORIGIN_Y_LO, 0x00);
854 i = rcrt(CRT_ID_HWGC_MODE);
855 wcrt(CRT_ID_HWGC_FG_STACK, 0x00);
856 wcrt(CRT_ID_HWGC_FG_STACK, 0x00);
857 wcrt(CRT_ID_HWGC_FG_STACK, 0x00);
858 wcrt(CRT_ID_HWGC_BG_STACK, 0x00);
859 wcrt(CRT_ID_HWGC_BG_STACK, 0x00);
860 wcrt(CRT_ID_HWGC_BG_STACK, 0x00);
861 wcrt(CRT_ID_HWGC_START_AD_HI, 0x00);
862 wcrt(CRT_ID_HWGC_START_AD_LO, 0x00);
863 wcrt(CRT_ID_HWGC_DSTART_X, 0x00);
864 wcrt(CRT_ID_HWGC_DSTART_Y, 0x00);
865
866 wcrt(CRT_ID_UNDERLINE_LOC, 0x00);
867
868 wcrt(CRT_ID_MODE_CONTROL, 0xe3);
869 wcrt(CRT_ID_BACKWAD_COMP_2, 0x22); /* blank bdr bit 5 blanking only on 8 bit */
870
871 wcrt(CRT_ID_EX_SYNC_1, 0x00);
872
873 /* memory */
874
875 wcrt(CRT_ID_EXT_SYS_CNTL_3, 0x00);
876 wcrt(CRT_ID_MEMORY_CONF, 0x08); /* config enhanced map */
877 wcrt(CRT_ID_EXT_MEM_CNTL_1, 0x08); /* MMIO Select (0x0c works as well)*/
878 wcrt(CRT_ID_EXT_MEM_CNTL_2, 0x02); /* why 02 big endian 00 works ? */
879 wcrt(CRT_ID_EXT_MEM_CNTL_4, 0x9f); /* config big endian - 0x00 ? */
880 wcrt(CRT_ID_LAW_POS_HI, 0x00);
881 wcrt(CRT_ID_LAW_POS_LO, 0x00);
882 wcrt(CRT_ID_EXT_MISC_CNTL_1, 0x81);
883 wcrt(CRT_ID_MISC_1, 0x90); /* must follow CRT_ID_EXT_MISC_CNTL_1 */
884 wcrt(CRT_ID_LAW_CNTL, 0x13); /* force 4 Meg for test */
885 if (cv3d_has_4mb()) {
886 v_ram_size = 0x00400000;
887 wcrt(CRT_ID_LAW_CNTL, 0x13); /* 4 MB */
888 } else {
889 v_ram_size = 0x00200000;
890 wcrt(CRT_ID_LAW_CNTL, 0x12); /* 2 MB */
891 }
892
893 if (on_zorro2)
894 v_ram_size -= 0x60000; /* we need some space for the registers */
895
896 wcrt(CRT_ID_EXT_SYS_CNTL_4, 0x00);
897 wcrt(CRT_ID_EXT_DAC_CNTL, 0x00); /* 0x10 for X11 cursor mode */
898
899 /* sequencer registers */
900
901 wseq(SEQ_ID_CLOCKING_MODE, 0x01); /* 8 dot clock */
902 wseq(SEQ_ID_MAP_MASK, 0xff);
903 wseq(SEQ_ID_CHAR_MAP_SELECT, 0x00);
904 wseq(SEQ_ID_MEMORY_MODE, 0x02);
905 wseq(SEQ_ID_RAMDAC_CNTL, 0x00);
906 wseq(SEQ_ID_SIGNAL_SELECT, 0x00);
907 wseq(SEQ_ID_EXT_SEQ_REG9, 0x00); /* MMIO and PIO reg access enabled */
908 wseq(SEQ_ID_EXT_MISC_SEQ, 0x00);
909 wseq(SEQ_ID_CLKSYN_CNTL_1, 0x00);
910 wseq(SEQ_ID_EXT_SEQ, 0x00);
911
912 /* graphic registers */
913
914 wgfx(GCT_ID_SET_RESET, 0x00);
915 wgfx(GCT_ID_ENABLE_SET_RESET, 0x00);
916 wgfx(GCT_ID_COLOR_COMPARE, 0x00);
917 wgfx(GCT_ID_DATA_ROTATE, 0x00);
918 wgfx(GCT_ID_READ_MAP_SELECT, 0x00);
919 wgfx(GCT_ID_GRAPHICS_MODE, 0x40);
920 wgfx(GCT_ID_MISC, 0x01);
921 wgfx(GCT_ID_COLOR_XCARE, 0x0f);
922 wgfx(GCT_ID_BITMASK, 0xff);
923
924 /* attribute registers */
925
926 for(i = 0; i <= 15; i++)
927 watr(ACT_ID_PALETTE0 + i, i);
928 watr(ACT_ID_ATTR_MODE_CNTL, 0x41);
929 watr(ACT_ID_OVERSCAN_COLOR, 0xff);
930 watr(ACT_ID_COLOR_PLANE_ENA, 0x0f);
931 watr(ACT_ID_HOR_PEL_PANNING, 0x00);
932 watr(ACT_ID_COLOR_SELECT, 0x00);
933
934 wb_mmio(VDAC_MASK, 0xff);
935
936 /* init local cmap as greyscale levels */
937
938 for (i = 0; i < 256; i++) {
939 virgefb_colour_table [i][0] = i;
940 virgefb_colour_table [i][1] = i;
941 virgefb_colour_table [i][2] = i;
942 }
943
944 /* clear framebuffer memory */
945
946 memset((char*)v_ram, 0x00, v_ram_size);
947
948 DPRINTK("EXIT\n");
949 return 0;
950 }
951
952
953 /*
954 * This function should fill in the `fix' structure based on the
955 * values in the `par' structure.
956 */
957
958 static int virgefb_encode_fix(struct fb_fix_screeninfo *fix,
959 struct virgefb_par *par)
960 {
961 DPRINTK("ENTER set video phys addr\n");
962
963 memset(fix, 0, sizeof(struct fb_fix_screeninfo));
964 strcpy(fix->id, virgefb_name);
965 if (on_zorro2)
966 fix->smem_start = v_ram_phys;
967 switch (par->var.bits_per_pixel) {
968 #ifdef FBCON_HAS_CFB8
969 case 8:
970 if (on_zorro2)
971 Select_Zorro2_FrameBuffer(ENDIAN_BYTE);
972 else
973 fix->smem_start = (v_ram_phys + CYBMEM_OFFSET_8);
974 break;
975 #endif
976 #ifdef FBCON_HAS_CFB16
977 case 16:
978 if (on_zorro2)
979 Select_Zorro2_FrameBuffer(ENDIAN_WORD);
980 else
981 fix->smem_start = (v_ram_phys + CYBMEM_OFFSET_16);
982 break;
983 #endif
984 #ifdef FBCON_HAS_CFB32
985 case 32:
986 if (on_zorro2)
987 Select_Zorro2_FrameBuffer(ENDIAN_LONG);
988 else
989 fix->smem_start = (v_ram_phys + CYBMEM_OFFSET_32);
990 break;
991 #endif
992 }
993
994 fix->smem_len = v_ram_size;
995 fix->mmio_start = mmio_regs_phys;
996 fix->mmio_len = 0x10000; /* TODO: verify this for the CV64/3D */
997
998 fix->type = FB_TYPE_PACKED_PIXELS;
999 fix->type_aux = 0;
1000 if (par->var.bits_per_pixel == 8)
1001 fix->visual = FB_VISUAL_PSEUDOCOLOR;
1002 else
1003 fix->visual = FB_VISUAL_TRUECOLOR;
1004
1005 fix->xpanstep = 0;
1006 fix->ypanstep = 0;
1007 fix->ywrapstep = 0;
1008 fix->line_length = par->var.xres_virtual*par->var.bits_per_pixel/8;
1009 fix->accel = FB_ACCEL_S3_VIRGE;
1010 DPRINTK("EXIT v_ram_phys = 0x%8.8lx\n", (unsigned long)fix->smem_start);
1011 return 0;
1012 }
1013
1014
1015 /*
1016 * Fill the `par' structure based on the values in `var'.
1017 * TODO: Verify and adjust values, return -EINVAL if bad.
1018 */
1019
1020 static int virgefb_decode_var(struct fb_var_screeninfo *var,
1021 struct virgefb_par *par)
1022 {
1023 DPRINTK("ENTER\n");
1024 par->var.xres = var->xres;
1025 par->var.yres = var->yres;
1026 par->var.xres_virtual = var->xres_virtual;
1027 par->var.yres_virtual = var->yres_virtual;
1028 /* roundup and validate */
1029 par->var.xres = (par->var.xres+7) & ~7;
1030 par->var.xres_virtual = (par->var.xres_virtual+7) & ~7;
1031 if (par->var.xres_virtual < par->var.xres)
1032 par->var.xres_virtual = par->var.xres;
1033 if (par->var.yres_virtual < par->var.yres)
1034 par->var.yres_virtual = par->var.yres;
1035 par->var.xoffset = var->xoffset;
1036 par->var.yoffset = var->yoffset;
1037 par->var.bits_per_pixel = var->bits_per_pixel;
1038 if (par->var.bits_per_pixel <= 8)
1039 par->var.bits_per_pixel = 8;
1040 else if (par->var.bits_per_pixel <= 16)
1041 par->var.bits_per_pixel = 16;
1042 else
1043 par->var.bits_per_pixel = 32;
1044 #ifndef FBCON_HAS_CFB32
1045 if (par->var.bits_per_pixel == 32)
1046 par->var.bits_per_pixel = 16;
1047 #endif
1048 #ifndef FBCON_HAS_CFB16
1049 if (par->var.bits_per_pixel == 16)
1050 par->var.bits_per_pixel = 8;
1051 #endif
1052 par->var.grayscale = var->grayscale;
1053 par->var.red = var->red;
1054 par->var.green = var->green;
1055 par->var.blue = var->blue;
1056 par->var.transp = var->transp;
1057 par->var.nonstd = var->nonstd;
1058 par->var.activate = var->activate;
1059 par->var.height = var->height;
1060 par->var.width = var->width;
1061 if (var->accel_flags & FB_ACCELF_TEXT) {
1062 par->var.accel_flags = FB_ACCELF_TEXT;
1063 } else {
1064 par->var.accel_flags = 0;
1065 }
1066 par->var.pixclock = var->pixclock;
1067 par->var.left_margin = var->left_margin;
1068 par->var.right_margin = var->right_margin;
1069 par->var.upper_margin = var->upper_margin;
1070 par->var.lower_margin = var->lower_margin;
1071 par->var.hsync_len = var->hsync_len;
1072 par->var.vsync_len = var->vsync_len;
1073 par->var.sync = var->sync;
1074 par->var.vmode = var->vmode;
1075 DPRINTK("EXIT\n");
1076 return 0;
1077 }
1078
1079 /*
1080 * Fill the `var' structure based on the values in `par' and maybe
1081 * other values read out of the hardware.
1082 */
1083
1084 static int virgefb_encode_var(struct fb_var_screeninfo *var,
1085 struct virgefb_par *par)
1086 {
1087 DPRINTK("ENTER\n");
1088 memset(var, 0, sizeof(struct fb_var_screeninfo)); /* need this ? */
1089 var->xres = par->var.xres;
1090 var->yres = par->var.yres;
1091 var->xres_virtual = par->var.xres_virtual;
1092 var->yres_virtual = par->var.yres_virtual;
1093 var->xoffset = par->var.xoffset;
1094 var->yoffset = par->var.yoffset;
1095 var->bits_per_pixel = par->var.bits_per_pixel;
1096 var->grayscale = par->var.grayscale;
1097 var->red = par->var.red;
1098 var->green = par->var.green;
1099 var->blue = par->var.blue;
1100 var->transp = par->var.transp;
1101 var->nonstd = par->var.nonstd;
1102 var->activate = par->var.activate;
1103 var->height = par->var.height;
1104 var->width = par->var.width;
1105 var->accel_flags = par->var.accel_flags;
1106 var->pixclock = par->var.pixclock;
1107 var->left_margin = par->var.left_margin;
1108 var->right_margin = par->var.right_margin;
1109 var->upper_margin = par->var.upper_margin;
1110 var->lower_margin = par->var.lower_margin;
1111 var->hsync_len = par->var.hsync_len;
1112 var->vsync_len = par->var.vsync_len;
1113 var->sync = par->var.sync;
1114 var->vmode = par->var.vmode;
1115 DPRINTK("EXIT\n");
1116 return 0;
1117 }
1118
1119 /*
1120 * Set a single color register. The values supplied are already
1121 * rounded down to the hardware's capabilities (according to the
1122 * entries in the var structure). Return != 0 for invalid regno.
1123 */
1124
1125 static int virgefb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
1126 u_int transp, struct fb_info *info)
1127 {
1128 DPRINTK("ENTER\n");
1129 if (((current_par.var.bits_per_pixel==8) && (regno>255)) ||
1130 ((current_par.var.bits_per_pixel!=8) && (regno>15))) {
1131 DPRINTK("EXIT\n");
1132 return 1;
1133 }
1134 if (((current_par.var.bits_per_pixel==8) && (regno<256)) ||
1135 ((current_par.var.bits_per_pixel!=8) && (regno<16))) {
1136 virgefb_colour_table [regno][0] = red >> 10;
1137 virgefb_colour_table [regno][1] = green >> 10;
1138 virgefb_colour_table [regno][2] = blue >> 10;
1139 }
1140
1141 switch (current_par.var.bits_per_pixel) {
1142 #ifdef FBCON_HAS_CFB8
1143 case 8:
1144 wb_mmio(VDAC_ADDRESS_W, (unsigned char)regno);
1145 wb_mmio(VDAC_DATA, ((unsigned char)(red >> 10)));
1146 wb_mmio(VDAC_DATA, ((unsigned char)(green >> 10)));
1147 wb_mmio(VDAC_DATA, ((unsigned char)(blue >> 10)));
1148 break;
1149 #endif
1150 #ifdef FBCON_HAS_CFB16
1151 case 16:
1152 fbcon_cmap.cfb16[regno] =
1153 ((red & 0xf800) |
1154 ((green & 0xfc00) >> 5) |
1155 ((blue & 0xf800) >> 11));
1156 break;
1157 #endif
1158 #ifdef FBCON_HAS_CFB32
1159 case 32:
1160 fbcon_cmap.cfb32[regno] =
1161 /* transp = 0's or 1's ? */
1162 (((red & 0xff00) << 8) |
1163 ((green & 0xff00) >> 0) |
1164 ((blue & 0xff00) >> 8));
1165 break;
1166 #endif
1167 }
1168 DPRINTK("EXIT\n");
1169 return 0;
1170 }
1171
1172
1173 /*
1174 * Read a single color register and split it into
1175 * colors/transparent. Return != 0 for invalid regno.
1176 */
1177
1178 static int virgefb_getcolreg(u_int regno, u_int *red, u_int *green, u_int *blue,
1179 u_int *transp, struct fb_info *info)
1180 {
1181 int t;
1182
1183 DPRINTK("ENTER\n");
1184 if (regno > 255) {
1185 DPRINTK("EXIT\n");
1186 return 1;
1187 }
1188 if (((current_par.var.bits_per_pixel==8) && (regno<256)) ||
1189 ((current_par.var.bits_per_pixel!=8) && (regno<16))) {
1190
1191 t = virgefb_colour_table [regno][0];
1192 *red = (t<<10) | (t<<4) | (t>>2);
1193 t = virgefb_colour_table [regno][1];
1194 *green = (t<<10) | (t<<4) | (t>>2);
1195 t = virgefb_colour_table [regno][2];
1196 *blue = (t<<10) | (t<<4) | (t>>2);
1197 }
1198 *transp = 0;
1199 DPRINTK("EXIT\n");
1200 return 0;
1201 }
1202
1203
1204 /*
1205 * (Un)Blank the screen
1206 */
1207
1208 static void virgefb_gfx_on_off(int blank)
1209 {
1210 DPRINTK("ENTER\n");
1211 gfx_on_off(blank);
1212 DPRINTK("EXIT\n");
1213 }
1214
1215 /*
1216 * CV3D low-level support
1217 */
1218
1219
1220 static inline void wait_3d_fifo_slots(int n) /* WaitQueue */
1221 {
1222 do {
1223 mb();
1224 } while (((rl_mmio(MR_SUBSYSTEM_STATUS_R) >> 8) & 0x1f) < (n + 2));
1225 }
1226
1227 static inline void virgefb_wait_for_idle(void) /* WaitIdle */
1228 {
1229 while(!(rl_mmio(MR_SUBSYSTEM_STATUS_R) & 0x2000)) ;
1230 blit_maybe_busy = 0;
1231 }
1232
1233 /*
1234 * BitBLT - Through the Plane
1235 */
1236
1237 static void virgefb_BitBLT(u_short curx, u_short cury, u_short destx, u_short desty,
1238 u_short width, u_short height, u_short stride, u_short depth)
1239 {
1240 unsigned int blitcmd = S3V_BITBLT | S3V_DRAW | S3V_BLT_COPY;
1241
1242 switch (depth) {
1243 #ifdef FBCON_HAS_CFB8
1244 case 8 :
1245 blitcmd |= S3V_DST_8BPP;
1246 break;
1247 #endif
1248 #ifdef FBCON_HAS_CFB16
1249 case 16 :
1250 blitcmd |= S3V_DST_16BPP;
1251 break;
1252 #endif
1253 #ifdef FBCON_HAS_CFB32
1254 case 32 :
1255 /* 32 bit uses 2 by 16 bit values, see fbcon_virge32_bmove */
1256 blitcmd |= S3V_DST_16BPP;
1257 break;
1258 #endif
1259 }
1260
1261 /* Set drawing direction */
1262 /* -Y, X maj, -X (default) */
1263 if (curx > destx) {
1264 blitcmd |= (1 << 25); /* Drawing direction +X */
1265 } else {
1266 curx += (width - 1);
1267 destx += (width - 1);
1268 }
1269
1270 if (cury > desty) {
1271 blitcmd |= (1 << 26); /* Drawing direction +Y */
1272 } else {
1273 cury += (height - 1);
1274 desty += (height - 1);
1275 }
1276
1277 wait_3d_fifo_slots(8); /* wait on fifo slots for 8 writes */
1278
1279 if (blit_maybe_busy)
1280 virgefb_wait_for_idle();
1281 blit_maybe_busy = 1;
1282
1283 wl_mmio(BLT_PATTERN_COLOR, 1); /* pattern fb color */
1284 wl_mmio(BLT_MONO_PATTERN_0, ~0);
1285 wl_mmio(BLT_MONO_PATTERN_1, ~0);
1286 wl_mmio(BLT_SIZE_X_Y, ((width << 16) | height));
1287 wl_mmio(BLT_SRC_X_Y, ((curx << 16) | cury));
1288 wl_mmio(BLT_DEST_X_Y, ((destx << 16) | desty));
1289 wl_mmio(BLT_SRC_DEST_STRIDE, (((stride << 16) | stride) /* & 0x0ff80ff8 */)); /* why is this needed now ? */
1290 wl_mmio(BLT_COMMAND_SET, blitcmd);
1291 }
1292
1293 /*
1294 * Rectangle Fill Solid
1295 */
1296
1297 static void virgefb_RectFill(u_short x, u_short y, u_short width, u_short height,
1298 u_short color, u_short stride, u_short depth)
1299 {
1300 unsigned int blitcmd = S3V_RECTFILL | S3V_DRAW |
1301 S3V_BLT_CLEAR | S3V_MONO_PAT | (1 << 26) | (1 << 25);
1302
1303 switch (depth) {
1304 #ifdef FBCON_HAS_CFB8
1305 case 8 :
1306 blitcmd |= S3V_DST_8BPP;
1307 break;
1308 #endif
1309 #ifdef FBCON_HAS_CFB16
1310 case 16 :
1311 blitcmd |= S3V_DST_16BPP;
1312 break;
1313 #endif
1314 #ifdef FBCON_HAS_CFB32
1315 case 32 :
1316 /* 32 bit uses 2 times 16 bit values, see fbcon_virge32_clear */
1317 blitcmd |= S3V_DST_16BPP;
1318 break;
1319 #endif
1320 }
1321
1322 wait_3d_fifo_slots(5); /* wait on fifo slots for 5 writes */
1323
1324 if (blit_maybe_busy)
1325 virgefb_wait_for_idle();
1326 blit_maybe_busy = 1;
1327
1328 wl_mmio(BLT_PATTERN_COLOR, (color & 0xff));
1329 wl_mmio(BLT_SIZE_X_Y, ((width << 16) | height));
1330 wl_mmio(BLT_DEST_X_Y, ((x << 16) | y));
1331 wl_mmio(BLT_SRC_DEST_STRIDE, (((stride << 16) | stride) /* & 0x0ff80ff8 */));
1332 wl_mmio(BLT_COMMAND_SET, blitcmd);
1333 }
1334
1335 /*
1336 * Move cursor to x, y
1337 */
1338
1339 #if 0
1340 static void virgefb_move_cursor(u_short x, u_short y)
1341 {
1342 DPRINTK("Yuck .... MoveCursor on a 3D\n");
1343 return 0;
1344 }
1345 #endif
1346
1347 /* -------------------- Interfaces to hardware functions -------------------- */
1348
1349 static struct fb_hwswitch virgefb_hw_switch = {
1350 .init = virge_init,
1351 .encode_fix = virgefb_encode_fix,
1352 .decode_var = virgefb_decode_var,
1353 .encode_var = virgefb_encode_var,
1354 .getcolreg = virgefb_getcolreg,
1355 .blank = virgefb_gfx_on_off
1356 };
1357
1358
1359 /* -------------------- Generic routines ------------------------------------ */
1360
1361
1362 /*
1363 * Fill the hardware's `par' structure.
1364 */
1365
1366 static void virgefb_get_par(struct virgefb_par *par)
1367 {
1368 DPRINTK("ENTER\n");
1369 if (current_par_valid) {
1370 *par = current_par;
1371 } else {
1372 fbhw->decode_var(&virgefb_default, par);
1373 }
1374 DPRINTK("EXIT\n");
1375 }
1376
1377
1378 static void virgefb_set_par(struct virgefb_par *par)
1379 {
1380 DPRINTK("ENTER\n");
1381 current_par = *par;
1382 current_par_valid = 1;
1383 DPRINTK("EXIT\n");
1384 }
1385
1386
1387 static void virgefb_set_video(struct fb_var_screeninfo *var)
1388 {
1389 /* Set clipping rectangle to current screen size */
1390
1391 unsigned int clip;
1392
1393 DPRINTK("ENTER\n");
1394 wait_3d_fifo_slots(4);
1395 clip = ((0 << 16) | (var->xres - 1));
1396 wl_mmio(BLT_CLIP_LEFT_RIGHT, clip);
1397 clip = ((0 << 16) | (var->yres - 1));
1398 wl_mmio(BLT_CLIP_TOP_BOTTOM, clip);
1399 wl_mmio(BLT_SRC_BASE, 0); /* seems we need to clear these two */
1400 wl_mmio(BLT_DEST_BASE, 0);
1401
1402 /* Load the video mode defined by the 'var' data */
1403
1404 virgefb_load_video_mode(var);
1405 DPRINTK("EXIT\n");
1406 }
1407
1408 /*
1409 Merge these two functions, Geert's suggestion.
1410 static int virgefb_set_var(struct fb_var_screeninfo *var, int con, struct fb_info *info);
1411 static int virgefb_do_fb_set_var(struct fb_var_screeninfo *var, int isactive);
1412 */
1413
1414 static int virgefb_do_fb_set_var(struct fb_var_screeninfo *var, int isactive)
1415 {
1416 int err, activate;
1417 struct virgefb_par par;
1418
1419 DPRINTK("ENTER\n");
1420 if ((err = fbhw->decode_var(var, &par))) {
1421 DPRINTK("EXIT\n");
1422 return (err);
1423 }
1424
1425 activate = var->activate;
1426 if ((var->activate & FB_ACTIVATE_MASK) == FB_ACTIVATE_NOW && isactive)
1427 virgefb_set_par(&par);
1428 fbhw->encode_var(var, &par);
1429 var->activate = activate;
1430 if ((var->activate & FB_ACTIVATE_MASK) == FB_ACTIVATE_NOW && isactive)
1431 virgefb_set_video(var);
1432 DPRINTK("EXIT\n");
1433 return 0;
1434 }
1435
1436
1437 /*
1438 * Get the Fixed Part of the Display
1439 */
1440
1441 static int virgefb_get_fix(struct fb_fix_screeninfo *fix, int con,
1442 struct fb_info *info)
1443 {
1444 struct virgefb_par par;
1445 int error = 0;
1446
1447 DPRINTK("ENTER\n");
1448 if (con == -1)
1449 virgefb_get_par(&par);
1450 else
1451 error = fbhw->decode_var(&fb_display[con].var, &par);
1452
1453 if (!error)
1454 error = fbhw->encode_fix(fix, &par);
1455 DPRINTK("EXIT\n");
1456 return(error);
1457 }
1458
1459
1460 /*
1461 * Get the User Defined Part of the Display
1462 */
1463
1464 static int virgefb_get_var(struct fb_var_screeninfo *var, int con,
1465 struct fb_info *info)
1466 {
1467 struct virgefb_par par;
1468 int error = 0;
1469
1470 DPRINTK("ENTER\n");
1471 if (con == -1) {
1472 virgefb_get_par(&par);
1473 error = fbhw->encode_var(var, &par);
1474 disp.var = *var; /* ++Andre: don't know if this is the right place */
1475 } else {
1476 *var = fb_display[con].var;
1477 }
1478 DPRINTK("EXIT\n");
1479 return(error);
1480 }
1481
1482 static void virgefb_set_disp(int con, struct fb_info *info)
1483 {
1484 struct fb_fix_screeninfo fix;
1485 struct display *display;
1486
1487 DPRINTK("ENTER\n");
1488 if (con >= 0)
1489 display = &fb_display[con];
1490 else
1491 display = &disp; /* used during initialization */
1492
1493 virgefb_get_fix(&fix, con, info);
1494 if (con == -1)
1495 con = 0;
1496 if(on_zorro2) {
1497 info->screen_base = (char*)v_ram;
1498 } else {
1499 switch (display->var.bits_per_pixel) {
1500 #ifdef FBCON_HAS_CFB8
1501 case 8:
1502 info->screen_base = (char*)(v_ram + CYBMEM_OFFSET_8);
1503 break;
1504 #endif
1505 #ifdef FBCON_HAS_CFB16
1506 case 16:
1507 info->screen_base = (char*)(v_ram + CYBMEM_OFFSET_16);
1508 break;
1509 #endif
1510 #ifdef FBCON_HAS_CFB32
1511 case 32:
1512 info->screen_base = (char*)(v_ram + CYBMEM_OFFSET_32);
1513 break;
1514 #endif
1515 }
1516 }
1517 display->visual = fix.visual;
1518 display->type = fix.type;
1519 display->type_aux = fix.type_aux;
1520 display->ypanstep = fix.ypanstep;
1521 display->ywrapstep = fix.ywrapstep;
1522 display->can_soft_blank = 1;
1523 display->inverse = virgefb_inverse;
1524 display->line_length = display->var.xres_virtual*
1525 display->var.bits_per_pixel/8;
1526
1527 switch (display->var.bits_per_pixel) {
1528 #ifdef FBCON_HAS_CFB8
1529 case 8:
1530 if (display->var.accel_flags & FB_ACCELF_TEXT) {
1531 display->dispsw = &fbcon_virge8;
1532 #warning FIXME: We should reinit the graphics engine here
1533 } else
1534 display->dispsw = &fbcon_cfb8;
1535 break;
1536 #endif
1537 #ifdef FBCON_HAS_CFB16
1538 case 16:
1539 if (display->var.accel_flags & FB_ACCELF_TEXT) {
1540 display->dispsw = &fbcon_virge16;
1541 } else
1542 display->dispsw = &fbcon_cfb16;
1543 display->dispsw_data = &fbcon_cmap.cfb16;
1544 break;
1545 #endif
1546 #ifdef FBCON_HAS_CFB32
1547 case 32:
1548 if (display->var.accel_flags & FB_ACCELF_TEXT) {
1549 display->dispsw = &fbcon_virge32;
1550 } else
1551 display->dispsw = &fbcon_cfb32;
1552 display->dispsw_data = &fbcon_cmap.cfb32;
1553 break;
1554 #endif
1555 default:
1556 display->dispsw = &fbcon_dummy;
1557 break;
1558 }
1559 DPRINTK("EXIT v_ram virt = 0x%8.8lx\n",(unsigned long)display->screen_base);
1560 }
1561
1562
1563 /*
1564 * Set the User Defined Part of the Display
1565 */
1566
1567 static int virgefb_set_var(struct fb_var_screeninfo *var, int con,
1568 struct fb_info *info)
1569 {
1570 int err, oldxres, oldyres, oldvxres, oldvyres, oldbpp, oldaccel;
1571
1572 DPRINTK("ENTER\n");
1573
1574 if ((err = virgefb_do_fb_set_var(var, con == info->currcon))) {
1575 DPRINTK("EXIT\n");
1576 return(err);
1577 }
1578 if ((var->activate & FB_ACTIVATE_MASK) == FB_ACTIVATE_NOW) {
1579 oldxres = fb_display[con].var.xres;
1580 oldyres = fb_display[con].var.yres;
1581 oldvxres = fb_display[con].var.xres_virtual;
1582 oldvyres = fb_display[con].var.yres_virtual;
1583 oldbpp = fb_display[con].var.bits_per_pixel;
1584 oldaccel = fb_display[con].var.accel_flags;
1585 fb_display[con].var = *var;
1586 if (oldxres != var->xres || oldyres != var->yres ||
1587 oldvxres != var->xres_virtual ||
1588 oldvyres != var->yres_virtual ||
1589 oldbpp != var->bits_per_pixel ||
1590 oldaccel != var->accel_flags) {
1591 virgefb_set_disp(con, info);
1592 if (fb_info.changevar)
1593 (*fb_info.changevar)(con);
1594 fb_alloc_cmap(&fb_display[con].cmap, 0, 0);
1595 do_install_cmap(con, info);
1596 }
1597 }
1598 var->activate = 0;
1599 DPRINTK("EXIT\n");
1600 return 0;
1601 }
1602
1603
1604 /*
1605 * Get the Colormap
1606 */
1607
1608 static int virgefb_get_cmap(struct fb_cmap *cmap, int kspc, int con,
1609 struct fb_info *info)
1610 {
1611 DPRINTK("ENTER\n");
1612 if (con == info->currcon) { /* current console? */
1613 DPRINTK("EXIT - console is current console, fb_get_cmap\n");
1614 return(fb_get_cmap(cmap, kspc, fbhw->getcolreg, info));
1615 } else if (fb_display[con].cmap.len) { /* non default colormap? */
1616 DPRINTK("Use console cmap\n");
1617 fb_copy_cmap(&fb_display[con].cmap, cmap, kspc ? 0 : 2);
1618 } else {
1619 DPRINTK("Use default cmap\n");
1620 fb_copy_cmap(fb_default_cmap(fb_display[con].var.bits_per_pixel==8 ? 256 : 16),
1621 cmap, kspc ? 0 : 2);
1622 }
1623 DPRINTK("EXIT\n");
1624 return 0;
1625 }
1626
1627 static struct fb_ops virgefb_ops = {
1628 .owner = THIS_MODULE,
1629 .fb_get_fix = virgefb_get_fix,
1630 .fb_get_var = virgefb_get_var,
1631 .fb_set_var = virgefb_set_var,
1632 .fb_get_cmap = virgefb_get_cmap,
1633 .fb_set_cmap = gen_set_cmap,
1634 .fb_setcolreg = virgefb_setcolreg,
1635 .fb_blank = virgefb_blank,
1636 };
1637
1638 int __init virgefb_setup(char *options)
1639 {
1640 char *this_opt;
1641 fb_info.fontname[0] = '\0';
1642
1643 DPRINTK("ENTER\n");
1644 if (!options || !*options) {
1645 DPRINTK("EXIT\n");
1646 return 0;
1647 }
1648
1649 while ((this_opt = strsep(&options, ",")) != NULL) {
1650 if (!*this_opt)
1651 continue;
1652 if (!strcmp(this_opt, "inverse")) {
1653 virgefb_inverse = 1;
1654 fb_invert_cmaps();
1655 } else if (!strncmp(this_opt, "font:", 5))
1656 strcpy(fb_info.fontname, this_opt+5);
1657 #ifdef FBCON_HAS_CFB8
1658 else if (!strcmp (this_opt, "virge8")){
1659 virgefb_default = virgefb_predefined[VIRGE8_DEFMODE].var;
1660 }
1661 #endif
1662 #ifdef FBCON_HAS_CFB16
1663 else if (!strcmp (this_opt, "virge16")){
1664 virgefb_default = virgefb_predefined[VIRGE16_DEFMODE].var;
1665 }
1666 #endif
1667 #ifdef FBCON_HAS_CFB32
1668 else if (!strcmp (this_opt, "virge32")){
1669 virgefb_default = virgefb_predefined[VIRGE32_DEFMODE].var;
1670 }
1671 #endif
1672 else
1673 virgefb_get_video_mode(this_opt);
1674 }
1675
1676 printk(KERN_INFO "mode : xres=%d, yres=%d, bpp=%d\n", virgefb_default.xres,
1677 virgefb_default.yres, virgefb_default.bits_per_pixel);
1678 DPRINTK("EXIT\n");
1679 return 0;
1680 }
1681
1682
1683 /*
1684 * Get a Video Mode
1685 */
1686
1687 static int __init virgefb_get_video_mode(const char *name)
1688 {
1689 int i;
1690
1691 DPRINTK("ENTER\n");
1692 for (i = 0; i < NUM_TOTAL_MODES; i++) {
1693 if (!strcmp(name, virgefb_predefined[i].name)) {
1694 virgefb_default = virgefb_predefined[i].var;
1695 DPRINTK("EXIT\n");
1696 return(i);
1697 }
1698 }
1699 /* ++Andre: set virgefb default mode */
1700
1701 /* prefer 16 bit depth, 8 if no 16, if no 8 or 16 use 32 */
1702
1703 #ifdef FBCON_HAS_CFB32
1704 virgefb_default = virgefb_predefined[VIRGE32_DEFMODE].var;
1705 #endif
1706 #ifdef FBCON_HAS_CFB8
1707 virgefb_default = virgefb_predefined[VIRGE8_DEFMODE].var;
1708 #endif
1709 #ifdef FBCON_HAS_CFB16
1710 virgefb_default = virgefb_predefined[VIRGE16_DEFMODE].var;
1711 #endif
1712 DPRINTK("EXIT\n");
1713 return 0;
1714 }
1715
1716 /*
1717 * Initialization
1718 */
1719
1720 int __init virgefb_init(void)
1721 {
1722 struct virgefb_par par;
1723 unsigned long board_addr, board_size;
1724 struct zorro_dev *z = NULL;
1725
1726 DPRINTK("ENTER\n");
1727
1728 z = zorro_find_device(ZORRO_PROD_PHASE5_CYBERVISION64_3D, NULL);
1729 if (!z)
1730 return -ENODEV;
1731
1732 board_addr = z->resource.start;
1733 if (board_addr < 0x01000000) {
1734
1735 /* board running in Z2 space. This includes the video memory
1736 as well as the S3 register set */
1737
1738 on_zorro2 = 1;
1739 board_size = 0x00400000;
1740
1741 if (!request_mem_region(board_addr, board_size, "S3 ViRGE"))
1742 return -ENOMEM;
1743
1744 v_ram_phys = board_addr;
1745 v_ram = ZTWO_VADDR(v_ram_phys);
1746 mmio_regs_phys = (unsigned long)(board_addr + 0x003c0000);
1747 vgaio_regs = (unsigned char *) ZTWO_VADDR(board_addr + 0x003c0000);
1748 mmio_regs = (unsigned char *)ZTWO_VADDR(mmio_regs_phys);
1749 vcode_switch_base = (unsigned long) ZTWO_VADDR(board_addr + 0x003a0000);
1750 printk(KERN_INFO "CV3D detected running in Z2 mode.\n");
1751
1752 } else {
1753
1754 /* board running in Z3 space. Separate video memory (3 apertures)
1755 and S3 register set */
1756
1757 on_zorro2 = 0;
1758 board_size = 0x01000000;
1759
1760 if (!request_mem_region(board_addr, board_size, "S3 ViRGE"))
1761 return -ENOMEM;
1762
1763 v_ram_phys = board_addr + 0x04000000;
1764 v_ram = (unsigned long)ioremap(v_ram_phys, 0x01000000);
1765 mmio_regs_phys = board_addr + 0x05000000;
1766 vgaio_regs = (unsigned char *)ioremap(board_addr +0x0c000000, 0x00100000); /* includes PCI regs */
1767 mmio_regs = ioremap(mmio_regs_phys, 0x00010000);
1768 vcode_switch_base = (unsigned long)ioremap(board_addr + 0x08000000, 0x1000);
1769 printk(KERN_INFO "CV3D detected running in Z3 mode\n");
1770 }
1771
1772 #if defined (VIRGEFBDEBUG)
1773 DPRINTK("board_addr : 0x%8.8lx\n",board_addr);
1774 DPRINTK("board_size : 0x%8.8lx\n",board_size);
1775 DPRINTK("mmio_regs_phy : 0x%8.8lx\n",mmio_regs_phys);
1776 DPRINTK("v_ram_phys : 0x%8.8lx\n",v_ram_phys);
1777 DPRINTK("vgaio_regs : 0x%8.8lx\n",(unsigned long)vgaio_regs);
1778 DPRINTK("mmio_regs : 0x%8.8lx\n",(unsigned long)mmio_regs);
1779 DPRINTK("v_ram : 0x%8.8lx\n",v_ram);
1780 DPRINTK("vcode sw base : 0x%8.8lx\n",vcode_switch_base);
1781 #endif
1782 fbhw = &virgefb_hw_switch;
1783 strcpy(fb_info.modename, virgefb_name);
1784 fb_info.changevar = NULL;
1785 fb_info.fbops = &virgefb_ops;
1786 fb_info.disp = &disp;
1787 fb_info.currcon = -1;
1788 fb_info.switch_con = &virgefb_switch;
1789 fb_info.updatevar = &virgefb_updatevar;
1790 fb_info.flags = FBINFO_FLAG_DEFAULT;
1791 fbhw->init();
1792 fbhw->decode_var(&virgefb_default, &par);
1793 fbhw->encode_var(&virgefb_default, &par);
1794 virgefb_do_fb_set_var(&virgefb_default, 1);
1795 virgefb_get_var(&fb_display[0].var, -1, &fb_info);
1796 virgefb_set_disp(-1, &fb_info);
1797 do_install_cmap(0, &fb_info);
1798
1799 if (register_framebuffer(&fb_info) < 0) {
1800 #warning release resources
1801 printk(KERN_ERR "virgefb.c: register_framebuffer failed\n");
1802 DPRINTK("EXIT\n");
1803 return -EINVAL;
1804 }
1805
1806 printk(KERN_INFO "fb%d: %s frame buffer device, using %ldK of video memory\n",
1807 fb_info.node, fb_info.modename, v_ram_size>>10);
1808
1809 /* TODO: This driver cannot be unloaded yet */
1810
1811 DPRINTK("EXIT\n");
1812 return 0;
1813 }
1814
1815
1816 static int virgefb_switch(int con, struct fb_info *info)
1817 {
1818 DPRINTK("ENTER\n");
1819 /* Do we have to save the colormap? */
1820 if (fb_display[info->currcon].cmap.len)
1821 fb_get_cmap(&fb_display[info->currcon].cmap, 1,
1822 fbhw->getcolreg, info);
1823 virgefb_do_fb_set_var(&fb_display[con].var, 1);
1824 info->currcon = con;
1825 /* Install new colormap */
1826 do_install_cmap(con, info);
1827 DPRINTK("EXIT\n");
1828 return 0;
1829 }
1830
1831
1832 /*
1833 * Update the `var' structure (called by fbcon.c)
1834 *
1835 * This call looks only at yoffset and the FB_VMODE_YWRAP flag in `var'.
1836 * Since it's called by a kernel driver, no range checking is done.
1837 */
1838
1839 static int virgefb_updatevar(int con, struct fb_info *info)
1840 {
1841 DPRINTK("ENTER\n");
1842 return 0;
1843 DPRINTK("EXIT\n");
1844 }
1845
1846 /*
1847 * Blank the display.
1848 */
1849
1850 static int virgefb_blank(int blank, struct fb_info *info)
1851 {
1852 DPRINTK("ENTER\n");
1853 fbhw->blank(blank);
1854 DPRINTK("EXIT\n");
1855 return 0;
1856 }
1857
1858
1859 /*
1860 * Text console acceleration
1861 */
1862
1863 #ifdef FBCON_HAS_CFB8
1864 static void fbcon_virge8_bmove(struct display *p, int sy, int sx, int dy,
1865 int dx, int height, int width)
1866 {
1867 sx *= 8; dx *= 8; width *= 8;
1868 virgefb_BitBLT((u_short)sx, (u_short)(sy*fontheight(p)), (u_short)dx,
1869 (u_short)(dy*fontheight(p)), (u_short)width,
1870 (u_short)(height*fontheight(p)), (u_short)p->next_line, 8);
1871 }
1872
1873 static void fbcon_virge8_clear(struct vc_data *conp, struct display *p, int sy,
1874 int sx, int height, int width)
1875 {
1876 unsigned char bg;
1877
1878 sx *= 8; width *= 8;
1879 bg = attr_bgcol_ec(p,conp);
1880 virgefb_RectFill((u_short)sx, (u_short)(sy*fontheight(p)),
1881 (u_short)width, (u_short)(height*fontheight(p)),
1882 (u_short)bg, (u_short)p->next_line, 8);
1883 }
1884
1885 static void fbcon_virge8_putc(struct vc_data *conp, struct display *p, int c, int yy,
1886 int xx)
1887 {
1888 if (blit_maybe_busy)
1889 virgefb_wait_for_idle();
1890 fbcon_cfb8_putc(conp, p, c, yy, xx);
1891 }
1892
1893 static void fbcon_virge8_putcs(struct vc_data *conp, struct display *p,
1894 const unsigned short *s, int count, int yy, int xx)
1895 {
1896 if (blit_maybe_busy)
1897 virgefb_wait_for_idle();
1898 fbcon_cfb8_putcs(conp, p, s, count, yy, xx);
1899 }
1900
1901 static void fbcon_virge8_revc(struct display *p, int xx, int yy)
1902 {
1903 if (blit_maybe_busy)
1904 virgefb_wait_for_idle();
1905 fbcon_cfb8_revc(p, xx, yy);
1906 }
1907
1908 static void fbcon_virge8_clear_margins(struct vc_data *conp, struct display *p,
1909 int bottom_only)
1910 {
1911 if (blit_maybe_busy)
1912 virgefb_wait_for_idle();
1913 fbcon_cfb8_clear_margins(conp, p, bottom_only);
1914 }
1915
1916 static struct display_switch fbcon_virge8 = {
1917 .setup = fbcon_cfb8_setup,
1918 .bmove = fbcon_virge8_bmove,
1919 .clear = fbcon_virge8_clear,
1920 .putc = fbcon_virge8_putc,
1921 .putcs = fbcon_virge8_putcs,
1922 .revc = fbcon_virge8_revc,
1923 .clear_margins = fbcon_virge8_clear_margins,
1924 .fontwidthmask = FONTWIDTH(4)|FONTWIDTH(8)|FONTWIDTH(12)|FONTWIDTH(16)
1925 };
1926 #endif
1927
1928 #ifdef FBCON_HAS_CFB16
1929 static void fbcon_virge16_bmove(struct display *p, int sy, int sx, int dy,
1930 int dx, int height, int width)
1931 {
1932 sx *= 8; dx *= 8; width *= 8;
1933 virgefb_BitBLT((u_short)sx, (u_short)(sy*fontheight(p)), (u_short)dx,
1934 (u_short)(dy*fontheight(p)), (u_short)width,
1935 (u_short)(height*fontheight(p)), (u_short)p->next_line, 16);
1936 }
1937
1938 static void fbcon_virge16_clear(struct vc_data *conp, struct display *p, int sy,
1939 int sx, int height, int width)
1940 {
1941 unsigned char bg;
1942
1943 sx *= 8; width *= 8;
1944 bg = attr_bgcol_ec(p,conp);
1945 virgefb_RectFill((u_short)sx, (u_short)(sy*fontheight(p)),
1946 (u_short)width, (u_short)(height*fontheight(p)),
1947 (u_short)bg, (u_short)p->next_line, 16);
1948 }
1949
1950 static void fbcon_virge16_putc(struct vc_data *conp, struct display *p, int c, int yy,
1951 int xx)
1952 {
1953 if (blit_maybe_busy)
1954 virgefb_wait_for_idle();
1955 fbcon_cfb16_putc(conp, p, c, yy, xx);
1956 }
1957
1958 static void fbcon_virge16_putcs(struct vc_data *conp, struct display *p,
1959 const unsigned short *s, int count, int yy, int xx)
1960 {
1961 if (blit_maybe_busy)
1962 virgefb_wait_for_idle();
1963 fbcon_cfb16_putcs(conp, p, s, count, yy, xx);
1964 }
1965
1966 static void fbcon_virge16_revc(struct display *p, int xx, int yy)
1967 {
1968 if (blit_maybe_busy)
1969 virgefb_wait_for_idle();
1970 fbcon_cfb16_revc(p, xx, yy);
1971 }
1972
1973 static void fbcon_virge16_clear_margins(struct vc_data *conp, struct display *p,
1974 int bottom_only)
1975 {
1976 if (blit_maybe_busy)
1977 virgefb_wait_for_idle();
1978 fbcon_cfb16_clear_margins(conp, p, bottom_only);
1979 }
1980
1981 static struct display_switch fbcon_virge16 = {
1982 .setup = fbcon_cfb16_setup,
1983 .bmove = fbcon_virge16_bmove,
1984 .clear = fbcon_virge16_clear,
1985 .putc = fbcon_virge16_putc,
1986 .putcs = fbcon_virge16_putcs,
1987 .revc = fbcon_virge16_revc,
1988 .clear_margins = fbcon_virge16_clear_margins,
1989 .fontwidthmask = FONTWIDTH(4)|FONTWIDTH(8)|FONTWIDTH(12)|FONTWIDTH(16)
1990 };
1991 #endif
1992
1993 #ifdef FBCON_HAS_CFB32
1994 static void fbcon_virge32_bmove(struct display *p, int sy, int sx, int dy,
1995 int dx, int height, int width)
1996 {
1997 sx *= 16; dx *= 16; width *= 16; /* doubled these values to do 32 bit blit */
1998 virgefb_BitBLT((u_short)sx, (u_short)(sy*fontheight(p)), (u_short)dx,
1999 (u_short)(dy*fontheight(p)), (u_short)width,
2000 (u_short)(height*fontheight(p)), (u_short)p->next_line, 16);
2001 }
2002
2003 static void fbcon_virge32_clear(struct vc_data *conp, struct display *p, int sy,
2004 int sx, int height, int width)
2005 {
2006 unsigned char bg;
2007
2008 sx *= 16; width *= 16; /* doubled these values to do 32 bit blit */
2009 bg = attr_bgcol_ec(p,conp);
2010 virgefb_RectFill((u_short)sx, (u_short)(sy*fontheight(p)),
2011 (u_short)width, (u_short)(height*fontheight(p)),
2012 (u_short)bg, (u_short)p->next_line, 16);
2013 }
2014
2015 static void fbcon_virge32_putc(struct vc_data *conp, struct display *p, int c, int yy,
2016 int xx)
2017 {
2018 if (blit_maybe_busy)
2019 virgefb_wait_for_idle();
2020 fbcon_cfb32_putc(conp, p, c, yy, xx);
2021 }
2022
2023 static void fbcon_virge32_putcs(struct vc_data *conp, struct display *p,
2024 const unsigned short *s, int count, int yy, int xx)
2025 {
2026 if (blit_maybe_busy)
2027 virgefb_wait_for_idle();
2028 fbcon_cfb32_putcs(conp, p, s, count, yy, xx);
2029 }
2030
2031 static void fbcon_virge32_revc(struct display *p, int xx, int yy)
2032 {
2033 if (blit_maybe_busy)
2034 virgefb_wait_for_idle();
2035 fbcon_cfb32_revc(p, xx, yy);
2036 }
2037
2038 static void fbcon_virge32_clear_margins(struct vc_data *conp, struct display *p,
2039 int bottom_only)
2040 {
2041 if (blit_maybe_busy)
2042 virgefb_wait_for_idle();
2043 fbcon_cfb32_clear_margins(conp, p, bottom_only);
2044 }
2045
2046 static struct display_switch fbcon_virge32 = {
2047 .setup = fbcon_cfb32_setup,
2048 .bmove = fbcon_virge32_bmove,
2049 .clear = fbcon_virge32_clear,
2050 .putc = fbcon_virge32_putc,
2051 .putcs = fbcon_virge32_putcs,
2052 .revc = fbcon_virge32_revc,
2053 .clear_margins = fbcon_virge32_clear_margins,
2054 .fontwidthmask = FONTWIDTH(4)|FONTWIDTH(8)|FONTWIDTH(12)|FONTWIDTH(16)
2055 };
2056 #endif
2057
2058 #ifdef MODULE
2059 MODULE_LICENSE("GPL");
2060
2061 int init_module(void)
2062 {
2063 return virgefb_init();
2064 }
2065 #endif /* MODULE */
2066
2067 static int cv3d_has_4mb(void)
2068 {
2069 /* cyberfb version didn't work, neither does this (not reliably)
2070 forced to return 4MB */
2071 #if 0
2072 volatile unsigned long *t0, *t2;
2073 #endif
2074 DPRINTK("ENTER\n");
2075 #if 0
2076 /* write patterns in memory and test if they can be read */
2077 t0 = (volatile unsigned long *)v_ram;
2078 t2 = (volatile unsigned long *)(v_ram + 0x00200000);
2079 *t0 = 0x87654321;
2080 *t2 = 0x12345678;
2081
2082 if (*t0 != 0x87654321) {
2083 /* read of first location failed */
2084 DPRINTK("EXIT - 0MB !\n");
2085 return 0;
2086 }
2087
2088 if (*t2 == 0x87654321) {
2089 /* should read 0x12345678 if 4MB */
2090 DPRINTK("EXIT - 2MB(a) \n");
2091 return 0;
2092 }
2093
2094 if (*t2 != 0x12345678) {
2095 /* upper 2MB read back match failed */
2096 DPRINTK("EXIT - 2MB(b)\n");
2097 return 0;
2098 }
2099
2100 /* may have 4MB */
2101
2102 *t2 = 0xAAAAAAAA;
2103
2104 if(*t2 != 0xAAAAAAAA) {
2105 /* upper 2MB read back match failed */
2106 DPRINTK("EXIT - 2MB(c)\n");
2107 return 0;
2108 }
2109
2110 *t2 = 0x55555555;
2111
2112 if(*t2 != 0x55555555) {
2113 /* upper 2MB read back match failed */
2114 DPRINTK("EXIT - 2MB(d)\n");
2115 return 0;
2116 }
2117
2118 #endif
2119 DPRINTK("EXIT - 4MB\n");
2120 return 1;
2121 }
2122
2123
2124 /*
2125 * Computes M, N, and R pll params for freq arg.
2126 * Returns 16 bits - hi 0MMMMMM lo 0RRNNNNN
2127 */
2128
2129 #define REFCLOCK 14318000
2130
2131 static unsigned short virgefb_compute_clock(unsigned long freq)
2132 {
2133
2134 unsigned char m, n, r, rpwr;
2135 unsigned long diff, ftry, save = ~0UL;
2136 unsigned short mnr;
2137
2138 DPRINTK("ENTER\n");
2139
2140 for (r = 0, rpwr = 1 ; r < 4 ; r++, rpwr *= 2) {
2141 if ((135000000 <= (rpwr * freq)) && ((rpwr * freq) <= 270000000)) {
2142 for (n = 1 ; n < 32 ; n++) {
2143 m = ((freq * (n + 2) * rpwr)/REFCLOCK) - 2;
2144 if (m == 0 || m >127)
2145 break;
2146 ftry = ((REFCLOCK / (n + 2)) * (m + 2)) / rpwr;
2147 if (ftry > freq)
2148 diff = ftry - freq;
2149 else
2150 diff = freq - ftry;
2151 if (diff < save) {
2152 save = diff;
2153 mnr = (m << 8) | (r<<5) | (n & 0x7f);
2154 }
2155 }
2156 }
2157 }
2158 if (save == ~0UL)
2159 printk("Can't compute clock PLL values for %ld Hz clock\n", freq);
2160 DPRINTK("EXIT\n");
2161 return(mnr);
2162 }
2163
2164 static void virgefb_load_video_mode(struct fb_var_screeninfo *video_mode)
2165 {
2166 unsigned char lace, dblscan, tmp;
2167 unsigned short mnr;
2168 unsigned short HT, HDE, HBS, HBW, HSS, HSW;
2169 unsigned short VT, VDE, VBS, VBW, VSS, VSW;
2170 unsigned short SCO;
2171 int cr11;
2172 int cr67;
2173 int hmul;
2174 int xres, xres_virtual, hfront, hsync, hback;
2175 int yres, vfront, vsync, vback;
2176 int bpp;
2177 int i;
2178 long freq;
2179
2180 DPRINTK("ENTER : %dx%d-%d\n",video_mode->xres, video_mode->yres,
2181 video_mode->bits_per_pixel);
2182
2183 bpp = video_mode->bits_per_pixel;
2184 xres = video_mode->xres;
2185 xres_virtual = video_mode->xres_virtual;
2186 hfront = video_mode->right_margin;
2187 hsync = video_mode->hsync_len;
2188 hback = video_mode->left_margin;
2189
2190 lace = 0;
2191 dblscan = 0;
2192
2193 if (video_mode->vmode & FB_VMODE_DOUBLE) {
2194 yres = video_mode->yres * 2;
2195 vfront = video_mode->lower_margin * 2;
2196 vsync = video_mode->vsync_len * 2;
2197 vback = video_mode->upper_margin * 2;
2198 dblscan = 1;
2199 } else if (video_mode->vmode & FB_VMODE_INTERLACED) {
2200 yres = (video_mode->yres + 1) / 2;
2201 vfront = (video_mode->lower_margin + 1) / 2;
2202 vsync = (video_mode->vsync_len + 1) / 2;
2203 vback = (video_mode->upper_margin + 1) / 2;
2204 lace = 1;
2205 } else {
2206 yres = video_mode->yres;
2207 vfront = video_mode->lower_margin;
2208 vsync = video_mode->vsync_len;
2209 vback = video_mode->upper_margin;
2210 }
2211
2212 switch (bpp) {
2213 case 8:
2214 video_mode->red.offset = 0;
2215 video_mode->green.offset = 0;
2216 video_mode->blue.offset = 0;
2217 video_mode->transp.offset = 0;
2218 video_mode->red.length = 8;
2219 video_mode->green.length = 8;
2220 video_mode->blue.length = 8;
2221 video_mode->transp.length = 0;
2222 hmul = 1;
2223 cr67 = 0x00;
2224 SCO = xres_virtual / 8;
2225 break;
2226 case 16:
2227 video_mode->red.offset = 11;
2228 video_mode->green.offset = 5;
2229 video_mode->blue.offset = 0;
2230 video_mode->transp.offset = 0;
2231 video_mode->red.length = 5;
2232 video_mode->green.length = 6;
2233 video_mode->blue.length = 5;
2234 video_mode->transp.length = 0;
2235 hmul = 2;
2236 cr67 = 0x50;
2237 SCO = xres_virtual / 4;
2238 break;
2239 case 32:
2240 video_mode->red.offset = 16;
2241 video_mode->green.offset = 8;
2242 video_mode->blue.offset = 0;
2243 video_mode->transp.offset = 24;
2244 video_mode->red.length = 8;
2245 video_mode->green.length = 8;
2246 video_mode->blue.length = 8;
2247 video_mode->transp.length = 8;
2248 hmul = 1;
2249 cr67 = 0xd0;
2250 SCO = xres_virtual / 2;
2251 break;
2252 }
2253
2254 HT = (((xres + hfront + hsync + hback) / 8) * hmul) - 5;
2255 HDE = ((xres / 8) * hmul) - 1;
2256 HBS = (xres / 8) * hmul;
2257 HSS = ((xres + hfront) / 8) * hmul;
2258 HSW = (hsync / 8) * hmul;
2259 HBW = (((hfront + hsync + hback) / 8) * hmul) - 2;
2260
2261 VT = yres + vfront + vsync + vback - 2;
2262 VDE = yres - 1;
2263 VBS = yres - 1;
2264 VSS = yres + vfront;
2265 VSW = vsync;
2266 VBW = vfront + vsync + vback - 2;
2267
2268 #ifdef VIRGEFBDEBUG
2269 DPRINTK("HDE : 0x%4.4x, %4.4d\n", HDE, HDE);
2270 DPRINTK("HBS : 0x%4.4x, %4.4d\n", HBS, HBS);
2271 DPRINTK("HSS : 0x%4.4x, %4.4d\n", HSS, HSS);
2272 DPRINTK("HSW : 0x%4.4x, %4.4d\n", HSW, HSW);
2273 DPRINTK("HBW : 0x%4.4x, %4.4d\n", HBW, HBW);
2274 DPRINTK("HSS + HSW : 0x%4.4x, %4.4d\n", HSS+HSW, HSS+HSW);
2275 DPRINTK("HBS + HBW : 0x%4.4x, %4.4d\n", HBS+HBW, HBS+HBW);
2276 DPRINTK("HT : 0x%4.4x, %4.4d\n", HT, HT);
2277 DPRINTK("VDE : 0x%4.4x, %4.4d\n", VDE, VDE);
2278 DPRINTK("VBS : 0x%4.4x, %4.4d\n", VBS, VBS);
2279 DPRINTK("VSS : 0x%4.4x, %4.4d\n", VSS, VSS);
2280 DPRINTK("VSW : 0x%4.4x, %4.4d\n", VSW, VSW);
2281 DPRINTK("VBW : 0x%4.4x, %4.4d\n", VBW, VBW);
2282 DPRINTK("VT : 0x%4.4x, %4.4d\n", VT, VT);
2283 #endif
2284
2285 /* turn gfx off, don't mess up the display */
2286
2287 gfx_on_off(1);
2288
2289 /* H and V sync polarity */
2290
2291 tmp = rb_mmio(GREG_MISC_OUTPUT_R) & 0x2f; /* colour, ram enable, clk sr12/s13 sel */
2292 if (!(video_mode->sync & FB_SYNC_HOR_HIGH_ACT))
2293 tmp |= 0x40; /* neg H sync polarity */
2294 if (!(video_mode->sync & FB_SYNC_VERT_HIGH_ACT))
2295 tmp |= 0x80; /* neg V sync polarity */
2296 tmp |= 0x0c; /* clk from sr12/sr13 */
2297 wb_mmio(GREG_MISC_OUTPUT_W, tmp);
2298
2299 /* clocks */
2300
2301 wseq(SEQ_ID_BUS_REQ_CNTL, 0xc0); /* 2 clk mem wr and /RAS1 */
2302 wseq(SEQ_ID_CLKSYN_CNTL_2, 0x80); /* b7 is 2 mem clk wr */
2303 mnr = virgefb_compute_clock(MEMCLOCK);
2304 DPRINTK("mem clock %d, m %d, n %d, r %d.\n", MEMCLOCK, ((mnr>>8)&0x7f), (mnr&0x1f), ((mnr >> 5)&0x03));
2305 wseq(SEQ_ID_MCLK_LO, (mnr & 0x7f));
2306 wseq(SEQ_ID_MCLK_HI, ((mnr & 0x7f00) >> 8));
2307 freq = (1000000000 / video_mode->pixclock) * 1000; /* pixclock is in ps ... convert to Hz */
2308 mnr = virgefb_compute_clock(freq);
2309 DPRINTK("dot clock %ld, m %d, n %d, r %d.\n", freq, ((mnr>>8)&0x7f), (mnr&0x1f), ((mnr>>5)&0x03));
2310 wseq(SEQ_ID_DCLK_LO, (mnr & 0x7f));
2311 wseq(SEQ_ID_DCLK_HI, ((mnr & 0x7f00) >> 8));
2312 wseq(SEQ_ID_CLKSYN_CNTL_2, 0xa0);
2313 wseq(SEQ_ID_CLKSYN_CNTL_2, 0x80);
2314 udelay(100);
2315
2316 /* load display parameters into board */
2317
2318 /* not sure about sync and blanking extensions bits in cr5d and cr5 */
2319
2320 wcrt(CRT_ID_EXT_HOR_OVF, /* 0x5d */
2321 ((HT & 0x100) ? 0x01 : 0x00) |
2322 ((HDE & 0x100) ? 0x02 : 0x00) |
2323 ((HBS & 0x100) ? 0x04 : 0x00) |
2324 /* (((HBS + HBW) & 0x40) ? 0x08 : 0x00) | */
2325 ((HSS & 0x100) ? 0x10 : 0x00) |
2326 /* (((HSS + HSW) & 0x20) ? 0x20 : 0x00) | */
2327 ((HSW >= 0x20) ? 0x20 : 0x00) |
2328 (((HT-5) & 0x100) ? 0x40 : 0x00));
2329
2330 wcrt(CRT_ID_EXT_VER_OVF, /* 0x5e */
2331 ((VT & 0x400) ? 0x01 : 0x00) |
2332 ((VDE & 0x400) ? 0x02 : 0x00) |
2333 ((VBS & 0x400) ? 0x04 : 0x00) |
2334 ((VSS & 0x400) ? 0x10 : 0x00) |
2335 0x40); /* line compare */
2336
2337 wcrt(CRT_ID_START_VER_RETR, VSS);
2338 cr11 = rcrt(CRT_ID_END_VER_RETR) | 0x20; /* vert interrupt flag */
2339 wcrt(CRT_ID_END_VER_RETR, ((cr11 & 0x20) | ((VSS + VSW) & 0x0f))); /* keeps vert irq enable state, also has unlock bit cr0 to 7 */
2340 wcrt(CRT_ID_VER_DISP_ENA_END, VDE);
2341 wcrt(CRT_ID_START_VER_BLANK, VBS);
2342 wcrt(CRT_ID_END_VER_BLANK, VBS + VBW); /* might be +/- 1 out */
2343 wcrt(CRT_ID_HOR_TOTAL, HT);
2344 wcrt(CRT_ID_DISPLAY_FIFO, HT - 5);
2345 wcrt(CRT_ID_BACKWAD_COMP_3, 0x10); /* enable display fifo */
2346 wcrt(CRT_ID_HOR_DISP_ENA_END, HDE);
2347 wcrt(CRT_ID_START_HOR_BLANK , HBS);
2348 wcrt(CRT_ID_END_HOR_BLANK, (HBS + HBW) & 0x1f);
2349 wcrt(CRT_ID_START_HOR_RETR, HSS);
2350 wcrt(CRT_ID_END_HOR_RETR, /* cr5 */
2351 ((HSS + HSW) & 0x1f) |
2352 (((HBS + HBW) & 0x20) ? 0x80 : 0x00));
2353 wcrt(CRT_ID_VER_TOTAL, VT);
2354 wcrt(CRT_ID_OVERFLOW,
2355 ((VT & 0x100) ? 0x01 : 0x00) |
2356 ((VDE & 0x100) ? 0x02 : 0x00) |
2357 ((VSS & 0x100) ? 0x04 : 0x00) |
2358 ((VBS & 0x100) ? 0x08 : 0x00) |
2359 0x10 |
2360 ((VT & 0x200) ? 0x20 : 0x00) |
2361 ((VDE & 0x200) ? 0x40 : 0x00) |
2362 ((VSS & 0x200) ? 0x80 : 0x00));
2363 wcrt(CRT_ID_MAX_SCAN_LINE,
2364 (dblscan ? 0x80 : 0x00) |
2365 0x40 |
2366 ((VBS & 0x200) ? 0x20 : 0x00));
2367 wcrt(CRT_ID_LINE_COMPARE, 0xff);
2368 wcrt(CRT_ID_LACE_RETR_START, HT / 2); /* (HT-5)/2 ? */
2369 wcrt(CRT_ID_LACE_CONTROL, (lace ? 0x20 : 0x00));
2370
2371 wcrt(CRT_ID_SCREEN_OFFSET, SCO);
2372 wcrt(CRT_ID_EXT_SYS_CNTL_2, (SCO >> 4) & 0x30 );
2373
2374 /* wait for vert sync before cr67 update */
2375
2376 for (i=0; i < 10000; i++) {
2377 udelay(10);
2378 mb();
2379 if (rb_mmio(GREG_INPUT_STATUS1_R) & 0x08)
2380 break;
2381 }
2382
2383 wl_mmio(0x8200, 0x0000c000); /* fifo control (0x00110400 ?) */
2384 wcrt(CRT_ID_EXT_MISC_CNTL_2, cr67);
2385
2386 /* enable video */
2387
2388 tmp = rb_mmio(ACT_ADDRESS_RESET);
2389 wb_mmio(ACT_ADDRESS_W, ((bpp == 8) ? 0x20 : 0x00)); /* set b5, ENB PLT in attr idx reg) */
2390 tmp = rb_mmio(ACT_ADDRESS_RESET);
2391
2392 /* turn gfx on again */
2393
2394 gfx_on_off(0);
2395
2396 /* pass-through */
2397
2398 SetVSwitch(1); /* cv3d */
2399
2400 DUMP;
2401 DPRINTK("EXIT\n");
2402 }
2403
2404 static inline void gfx_on_off(int toggle)
2405 {
2406 unsigned char tmp;
2407
2408 DPRINTK("ENTER gfx %s\n", (toggle ? "off" : "on"));
2409
2410 toggle = (toggle & 0x01) << 5;
2411 tmp = rseq(SEQ_ID_CLOCKING_MODE) & (~(0x01 << 5));
2412 wseq(SEQ_ID_CLOCKING_MODE, tmp | toggle);
2413
2414 DPRINTK("EXIT\n");
2415 }
2416
2417 #if defined (VIRGEFBDUMP)
2418
2419 /*
2420 * Dump board registers
2421 */
2422
2423 static void cv64_dump(void)
2424 {
2425 int i;
2426 u8 c, b;
2427 u16 w;
2428 u32 l;
2429
2430 /* crt, seq, gfx and atr regs */
2431
2432 SelectMMIO;
2433
2434 printk("\n");
2435 for (i = 0; i <= 0x6f; i++) {
2436 wb_mmio(CRT_ADDRESS, i);
2437 printk("crt idx : 0x%2.2x : 0x%2.2x\n", i, rb_mmio(CRT_ADDRESS_R));
2438 }
2439 for (i = 0; i <= 0x1c; i++) {
2440 wb_mmio(SEQ_ADDRESS, i);
2441 printk("seq idx : 0x%2.2x : 0x%2.2x\n", i, rb_mmio(SEQ_ADDRESS_R));
2442 }
2443 for (i = 0; i <= 8; i++) {
2444 wb_mmio(GCT_ADDRESS, i);
2445 printk("gfx idx : 0x%2.2x : 0x%2.2x\n", i, rb_mmio(GCT_ADDRESS_R));
2446 }
2447 for (i = 0; i <= 0x14; i++) {
2448 c = rb_mmio(ACT_ADDRESS_RESET);
2449 wb_mmio(ACT_ADDRESS_W, i);
2450 printk("atr idx : 0x%2.2x : 0x%2.2x\n", i, rb_mmio(ACT_ADDRESS_R));
2451 }
2452
2453 /* re-enable video access to palette */
2454
2455 c = rb_mmio(ACT_ADDRESS_RESET);
2456 udelay(10);
2457 wb_mmio(ACT_ADDRESS_W, 0x20);
2458 c = rb_mmio(ACT_ADDRESS_RESET);
2459 udelay(10);
2460
2461 /* general regs */
2462
2463 printk("0x3cc(w 0x3c2) : 0x%2.2x\n", rb_mmio(0x3cc)); /* GREG_MISC_OUTPUT READ */
2464 printk("0x3c2(-------) : 0x%2.2x\n", rb_mmio(0x3c2)); /* GREG_INPUT_STATUS 0 READ */
2465 printk("0x3c3(w 0x3c3) : 0x%2.2x\n", rb_vgaio(0x3c3)); /* GREG_VIDEO_SUBS_ENABLE */
2466 printk("0x3ca(w 0x3da) : 0x%2.2x\n", rb_vgaio(0x3ca)); /* GREG_FEATURE_CONTROL read */
2467 printk("0x3da(-------) : 0x%2.2x\n", rb_mmio(0x3da)); /* GREG_INPUT_STATUS 1 READ */
2468
2469 /* engine regs */
2470
2471 for (i = 0x8180; i <= 0x8200; i = i + 4)
2472 printk("0x%8.8x : 0x%8.8x\n", i, rl_mmio(i));
2473
2474 i = 0x8504;
2475 printk("0x%8.8x : 0x%8.8x\n", i, rl_mmio(i));
2476 i = 0x850c;
2477 printk("0x%8.8x : 0x%8.8x\n", i, rl_mmio(i));
2478 for (i = 0xa4d4; i <= 0xa50c; i = i + 4)
2479 printk("0x%8.8x : 0x%8.8x\n", i, rl_mmio(i));
2480
2481 /* PCI regs */
2482
2483 SelectCFG;
2484
2485 for (c = 0; c < 0x08; c = c + 2) {
2486 w = (*((u16 *)((u32)(vgaio_regs + c + (on_zorro2 ? 0 : 0x000e0000)) ^ 2)));
2487 printk("pci 0x%2.2x : 0x%4.4x\n", c, w);
2488 }
2489 c = 8;
2490 l = (*((u32 *)((u32)(vgaio_regs + c + (on_zorro2 ? 0 : 0x000e0000)))));
2491 printk("pci 0x%2.2x : 0x%8.8x\n", c, l);
2492 c = 0x0d;
2493 b = (*((u8 *)((u32)(vgaio_regs + c + (on_zorro2 ? 0 : 0x000e0000)) ^ 3)));
2494 printk("pci 0x%2.2x : 0x%2.2x\n", c, b);
2495 c = 0x10;
2496 l = (*((u32 *)((u32)(vgaio_regs + c + (on_zorro2 ? 0 : 0x000e0000)))));
2497 printk("pci 0x%2.2x : 0x%8.8x\n", c, l);
2498 c = 0x30;
2499 l = (*((u32 *)((u32)(vgaio_regs + c + (on_zorro2 ? 0 : 0x000e0000)))));
2500 printk("pci 0x%2.2x : 0x%8.8x\n", c, l);
2501 c = 0x3c;
2502 b = (*((u8 *)((u32)(vgaio_regs + c + (on_zorro2 ? 0 : 0x000e0000)) ^ 3)));
2503 printk("pci 0x%2.2x : 0x%2.2x\n", c, b);
2504 c = 0x3d;
2505 b = (*((u8 *)((u32)(vgaio_regs + c + (on_zorro2 ? 0 : 0x000e0000)) ^ 3)));
2506 printk("pci 0x%2.2x : 0x%2.2x\n", c, b);
2507 c = 0x3e;
2508 w = (*((u16 *)((u32)(vgaio_regs + c + (on_zorro2 ? 0 : 0x000e0000)) ^ 2)));
2509 printk("pci 0x%2.2x : 0x%4.4x\n", c, w);
2510 SelectMMIO;
2511 }
2512 #endif
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree