1 /* smp.c: Sparc64 SMP support.
3 * Copyright (C) 1997, 2007, 2008 David S. Miller (davem@davemloft.net)
6 #include <linux/module.h>
7 #include <linux/kernel.h>
8 #include <linux/sched.h>
10 #include <linux/pagemap.h>
11 #include <linux/threads.h>
12 #include <linux/smp.h>
13 #include <linux/interrupt.h>
14 #include <linux/kernel_stat.h>
15 #include <linux/delay.h>
16 #include <linux/init.h>
17 #include <linux/spinlock.h>
19 #include <linux/seq_file.h>
20 #include <linux/cache.h>
21 #include <linux/jiffies.h>
22 #include <linux/profile.h>
23 #include <linux/lmb.h>
26 #include <asm/ptrace.h>
27 #include <asm/atomic.h>
28 #include <asm/tlbflush.h>
29 #include <asm/mmu_context.h>
30 #include <asm/cpudata.h>
31 #include <asm/hvtramp.h>
33 #include <asm/timer.h>
36 #include <asm/irq_regs.h>
38 #include <asm/pgtable.h>
39 #include <asm/oplib.h>
40 #include <asm/uaccess.h>
41 #include <asm/starfire.h>
43 #include <asm/sections.h>
45 #include <asm/mdesc.h>
47 #include <asm/hypervisor.h>
49 int sparc64_multi_core __read_mostly
;
51 cpumask_t cpu_possible_map __read_mostly
= CPU_MASK_NONE
;
52 cpumask_t cpu_online_map __read_mostly
= CPU_MASK_NONE
;
53 DEFINE_PER_CPU(cpumask_t
, cpu_sibling_map
) = CPU_MASK_NONE
;
54 cpumask_t cpu_core_map
[NR_CPUS
] __read_mostly
=
55 { [0 ... NR_CPUS
-1] = CPU_MASK_NONE
};
57 EXPORT_SYMBOL(cpu_possible_map
);
58 EXPORT_SYMBOL(cpu_online_map
);
59 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map
);
60 EXPORT_SYMBOL(cpu_core_map
);
62 static cpumask_t smp_commenced_mask
;
64 void smp_info(struct seq_file
*m
)
68 seq_printf(m
, "State:\n");
69 for_each_online_cpu(i
)
70 seq_printf(m
, "CPU%d:\t\tonline\n", i
);
73 void smp_bogo(struct seq_file
*m
)
77 for_each_online_cpu(i
)
79 "Cpu%dClkTck\t: %016lx\n",
80 i
, cpu_data(i
).clock_tick
);
83 extern void setup_sparc64_timer(void);
85 static volatile unsigned long callin_flag
= 0;
87 void __cpuinit
smp_callin(void)
89 int cpuid
= hard_smp_processor_id();
91 __local_per_cpu_offset
= __per_cpu_offset(cpuid
);
93 if (tlb_type
== hypervisor
)
94 sun4v_ktsb_register();
98 setup_sparc64_timer();
100 if (cheetah_pcache_forced_on
)
101 cheetah_enable_pcache();
106 __asm__
__volatile__("membar #Sync\n\t"
107 "flush %%g6" : : : "memory");
109 /* Clear this or we will die instantly when we
110 * schedule back to this idler...
112 current_thread_info()->new_child
= 0;
114 /* Attach to the address space of init_task. */
115 atomic_inc(&init_mm
.mm_count
);
116 current
->active_mm
= &init_mm
;
118 while (!cpu_isset(cpuid
, smp_commenced_mask
))
122 cpu_set(cpuid
, cpu_online_map
);
125 /* idle thread is expected to have preempt disabled */
131 printk("CPU[%d]: Returns from cpu_idle!\n", smp_processor_id());
132 panic("SMP bolixed\n");
135 /* This tick register synchronization scheme is taken entirely from
136 * the ia64 port, see arch/ia64/kernel/smpboot.c for details and credit.
138 * The only change I've made is to rework it so that the master
139 * initiates the synchonization instead of the slave. -DaveM
143 #define SLAVE (SMP_CACHE_BYTES/sizeof(unsigned long))
145 #define NUM_ROUNDS 64 /* magic value */
146 #define NUM_ITERS 5 /* likewise */
148 static DEFINE_SPINLOCK(itc_sync_lock
);
149 static unsigned long go
[SLAVE
+ 1];
151 #define DEBUG_TICK_SYNC 0
153 static inline long get_delta (long *rt
, long *master
)
155 unsigned long best_t0
= 0, best_t1
= ~0UL, best_tm
= 0;
156 unsigned long tcenter
, t0
, t1
, tm
;
159 for (i
= 0; i
< NUM_ITERS
; i
++) {
160 t0
= tick_ops
->get_tick();
163 while (!(tm
= go
[SLAVE
]))
167 t1
= tick_ops
->get_tick();
169 if (t1
- t0
< best_t1
- best_t0
)
170 best_t0
= t0
, best_t1
= t1
, best_tm
= tm
;
173 *rt
= best_t1
- best_t0
;
174 *master
= best_tm
- best_t0
;
176 /* average best_t0 and best_t1 without overflow: */
177 tcenter
= (best_t0
/2 + best_t1
/2);
178 if (best_t0
% 2 + best_t1
% 2 == 2)
180 return tcenter
- best_tm
;
183 void smp_synchronize_tick_client(void)
185 long i
, delta
, adj
, adjust_latency
= 0, done
= 0;
186 unsigned long flags
, rt
, master_time_stamp
, bound
;
189 long rt
; /* roundtrip time */
190 long master
; /* master's timestamp */
191 long diff
; /* difference between midpoint and master's timestamp */
192 long lat
; /* estimate of itc adjustment latency */
201 local_irq_save(flags
);
203 for (i
= 0; i
< NUM_ROUNDS
; i
++) {
204 delta
= get_delta(&rt
, &master_time_stamp
);
206 done
= 1; /* let's lock on to this... */
212 adjust_latency
+= -delta
;
213 adj
= -delta
+ adjust_latency
/4;
217 tick_ops
->add_tick(adj
);
221 t
[i
].master
= master_time_stamp
;
223 t
[i
].lat
= adjust_latency
/4;
227 local_irq_restore(flags
);
230 for (i
= 0; i
< NUM_ROUNDS
; i
++)
231 printk("rt=%5ld master=%5ld diff=%5ld adjlat=%5ld\n",
232 t
[i
].rt
, t
[i
].master
, t
[i
].diff
, t
[i
].lat
);
235 printk(KERN_INFO
"CPU %d: synchronized TICK with master CPU "
236 "(last diff %ld cycles, maxerr %lu cycles)\n",
237 smp_processor_id(), delta
, rt
);
240 static void smp_start_sync_tick_client(int cpu
);
242 static void smp_synchronize_one_tick(int cpu
)
244 unsigned long flags
, i
;
248 smp_start_sync_tick_client(cpu
);
250 /* wait for client to be ready */
254 /* now let the client proceed into his loop */
258 spin_lock_irqsave(&itc_sync_lock
, flags
);
260 for (i
= 0; i
< NUM_ROUNDS
*NUM_ITERS
; i
++) {
265 go
[SLAVE
] = tick_ops
->get_tick();
269 spin_unlock_irqrestore(&itc_sync_lock
, flags
);
272 #if defined(CONFIG_SUN_LDOMS) && defined(CONFIG_HOTPLUG_CPU)
273 /* XXX Put this in some common place. XXX */
274 static unsigned long kimage_addr_to_ra(void *p
)
276 unsigned long val
= (unsigned long) p
;
278 return kern_base
+ (val
- KERNBASE
);
281 static void ldom_startcpu_cpuid(unsigned int cpu
, unsigned long thread_reg
)
283 extern unsigned long sparc64_ttable_tl0
;
284 extern unsigned long kern_locked_tte_data
;
285 struct hvtramp_descr
*hdesc
;
286 unsigned long trampoline_ra
;
287 struct trap_per_cpu
*tb
;
288 u64 tte_vaddr
, tte_data
;
289 unsigned long hv_err
;
292 hdesc
= kzalloc(sizeof(*hdesc
) +
293 (sizeof(struct hvtramp_mapping
) *
294 num_kernel_image_mappings
- 1),
297 printk(KERN_ERR
"ldom_startcpu_cpuid: Cannot allocate "
303 hdesc
->num_mappings
= num_kernel_image_mappings
;
305 tb
= &trap_block
[cpu
];
308 hdesc
->fault_info_va
= (unsigned long) &tb
->fault_info
;
309 hdesc
->fault_info_pa
= kimage_addr_to_ra(&tb
->fault_info
);
311 hdesc
->thread_reg
= thread_reg
;
313 tte_vaddr
= (unsigned long) KERNBASE
;
314 tte_data
= kern_locked_tte_data
;
316 for (i
= 0; i
< hdesc
->num_mappings
; i
++) {
317 hdesc
->maps
[i
].vaddr
= tte_vaddr
;
318 hdesc
->maps
[i
].tte
= tte_data
;
319 tte_vaddr
+= 0x400000;
320 tte_data
+= 0x400000;
323 trampoline_ra
= kimage_addr_to_ra(hv_cpu_startup
);
325 hv_err
= sun4v_cpu_start(cpu
, trampoline_ra
,
326 kimage_addr_to_ra(&sparc64_ttable_tl0
),
329 printk(KERN_ERR
"ldom_startcpu_cpuid: sun4v_cpu_start() "
330 "gives error %lu\n", hv_err
);
334 extern unsigned long sparc64_cpu_startup
;
336 /* The OBP cpu startup callback truncates the 3rd arg cookie to
337 * 32-bits (I think) so to be safe we have it read the pointer
338 * contained here so we work on >4GB machines. -DaveM
340 static struct thread_info
*cpu_new_thread
= NULL
;
342 static int __devinit
smp_boot_one_cpu(unsigned int cpu
)
344 struct trap_per_cpu
*tb
= &trap_block
[cpu
];
345 unsigned long entry
=
346 (unsigned long)(&sparc64_cpu_startup
);
347 unsigned long cookie
=
348 (unsigned long)(&cpu_new_thread
);
349 struct task_struct
*p
;
356 cpu_new_thread
= task_thread_info(p
);
358 if (tlb_type
== hypervisor
) {
359 #if defined(CONFIG_SUN_LDOMS) && defined(CONFIG_HOTPLUG_CPU)
360 if (ldom_domaining_enabled
)
361 ldom_startcpu_cpuid(cpu
,
362 (unsigned long) cpu_new_thread
);
365 prom_startcpu_cpuid(cpu
, entry
, cookie
);
367 struct device_node
*dp
= of_find_node_by_cpuid(cpu
);
369 prom_startcpu(dp
->node
, entry
, cookie
);
372 for (timeout
= 0; timeout
< 50000; timeout
++) {
381 printk("Processor %d is stuck.\n", cpu
);
384 cpu_new_thread
= NULL
;
394 static void spitfire_xcall_helper(u64 data0
, u64 data1
, u64 data2
, u64 pstate
, unsigned long cpu
)
399 if (this_is_starfire
) {
400 /* map to real upaid */
401 cpu
= (((cpu
& 0x3c) << 1) |
402 ((cpu
& 0x40) >> 4) |
406 target
= (cpu
<< 14) | 0x70;
408 /* Ok, this is the real Spitfire Errata #54.
409 * One must read back from a UDB internal register
410 * after writes to the UDB interrupt dispatch, but
411 * before the membar Sync for that write.
412 * So we use the high UDB control register (ASI 0x7f,
413 * ADDR 0x20) for the dummy read. -DaveM
416 __asm__
__volatile__(
417 "wrpr %1, %2, %%pstate\n\t"
418 "stxa %4, [%0] %3\n\t"
419 "stxa %5, [%0+%8] %3\n\t"
421 "stxa %6, [%0+%8] %3\n\t"
423 "stxa %%g0, [%7] %3\n\t"
426 "ldxa [%%g1] 0x7f, %%g0\n\t"
429 : "r" (pstate
), "i" (PSTATE_IE
), "i" (ASI_INTR_W
),
430 "r" (data0
), "r" (data1
), "r" (data2
), "r" (target
),
431 "r" (0x10), "0" (tmp
)
434 /* NOTE: PSTATE_IE is still clear. */
437 __asm__
__volatile__("ldxa [%%g0] %1, %0"
439 : "i" (ASI_INTR_DISPATCH_STAT
));
441 __asm__
__volatile__("wrpr %0, 0x0, %%pstate"
448 } while (result
& 0x1);
449 __asm__
__volatile__("wrpr %0, 0x0, %%pstate"
452 printk("CPU[%d]: mondo stuckage result[%016lx]\n",
453 smp_processor_id(), result
);
460 static void spitfire_xcall_deliver(struct trap_per_cpu
*tb
, int cnt
)
462 u64
*mondo
, data0
, data1
, data2
;
467 __asm__
__volatile__("rdpr %%pstate, %0" : "=r" (pstate
));
468 cpu_list
= __va(tb
->cpu_list_pa
);
469 mondo
= __va(tb
->cpu_mondo_block_pa
);
473 for (i
= 0; i
< cnt
; i
++)
474 spitfire_xcall_helper(data0
, data1
, data2
, pstate
, cpu_list
[i
]);
477 /* Cheetah now allows to send the whole 64-bytes of data in the interrupt
478 * packet, but we have no use for that. However we do take advantage of
479 * the new pipelining feature (ie. dispatch to multiple cpus simultaneously).
481 static void cheetah_xcall_deliver(struct trap_per_cpu
*tb
, int cnt
)
483 int nack_busy_id
, is_jbus
, need_more
;
484 u64
*mondo
, pstate
, ver
, busy_mask
;
487 cpu_list
= __va(tb
->cpu_list_pa
);
488 mondo
= __va(tb
->cpu_mondo_block_pa
);
490 /* Unfortunately, someone at Sun had the brilliant idea to make the
491 * busy/nack fields hard-coded by ITID number for this Ultra-III
492 * derivative processor.
494 __asm__ ("rdpr %%ver, %0" : "=r" (ver
));
495 is_jbus
= ((ver
>> 32) == __JALAPENO_ID
||
496 (ver
>> 32) == __SERRANO_ID
);
498 __asm__
__volatile__("rdpr %%pstate, %0" : "=r" (pstate
));
502 __asm__
__volatile__("wrpr %0, %1, %%pstate\n\t"
503 : : "r" (pstate
), "i" (PSTATE_IE
));
505 /* Setup the dispatch data registers. */
506 __asm__
__volatile__("stxa %0, [%3] %6\n\t"
507 "stxa %1, [%4] %6\n\t"
508 "stxa %2, [%5] %6\n\t"
511 : "r" (mondo
[0]), "r" (mondo
[1]), "r" (mondo
[2]),
512 "r" (0x40), "r" (0x50), "r" (0x60),
520 for (i
= 0; i
< cnt
; i
++) {
527 target
= (nr
<< 14) | 0x70;
529 busy_mask
|= (0x1UL
<< (nr
* 2));
531 target
|= (nack_busy_id
<< 24);
532 busy_mask
|= (0x1UL
<<
535 __asm__
__volatile__(
536 "stxa %%g0, [%0] %1\n\t"
539 : "r" (target
), "i" (ASI_INTR_W
));
541 if (nack_busy_id
== 32) {
548 /* Now, poll for completion. */
550 u64 dispatch_stat
, nack_mask
;
553 stuck
= 100000 * nack_busy_id
;
554 nack_mask
= busy_mask
<< 1;
556 __asm__
__volatile__("ldxa [%%g0] %1, %0"
557 : "=r" (dispatch_stat
)
558 : "i" (ASI_INTR_DISPATCH_STAT
));
559 if (!(dispatch_stat
& (busy_mask
| nack_mask
))) {
560 __asm__
__volatile__("wrpr %0, 0x0, %%pstate"
562 if (unlikely(need_more
)) {
564 for (i
= 0; i
< cnt
; i
++) {
565 if (cpu_list
[i
] == 0xffff)
567 cpu_list
[i
] = 0xffff;
578 } while (dispatch_stat
& busy_mask
);
580 __asm__
__volatile__("wrpr %0, 0x0, %%pstate"
583 if (dispatch_stat
& busy_mask
) {
584 /* Busy bits will not clear, continue instead
585 * of freezing up on this cpu.
587 printk("CPU[%d]: mondo stuckage result[%016lx]\n",
588 smp_processor_id(), dispatch_stat
);
590 int i
, this_busy_nack
= 0;
592 /* Delay some random time with interrupts enabled
593 * to prevent deadlock.
595 udelay(2 * nack_busy_id
);
597 /* Clear out the mask bits for cpus which did not
600 for (i
= 0; i
< cnt
; i
++) {
608 check_mask
= (0x2UL
<< (2*nr
));
610 check_mask
= (0x2UL
<<
612 if ((dispatch_stat
& check_mask
) == 0)
613 cpu_list
[i
] = 0xffff;
615 if (this_busy_nack
== 64)
624 /* Multi-cpu list version. */
625 static void hypervisor_xcall_deliver(struct trap_per_cpu
*tb
, int cnt
)
627 int retries
, this_cpu
, prev_sent
, i
, saw_cpu_error
;
628 unsigned long status
;
631 this_cpu
= smp_processor_id();
633 cpu_list
= __va(tb
->cpu_list_pa
);
639 int forward_progress
, n_sent
;
641 status
= sun4v_cpu_mondo_send(cnt
,
643 tb
->cpu_mondo_block_pa
);
645 /* HV_EOK means all cpus received the xcall, we're done. */
646 if (likely(status
== HV_EOK
))
649 /* First, see if we made any forward progress.
651 * The hypervisor indicates successful sends by setting
652 * cpu list entries to the value 0xffff.
655 for (i
= 0; i
< cnt
; i
++) {
656 if (likely(cpu_list
[i
] == 0xffff))
660 forward_progress
= 0;
661 if (n_sent
> prev_sent
)
662 forward_progress
= 1;
666 /* If we get a HV_ECPUERROR, then one or more of the cpus
667 * in the list are in error state. Use the cpu_state()
668 * hypervisor call to find out which cpus are in error state.
670 if (unlikely(status
== HV_ECPUERROR
)) {
671 for (i
= 0; i
< cnt
; i
++) {
679 err
= sun4v_cpu_state(cpu
);
680 if (err
== HV_CPU_STATE_ERROR
) {
681 saw_cpu_error
= (cpu
+ 1);
682 cpu_list
[i
] = 0xffff;
685 } else if (unlikely(status
!= HV_EWOULDBLOCK
))
686 goto fatal_mondo_error
;
688 /* Don't bother rewriting the CPU list, just leave the
689 * 0xffff and non-0xffff entries in there and the
690 * hypervisor will do the right thing.
692 * Only advance timeout state if we didn't make any
695 if (unlikely(!forward_progress
)) {
696 if (unlikely(++retries
> 10000))
697 goto fatal_mondo_timeout
;
699 /* Delay a little bit to let other cpus catch up
700 * on their cpu mondo queue work.
706 if (unlikely(saw_cpu_error
))
707 goto fatal_mondo_cpu_error
;
711 fatal_mondo_cpu_error
:
712 printk(KERN_CRIT
"CPU[%d]: SUN4V mondo cpu error, some target cpus "
713 "(including %d) were in error state\n",
714 this_cpu
, saw_cpu_error
- 1);
718 printk(KERN_CRIT
"CPU[%d]: SUN4V mondo timeout, no forward "
719 " progress after %d retries.\n",
721 goto dump_cpu_list_and_out
;
724 printk(KERN_CRIT
"CPU[%d]: Unexpected SUN4V mondo error %lu\n",
726 printk(KERN_CRIT
"CPU[%d]: Args were cnt(%d) cpulist_pa(%lx) "
727 "mondo_block_pa(%lx)\n",
728 this_cpu
, cnt
, tb
->cpu_list_pa
, tb
->cpu_mondo_block_pa
);
730 dump_cpu_list_and_out
:
731 printk(KERN_CRIT
"CPU[%d]: CPU list [ ", this_cpu
);
732 for (i
= 0; i
< cnt
; i
++)
733 printk("%u ", cpu_list
[i
]);
737 static void (*xcall_deliver_impl
)(struct trap_per_cpu
*, int);
739 static void xcall_deliver(u64 data0
, u64 data1
, u64 data2
, const cpumask_t
*mask
)
741 struct trap_per_cpu
*tb
;
742 int this_cpu
, i
, cnt
;
747 /* We have to do this whole thing with interrupts fully disabled.
748 * Otherwise if we send an xcall from interrupt context it will
749 * corrupt both our mondo block and cpu list state.
751 * One consequence of this is that we cannot use timeout mechanisms
752 * that depend upon interrupts being delivered locally. So, for
753 * example, we cannot sample jiffies and expect it to advance.
755 * Fortunately, udelay() uses %stick/%tick so we can use that.
757 local_irq_save(flags
);
759 this_cpu
= smp_processor_id();
760 tb
= &trap_block
[this_cpu
];
762 mondo
= __va(tb
->cpu_mondo_block_pa
);
768 cpu_list
= __va(tb
->cpu_list_pa
);
770 /* Setup the initial cpu list. */
772 for_each_cpu_mask_nr(i
, *mask
) {
773 if (i
== this_cpu
|| !cpu_online(i
))
779 xcall_deliver_impl(tb
, cnt
);
781 local_irq_restore(flags
);
784 /* Send cross call to all processors mentioned in MASK_P
785 * except self. Really, there are only two cases currently,
786 * "&cpu_online_map" and "&mm->cpu_vm_mask".
788 static void smp_cross_call_masked(unsigned long *func
, u32 ctx
, u64 data1
, u64 data2
, const cpumask_t
*mask
)
790 u64 data0
= (((u64
)ctx
)<<32 | (((u64
)func
) & 0xffffffff));
792 xcall_deliver(data0
, data1
, data2
, mask
);
795 /* Send cross call to all processors except self. */
796 static void smp_cross_call(unsigned long *func
, u32 ctx
, u64 data1
, u64 data2
)
798 smp_cross_call_masked(func
, ctx
, data1
, data2
, &cpu_online_map
);
801 extern unsigned long xcall_sync_tick
;
803 static void smp_start_sync_tick_client(int cpu
)
805 xcall_deliver((u64
) &xcall_sync_tick
, 0, 0,
806 &cpumask_of_cpu(cpu
));
809 extern unsigned long xcall_call_function
;
811 void arch_send_call_function_ipi(cpumask_t mask
)
813 xcall_deliver((u64
) &xcall_call_function
, 0, 0, &mask
);
816 extern unsigned long xcall_call_function_single
;
818 void arch_send_call_function_single_ipi(int cpu
)
820 xcall_deliver((u64
) &xcall_call_function_single
, 0, 0,
821 &cpumask_of_cpu(cpu
));
824 void smp_call_function_client(int irq
, struct pt_regs
*regs
)
826 clear_softint(1 << irq
);
827 generic_smp_call_function_interrupt();
830 void smp_call_function_single_client(int irq
, struct pt_regs
*regs
)
832 clear_softint(1 << irq
);
833 generic_smp_call_function_single_interrupt();
836 static void tsb_sync(void *info
)
838 struct trap_per_cpu
*tp
= &trap_block
[raw_smp_processor_id()];
839 struct mm_struct
*mm
= info
;
841 /* It is not valid to test "currrent->active_mm == mm" here.
843 * The value of "current" is not changed atomically with
844 * switch_mm(). But that's OK, we just need to check the
845 * current cpu's trap block PGD physical address.
847 if (tp
->pgd_paddr
== __pa(mm
->pgd
))
848 tsb_context_switch(mm
);
851 void smp_tsb_sync(struct mm_struct
*mm
)
853 smp_call_function_mask(mm
->cpu_vm_mask
, tsb_sync
, mm
, 1);
856 extern unsigned long xcall_flush_tlb_mm
;
857 extern unsigned long xcall_flush_tlb_pending
;
858 extern unsigned long xcall_flush_tlb_kernel_range
;
859 extern unsigned long xcall_fetch_glob_regs
;
860 extern unsigned long xcall_receive_signal
;
861 extern unsigned long xcall_new_mmu_context_version
;
863 extern unsigned long xcall_kgdb_capture
;
866 #ifdef DCACHE_ALIASING_POSSIBLE
867 extern unsigned long xcall_flush_dcache_page_cheetah
;
869 extern unsigned long xcall_flush_dcache_page_spitfire
;
871 #ifdef CONFIG_DEBUG_DCFLUSH
872 extern atomic_t dcpage_flushes
;
873 extern atomic_t dcpage_flushes_xcall
;
876 static inline void __local_flush_dcache_page(struct page
*page
)
878 #ifdef DCACHE_ALIASING_POSSIBLE
879 __flush_dcache_page(page_address(page
),
880 ((tlb_type
== spitfire
) &&
881 page_mapping(page
) != NULL
));
883 if (page_mapping(page
) != NULL
&&
884 tlb_type
== spitfire
)
885 __flush_icache_page(__pa(page_address(page
)));
889 void smp_flush_dcache_page_impl(struct page
*page
, int cpu
)
893 if (tlb_type
== hypervisor
)
896 #ifdef CONFIG_DEBUG_DCFLUSH
897 atomic_inc(&dcpage_flushes
);
900 this_cpu
= get_cpu();
902 if (cpu
== this_cpu
) {
903 __local_flush_dcache_page(page
);
904 } else if (cpu_online(cpu
)) {
905 void *pg_addr
= page_address(page
);
908 if (tlb_type
== spitfire
) {
909 data0
= ((u64
)&xcall_flush_dcache_page_spitfire
);
910 if (page_mapping(page
) != NULL
)
911 data0
|= ((u64
)1 << 32);
912 } else if (tlb_type
== cheetah
|| tlb_type
== cheetah_plus
) {
913 #ifdef DCACHE_ALIASING_POSSIBLE
914 data0
= ((u64
)&xcall_flush_dcache_page_cheetah
);
918 xcall_deliver(data0
, __pa(pg_addr
),
919 (u64
) pg_addr
, &cpumask_of_cpu(cpu
));
920 #ifdef CONFIG_DEBUG_DCFLUSH
921 atomic_inc(&dcpage_flushes_xcall
);
929 void flush_dcache_page_all(struct mm_struct
*mm
, struct page
*page
)
935 if (tlb_type
== hypervisor
)
938 this_cpu
= get_cpu();
940 #ifdef CONFIG_DEBUG_DCFLUSH
941 atomic_inc(&dcpage_flushes
);
944 pg_addr
= page_address(page
);
945 if (tlb_type
== spitfire
) {
946 data0
= ((u64
)&xcall_flush_dcache_page_spitfire
);
947 if (page_mapping(page
) != NULL
)
948 data0
|= ((u64
)1 << 32);
949 } else if (tlb_type
== cheetah
|| tlb_type
== cheetah_plus
) {
950 #ifdef DCACHE_ALIASING_POSSIBLE
951 data0
= ((u64
)&xcall_flush_dcache_page_cheetah
);
955 xcall_deliver(data0
, __pa(pg_addr
),
956 (u64
) pg_addr
, &cpu_online_map
);
957 #ifdef CONFIG_DEBUG_DCFLUSH
958 atomic_inc(&dcpage_flushes_xcall
);
961 __local_flush_dcache_page(page
);
966 void smp_new_mmu_context_version_client(int irq
, struct pt_regs
*regs
)
968 struct mm_struct
*mm
;
971 clear_softint(1 << irq
);
973 /* See if we need to allocate a new TLB context because
974 * the version of the one we are using is now out of date.
976 mm
= current
->active_mm
;
977 if (unlikely(!mm
|| (mm
== &init_mm
)))
980 spin_lock_irqsave(&mm
->context
.lock
, flags
);
982 if (unlikely(!CTX_VALID(mm
->context
)))
983 get_new_mmu_context(mm
);
985 spin_unlock_irqrestore(&mm
->context
.lock
, flags
);
987 load_secondary_context(mm
);
988 __flush_tlb_mm(CTX_HWBITS(mm
->context
),
992 void smp_new_mmu_context_version(void)
994 smp_cross_call(&xcall_new_mmu_context_version
, 0, 0, 0);
998 void kgdb_roundup_cpus(unsigned long flags
)
1000 smp_cross_call(&xcall_kgdb_capture
, 0, 0, 0);
1004 void smp_fetch_global_regs(void)
1006 smp_cross_call(&xcall_fetch_glob_regs
, 0, 0, 0);
1009 /* We know that the window frames of the user have been flushed
1010 * to the stack before we get here because all callers of us
1011 * are flush_tlb_*() routines, and these run after flush_cache_*()
1012 * which performs the flushw.
1014 * The SMP TLB coherency scheme we use works as follows:
1016 * 1) mm->cpu_vm_mask is a bit mask of which cpus an address
1017 * space has (potentially) executed on, this is the heuristic
1018 * we use to avoid doing cross calls.
1020 * Also, for flushing from kswapd and also for clones, we
1021 * use cpu_vm_mask as the list of cpus to make run the TLB.
1023 * 2) TLB context numbers are shared globally across all processors
1024 * in the system, this allows us to play several games to avoid
1027 * One invariant is that when a cpu switches to a process, and
1028 * that processes tsk->active_mm->cpu_vm_mask does not have the
1029 * current cpu's bit set, that tlb context is flushed locally.
1031 * If the address space is non-shared (ie. mm->count == 1) we avoid
1032 * cross calls when we want to flush the currently running process's
1033 * tlb state. This is done by clearing all cpu bits except the current
1034 * processor's in current->active_mm->cpu_vm_mask and performing the
1035 * flush locally only. This will force any subsequent cpus which run
1036 * this task to flush the context from the local tlb if the process
1037 * migrates to another cpu (again).
1039 * 3) For shared address spaces (threads) and swapping we bite the
1040 * bullet for most cases and perform the cross call (but only to
1041 * the cpus listed in cpu_vm_mask).
1043 * The performance gain from "optimizing" away the cross call for threads is
1044 * questionable (in theory the big win for threads is the massive sharing of
1045 * address space state across processors).
1048 /* This currently is only used by the hugetlb arch pre-fault
1049 * hook on UltraSPARC-III+ and later when changing the pagesize
1050 * bits of the context register for an address space.
1052 void smp_flush_tlb_mm(struct mm_struct
*mm
)
1054 u32 ctx
= CTX_HWBITS(mm
->context
);
1055 int cpu
= get_cpu();
1057 if (atomic_read(&mm
->mm_users
) == 1) {
1058 mm
->cpu_vm_mask
= cpumask_of_cpu(cpu
);
1059 goto local_flush_and_out
;
1062 smp_cross_call_masked(&xcall_flush_tlb_mm
,
1066 local_flush_and_out
:
1067 __flush_tlb_mm(ctx
, SECONDARY_CONTEXT
);
1072 void smp_flush_tlb_pending(struct mm_struct
*mm
, unsigned long nr
, unsigned long *vaddrs
)
1074 u32 ctx
= CTX_HWBITS(mm
->context
);
1075 int cpu
= get_cpu();
1077 if (mm
== current
->active_mm
&& atomic_read(&mm
->mm_users
) == 1)
1078 mm
->cpu_vm_mask
= cpumask_of_cpu(cpu
);
1080 smp_cross_call_masked(&xcall_flush_tlb_pending
,
1081 ctx
, nr
, (unsigned long) vaddrs
,
1084 __flush_tlb_pending(ctx
, nr
, vaddrs
);
1089 void smp_flush_tlb_kernel_range(unsigned long start
, unsigned long end
)
1092 end
= PAGE_ALIGN(end
);
1094 smp_cross_call(&xcall_flush_tlb_kernel_range
,
1097 __flush_tlb_kernel_range(start
, end
);
1102 /* #define CAPTURE_DEBUG */
1103 extern unsigned long xcall_capture
;
1105 static atomic_t smp_capture_depth
= ATOMIC_INIT(0);
1106 static atomic_t smp_capture_registry
= ATOMIC_INIT(0);
1107 static unsigned long penguins_are_doing_time
;
1109 void smp_capture(void)
1111 int result
= atomic_add_ret(1, &smp_capture_depth
);
1114 int ncpus
= num_online_cpus();
1116 #ifdef CAPTURE_DEBUG
1117 printk("CPU[%d]: Sending penguins to jail...",
1118 smp_processor_id());
1120 penguins_are_doing_time
= 1;
1121 membar_storestore_loadstore();
1122 atomic_inc(&smp_capture_registry
);
1123 smp_cross_call(&xcall_capture
, 0, 0, 0);
1124 while (atomic_read(&smp_capture_registry
) != ncpus
)
1126 #ifdef CAPTURE_DEBUG
1132 void smp_release(void)
1134 if (atomic_dec_and_test(&smp_capture_depth
)) {
1135 #ifdef CAPTURE_DEBUG
1136 printk("CPU[%d]: Giving pardon to "
1137 "imprisoned penguins\n",
1138 smp_processor_id());
1140 penguins_are_doing_time
= 0;
1141 membar_storeload_storestore();
1142 atomic_dec(&smp_capture_registry
);
1146 /* Imprisoned penguins run with %pil == 15, but PSTATE_IE set, so they
1147 * can service tlb flush xcalls...
1149 extern void prom_world(int);
1151 void smp_penguin_jailcell(int irq
, struct pt_regs
*regs
)
1153 clear_softint(1 << irq
);
1157 __asm__
__volatile__("flushw");
1159 atomic_inc(&smp_capture_registry
);
1160 membar_storeload_storestore();
1161 while (penguins_are_doing_time
)
1163 atomic_dec(&smp_capture_registry
);
1169 /* /proc/profile writes can call this, don't __init it please. */
1170 int setup_profiling_timer(unsigned int multiplier
)
1175 void __init
smp_prepare_cpus(unsigned int max_cpus
)
1179 void __devinit
smp_prepare_boot_cpu(void)
1183 void __init
smp_setup_processor_id(void)
1185 if (tlb_type
== spitfire
)
1186 xcall_deliver_impl
= spitfire_xcall_deliver
;
1187 else if (tlb_type
== cheetah
|| tlb_type
== cheetah_plus
)
1188 xcall_deliver_impl
= cheetah_xcall_deliver
;
1190 xcall_deliver_impl
= hypervisor_xcall_deliver
;
1193 void __devinit
smp_fill_in_sib_core_maps(void)
1197 for_each_present_cpu(i
) {
1200 cpus_clear(cpu_core_map
[i
]);
1201 if (cpu_data(i
).core_id
== 0) {
1202 cpu_set(i
, cpu_core_map
[i
]);
1206 for_each_present_cpu(j
) {
1207 if (cpu_data(i
).core_id
==
1208 cpu_data(j
).core_id
)
1209 cpu_set(j
, cpu_core_map
[i
]);
1213 for_each_present_cpu(i
) {
1216 cpus_clear(per_cpu(cpu_sibling_map
, i
));
1217 if (cpu_data(i
).proc_id
== -1) {
1218 cpu_set(i
, per_cpu(cpu_sibling_map
, i
));
1222 for_each_present_cpu(j
) {
1223 if (cpu_data(i
).proc_id
==
1224 cpu_data(j
).proc_id
)
1225 cpu_set(j
, per_cpu(cpu_sibling_map
, i
));
1230 int __cpuinit
__cpu_up(unsigned int cpu
)
1232 int ret
= smp_boot_one_cpu(cpu
);
1235 cpu_set(cpu
, smp_commenced_mask
);
1236 while (!cpu_isset(cpu
, cpu_online_map
))
1238 if (!cpu_isset(cpu
, cpu_online_map
)) {
1241 /* On SUN4V, writes to %tick and %stick are
1244 if (tlb_type
!= hypervisor
)
1245 smp_synchronize_one_tick(cpu
);
1251 #ifdef CONFIG_HOTPLUG_CPU
1252 void cpu_play_dead(void)
1254 int cpu
= smp_processor_id();
1255 unsigned long pstate
;
1259 if (tlb_type
== hypervisor
) {
1260 struct trap_per_cpu
*tb
= &trap_block
[cpu
];
1262 sun4v_cpu_qconf(HV_CPU_QUEUE_CPU_MONDO
,
1263 tb
->cpu_mondo_pa
, 0);
1264 sun4v_cpu_qconf(HV_CPU_QUEUE_DEVICE_MONDO
,
1265 tb
->dev_mondo_pa
, 0);
1266 sun4v_cpu_qconf(HV_CPU_QUEUE_RES_ERROR
,
1267 tb
->resum_mondo_pa
, 0);
1268 sun4v_cpu_qconf(HV_CPU_QUEUE_NONRES_ERROR
,
1269 tb
->nonresum_mondo_pa
, 0);
1272 cpu_clear(cpu
, smp_commenced_mask
);
1273 membar_safe("#Sync");
1275 local_irq_disable();
1277 __asm__
__volatile__(
1278 "rdpr %%pstate, %0\n\t"
1279 "wrpr %0, %1, %%pstate"
1287 int __cpu_disable(void)
1289 int cpu
= smp_processor_id();
1293 for_each_cpu_mask(i
, cpu_core_map
[cpu
])
1294 cpu_clear(cpu
, cpu_core_map
[i
]);
1295 cpus_clear(cpu_core_map
[cpu
]);
1297 for_each_cpu_mask(i
, per_cpu(cpu_sibling_map
, cpu
))
1298 cpu_clear(cpu
, per_cpu(cpu_sibling_map
, i
));
1299 cpus_clear(per_cpu(cpu_sibling_map
, cpu
));
1308 /* Make sure no interrupts point to this cpu. */
1313 local_irq_disable();
1316 cpu_clear(cpu
, cpu_online_map
);
1322 void __cpu_die(unsigned int cpu
)
1326 for (i
= 0; i
< 100; i
++) {
1328 if (!cpu_isset(cpu
, smp_commenced_mask
))
1332 if (cpu_isset(cpu
, smp_commenced_mask
)) {
1333 printk(KERN_ERR
"CPU %u didn't die...\n", cpu
);
1335 #if defined(CONFIG_SUN_LDOMS)
1336 unsigned long hv_err
;
1340 hv_err
= sun4v_cpu_stop(cpu
);
1341 if (hv_err
== HV_EOK
) {
1342 cpu_clear(cpu
, cpu_present_map
);
1345 } while (--limit
> 0);
1347 printk(KERN_ERR
"sun4v_cpu_stop() fails err=%lu\n",
1355 void __init
smp_cpus_done(unsigned int max_cpus
)
1359 void smp_send_reschedule(int cpu
)
1361 xcall_deliver((u64
) &xcall_receive_signal
, 0, 0,
1362 &cpumask_of_cpu(cpu
));
1365 void smp_receive_signal_client(int irq
, struct pt_regs
*regs
)
1367 clear_softint(1 << irq
);
1370 /* This is a nop because we capture all other cpus
1371 * anyways when making the PROM active.
1373 void smp_send_stop(void)
1377 unsigned long __per_cpu_base __read_mostly
;
1378 unsigned long __per_cpu_shift __read_mostly
;
1380 EXPORT_SYMBOL(__per_cpu_base
);
1381 EXPORT_SYMBOL(__per_cpu_shift
);
1383 void __init
real_setup_per_cpu_areas(void)
1385 unsigned long paddr
, goal
, size
, i
;
1388 /* Copy section for each CPU (we discard the original) */
1389 goal
= PERCPU_ENOUGH_ROOM
;
1391 __per_cpu_shift
= PAGE_SHIFT
;
1392 for (size
= PAGE_SIZE
; size
< goal
; size
<<= 1UL)
1395 paddr
= lmb_alloc(size
* NR_CPUS
, PAGE_SIZE
);
1397 prom_printf("Cannot allocate per-cpu memory.\n");
1402 __per_cpu_base
= ptr
- __per_cpu_start
;
1404 for (i
= 0; i
< NR_CPUS
; i
++, ptr
+= size
)
1405 memcpy(ptr
, __per_cpu_start
, __per_cpu_end
- __per_cpu_start
);
1407 /* Setup %g5 for the boot cpu. */
1408 __local_per_cpu_offset
= __per_cpu_offset(smp_processor_id());