2 * TI DaVinci GPIO Support
4 * Copyright (c) 2006-2007 David Brownell
5 * Copyright (c) 2007, MontaVista Software, Inc. <source@mvista.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
13 #include <linux/errno.h>
14 #include <linux/kernel.h>
15 #include <linux/clk.h>
16 #include <linux/err.h>
19 #include <mach/gpio.h>
21 #include <asm/mach/irq.h>
23 static DEFINE_SPINLOCK(gpio_lock
);
25 #define chip2controller(chip) \
26 container_of(chip, struct davinci_gpio_controller, chip)
28 static struct davinci_gpio_controller chips
[DIV_ROUND_UP(DAVINCI_N_GPIO
, 32)];
30 /* create a non-inlined version */
31 static struct davinci_gpio_regs __iomem __init
*gpio2regs(unsigned gpio
)
33 return __gpio_to_controller(gpio
);
36 static inline struct davinci_gpio_regs __iomem
*irq2regs(int irq
)
38 struct davinci_gpio_regs __iomem
*g
;
40 g
= (__force
struct davinci_gpio_regs __iomem
*)get_irq_chip_data(irq
);
45 static int __init
davinci_gpio_irq_setup(void);
47 /*--------------------------------------------------------------------------*/
50 * board setup code *MUST* set PINMUX0 and PINMUX1 as
51 * needed, and enable the GPIO clock.
54 static inline int __davinci_direction(struct gpio_chip
*chip
,
55 unsigned offset
, bool out
, int value
)
57 struct davinci_gpio_controller
*d
= chip2controller(chip
);
58 struct davinci_gpio_regs __iomem
*g
= d
->regs
;
60 u32 mask
= 1 << offset
;
62 spin_lock(&gpio_lock
);
63 temp
= __raw_readl(&g
->dir
);
66 __raw_writel(mask
, value
? &g
->set_data
: &g
->clr_data
);
70 __raw_writel(temp
, &g
->dir
);
71 spin_unlock(&gpio_lock
);
76 static int davinci_direction_in(struct gpio_chip
*chip
, unsigned offset
)
78 return __davinci_direction(chip
, offset
, false, 0);
82 davinci_direction_out(struct gpio_chip
*chip
, unsigned offset
, int value
)
84 return __davinci_direction(chip
, offset
, true, value
);
88 * Read the pin's value (works even if it's set up as output);
89 * returns zero/nonzero.
91 * Note that changes are synched to the GPIO clock, so reading values back
92 * right after you've set them may give old values.
94 static int davinci_gpio_get(struct gpio_chip
*chip
, unsigned offset
)
96 struct davinci_gpio_controller
*d
= chip2controller(chip
);
97 struct davinci_gpio_regs __iomem
*g
= d
->regs
;
99 return (1 << offset
) & __raw_readl(&g
->in_data
);
103 * Assuming the pin is muxed as a gpio output, set its output value.
106 davinci_gpio_set(struct gpio_chip
*chip
, unsigned offset
, int value
)
108 struct davinci_gpio_controller
*d
= chip2controller(chip
);
109 struct davinci_gpio_regs __iomem
*g
= d
->regs
;
111 __raw_writel((1 << offset
), value
? &g
->set_data
: &g
->clr_data
);
114 static int __init
davinci_gpio_setup(void)
118 struct davinci_soc_info
*soc_info
= &davinci_soc_info
;
121 * The gpio banks conceptually expose a segmented bitmap,
122 * and "ngpio" is one more than the largest zero-based
123 * bit index that's valid.
125 ngpio
= soc_info
->gpio_num
;
127 pr_err("GPIO setup: how many GPIOs?\n");
131 if (WARN_ON(DAVINCI_N_GPIO
< ngpio
))
132 ngpio
= DAVINCI_N_GPIO
;
134 for (i
= 0, base
= 0; base
< ngpio
; i
++, base
+= 32) {
135 chips
[i
].chip
.label
= "DaVinci";
137 chips
[i
].chip
.direction_input
= davinci_direction_in
;
138 chips
[i
].chip
.get
= davinci_gpio_get
;
139 chips
[i
].chip
.direction_output
= davinci_direction_out
;
140 chips
[i
].chip
.set
= davinci_gpio_set
;
142 chips
[i
].chip
.base
= base
;
143 chips
[i
].chip
.ngpio
= ngpio
- base
;
144 if (chips
[i
].chip
.ngpio
> 32)
145 chips
[i
].chip
.ngpio
= 32;
147 chips
[i
].regs
= gpio2regs(base
);
149 gpiochip_add(&chips
[i
].chip
);
152 davinci_gpio_irq_setup();
155 pure_initcall(davinci_gpio_setup
);
157 /*--------------------------------------------------------------------------*/
159 * We expect irqs will normally be set up as input pins, but they can also be
160 * used as output pins ... which is convenient for testing.
162 * NOTE: The first few GPIOs also have direct INTC hookups in addition
163 * to their GPIOBNK0 irq, with a bit less overhead.
165 * All those INTC hookups (direct, plus several IRQ banks) can also
166 * serve as EDMA event triggers.
169 static void gpio_irq_disable(unsigned irq
)
171 struct davinci_gpio_regs __iomem
*g
= irq2regs(irq
);
172 u32 mask
= (u32
) get_irq_data(irq
);
174 __raw_writel(mask
, &g
->clr_falling
);
175 __raw_writel(mask
, &g
->clr_rising
);
178 static void gpio_irq_enable(unsigned irq
)
180 struct davinci_gpio_regs __iomem
*g
= irq2regs(irq
);
181 u32 mask
= (u32
) get_irq_data(irq
);
182 unsigned status
= irq_desc
[irq
].status
;
184 status
&= IRQ_TYPE_EDGE_FALLING
| IRQ_TYPE_EDGE_RISING
;
186 status
= IRQ_TYPE_EDGE_FALLING
| IRQ_TYPE_EDGE_RISING
;
188 if (status
& IRQ_TYPE_EDGE_FALLING
)
189 __raw_writel(mask
, &g
->set_falling
);
190 if (status
& IRQ_TYPE_EDGE_RISING
)
191 __raw_writel(mask
, &g
->set_rising
);
194 static int gpio_irq_type(unsigned irq
, unsigned trigger
)
196 struct davinci_gpio_regs __iomem
*g
= irq2regs(irq
);
197 u32 mask
= (u32
) get_irq_data(irq
);
199 if (trigger
& ~(IRQ_TYPE_EDGE_FALLING
| IRQ_TYPE_EDGE_RISING
))
202 irq_desc
[irq
].status
&= ~IRQ_TYPE_SENSE_MASK
;
203 irq_desc
[irq
].status
|= trigger
;
205 /* don't enable the IRQ if it's currently disabled */
206 if (irq_desc
[irq
].depth
== 0) {
207 __raw_writel(mask
, (trigger
& IRQ_TYPE_EDGE_FALLING
)
208 ? &g
->set_falling
: &g
->clr_falling
);
209 __raw_writel(mask
, (trigger
& IRQ_TYPE_EDGE_RISING
)
210 ? &g
->set_rising
: &g
->clr_rising
);
215 static struct irq_chip gpio_irqchip
= {
217 .enable
= gpio_irq_enable
,
218 .disable
= gpio_irq_disable
,
219 .set_type
= gpio_irq_type
,
223 gpio_irq_handler(unsigned irq
, struct irq_desc
*desc
)
225 struct davinci_gpio_regs __iomem
*g
= irq2regs(irq
);
228 /* we only care about one bank */
232 /* temporarily mask (level sensitive) parent IRQ */
233 desc
->chip
->mask(irq
);
234 desc
->chip
->ack(irq
);
241 status
= __raw_readl(&g
->intstat
) & mask
;
244 __raw_writel(status
, &g
->intstat
);
248 /* now demux them to the right lowlevel handler */
249 n
= (int)get_irq_data(irq
);
253 generic_handle_irq(n
- 1);
257 desc
->chip
->unmask(irq
);
258 /* now it may re-trigger */
261 static int gpio_to_irq_banked(struct gpio_chip
*chip
, unsigned offset
)
263 struct davinci_gpio_controller
*d
= chip2controller(chip
);
265 if (d
->irq_base
>= 0)
266 return d
->irq_base
+ offset
;
271 static int gpio_to_irq_unbanked(struct gpio_chip
*chip
, unsigned offset
)
273 struct davinci_soc_info
*soc_info
= &davinci_soc_info
;
275 /* NOTE: we assume for now that only irqs in the first gpio_chip
276 * can provide direct-mapped IRQs to AINTC (up to 32 GPIOs).
278 if (offset
< soc_info
->gpio_unbanked
)
279 return soc_info
->gpio_irq
+ offset
;
284 static int gpio_irq_type_unbanked(unsigned irq
, unsigned trigger
)
286 struct davinci_gpio_regs __iomem
*g
= irq2regs(irq
);
287 u32 mask
= (u32
) get_irq_data(irq
);
289 if (trigger
& ~(IRQ_TYPE_EDGE_FALLING
| IRQ_TYPE_EDGE_RISING
))
292 __raw_writel(mask
, (trigger
& IRQ_TYPE_EDGE_FALLING
)
293 ? &g
->set_falling
: &g
->clr_falling
);
294 __raw_writel(mask
, (trigger
& IRQ_TYPE_EDGE_RISING
)
295 ? &g
->set_rising
: &g
->clr_rising
);
301 * NOTE: for suspend/resume, probably best to make a platform_device with
302 * suspend_late/resume_resume calls hooking into results of the set_wake()
303 * calls ... so if no gpios are wakeup events the clock can be disabled,
304 * with outputs left at previously set levels, and so that VDD3P3V.IOPWDN0
305 * (dm6446) can be set appropriately for GPIOV33 pins.
308 static int __init
davinci_gpio_irq_setup(void)
310 unsigned gpio
, irq
, bank
;
313 unsigned ngpio
, bank_irq
;
314 struct davinci_soc_info
*soc_info
= &davinci_soc_info
;
315 struct davinci_gpio_regs __iomem
*g
;
317 ngpio
= soc_info
->gpio_num
;
319 bank_irq
= soc_info
->gpio_irq
;
321 printk(KERN_ERR
"Don't know first GPIO bank IRQ.\n");
325 clk
= clk_get(NULL
, "gpio");
327 printk(KERN_ERR
"Error %ld getting gpio clock?\n",
333 /* Arrange gpio_to_irq() support, handling either direct IRQs or
334 * banked IRQs. Having GPIOs in the first GPIO bank use direct
335 * IRQs, while the others use banked IRQs, would need some setup
336 * tweaks to recognize hardware which can do that.
338 for (gpio
= 0, bank
= 0; gpio
< ngpio
; bank
++, gpio
+= 32) {
339 chips
[bank
].chip
.to_irq
= gpio_to_irq_banked
;
340 chips
[bank
].irq_base
= soc_info
->gpio_unbanked
342 : (soc_info
->intc_irq_num
+ gpio
);
346 * AINTC can handle direct/unbanked IRQs for GPIOs, with the GPIO
347 * controller only handling trigger modes. We currently assume no
348 * IRQ mux conflicts; gpio_irq_type_unbanked() is only for GPIOs.
350 if (soc_info
->gpio_unbanked
) {
351 static struct irq_chip gpio_irqchip_unbanked
;
353 /* pass "bank 0" GPIO IRQs to AINTC */
354 chips
[0].chip
.to_irq
= gpio_to_irq_unbanked
;
357 /* AINTC handles mask/unmask; GPIO handles triggering */
359 gpio_irqchip_unbanked
= *get_irq_desc_chip(irq_to_desc(irq
));
360 gpio_irqchip_unbanked
.name
= "GPIO-AINTC";
361 gpio_irqchip_unbanked
.set_type
= gpio_irq_type_unbanked
;
363 /* default trigger: both edges */
365 __raw_writel(~0, &g
->set_falling
);
366 __raw_writel(~0, &g
->set_rising
);
368 /* set the direct IRQs up to use that irqchip */
369 for (gpio
= 0; gpio
< soc_info
->gpio_unbanked
; gpio
++, irq
++) {
370 set_irq_chip(irq
, &gpio_irqchip_unbanked
);
371 set_irq_data(irq
, (void *) __gpio_mask(gpio
));
372 set_irq_chip_data(irq
, (__force
void *) g
);
373 irq_desc
[irq
].status
|= IRQ_TYPE_EDGE_BOTH
;
380 * Or, AINTC can handle IRQs for banks of 16 GPIO IRQs, which we
381 * then chain through our own handler.
383 for (gpio
= 0, irq
= gpio_to_irq(0), bank
= 0;
385 bank
++, bank_irq
++) {
388 /* disabled by default, enabled only as needed */
390 __raw_writel(~0, &g
->clr_falling
);
391 __raw_writel(~0, &g
->clr_rising
);
393 /* set up all irqs in this bank */
394 set_irq_chained_handler(bank_irq
, gpio_irq_handler
);
395 set_irq_chip_data(bank_irq
, (__force
void *) g
);
396 set_irq_data(bank_irq
, (void *) irq
);
398 for (i
= 0; i
< 16 && gpio
< ngpio
; i
++, irq
++, gpio
++) {
399 set_irq_chip(irq
, &gpio_irqchip
);
400 set_irq_chip_data(irq
, (__force
void *) g
);
401 set_irq_data(irq
, (void *) __gpio_mask(gpio
));
402 set_irq_handler(irq
, handle_simple_irq
);
403 set_irq_flags(irq
, IRQF_VALID
);
410 /* BINTEN -- per-bank interrupt enable. genirq would also let these
411 * bits be set/cleared dynamically.
413 __raw_writel(binten
, soc_info
->gpio_base
+ 0x08);
415 printk(KERN_INFO
"DaVinci: %d gpio irqs\n", irq
- gpio_to_irq(0));