2 * Copyright © 2006-2007 Intel Corporation
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License along with
14 * this program; if not, write to the Free Software Foundation, Inc.,
15 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 * Eric Anholt <eric@anholt.net>
21 #include <linux/i2c.h>
22 #include <linux/pm_runtime.h>
27 #include "psb_intel_drv.h"
28 #include "psb_intel_reg.h"
29 #include "psb_intel_display.h"
30 #include "psb_powermgmt.h"
33 struct psb_intel_clock_t
{
45 struct psb_intel_range_t
{
49 struct psb_intel_p2_t
{
54 #define INTEL_P2_NUM 2
56 struct psb_intel_limit_t
{
57 struct psb_intel_range_t dot
, vco
, n
, m
, m1
, m2
, p
, p1
;
58 struct psb_intel_p2_t p2
;
61 #define I8XX_DOT_MIN 25000
62 #define I8XX_DOT_MAX 350000
63 #define I8XX_VCO_MIN 930000
64 #define I8XX_VCO_MAX 1400000
68 #define I8XX_M_MAX 140
69 #define I8XX_M1_MIN 18
70 #define I8XX_M1_MAX 26
72 #define I8XX_M2_MAX 16
74 #define I8XX_P_MAX 128
76 #define I8XX_P1_MAX 33
77 #define I8XX_P1_LVDS_MIN 1
78 #define I8XX_P1_LVDS_MAX 6
79 #define I8XX_P2_SLOW 4
80 #define I8XX_P2_FAST 2
81 #define I8XX_P2_LVDS_SLOW 14
82 #define I8XX_P2_LVDS_FAST 14 /* No fast option */
83 #define I8XX_P2_SLOW_LIMIT 165000
85 #define I9XX_DOT_MIN 20000
86 #define I9XX_DOT_MAX 400000
87 #define I9XX_VCO_MIN 1400000
88 #define I9XX_VCO_MAX 2800000
92 #define I9XX_M_MAX 120
93 #define I9XX_M1_MIN 10
94 #define I9XX_M1_MAX 20
97 #define I9XX_P_SDVO_DAC_MIN 5
98 #define I9XX_P_SDVO_DAC_MAX 80
99 #define I9XX_P_LVDS_MIN 7
100 #define I9XX_P_LVDS_MAX 98
101 #define I9XX_P1_MIN 1
102 #define I9XX_P1_MAX 8
103 #define I9XX_P2_SDVO_DAC_SLOW 10
104 #define I9XX_P2_SDVO_DAC_FAST 5
105 #define I9XX_P2_SDVO_DAC_SLOW_LIMIT 200000
106 #define I9XX_P2_LVDS_SLOW 14
107 #define I9XX_P2_LVDS_FAST 7
108 #define I9XX_P2_LVDS_SLOW_LIMIT 112000
110 #define INTEL_LIMIT_I8XX_DVO_DAC 0
111 #define INTEL_LIMIT_I8XX_LVDS 1
112 #define INTEL_LIMIT_I9XX_SDVO_DAC 2
113 #define INTEL_LIMIT_I9XX_LVDS 3
115 static const struct psb_intel_limit_t psb_intel_limits
[] = {
116 { /* INTEL_LIMIT_I8XX_DVO_DAC */
117 .dot
= {.min
= I8XX_DOT_MIN
, .max
= I8XX_DOT_MAX
},
118 .vco
= {.min
= I8XX_VCO_MIN
, .max
= I8XX_VCO_MAX
},
119 .n
= {.min
= I8XX_N_MIN
, .max
= I8XX_N_MAX
},
120 .m
= {.min
= I8XX_M_MIN
, .max
= I8XX_M_MAX
},
121 .m1
= {.min
= I8XX_M1_MIN
, .max
= I8XX_M1_MAX
},
122 .m2
= {.min
= I8XX_M2_MIN
, .max
= I8XX_M2_MAX
},
123 .p
= {.min
= I8XX_P_MIN
, .max
= I8XX_P_MAX
},
124 .p1
= {.min
= I8XX_P1_MIN
, .max
= I8XX_P1_MAX
},
125 .p2
= {.dot_limit
= I8XX_P2_SLOW_LIMIT
,
126 .p2_slow
= I8XX_P2_SLOW
, .p2_fast
= I8XX_P2_FAST
},
128 { /* INTEL_LIMIT_I8XX_LVDS */
129 .dot
= {.min
= I8XX_DOT_MIN
, .max
= I8XX_DOT_MAX
},
130 .vco
= {.min
= I8XX_VCO_MIN
, .max
= I8XX_VCO_MAX
},
131 .n
= {.min
= I8XX_N_MIN
, .max
= I8XX_N_MAX
},
132 .m
= {.min
= I8XX_M_MIN
, .max
= I8XX_M_MAX
},
133 .m1
= {.min
= I8XX_M1_MIN
, .max
= I8XX_M1_MAX
},
134 .m2
= {.min
= I8XX_M2_MIN
, .max
= I8XX_M2_MAX
},
135 .p
= {.min
= I8XX_P_MIN
, .max
= I8XX_P_MAX
},
136 .p1
= {.min
= I8XX_P1_LVDS_MIN
, .max
= I8XX_P1_LVDS_MAX
},
137 .p2
= {.dot_limit
= I8XX_P2_SLOW_LIMIT
,
138 .p2_slow
= I8XX_P2_LVDS_SLOW
, .p2_fast
= I8XX_P2_LVDS_FAST
},
140 { /* INTEL_LIMIT_I9XX_SDVO_DAC */
141 .dot
= {.min
= I9XX_DOT_MIN
, .max
= I9XX_DOT_MAX
},
142 .vco
= {.min
= I9XX_VCO_MIN
, .max
= I9XX_VCO_MAX
},
143 .n
= {.min
= I9XX_N_MIN
, .max
= I9XX_N_MAX
},
144 .m
= {.min
= I9XX_M_MIN
, .max
= I9XX_M_MAX
},
145 .m1
= {.min
= I9XX_M1_MIN
, .max
= I9XX_M1_MAX
},
146 .m2
= {.min
= I9XX_M2_MIN
, .max
= I9XX_M2_MAX
},
147 .p
= {.min
= I9XX_P_SDVO_DAC_MIN
, .max
= I9XX_P_SDVO_DAC_MAX
},
148 .p1
= {.min
= I9XX_P1_MIN
, .max
= I9XX_P1_MAX
},
149 .p2
= {.dot_limit
= I9XX_P2_SDVO_DAC_SLOW_LIMIT
,
150 .p2_slow
= I9XX_P2_SDVO_DAC_SLOW
, .p2_fast
=
151 I9XX_P2_SDVO_DAC_FAST
},
153 { /* INTEL_LIMIT_I9XX_LVDS */
154 .dot
= {.min
= I9XX_DOT_MIN
, .max
= I9XX_DOT_MAX
},
155 .vco
= {.min
= I9XX_VCO_MIN
, .max
= I9XX_VCO_MAX
},
156 .n
= {.min
= I9XX_N_MIN
, .max
= I9XX_N_MAX
},
157 .m
= {.min
= I9XX_M_MIN
, .max
= I9XX_M_MAX
},
158 .m1
= {.min
= I9XX_M1_MIN
, .max
= I9XX_M1_MAX
},
159 .m2
= {.min
= I9XX_M2_MIN
, .max
= I9XX_M2_MAX
},
160 .p
= {.min
= I9XX_P_LVDS_MIN
, .max
= I9XX_P_LVDS_MAX
},
161 .p1
= {.min
= I9XX_P1_MIN
, .max
= I9XX_P1_MAX
},
162 /* The single-channel range is 25-112Mhz, and dual-channel
163 * is 80-224Mhz. Prefer single channel as much as possible.
165 .p2
= {.dot_limit
= I9XX_P2_LVDS_SLOW_LIMIT
,
166 .p2_slow
= I9XX_P2_LVDS_SLOW
, .p2_fast
= I9XX_P2_LVDS_FAST
},
170 static const struct psb_intel_limit_t
*psb_intel_limit(struct drm_crtc
*crtc
)
172 const struct psb_intel_limit_t
*limit
;
174 if (psb_intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
175 limit
= &psb_intel_limits
[INTEL_LIMIT_I9XX_LVDS
];
177 limit
= &psb_intel_limits
[INTEL_LIMIT_I9XX_SDVO_DAC
];
181 /** Derive the pixel clock for the given refclk and divisors for 8xx chips. */
183 static void i8xx_clock(int refclk
, struct psb_intel_clock_t
*clock
)
185 clock
->m
= 5 * (clock
->m1
+ 2) + (clock
->m2
+ 2);
186 clock
->p
= clock
->p1
* clock
->p2
;
187 clock
->vco
= refclk
* clock
->m
/ (clock
->n
+ 2);
188 clock
->dot
= clock
->vco
/ clock
->p
;
191 /** Derive the pixel clock for the given refclk and divisors for 9xx chips. */
193 static void i9xx_clock(int refclk
, struct psb_intel_clock_t
*clock
)
195 clock
->m
= 5 * (clock
->m1
+ 2) + (clock
->m2
+ 2);
196 clock
->p
= clock
->p1
* clock
->p2
;
197 clock
->vco
= refclk
* clock
->m
/ (clock
->n
+ 2);
198 clock
->dot
= clock
->vco
/ clock
->p
;
201 static void psb_intel_clock(struct drm_device
*dev
, int refclk
,
202 struct psb_intel_clock_t
*clock
)
204 return i9xx_clock(refclk
, clock
);
208 * Returns whether any output on the specified pipe is of the specified type
210 bool psb_intel_pipe_has_type(struct drm_crtc
*crtc
, int type
)
212 struct drm_device
*dev
= crtc
->dev
;
213 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
214 struct drm_connector
*l_entry
;
216 list_for_each_entry(l_entry
, &mode_config
->connector_list
, head
) {
217 if (l_entry
->encoder
&& l_entry
->encoder
->crtc
== crtc
) {
218 struct psb_intel_output
*psb_intel_output
=
219 to_psb_intel_output(l_entry
);
220 if (psb_intel_output
->type
== type
)
227 #define INTELPllInvalid(s) { /* ErrorF (s) */; return false; }
229 * Returns whether the given set of divisors are valid for a given refclk with
230 * the given connectors.
233 static bool psb_intel_PLL_is_valid(struct drm_crtc
*crtc
,
234 struct psb_intel_clock_t
*clock
)
236 const struct psb_intel_limit_t
*limit
= psb_intel_limit(crtc
);
238 if (clock
->p1
< limit
->p1
.min
|| limit
->p1
.max
< clock
->p1
)
239 INTELPllInvalid("p1 out of range\n");
240 if (clock
->p
< limit
->p
.min
|| limit
->p
.max
< clock
->p
)
241 INTELPllInvalid("p out of range\n");
242 if (clock
->m2
< limit
->m2
.min
|| limit
->m2
.max
< clock
->m2
)
243 INTELPllInvalid("m2 out of range\n");
244 if (clock
->m1
< limit
->m1
.min
|| limit
->m1
.max
< clock
->m1
)
245 INTELPllInvalid("m1 out of range\n");
246 if (clock
->m1
<= clock
->m2
)
247 INTELPllInvalid("m1 <= m2\n");
248 if (clock
->m
< limit
->m
.min
|| limit
->m
.max
< clock
->m
)
249 INTELPllInvalid("m out of range\n");
250 if (clock
->n
< limit
->n
.min
|| limit
->n
.max
< clock
->n
)
251 INTELPllInvalid("n out of range\n");
252 if (clock
->vco
< limit
->vco
.min
|| limit
->vco
.max
< clock
->vco
)
253 INTELPllInvalid("vco out of range\n");
254 /* XXX: We may need to be checking "Dot clock"
255 * depending on the multiplier, connector, etc.,
256 * rather than just a single range.
258 if (clock
->dot
< limit
->dot
.min
|| limit
->dot
.max
< clock
->dot
)
259 INTELPllInvalid("dot out of range\n");
265 * Returns a set of divisors for the desired target clock with the given
266 * refclk, or FALSE. The returned values represent the clock equation:
267 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
269 static bool psb_intel_find_best_PLL(struct drm_crtc
*crtc
, int target
,
271 struct psb_intel_clock_t
*best_clock
)
273 struct drm_device
*dev
= crtc
->dev
;
274 struct psb_intel_clock_t clock
;
275 const struct psb_intel_limit_t
*limit
= psb_intel_limit(crtc
);
278 if (psb_intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) &&
279 (REG_READ(LVDS
) & LVDS_PORT_EN
) != 0) {
281 * For LVDS, if the panel is on, just rely on its current
282 * settings for dual-channel. We haven't figured out how to
283 * reliably set up different single/dual channel state, if we
286 if ((REG_READ(LVDS
) & LVDS_CLKB_POWER_MASK
) ==
288 clock
.p2
= limit
->p2
.p2_fast
;
290 clock
.p2
= limit
->p2
.p2_slow
;
292 if (target
< limit
->p2
.dot_limit
)
293 clock
.p2
= limit
->p2
.p2_slow
;
295 clock
.p2
= limit
->p2
.p2_fast
;
298 memset(best_clock
, 0, sizeof(*best_clock
));
300 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
302 for (clock
.m2
= limit
->m2
.min
;
303 clock
.m2
< clock
.m1
&& clock
.m2
<= limit
->m2
.max
;
305 for (clock
.n
= limit
->n
.min
;
306 clock
.n
<= limit
->n
.max
; clock
.n
++) {
307 for (clock
.p1
= limit
->p1
.min
;
308 clock
.p1
<= limit
->p1
.max
;
312 psb_intel_clock(dev
, refclk
, &clock
);
314 if (!psb_intel_PLL_is_valid
318 this_err
= abs(clock
.dot
- target
);
319 if (this_err
< err
) {
328 return err
!= target
;
331 void psb_intel_wait_for_vblank(struct drm_device
*dev
)
333 /* Wait for 20ms, i.e. one cycle at 50hz. */
337 int psb_intel_pipe_set_base(struct drm_crtc
*crtc
,
338 int x
, int y
, struct drm_framebuffer
*old_fb
)
340 struct drm_device
*dev
= crtc
->dev
;
341 /* struct drm_i915_master_private *master_priv; */
342 struct psb_intel_crtc
*psb_intel_crtc
= to_psb_intel_crtc(crtc
);
343 struct psb_framebuffer
*psbfb
= to_psb_fb(crtc
->fb
);
344 int pipe
= psb_intel_crtc
->pipe
;
345 unsigned long start
, offset
;
346 int dspbase
= (pipe
== 0 ? DSPABASE
: DSPBBASE
);
347 int dspsurf
= (pipe
== 0 ? DSPASURF
: DSPBSURF
);
348 int dspstride
= (pipe
== 0) ? DSPASTRIDE
: DSPBSTRIDE
;
349 int dspcntr_reg
= (pipe
== 0) ? DSPACNTR
: DSPBCNTR
;
353 if (!gma_power_begin(dev
, true))
358 dev_dbg(dev
->dev
, "No FB bound\n");
359 goto psb_intel_pipe_cleaner
;
362 /* We are displaying this buffer, make sure it is actually loaded
364 ret
= psb_gtt_pin(psbfb
->gtt
);
366 goto psb_intel_pipe_set_base_exit
;
367 start
= psbfb
->gtt
->offset
;
369 offset
= y
* crtc
->fb
->pitch
+ x
* (crtc
->fb
->bits_per_pixel
/ 8);
371 REG_WRITE(dspstride
, crtc
->fb
->pitch
);
373 dspcntr
= REG_READ(dspcntr_reg
);
374 dspcntr
&= ~DISPPLANE_PIXFORMAT_MASK
;
376 switch (crtc
->fb
->bits_per_pixel
) {
378 dspcntr
|= DISPPLANE_8BPP
;
381 if (crtc
->fb
->depth
== 15)
382 dspcntr
|= DISPPLANE_15_16BPP
;
384 dspcntr
|= DISPPLANE_16BPP
;
388 dspcntr
|= DISPPLANE_32BPP_NO_ALPHA
;
391 dev_err(dev
->dev
, "Unknown color depth\n");
393 psb_gtt_unpin(psbfb
->gtt
);
394 goto psb_intel_pipe_set_base_exit
;
396 REG_WRITE(dspcntr_reg
, dspcntr
);
399 if (0 /* FIXMEAC - check what PSB needs */) {
400 REG_WRITE(dspbase
, offset
);
402 REG_WRITE(dspsurf
, start
);
405 REG_WRITE(dspbase
, start
+ offset
);
409 psb_intel_pipe_cleaner
:
410 /* If there was a previous display we can now unpin it */
412 psb_gtt_unpin(to_psb_fb(old_fb
)->gtt
);
414 psb_intel_pipe_set_base_exit
:
420 * Sets the power management mode of the pipe and plane.
422 * This code should probably grow support for turning the cursor off and back
423 * on appropriately at the same time as we're turning the pipe off/on.
425 static void psb_intel_crtc_dpms(struct drm_crtc
*crtc
, int mode
)
427 struct drm_device
*dev
= crtc
->dev
;
428 /* struct drm_i915_master_private *master_priv; */
429 /* struct drm_i915_private *dev_priv = dev->dev_private; */
430 struct psb_intel_crtc
*psb_intel_crtc
= to_psb_intel_crtc(crtc
);
431 int pipe
= psb_intel_crtc
->pipe
;
432 int dpll_reg
= (pipe
== 0) ? DPLL_A
: DPLL_B
;
433 int dspcntr_reg
= (pipe
== 0) ? DSPACNTR
: DSPBCNTR
;
434 int dspbase_reg
= (pipe
== 0) ? DSPABASE
: DSPBBASE
;
435 int pipeconf_reg
= (pipe
== 0) ? PIPEACONF
: PIPEBCONF
;
439 /* XXX: When our outputs are all unaware of DPMS modes other than off
440 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
443 case DRM_MODE_DPMS_ON
:
444 case DRM_MODE_DPMS_STANDBY
:
445 case DRM_MODE_DPMS_SUSPEND
:
446 /* Enable the DPLL */
447 temp
= REG_READ(dpll_reg
);
448 if ((temp
& DPLL_VCO_ENABLE
) == 0) {
449 REG_WRITE(dpll_reg
, temp
);
451 /* Wait for the clocks to stabilize. */
453 REG_WRITE(dpll_reg
, temp
| DPLL_VCO_ENABLE
);
455 /* Wait for the clocks to stabilize. */
457 REG_WRITE(dpll_reg
, temp
| DPLL_VCO_ENABLE
);
459 /* Wait for the clocks to stabilize. */
463 /* Enable the pipe */
464 temp
= REG_READ(pipeconf_reg
);
465 if ((temp
& PIPEACONF_ENABLE
) == 0)
466 REG_WRITE(pipeconf_reg
, temp
| PIPEACONF_ENABLE
);
468 /* Enable the plane */
469 temp
= REG_READ(dspcntr_reg
);
470 if ((temp
& DISPLAY_PLANE_ENABLE
) == 0) {
471 REG_WRITE(dspcntr_reg
,
472 temp
| DISPLAY_PLANE_ENABLE
);
473 /* Flush the plane changes */
474 REG_WRITE(dspbase_reg
, REG_READ(dspbase_reg
));
477 psb_intel_crtc_load_lut(crtc
);
479 /* Give the overlay scaler a chance to enable
480 * if it's on this pipe */
481 /* psb_intel_crtc_dpms_video(crtc, true); TODO */
483 case DRM_MODE_DPMS_OFF
:
484 /* Give the overlay scaler a chance to disable
485 * if it's on this pipe */
486 /* psb_intel_crtc_dpms_video(crtc, FALSE); TODO */
488 /* Disable the VGA plane that we never use */
489 REG_WRITE(VGACNTRL
, VGA_DISP_DISABLE
);
491 /* Disable display plane */
492 temp
= REG_READ(dspcntr_reg
);
493 if ((temp
& DISPLAY_PLANE_ENABLE
) != 0) {
494 REG_WRITE(dspcntr_reg
,
495 temp
& ~DISPLAY_PLANE_ENABLE
);
496 /* Flush the plane changes */
497 REG_WRITE(dspbase_reg
, REG_READ(dspbase_reg
));
498 REG_READ(dspbase_reg
);
501 /* Next, disable display pipes */
502 temp
= REG_READ(pipeconf_reg
);
503 if ((temp
& PIPEACONF_ENABLE
) != 0) {
504 REG_WRITE(pipeconf_reg
, temp
& ~PIPEACONF_ENABLE
);
505 REG_READ(pipeconf_reg
);
508 /* Wait for vblank for the disable to take effect. */
509 psb_intel_wait_for_vblank(dev
);
511 temp
= REG_READ(dpll_reg
);
512 if ((temp
& DPLL_VCO_ENABLE
) != 0) {
513 REG_WRITE(dpll_reg
, temp
& ~DPLL_VCO_ENABLE
);
517 /* Wait for the clocks to turn off. */
522 enabled
= crtc
->enabled
&& mode
!= DRM_MODE_DPMS_OFF
;
524 /*Set FIFO Watermarks*/
525 REG_WRITE(DSPARB
, 0x3F3E);
528 static void psb_intel_crtc_prepare(struct drm_crtc
*crtc
)
530 struct drm_crtc_helper_funcs
*crtc_funcs
= crtc
->helper_private
;
531 crtc_funcs
->dpms(crtc
, DRM_MODE_DPMS_OFF
);
534 static void psb_intel_crtc_commit(struct drm_crtc
*crtc
)
536 struct drm_crtc_helper_funcs
*crtc_funcs
= crtc
->helper_private
;
537 crtc_funcs
->dpms(crtc
, DRM_MODE_DPMS_ON
);
540 void psb_intel_encoder_prepare(struct drm_encoder
*encoder
)
542 struct drm_encoder_helper_funcs
*encoder_funcs
=
543 encoder
->helper_private
;
544 /* lvds has its own version of prepare see psb_intel_lvds_prepare */
545 encoder_funcs
->dpms(encoder
, DRM_MODE_DPMS_OFF
);
548 void psb_intel_encoder_commit(struct drm_encoder
*encoder
)
550 struct drm_encoder_helper_funcs
*encoder_funcs
=
551 encoder
->helper_private
;
552 /* lvds has its own version of commit see psb_intel_lvds_commit */
553 encoder_funcs
->dpms(encoder
, DRM_MODE_DPMS_ON
);
556 static bool psb_intel_crtc_mode_fixup(struct drm_crtc
*crtc
,
557 struct drm_display_mode
*mode
,
558 struct drm_display_mode
*adjusted_mode
)
565 * Return the pipe currently connected to the panel fitter,
566 * or -1 if the panel fitter is not present or not in use
568 static int psb_intel_panel_fitter_pipe(struct drm_device
*dev
)
572 pfit_control
= REG_READ(PFIT_CONTROL
);
574 /* See if the panel fitter is in use */
575 if ((pfit_control
& PFIT_ENABLE
) == 0)
577 /* Must be on PIPE 1 for PSB */
581 static int psb_intel_crtc_mode_set(struct drm_crtc
*crtc
,
582 struct drm_display_mode
*mode
,
583 struct drm_display_mode
*adjusted_mode
,
585 struct drm_framebuffer
*old_fb
)
587 struct drm_device
*dev
= crtc
->dev
;
588 struct psb_intel_crtc
*psb_intel_crtc
= to_psb_intel_crtc(crtc
);
589 struct drm_crtc_helper_funcs
*crtc_funcs
= crtc
->helper_private
;
590 int pipe
= psb_intel_crtc
->pipe
;
591 int fp_reg
= (pipe
== 0) ? FPA0
: FPB0
;
592 int dpll_reg
= (pipe
== 0) ? DPLL_A
: DPLL_B
;
593 int dspcntr_reg
= (pipe
== 0) ? DSPACNTR
: DSPBCNTR
;
594 int pipeconf_reg
= (pipe
== 0) ? PIPEACONF
: PIPEBCONF
;
595 int htot_reg
= (pipe
== 0) ? HTOTAL_A
: HTOTAL_B
;
596 int hblank_reg
= (pipe
== 0) ? HBLANK_A
: HBLANK_B
;
597 int hsync_reg
= (pipe
== 0) ? HSYNC_A
: HSYNC_B
;
598 int vtot_reg
= (pipe
== 0) ? VTOTAL_A
: VTOTAL_B
;
599 int vblank_reg
= (pipe
== 0) ? VBLANK_A
: VBLANK_B
;
600 int vsync_reg
= (pipe
== 0) ? VSYNC_A
: VSYNC_B
;
601 int dspsize_reg
= (pipe
== 0) ? DSPASIZE
: DSPBSIZE
;
602 int dsppos_reg
= (pipe
== 0) ? DSPAPOS
: DSPBPOS
;
603 int pipesrc_reg
= (pipe
== 0) ? PIPEASRC
: PIPEBSRC
;
605 struct psb_intel_clock_t clock
;
606 u32 dpll
= 0, fp
= 0, dspcntr
, pipeconf
;
607 bool ok
, is_sdvo
= false, is_dvo
= false;
608 bool is_crt
= false, is_lvds
= false, is_tv
= false;
609 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
610 struct drm_connector
*connector
;
612 /* No scan out no play */
613 if (crtc
->fb
== NULL
) {
614 crtc_funcs
->mode_set_base(crtc
, x
, y
, old_fb
);
618 list_for_each_entry(connector
, &mode_config
->connector_list
, head
) {
619 struct psb_intel_output
*psb_intel_output
=
620 to_psb_intel_output(connector
);
622 if (!connector
->encoder
623 || connector
->encoder
->crtc
!= crtc
)
626 switch (psb_intel_output
->type
) {
627 case INTEL_OUTPUT_LVDS
:
630 case INTEL_OUTPUT_SDVO
:
633 case INTEL_OUTPUT_DVO
:
636 case INTEL_OUTPUT_TVOUT
:
639 case INTEL_OUTPUT_ANALOG
:
647 ok
= psb_intel_find_best_PLL(crtc
, adjusted_mode
->clock
, refclk
,
650 dev_err(dev
->dev
, "Couldn't find PLL settings for mode!\n");
654 fp
= clock
.n
<< 16 | clock
.m1
<< 8 | clock
.m2
;
656 dpll
= DPLL_VGA_MODE_DIS
;
658 dpll
|= DPLLB_MODE_LVDS
;
659 dpll
|= DPLL_DVO_HIGH_SPEED
;
661 dpll
|= DPLLB_MODE_DAC_SERIAL
;
663 int sdvo_pixel_multiply
=
664 adjusted_mode
->clock
/ mode
->clock
;
665 dpll
|= DPLL_DVO_HIGH_SPEED
;
667 (sdvo_pixel_multiply
- 1) << SDVO_MULTIPLIER_SHIFT_HIRES
;
670 /* compute bitmask from p1 value */
671 dpll
|= (1 << (clock
.p1
- 1)) << 16;
674 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
677 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
680 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
683 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
688 /* XXX: just matching BIOS for now */
689 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
692 dpll
|= PLL_REF_INPUT_DREFCLK
;
695 pipeconf
= REG_READ(pipeconf_reg
);
697 /* Set up the display plane register */
698 dspcntr
= DISPPLANE_GAMMA_ENABLE
;
701 dspcntr
|= DISPPLANE_SEL_PIPE_A
;
703 dspcntr
|= DISPPLANE_SEL_PIPE_B
;
705 dspcntr
|= DISPLAY_PLANE_ENABLE
;
706 pipeconf
|= PIPEACONF_ENABLE
;
707 dpll
|= DPLL_VCO_ENABLE
;
710 /* Disable the panel fitter if it was on our pipe */
711 if (psb_intel_panel_fitter_pipe(dev
) == pipe
)
712 REG_WRITE(PFIT_CONTROL
, 0);
714 drm_mode_debug_printmodeline(mode
);
716 if (dpll
& DPLL_VCO_ENABLE
) {
717 REG_WRITE(fp_reg
, fp
);
718 REG_WRITE(dpll_reg
, dpll
& ~DPLL_VCO_ENABLE
);
723 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
724 * This is an exception to the general rule that mode_set doesn't turn
728 u32 lvds
= REG_READ(LVDS
);
730 lvds
&= ~LVDS_PIPEB_SELECT
;
732 lvds
|= LVDS_PIPEB_SELECT
;
734 lvds
|= LVDS_PORT_EN
| LVDS_A0A2_CLKA_POWER_UP
;
735 /* Set the B0-B3 data pairs corresponding to
736 * whether we're going to
737 * set the DPLLs for dual-channel mode or not.
739 lvds
&= ~(LVDS_B0B3_POWER_UP
| LVDS_CLKB_POWER_UP
);
741 lvds
|= LVDS_B0B3_POWER_UP
| LVDS_CLKB_POWER_UP
;
743 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
744 * appropriately here, but we need to look more
745 * thoroughly into how panels behave in the two modes.
748 REG_WRITE(LVDS
, lvds
);
752 REG_WRITE(fp_reg
, fp
);
753 REG_WRITE(dpll_reg
, dpll
);
755 /* Wait for the clocks to stabilize. */
758 /* write it again -- the BIOS does, after all */
759 REG_WRITE(dpll_reg
, dpll
);
762 /* Wait for the clocks to stabilize. */
765 REG_WRITE(htot_reg
, (adjusted_mode
->crtc_hdisplay
- 1) |
766 ((adjusted_mode
->crtc_htotal
- 1) << 16));
767 REG_WRITE(hblank_reg
, (adjusted_mode
->crtc_hblank_start
- 1) |
768 ((adjusted_mode
->crtc_hblank_end
- 1) << 16));
769 REG_WRITE(hsync_reg
, (adjusted_mode
->crtc_hsync_start
- 1) |
770 ((adjusted_mode
->crtc_hsync_end
- 1) << 16));
771 REG_WRITE(vtot_reg
, (adjusted_mode
->crtc_vdisplay
- 1) |
772 ((adjusted_mode
->crtc_vtotal
- 1) << 16));
773 REG_WRITE(vblank_reg
, (adjusted_mode
->crtc_vblank_start
- 1) |
774 ((adjusted_mode
->crtc_vblank_end
- 1) << 16));
775 REG_WRITE(vsync_reg
, (adjusted_mode
->crtc_vsync_start
- 1) |
776 ((adjusted_mode
->crtc_vsync_end
- 1) << 16));
777 /* pipesrc and dspsize control the size that is scaled from,
778 * which should always be the user's requested size.
780 REG_WRITE(dspsize_reg
,
781 ((mode
->vdisplay
- 1) << 16) | (mode
->hdisplay
- 1));
782 REG_WRITE(dsppos_reg
, 0);
783 REG_WRITE(pipesrc_reg
,
784 ((mode
->hdisplay
- 1) << 16) | (mode
->vdisplay
- 1));
785 REG_WRITE(pipeconf_reg
, pipeconf
);
786 REG_READ(pipeconf_reg
);
788 psb_intel_wait_for_vblank(dev
);
790 REG_WRITE(dspcntr_reg
, dspcntr
);
792 /* Flush the plane changes */
793 crtc_funcs
->mode_set_base(crtc
, x
, y
, old_fb
);
795 psb_intel_wait_for_vblank(dev
);
800 /** Loads the palette/gamma unit for the CRTC with the prepared values */
801 void psb_intel_crtc_load_lut(struct drm_crtc
*crtc
)
803 struct drm_device
*dev
= crtc
->dev
;
804 struct drm_psb_private
*dev_priv
=
805 (struct drm_psb_private
*)dev
->dev_private
;
806 struct psb_intel_crtc
*psb_intel_crtc
= to_psb_intel_crtc(crtc
);
807 int palreg
= PALETTE_A
;
810 /* The clocks have to be on to load the palette. */
814 switch (psb_intel_crtc
->pipe
) {
824 dev_err(dev
->dev
, "Illegal Pipe Number.\n");
828 if (gma_power_begin(dev
, false)) {
829 for (i
= 0; i
< 256; i
++) {
830 REG_WRITE(palreg
+ 4 * i
,
831 ((psb_intel_crtc
->lut_r
[i
] +
832 psb_intel_crtc
->lut_adj
[i
]) << 16) |
833 ((psb_intel_crtc
->lut_g
[i
] +
834 psb_intel_crtc
->lut_adj
[i
]) << 8) |
835 (psb_intel_crtc
->lut_b
[i
] +
836 psb_intel_crtc
->lut_adj
[i
]));
840 for (i
= 0; i
< 256; i
++) {
841 dev_priv
->save_palette_a
[i
] =
842 ((psb_intel_crtc
->lut_r
[i
] +
843 psb_intel_crtc
->lut_adj
[i
]) << 16) |
844 ((psb_intel_crtc
->lut_g
[i
] +
845 psb_intel_crtc
->lut_adj
[i
]) << 8) |
846 (psb_intel_crtc
->lut_b
[i
] +
847 psb_intel_crtc
->lut_adj
[i
]);
854 * Save HW states of giving crtc
856 static void psb_intel_crtc_save(struct drm_crtc
*crtc
)
858 struct drm_device
*dev
= crtc
->dev
;
859 /* struct drm_psb_private *dev_priv =
860 (struct drm_psb_private *)dev->dev_private; */
861 struct psb_intel_crtc
*psb_intel_crtc
= to_psb_intel_crtc(crtc
);
862 struct psb_intel_crtc_state
*crtc_state
= psb_intel_crtc
->crtc_state
;
863 int pipeA
= (psb_intel_crtc
->pipe
== 0);
868 dev_err(dev
->dev
, "No CRTC state found\n");
872 crtc_state
->saveDSPCNTR
= REG_READ(pipeA
? DSPACNTR
: DSPBCNTR
);
873 crtc_state
->savePIPECONF
= REG_READ(pipeA
? PIPEACONF
: PIPEBCONF
);
874 crtc_state
->savePIPESRC
= REG_READ(pipeA
? PIPEASRC
: PIPEBSRC
);
875 crtc_state
->saveFP0
= REG_READ(pipeA
? FPA0
: FPB0
);
876 crtc_state
->saveFP1
= REG_READ(pipeA
? FPA1
: FPB1
);
877 crtc_state
->saveDPLL
= REG_READ(pipeA
? DPLL_A
: DPLL_B
);
878 crtc_state
->saveHTOTAL
= REG_READ(pipeA
? HTOTAL_A
: HTOTAL_B
);
879 crtc_state
->saveHBLANK
= REG_READ(pipeA
? HBLANK_A
: HBLANK_B
);
880 crtc_state
->saveHSYNC
= REG_READ(pipeA
? HSYNC_A
: HSYNC_B
);
881 crtc_state
->saveVTOTAL
= REG_READ(pipeA
? VTOTAL_A
: VTOTAL_B
);
882 crtc_state
->saveVBLANK
= REG_READ(pipeA
? VBLANK_A
: VBLANK_B
);
883 crtc_state
->saveVSYNC
= REG_READ(pipeA
? VSYNC_A
: VSYNC_B
);
884 crtc_state
->saveDSPSTRIDE
= REG_READ(pipeA
? DSPASTRIDE
: DSPBSTRIDE
);
886 /*NOTE: DSPSIZE DSPPOS only for psb*/
887 crtc_state
->saveDSPSIZE
= REG_READ(pipeA
? DSPASIZE
: DSPBSIZE
);
888 crtc_state
->saveDSPPOS
= REG_READ(pipeA
? DSPAPOS
: DSPBPOS
);
890 crtc_state
->saveDSPBASE
= REG_READ(pipeA
? DSPABASE
: DSPBBASE
);
892 paletteReg
= pipeA
? PALETTE_A
: PALETTE_B
;
893 for (i
= 0; i
< 256; ++i
)
894 crtc_state
->savePalette
[i
] = REG_READ(paletteReg
+ (i
<< 2));
898 * Restore HW states of giving crtc
900 static void psb_intel_crtc_restore(struct drm_crtc
*crtc
)
902 struct drm_device
*dev
= crtc
->dev
;
903 /* struct drm_psb_private * dev_priv =
904 (struct drm_psb_private *)dev->dev_private; */
905 struct psb_intel_crtc
*psb_intel_crtc
= to_psb_intel_crtc(crtc
);
906 struct psb_intel_crtc_state
*crtc_state
= psb_intel_crtc
->crtc_state
;
907 /* struct drm_crtc_helper_funcs * crtc_funcs = crtc->helper_private; */
908 int pipeA
= (psb_intel_crtc
->pipe
== 0);
913 dev_err(dev
->dev
, "No crtc state\n");
917 if (crtc_state
->saveDPLL
& DPLL_VCO_ENABLE
) {
918 REG_WRITE(pipeA
? DPLL_A
: DPLL_B
,
919 crtc_state
->saveDPLL
& ~DPLL_VCO_ENABLE
);
920 REG_READ(pipeA
? DPLL_A
: DPLL_B
);
924 REG_WRITE(pipeA
? FPA0
: FPB0
, crtc_state
->saveFP0
);
925 REG_READ(pipeA
? FPA0
: FPB0
);
927 REG_WRITE(pipeA
? FPA1
: FPB1
, crtc_state
->saveFP1
);
928 REG_READ(pipeA
? FPA1
: FPB1
);
930 REG_WRITE(pipeA
? DPLL_A
: DPLL_B
, crtc_state
->saveDPLL
);
931 REG_READ(pipeA
? DPLL_A
: DPLL_B
);
934 REG_WRITE(pipeA
? HTOTAL_A
: HTOTAL_B
, crtc_state
->saveHTOTAL
);
935 REG_WRITE(pipeA
? HBLANK_A
: HBLANK_B
, crtc_state
->saveHBLANK
);
936 REG_WRITE(pipeA
? HSYNC_A
: HSYNC_B
, crtc_state
->saveHSYNC
);
937 REG_WRITE(pipeA
? VTOTAL_A
: VTOTAL_B
, crtc_state
->saveVTOTAL
);
938 REG_WRITE(pipeA
? VBLANK_A
: VBLANK_B
, crtc_state
->saveVBLANK
);
939 REG_WRITE(pipeA
? VSYNC_A
: VSYNC_B
, crtc_state
->saveVSYNC
);
940 REG_WRITE(pipeA
? DSPASTRIDE
: DSPBSTRIDE
, crtc_state
->saveDSPSTRIDE
);
942 REG_WRITE(pipeA
? DSPASIZE
: DSPBSIZE
, crtc_state
->saveDSPSIZE
);
943 REG_WRITE(pipeA
? DSPAPOS
: DSPBPOS
, crtc_state
->saveDSPPOS
);
945 REG_WRITE(pipeA
? PIPEASRC
: PIPEBSRC
, crtc_state
->savePIPESRC
);
946 REG_WRITE(pipeA
? DSPABASE
: DSPBBASE
, crtc_state
->saveDSPBASE
);
947 REG_WRITE(pipeA
? PIPEACONF
: PIPEBCONF
, crtc_state
->savePIPECONF
);
949 psb_intel_wait_for_vblank(dev
);
951 REG_WRITE(pipeA
? DSPACNTR
: DSPBCNTR
, crtc_state
->saveDSPCNTR
);
952 REG_WRITE(pipeA
? DSPABASE
: DSPBBASE
, crtc_state
->saveDSPBASE
);
954 psb_intel_wait_for_vblank(dev
);
956 paletteReg
= pipeA
? PALETTE_A
: PALETTE_B
;
957 for (i
= 0; i
< 256; ++i
)
958 REG_WRITE(paletteReg
+ (i
<< 2), crtc_state
->savePalette
[i
]);
961 static int psb_intel_crtc_cursor_set(struct drm_crtc
*crtc
,
962 struct drm_file
*file_priv
,
964 uint32_t width
, uint32_t height
)
966 struct drm_device
*dev
= crtc
->dev
;
967 struct psb_intel_crtc
*psb_intel_crtc
= to_psb_intel_crtc(crtc
);
968 int pipe
= psb_intel_crtc
->pipe
;
969 uint32_t control
= (pipe
== 0) ? CURACNTR
: CURBCNTR
;
970 uint32_t base
= (pipe
== 0) ? CURABASE
: CURBBASE
;
973 struct gtt_range
*gt
;
974 struct drm_gem_object
*obj
;
977 /* if we want to turn of the cursor ignore width and height */
979 /* turn off the cursor */
980 temp
= CURSOR_MODE_DISABLE
;
982 if (gma_power_begin(dev
, false)) {
983 REG_WRITE(control
, temp
);
988 /* Unpin the old GEM object */
989 if (psb_intel_crtc
->cursor_obj
) {
990 gt
= container_of(psb_intel_crtc
->cursor_obj
,
991 struct gtt_range
, gem
);
993 drm_gem_object_unreference(psb_intel_crtc
->cursor_obj
);
994 psb_intel_crtc
->cursor_obj
= NULL
;
1000 /* Currently we only support 64x64 cursors */
1001 if (width
!= 64 || height
!= 64) {
1002 dev_dbg(dev
->dev
, "we currently only support 64x64 cursors\n");
1006 obj
= drm_gem_object_lookup(dev
, file_priv
, handle
);
1010 if (obj
->size
< width
* height
* 4) {
1011 dev_dbg(dev
->dev
, "buffer is to small\n");
1015 gt
= container_of(obj
, struct gtt_range
, gem
);
1017 /* Pin the memory into the GTT */
1018 ret
= psb_gtt_pin(gt
);
1020 dev_err(dev
->dev
, "Can not pin down handle 0x%x\n", handle
);
1025 addr
= gt
->offset
; /* Or resource.start ??? */
1027 psb_intel_crtc
->cursor_addr
= addr
;
1030 /* set the pipe for the cursor */
1031 temp
|= (pipe
<< 28);
1032 temp
|= CURSOR_MODE_64_ARGB_AX
| MCURSOR_GAMMA_ENABLE
;
1034 if (gma_power_begin(dev
, false)) {
1035 REG_WRITE(control
, temp
);
1036 REG_WRITE(base
, addr
);
1040 /* unpin the old bo */
1041 if (psb_intel_crtc
->cursor_obj
&& psb_intel_crtc
->cursor_obj
!= obj
) {
1042 gt
= container_of(psb_intel_crtc
->cursor_obj
,
1043 struct gtt_range
, gem
);
1045 drm_gem_object_unreference(psb_intel_crtc
->cursor_obj
);
1046 psb_intel_crtc
->cursor_obj
= obj
;
1052 static int psb_intel_crtc_cursor_move(struct drm_crtc
*crtc
, int x
, int y
)
1054 struct drm_device
*dev
= crtc
->dev
;
1055 struct psb_intel_crtc
*psb_intel_crtc
= to_psb_intel_crtc(crtc
);
1056 int pipe
= psb_intel_crtc
->pipe
;
1062 temp
|= (CURSOR_POS_SIGN
<< CURSOR_X_SHIFT
);
1066 temp
|= (CURSOR_POS_SIGN
<< CURSOR_Y_SHIFT
);
1070 temp
|= ((x
& CURSOR_POS_MASK
) << CURSOR_X_SHIFT
);
1071 temp
|= ((y
& CURSOR_POS_MASK
) << CURSOR_Y_SHIFT
);
1073 addr
= psb_intel_crtc
->cursor_addr
;
1075 if (gma_power_begin(dev
, false)) {
1076 REG_WRITE((pipe
== 0) ? CURAPOS
: CURBPOS
, temp
);
1077 REG_WRITE((pipe
== 0) ? CURABASE
: CURBBASE
, addr
);
1083 static void psb_intel_crtc_gamma_set(struct drm_crtc
*crtc
, u16
*red
,
1084 u16
*green
, u16
*blue
, uint32_t type
, uint32_t size
)
1086 struct psb_intel_crtc
*psb_intel_crtc
= to_psb_intel_crtc(crtc
);
1092 for (i
= 0; i
< 256; i
++) {
1093 psb_intel_crtc
->lut_r
[i
] = red
[i
] >> 8;
1094 psb_intel_crtc
->lut_g
[i
] = green
[i
] >> 8;
1095 psb_intel_crtc
->lut_b
[i
] = blue
[i
] >> 8;
1098 psb_intel_crtc_load_lut(crtc
);
1101 static int psb_crtc_set_config(struct drm_mode_set
*set
)
1104 struct drm_device
*dev
= set
->crtc
->dev
;
1105 struct drm_psb_private
*dev_priv
= dev
->dev_private
;
1107 if (!dev_priv
->rpm_enabled
)
1108 return drm_crtc_helper_set_config(set
);
1110 pm_runtime_forbid(&dev
->pdev
->dev
);
1111 ret
= drm_crtc_helper_set_config(set
);
1112 pm_runtime_allow(&dev
->pdev
->dev
);
1116 /* Returns the clock of the currently programmed mode of the given pipe. */
1117 static int psb_intel_crtc_clock_get(struct drm_device
*dev
,
1118 struct drm_crtc
*crtc
)
1120 struct psb_intel_crtc
*psb_intel_crtc
= to_psb_intel_crtc(crtc
);
1121 int pipe
= psb_intel_crtc
->pipe
;
1124 struct psb_intel_clock_t clock
;
1126 struct drm_psb_private
*dev_priv
= dev
->dev_private
;
1128 if (gma_power_begin(dev
, false)) {
1129 dpll
= REG_READ((pipe
== 0) ? DPLL_A
: DPLL_B
);
1130 if ((dpll
& DISPLAY_RATE_SELECT_FPA1
) == 0)
1131 fp
= REG_READ((pipe
== 0) ? FPA0
: FPB0
);
1133 fp
= REG_READ((pipe
== 0) ? FPA1
: FPB1
);
1134 is_lvds
= (pipe
== 1) && (REG_READ(LVDS
) & LVDS_PORT_EN
);
1137 dpll
= (pipe
== 0) ?
1138 dev_priv
->saveDPLL_A
: dev_priv
->saveDPLL_B
;
1140 if ((dpll
& DISPLAY_RATE_SELECT_FPA1
) == 0)
1142 dev_priv
->saveFPA0
:
1146 dev_priv
->saveFPA1
:
1149 is_lvds
= (pipe
== 1) && (dev_priv
->saveLVDS
& LVDS_PORT_EN
);
1152 clock
.m1
= (fp
& FP_M1_DIV_MASK
) >> FP_M1_DIV_SHIFT
;
1153 clock
.m2
= (fp
& FP_M2_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
1154 clock
.n
= (fp
& FP_N_DIV_MASK
) >> FP_N_DIV_SHIFT
;
1159 DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS
) >>
1160 DPLL_FPA01_P1_POST_DIV_SHIFT
);
1163 if ((dpll
& PLL_REF_INPUT_MASK
) ==
1164 PLLB_REF_INPUT_SPREADSPECTRUMIN
) {
1165 /* XXX: might not be 66MHz */
1166 i8xx_clock(66000, &clock
);
1168 i8xx_clock(48000, &clock
);
1170 if (dpll
& PLL_P1_DIVIDE_BY_TWO
)
1175 DPLL_FPA01_P1_POST_DIV_MASK_I830
) >>
1176 DPLL_FPA01_P1_POST_DIV_SHIFT
) + 2;
1178 if (dpll
& PLL_P2_DIVIDE_BY_4
)
1183 i8xx_clock(48000, &clock
);
1186 /* XXX: It would be nice to validate the clocks, but we can't reuse
1187 * i830PllIsValid() because it relies on the xf86_config connector
1188 * configuration being accurate, which it isn't necessarily.
1194 /** Returns the currently programmed mode of the given pipe. */
1195 struct drm_display_mode
*psb_intel_crtc_mode_get(struct drm_device
*dev
,
1196 struct drm_crtc
*crtc
)
1198 struct psb_intel_crtc
*psb_intel_crtc
= to_psb_intel_crtc(crtc
);
1199 int pipe
= psb_intel_crtc
->pipe
;
1200 struct drm_display_mode
*mode
;
1205 struct drm_psb_private
*dev_priv
= dev
->dev_private
;
1207 if (gma_power_begin(dev
, false)) {
1208 htot
= REG_READ((pipe
== 0) ? HTOTAL_A
: HTOTAL_B
);
1209 hsync
= REG_READ((pipe
== 0) ? HSYNC_A
: HSYNC_B
);
1210 vtot
= REG_READ((pipe
== 0) ? VTOTAL_A
: VTOTAL_B
);
1211 vsync
= REG_READ((pipe
== 0) ? VSYNC_A
: VSYNC_B
);
1214 htot
= (pipe
== 0) ?
1215 dev_priv
->saveHTOTAL_A
: dev_priv
->saveHTOTAL_B
;
1216 hsync
= (pipe
== 0) ?
1217 dev_priv
->saveHSYNC_A
: dev_priv
->saveHSYNC_B
;
1218 vtot
= (pipe
== 0) ?
1219 dev_priv
->saveVTOTAL_A
: dev_priv
->saveVTOTAL_B
;
1220 vsync
= (pipe
== 0) ?
1221 dev_priv
->saveVSYNC_A
: dev_priv
->saveVSYNC_B
;
1224 mode
= kzalloc(sizeof(*mode
), GFP_KERNEL
);
1228 mode
->clock
= psb_intel_crtc_clock_get(dev
, crtc
);
1229 mode
->hdisplay
= (htot
& 0xffff) + 1;
1230 mode
->htotal
= ((htot
& 0xffff0000) >> 16) + 1;
1231 mode
->hsync_start
= (hsync
& 0xffff) + 1;
1232 mode
->hsync_end
= ((hsync
& 0xffff0000) >> 16) + 1;
1233 mode
->vdisplay
= (vtot
& 0xffff) + 1;
1234 mode
->vtotal
= ((vtot
& 0xffff0000) >> 16) + 1;
1235 mode
->vsync_start
= (vsync
& 0xffff) + 1;
1236 mode
->vsync_end
= ((vsync
& 0xffff0000) >> 16) + 1;
1238 drm_mode_set_name(mode
);
1239 drm_mode_set_crtcinfo(mode
, 0);
1244 static void psb_intel_crtc_destroy(struct drm_crtc
*crtc
)
1246 struct psb_intel_crtc
*psb_intel_crtc
= to_psb_intel_crtc(crtc
);
1247 struct gtt_range
*gt
;
1249 /* Unpin the old GEM object */
1250 if (psb_intel_crtc
->cursor_obj
) {
1251 gt
= container_of(psb_intel_crtc
->cursor_obj
,
1252 struct gtt_range
, gem
);
1254 drm_gem_object_unreference(psb_intel_crtc
->cursor_obj
);
1255 psb_intel_crtc
->cursor_obj
= NULL
;
1257 kfree(psb_intel_crtc
->crtc_state
);
1258 drm_crtc_cleanup(crtc
);
1259 kfree(psb_intel_crtc
);
1262 static const struct drm_crtc_helper_funcs psb_intel_helper_funcs
= {
1263 .dpms
= psb_intel_crtc_dpms
,
1264 .mode_fixup
= psb_intel_crtc_mode_fixup
,
1265 .mode_set
= psb_intel_crtc_mode_set
,
1266 .mode_set_base
= psb_intel_pipe_set_base
,
1267 .prepare
= psb_intel_crtc_prepare
,
1268 .commit
= psb_intel_crtc_commit
,
1271 const struct drm_crtc_funcs psb_intel_crtc_funcs
= {
1272 .save
= psb_intel_crtc_save
,
1273 .restore
= psb_intel_crtc_restore
,
1274 .cursor_set
= psb_intel_crtc_cursor_set
,
1275 .cursor_move
= psb_intel_crtc_cursor_move
,
1276 .gamma_set
= psb_intel_crtc_gamma_set
,
1277 .set_config
= psb_crtc_set_config
,
1278 .destroy
= psb_intel_crtc_destroy
,
1281 void psb_intel_crtc_init(struct drm_device
*dev
, int pipe
,
1282 struct psb_intel_mode_device
*mode_dev
)
1284 struct drm_psb_private
*dev_priv
= dev
->dev_private
;
1285 struct psb_intel_crtc
*psb_intel_crtc
;
1287 uint16_t *r_base
, *g_base
, *b_base
;
1289 /* We allocate a extra array of drm_connector pointers
1290 * for fbdev after the crtc */
1292 kzalloc(sizeof(struct psb_intel_crtc
) +
1293 (INTELFB_CONN_LIMIT
* sizeof(struct drm_connector
*)),
1295 if (psb_intel_crtc
== NULL
)
1298 psb_intel_crtc
->crtc_state
=
1299 kzalloc(sizeof(struct psb_intel_crtc_state
), GFP_KERNEL
);
1300 if (!psb_intel_crtc
->crtc_state
) {
1301 dev_err(dev
->dev
, "Crtc state error: No memory\n");
1302 kfree(psb_intel_crtc
);
1306 drm_crtc_init(dev
, &psb_intel_crtc
->base
, &psb_intel_crtc_funcs
);
1308 drm_mode_crtc_set_gamma_size(&psb_intel_crtc
->base
, 256);
1309 psb_intel_crtc
->pipe
= pipe
;
1310 psb_intel_crtc
->plane
= pipe
;
1312 r_base
= psb_intel_crtc
->base
.gamma_store
;
1313 g_base
= r_base
+ 256;
1314 b_base
= g_base
+ 256;
1315 for (i
= 0; i
< 256; i
++) {
1316 psb_intel_crtc
->lut_r
[i
] = i
;
1317 psb_intel_crtc
->lut_g
[i
] = i
;
1318 psb_intel_crtc
->lut_b
[i
] = i
;
1323 psb_intel_crtc
->lut_adj
[i
] = 0;
1326 psb_intel_crtc
->mode_dev
= mode_dev
;
1327 psb_intel_crtc
->cursor_addr
= 0;
1330 drm_crtc_helper_add(&psb_intel_crtc
->base
,
1331 &mrst_helper_funcs
);
1333 drm_crtc_helper_add(&psb_intel_crtc
->base
,
1334 &psb_intel_helper_funcs
);
1336 /* Setup the array of drm_connector pointer array */
1337 psb_intel_crtc
->mode_set
.crtc
= &psb_intel_crtc
->base
;
1338 BUG_ON(pipe
>= ARRAY_SIZE(dev_priv
->plane_to_crtc_mapping
) ||
1339 dev_priv
->plane_to_crtc_mapping
[psb_intel_crtc
->plane
] != NULL
);
1340 dev_priv
->plane_to_crtc_mapping
[psb_intel_crtc
->plane
] =
1341 &psb_intel_crtc
->base
;
1342 dev_priv
->pipe_to_crtc_mapping
[psb_intel_crtc
->pipe
] =
1343 &psb_intel_crtc
->base
;
1344 psb_intel_crtc
->mode_set
.connectors
=
1345 (struct drm_connector
**) (psb_intel_crtc
+ 1);
1346 psb_intel_crtc
->mode_set
.num_connectors
= 0;
1349 int psb_intel_get_pipe_from_crtc_id(struct drm_device
*dev
, void *data
,
1350 struct drm_file
*file_priv
)
1352 struct drm_psb_private
*dev_priv
= dev
->dev_private
;
1353 struct drm_psb_get_pipe_from_crtc_id_arg
*pipe_from_crtc_id
= data
;
1354 struct drm_mode_object
*drmmode_obj
;
1355 struct psb_intel_crtc
*crtc
;
1358 dev_err(dev
->dev
, "called with no initialization\n");
1362 drmmode_obj
= drm_mode_object_find(dev
, pipe_from_crtc_id
->crtc_id
,
1363 DRM_MODE_OBJECT_CRTC
);
1366 dev_err(dev
->dev
, "no such CRTC id\n");
1370 crtc
= to_psb_intel_crtc(obj_to_crtc(drmmode_obj
));
1371 pipe_from_crtc_id
->pipe
= crtc
->pipe
;
1376 struct drm_crtc
*psb_intel_get_crtc_from_pipe(struct drm_device
*dev
, int pipe
)
1378 struct drm_crtc
*crtc
= NULL
;
1380 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
1381 struct psb_intel_crtc
*psb_intel_crtc
= to_psb_intel_crtc(crtc
);
1382 if (psb_intel_crtc
->pipe
== pipe
)
1388 int psb_intel_connector_clones(struct drm_device
*dev
, int type_mask
)
1391 struct drm_connector
*connector
;
1394 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
1396 struct psb_intel_output
*psb_intel_output
=
1397 to_psb_intel_output(connector
);
1398 if (type_mask
& (1 << psb_intel_output
->type
))
1399 index_mask
|= (1 << entry
);
1406 void psb_intel_modeset_cleanup(struct drm_device
*dev
)
1408 drm_mode_config_cleanup(dev
);
1412 /* current intel driver doesn't take advantage of encoders
1413 always give back the encoder for the connector
1415 struct drm_encoder
*psb_intel_best_encoder(struct drm_connector
*connector
)
1417 struct psb_intel_output
*psb_intel_output
=
1418 to_psb_intel_output(connector
);
1420 return &psb_intel_output
->enc
;