arch/powerpc/include/asm/perf_counter.h

   1 /*
   2  * Performance counter support - PowerPC-specific definitions.
   3  *
   4  * Copyright 2008-2009 Paul Mackerras, IBM Corporation.
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version
   9  * 2 of the License, or (at your option) any later version.
  10  */
  11 #include <linux/types.h>
  12
  13 #include <asm/hw_irq.h>
  14
  15 #define MAX_HWCOUNTERS          8
  16 #define MAX_EVENT_ALTERNATIVES  8
  17 #define MAX_LIMITED_HWCOUNTERS  2
  18
  19 /*
  20  * This struct provides the constants and functions needed to
  21  * describe the PMU on a particular POWER-family CPU.
  22  */
  23 struct power_pmu {
  24         int     n_counter;
  25         int     max_alternatives;
  26         u64     add_fields;
  27         u64     test_adder;
  28         int     (*compute_mmcr)(u64 events[], int n_ev,
  29                                 unsigned int hwc[], u64 mmcr[]);
  30         int     (*get_constraint)(u64 event, u64 *mskp, u64 *valp);
  31         int     (*get_alternatives)(u64 event, unsigned int flags,
  32                                     u64 alt[]);
  33         void    (*disable_pmc)(unsigned int pmc, u64 mmcr[]);
  34         int     (*limited_pmc_event)(u64 event);
  35         u32     flags;
  36         int     n_generic;
  37         int     *generic_events;
  38         int     (*cache_events)[PERF_COUNT_HW_CACHE_MAX]
  39                                [PERF_COUNT_HW_CACHE_OP_MAX]
  40                                [PERF_COUNT_HW_CACHE_RESULT_MAX];
  41 };
  42
  43 extern struct power_pmu *ppmu;
  44
  45 /*
  46  * Values for power_pmu.flags
  47  */
  48 #define PPMU_LIMITED_PMC5_6     1       /* PMC5/6 have limited function */
  49 #define PPMU_ALT_SIPR           2       /* uses alternate posn for SIPR/HV */
  50
  51 /*
  52  * Values for flags to get_alternatives()
  53  */
  54 #define PPMU_LIMITED_PMC_OK     1       /* can put this on a limited PMC */
  55 #define PPMU_LIMITED_PMC_REQD   2       /* have to put this on a limited PMC */
  56 #define PPMU_ONLY_COUNT_RUN     4       /* only counting in run state */
  57
  58 struct pt_regs;
  59 extern unsigned long perf_misc_flags(struct pt_regs *regs);
  60 #define perf_misc_flags(regs)   perf_misc_flags(regs)
  61
  62 extern unsigned long perf_instruction_pointer(struct pt_regs *regs);
  63
  64 /*
  65  * The power_pmu.get_constraint function returns a 64-bit value and
  66  * a 64-bit mask that express the constraints between this event and
  67  * other events.
  68  *
  69  * The value and mask are divided up into (non-overlapping) bitfields
  70  * of three different types:
  71  *
  72  * Select field: this expresses the constraint that some set of bits
  73  * in MMCR* needs to be set to a specific value for this event.  For a
  74  * select field, the mask contains 1s in every bit of the field, and
  75  * the value contains a unique value for each possible setting of the
  76  * MMCR* bits.  The constraint checking code will ensure that two events
  77  * that set the same field in their masks have the same value in their
  78  * value dwords.
  79  *
  80  * Add field: this expresses the constraint that there can be at most
  81  * N events in a particular class.  A field of k bits can be used for
  82  * N <= 2^(k-1) - 1.  The mask has the most significant bit of the field
  83  * set (and the other bits 0), and the value has only the least significant
  84  * bit of the field set.  In addition, the 'add_fields' and 'test_adder'
  85  * in the struct power_pmu for this processor come into play.  The
  86  * add_fields value contains 1 in the LSB of the field, and the
  87  * test_adder contains 2^(k-1) - 1 - N in the field.
  88  *
  89  * NAND field: this expresses the constraint that you may not have events
  90  * in all of a set of classes.  (For example, on PPC970, you can't select
  91  * events from the FPU, ISU and IDU simultaneously, although any two are
  92  * possible.)  For N classes, the field is N+1 bits wide, and each class
  93  * is assigned one bit from the least-significant N bits.  The mask has
  94  * only the most-significant bit set, and the value has only the bit
  95  * for the event's class set.  The test_adder has the least significant
  96  * bit set in the field.
  97  *
  98  * If an event is not subject to the constraint expressed by a particular
  99  * field, then it will have 0 in both the mask and value for that field.
 100  */