2 * dwc3-omap.c - OMAP Specific Glue layer
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions, and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 * 3. The names of the above-listed copyright holders may not be used
20 * to endorse or promote products derived from this software without
21 * specific prior written permission.
23 * ALTERNATIVELY, this software may be distributed under the terms of the
24 * GNU General Public License ("GPL") version 2, as published by the Free
25 * Software Foundation.
27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
28 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
29 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
31 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
32 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
33 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
34 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
35 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
36 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
37 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 #include <linux/kernel.h>
41 #include <linux/slab.h>
42 #include <linux/interrupt.h>
43 #include <linux/spinlock.h>
44 #include <linux/platform_device.h>
45 #include <linux/platform_data/dwc3-omap.h>
46 #include <linux/dma-mapping.h>
47 #include <linux/ioport.h>
53 * All these registers belong to OMAP's Wrapper around the
54 * DesignWare USB3 Core.
57 #define USBOTGSS_REVISION 0x0000
58 #define USBOTGSS_SYSCONFIG 0x0010
59 #define USBOTGSS_IRQ_EOI 0x0020
60 #define USBOTGSS_IRQSTATUS_RAW_0 0x0024
61 #define USBOTGSS_IRQSTATUS_0 0x0028
62 #define USBOTGSS_IRQENABLE_SET_0 0x002c
63 #define USBOTGSS_IRQENABLE_CLR_0 0x0030
64 #define USBOTGSS_IRQSTATUS_RAW_1 0x0034
65 #define USBOTGSS_IRQSTATUS_1 0x0038
66 #define USBOTGSS_IRQENABLE_SET_1 0x003c
67 #define USBOTGSS_IRQENABLE_CLR_1 0x0040
68 #define USBOTGSS_UTMI_OTG_CTRL 0x0080
69 #define USBOTGSS_UTMI_OTG_STATUS 0x0084
70 #define USBOTGSS_MMRAM_OFFSET 0x0100
71 #define USBOTGSS_FLADJ 0x0104
72 #define USBOTGSS_DEBUG_CFG 0x0108
73 #define USBOTGSS_DEBUG_DATA 0x010c
75 /* SYSCONFIG REGISTER */
76 #define USBOTGSS_SYSCONFIG_DMADISABLE (1 << 16)
77 #define USBOTGSS_SYSCONFIG_STANDBYMODE(x) ((x) << 4)
78 #define USBOTGSS_SYSCONFIG_IDLEMODE(x) ((x) << 2)
80 /* IRQ_EOI REGISTER */
81 #define USBOTGSS_IRQ_EOI_LINE_NUMBER (1 << 0)
84 #define USBOTGSS_IRQO_COREIRQ_ST (1 << 0)
87 #define USBOTGSS_IRQ1_DMADISABLECLR (1 << 17)
88 #define USBOTGSS_IRQ1_OEVT (1 << 16)
89 #define USBOTGSS_IRQ1_DRVVBUS_RISE (1 << 13)
90 #define USBOTGSS_IRQ1_CHRGVBUS_RISE (1 << 12)
91 #define USBOTGSS_IRQ1_DISCHRGVBUS_RISE (1 << 11)
92 #define USBOTGSS_IRQ1_IDPULLUP_RISE (1 << 8)
93 #define USBOTGSS_IRQ1_DRVVBUS_FALL (1 << 5)
94 #define USBOTGSS_IRQ1_CHRGVBUS_FALL (1 << 4)
95 #define USBOTGSS_IRQ1_DISCHRGVBUS_FALL (1 << 3)
96 #define USBOTGSS_IRQ1_IDPULLUP_FALL (1 << 0)
98 /* UTMI_OTG_CTRL REGISTER */
99 #define USBOTGSS_UTMI_OTG_CTRL_DRVVBUS (1 << 5)
100 #define USBOTGSS_UTMI_OTG_CTRL_CHRGVBUS (1 << 4)
101 #define USBOTGSS_UTMI_OTG_CTRL_DISCHRGVBUS (1 << 3)
102 #define USBOTGSS_UTMI_OTG_CTRL_IDPULLUP (1 << 0)
104 /* UTMI_OTG_STATUS REGISTER */
105 #define USBOTGSS_UTMI_OTG_STATUS_SW_MODE (1 << 31)
106 #define USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT (1 << 9)
107 #define USBOTGSS_UTMI_OTG_STATUS_TXBITSTUFFENABLE (1 << 8)
108 #define USBOTGSS_UTMI_OTG_STATUS_IDDIG (1 << 4)
109 #define USBOTGSS_UTMI_OTG_STATUS_SESSEND (1 << 3)
110 #define USBOTGSS_UTMI_OTG_STATUS_SESSVALID (1 << 2)
111 #define USBOTGSS_UTMI_OTG_STATUS_VBUSVALID (1 << 1)
117 struct platform_device
*dwc3
;
129 static irqreturn_t
dwc3_omap_interrupt(int irq
, void *_omap
)
131 struct dwc3_omap
*omap
= _omap
;
135 spin_lock(&omap
->lock
);
137 reg
= dwc3_readl(omap
->base
, USBOTGSS_IRQSTATUS_1
);
138 ctrl
= dwc3_readl(omap
->base
, USBOTGSS_UTMI_OTG_CTRL
);
140 if (reg
& USBOTGSS_IRQ1_DMADISABLECLR
) {
141 dev_dbg(omap
->dev
, "DMA Disable was Cleared\n");
142 omap
->dma_status
= false;
145 if (reg
& USBOTGSS_IRQ1_OEVT
)
146 dev_dbg(omap
->dev
, "OTG Event\n");
148 if (reg
& USBOTGSS_IRQ1_DRVVBUS_RISE
) {
149 dev_dbg(omap
->dev
, "DRVVBUS Rise\n");
150 ctrl
|= USBOTGSS_UTMI_OTG_CTRL_DRVVBUS
;
153 if (reg
& USBOTGSS_IRQ1_CHRGVBUS_RISE
) {
154 dev_dbg(omap
->dev
, "CHRGVBUS Rise\n");
155 ctrl
|= USBOTGSS_UTMI_OTG_CTRL_CHRGVBUS
;
158 if (reg
& USBOTGSS_IRQ1_DISCHRGVBUS_RISE
) {
159 dev_dbg(omap
->dev
, "DISCHRGVBUS Rise\n");
160 ctrl
|= USBOTGSS_UTMI_OTG_CTRL_DISCHRGVBUS
;
163 if (reg
& USBOTGSS_IRQ1_IDPULLUP_RISE
) {
164 dev_dbg(omap
->dev
, "IDPULLUP Rise\n");
165 ctrl
|= USBOTGSS_UTMI_OTG_CTRL_IDPULLUP
;
168 if (reg
& USBOTGSS_IRQ1_DRVVBUS_FALL
) {
169 dev_dbg(omap
->dev
, "DRVVBUS Fall\n");
170 ctrl
&= ~USBOTGSS_UTMI_OTG_CTRL_DRVVBUS
;
173 if (reg
& USBOTGSS_IRQ1_CHRGVBUS_FALL
) {
174 dev_dbg(omap
->dev
, "CHRGVBUS Fall\n");
175 ctrl
&= ~USBOTGSS_UTMI_OTG_CTRL_CHRGVBUS
;
178 if (reg
& USBOTGSS_IRQ1_DISCHRGVBUS_FALL
) {
179 dev_dbg(omap
->dev
, "DISCHRGVBUS Fall\n");
180 ctrl
&= ~USBOTGSS_UTMI_OTG_CTRL_DISCHRGVBUS
;
183 if (reg
& USBOTGSS_IRQ1_IDPULLUP_FALL
) {
184 dev_dbg(omap
->dev
, "IDPULLUP Fall\n");
185 ctrl
&= ~USBOTGSS_UTMI_OTG_CTRL_IDPULLUP
;
188 dwc3_writel(omap
->base
, USBOTGSS_UTMI_OTG_CTRL
, ctrl
);
190 spin_unlock(&omap
->lock
);
195 static int __devinit
dwc3_omap_probe(struct platform_device
*pdev
)
197 struct dwc3_omap_data
*pdata
= pdev
->dev
.platform_data
;
198 struct platform_device
*dwc3
;
199 struct dwc3_omap
*omap
;
200 struct resource
*res
;
210 omap
= kzalloc(sizeof(*omap
), GFP_KERNEL
);
212 dev_err(&pdev
->dev
, "not enough memory\n");
216 platform_set_drvdata(pdev
, omap
);
218 irq
= platform_get_irq(pdev
, 1);
220 dev_err(&pdev
->dev
, "missing IRQ resource\n");
225 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 1);
227 dev_err(&pdev
->dev
, "missing memory base resource\n");
232 base
= ioremap_nocache(res
->start
, resource_size(res
));
234 dev_err(&pdev
->dev
, "ioremap failed\n");
238 dwc3
= platform_device_alloc("dwc3-omap", -1);
240 dev_err(&pdev
->dev
, "couldn't allocate dwc3 device\n");
244 context
= kzalloc(resource_size(res
), GFP_KERNEL
);
246 dev_err(&pdev
->dev
, "couldn't allocate dwc3 context memory\n");
250 spin_lock_init(&omap
->lock
);
251 dma_set_coherent_mask(&dwc3
->dev
, pdev
->dev
.coherent_dma_mask
);
253 dwc3
->dev
.parent
= &pdev
->dev
;
254 dwc3
->dev
.dma_mask
= pdev
->dev
.dma_mask
;
255 dwc3
->dev
.dma_parms
= pdev
->dev
.dma_parms
;
256 omap
->resource_size
= resource_size(res
);
257 omap
->context
= context
;
258 omap
->dev
= &pdev
->dev
;
263 reg
= dwc3_readl(omap
->base
, USBOTGSS_UTMI_OTG_STATUS
);
266 dev_dbg(&pdev
->dev
, "missing platform data\n");
268 switch (pdata
->utmi_mode
) {
269 case DWC3_OMAP_UTMI_MODE_SW
:
270 reg
|= USBOTGSS_UTMI_OTG_STATUS_SW_MODE
;
272 case DWC3_OMAP_UTMI_MODE_HW
:
273 reg
&= ~USBOTGSS_UTMI_OTG_STATUS_SW_MODE
;
276 dev_dbg(&pdev
->dev
, "UNKNOWN utmi mode %d\n",
281 dwc3_writel(omap
->base
, USBOTGSS_UTMI_OTG_STATUS
, reg
);
283 /* check the DMA Status */
284 reg
= dwc3_readl(omap
->base
, USBOTGSS_SYSCONFIG
);
285 omap
->dma_status
= !!(reg
& USBOTGSS_SYSCONFIG_DMADISABLE
);
287 ret
= request_irq(omap
->irq
, dwc3_omap_interrupt
, 0,
288 "dwc3-wrapper", omap
);
290 dev_err(&pdev
->dev
, "failed to request IRQ #%d --> %d\n",
295 /* enable all IRQs */
296 reg
= USBOTGSS_IRQO_COREIRQ_ST
;
297 dwc3_writel(omap
->base
, USBOTGSS_IRQENABLE_SET_0
, reg
);
299 reg
= (USBOTGSS_IRQ1_OEVT
|
300 USBOTGSS_IRQ1_DRVVBUS_RISE
|
301 USBOTGSS_IRQ1_CHRGVBUS_RISE
|
302 USBOTGSS_IRQ1_DISCHRGVBUS_RISE
|
303 USBOTGSS_IRQ1_IDPULLUP_RISE
|
304 USBOTGSS_IRQ1_DRVVBUS_FALL
|
305 USBOTGSS_IRQ1_CHRGVBUS_FALL
|
306 USBOTGSS_IRQ1_DISCHRGVBUS_FALL
|
307 USBOTGSS_IRQ1_IDPULLUP_FALL
);
309 dwc3_writel(omap
->base
, USBOTGSS_IRQENABLE_SET_1
, reg
);
311 ret
= platform_device_add_resources(dwc3
, pdev
->resource
,
312 pdev
->num_resources
);
314 dev_err(&pdev
->dev
, "couldn't add resources to dwc3 device\n");
318 ret
= platform_device_add(dwc3
);
320 dev_err(&pdev
->dev
, "failed to register dwc3 device\n");
327 free_irq(omap
->irq
, omap
);
330 kfree(omap
->context
);
333 platform_device_put(dwc3
);
345 static int __devexit
dwc3_omap_remove(struct platform_device
*pdev
)
347 struct dwc3_omap
*omap
= platform_get_drvdata(pdev
);
349 platform_device_unregister(omap
->dwc3
);
351 free_irq(omap
->irq
, omap
);
354 kfree(omap
->context
);
360 static const struct of_device_id of_dwc3_matach
[] = {
366 MODULE_DEVICE_TABLE(of
, of_dwc3_matach
);
368 static struct platform_driver dwc3_omap_driver
= {
369 .probe
= dwc3_omap_probe
,
370 .remove
= __devexit_p(dwc3_omap_remove
),
373 .of_match_table
= of_dwc3_matach
,
377 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
378 MODULE_LICENSE("Dual BSD/GPL");
379 MODULE_DESCRIPTION("DesignWare USB3 OMAP Glue Layer");
381 static int __devinit
dwc3_omap_init(void)
383 return platform_driver_register(&dwc3_omap_driver
);
385 module_init(dwc3_omap_init
);
387 static void __exit
dwc3_omap_exit(void)
389 platform_driver_unregister(&dwc3_omap_driver
);
391 module_exit(dwc3_omap_exit
);