2 * Copyright (c) 2008 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include <linux/version.h>
21 #include <linux/autoconf.h>
22 #include <linux/kernel.h>
23 #include <linux/module.h>
24 #include <linux/spinlock.h>
25 #include <linux/errno.h>
26 #include <linux/skbuff.h>
27 #include <linux/netdevice.h>
28 #include <linux/etherdevice.h>
30 #include <linux/tcp.h>
32 #include <linux/delay.h>
33 #include <linux/wait.h>
34 #include <linux/pci.h>
35 #include <linux/interrupt.h>
36 #include <linux/sched.h>
37 #include <linux/list.h>
38 #include <asm/byteorder.h>
39 #include <linux/scatterlist.h>
41 #include <net/mac80211.h>
42 #include <linux/leds.h>
43 #include <linux/rfkill.h>
50 /* Macro to expand scalars to 64-bit objects */
52 #define ito64(x) (sizeof(x) == 8) ? \
53 (((unsigned long long int)(x)) & (0xff)) : \
55 (((unsigned long long int)(x)) & 0xffff) : \
56 ((sizeof(x) == 32) ? \
57 (((unsigned long long int)(x)) & 0xffffffff) : \
58 (unsigned long long int)(x))
60 /* increment with wrap-around */
61 #define INCR(_l, _sz) do { \
63 (_l) &= ((_sz) - 1); \
66 /* decrement with wrap-around */
67 #define DECR(_l, _sz) do { \
69 (_l) &= ((_sz) - 1); \
72 #define A_MAX(a, b) ((a) > (b) ? (a) : (b))
74 #define ASSERT(exp) do { \
75 if (unlikely(!(exp))) { \
80 #define TSF_TO_TU(_h,_l) \
81 ((((u32)(_h)) << 22) | (((u32)(_l)) >> 10))
83 #define ATH_TXQ_SETUP(sc, i) ((sc)->sc_txqsetup & (1<<i))
85 static const u8 ath_bcast_mac
[ETH_ALEN
] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
92 ATH_DBG_RESET
= 0x00000001,
93 ATH_DBG_PHY_IO
= 0x00000002,
94 ATH_DBG_REG_IO
= 0x00000004,
95 ATH_DBG_QUEUE
= 0x00000008,
96 ATH_DBG_EEPROM
= 0x00000010,
97 ATH_DBG_NF_CAL
= 0x00000020,
98 ATH_DBG_CALIBRATE
= 0x00000040,
99 ATH_DBG_CHANNEL
= 0x00000080,
100 ATH_DBG_INTERRUPT
= 0x00000100,
101 ATH_DBG_REGULATORY
= 0x00000200,
102 ATH_DBG_ANI
= 0x00000400,
103 ATH_DBG_POWER_MGMT
= 0x00000800,
104 ATH_DBG_XMIT
= 0x00001000,
105 ATH_DBG_BEACON
= 0x00002000,
106 ATH_DBG_RATE
= 0x00004000,
107 ATH_DBG_CONFIG
= 0x00008000,
108 ATH_DBG_KEYCACHE
= 0x00010000,
109 ATH_DBG_AGGR
= 0x00020000,
110 ATH_DBG_FATAL
= 0x00040000,
111 ATH_DBG_ANY
= 0xffffffff
114 #define DBG_DEFAULT (ATH_DBG_FATAL)
116 #define DPRINTF(sc, _m, _fmt, ...) do { \
117 if (sc->sc_debug & (_m)) \
118 printk(_fmt , ##__VA_ARGS__); \
121 /***************************/
122 /* Load-time Configuration */
123 /***************************/
125 /* Per-instance load-time (note: NOT run-time) configurations
126 * for Atheros Device */
130 u16 txpowlimit_override
;
131 u8 cabqReadytime
; /* Cabq Readytime % */
132 u8 swBeaconProcess
; /* Process received beacons in SW (vs HW) */
135 /*************************/
136 /* Descriptor Management */
137 /*************************/
139 #define ATH_TXBUF_RESET(_bf) do { \
140 (_bf)->bf_status = 0; \
141 (_bf)->bf_lastbf = NULL; \
142 (_bf)->bf_lastfrm = NULL; \
143 (_bf)->bf_next = NULL; \
144 memset(&((_bf)->bf_state), 0, \
145 sizeof(struct ath_buf_state)); \
155 BUF_SHORT_PREAMBLE
= BIT(6),
158 BUF_AGGR_BURST
= BIT(9),
159 BUF_CALC_AIRTIME
= BIT(10),
162 struct ath_buf_state
{
163 int bfs_nframes
; /* # frames in aggregate */
164 u16 bfs_al
; /* length of aggregate */
165 u16 bfs_frmlen
; /* length of frame */
166 int bfs_seqno
; /* sequence number */
167 int bfs_tidno
; /* tid of this frame */
168 int bfs_retries
; /* current retries */
169 u32 bf_type
; /* BUF_* (enum buffer_type) */
170 /* key type use to encrypt this frame */
172 enum ath9k_key_type bfs_keytype
;
175 #define bf_nframes bf_state.bfs_nframes
176 #define bf_al bf_state.bfs_al
177 #define bf_frmlen bf_state.bfs_frmlen
178 #define bf_retries bf_state.bfs_retries
179 #define bf_seqno bf_state.bfs_seqno
180 #define bf_tidno bf_state.bfs_tidno
181 #define bf_rcs bf_state.bfs_rcs
182 #define bf_keyix bf_state.bfs_keyix
183 #define bf_keytype bf_state.bfs_keytype
184 #define bf_isdata(bf) (bf->bf_state.bf_type & BUF_DATA)
185 #define bf_isaggr(bf) (bf->bf_state.bf_type & BUF_AGGR)
186 #define bf_isampdu(bf) (bf->bf_state.bf_type & BUF_AMPDU)
187 #define bf_isht(bf) (bf->bf_state.bf_type & BUF_HT)
188 #define bf_isretried(bf) (bf->bf_state.bf_type & BUF_RETRY)
189 #define bf_isxretried(bf) (bf->bf_state.bf_type & BUF_XRETRY)
190 #define bf_isshpreamble(bf) (bf->bf_state.bf_type & BUF_SHORT_PREAMBLE)
191 #define bf_isbar(bf) (bf->bf_state.bf_type & BUF_BAR)
192 #define bf_ispspoll(bf) (bf->bf_state.bf_type & BUF_PSPOLL)
193 #define bf_isaggrburst(bf) (bf->bf_state.bf_type & BUF_AGGR_BURST)
196 * Abstraction of a contiguous buffer to transmit/receive. There is only
197 * a single hw descriptor encapsulated here.
200 struct list_head list
;
201 struct list_head
*last
;
202 struct ath_buf
*bf_lastbf
; /* last buf of this unit (a frame or
204 struct ath_buf
*bf_lastfrm
; /* last buf of this frame */
205 struct ath_buf
*bf_next
; /* next subframe in the aggregate */
206 void *bf_mpdu
; /* enclosing frame structure */
207 struct ath_desc
*bf_desc
; /* virtual addr of desc */
208 dma_addr_t bf_daddr
; /* physical addr of desc */
209 dma_addr_t bf_buf_addr
; /* physical addr of data buffer */
211 u16 bf_flags
; /* tx descriptor flags */
212 struct ath_buf_state bf_state
; /* buffer state */
213 dma_addr_t bf_dmacontext
;
217 * reset the rx buffer.
218 * any new fields added to the athbuf and require
219 * reset need to be added to this macro.
220 * currently bf_status is the only one requires that
223 #define ATH_RXBUF_RESET(_bf) ((_bf)->bf_status = 0)
225 /* hw processing complete, desc processed by hal */
226 #define ATH_BUFSTATUS_DONE 0x00000001
227 /* hw processing complete, desc hold for hw */
228 #define ATH_BUFSTATUS_STALE 0x00000002
229 /* Rx-only: OS is done with this packet and it's ok to queued it to hw */
230 #define ATH_BUFSTATUS_FREE 0x00000004
232 /* DMA state for tx/rx descriptors */
236 struct ath_desc
*dd_desc
; /* descriptors */
237 dma_addr_t dd_desc_paddr
; /* physical addr of dd_desc */
238 u32 dd_desc_len
; /* size of dd_desc */
239 struct ath_buf
*dd_bufptr
; /* associated buffers */
240 dma_addr_t dd_dmacontext
;
243 int ath_descdma_setup(struct ath_softc
*sc
, struct ath_descdma
*dd
,
244 struct list_head
*head
, const char *name
,
245 int nbuf
, int ndesc
);
246 void ath_descdma_cleanup(struct ath_softc
*sc
, struct ath_descdma
*dd
,
247 struct list_head
*head
);
253 #define ATH_MAX_ANTENNA 3
254 #define ATH_RXBUF 512
255 #define WME_NUM_TID 16
257 int ath_startrecv(struct ath_softc
*sc
);
258 bool ath_stoprecv(struct ath_softc
*sc
);
259 void ath_flushrecv(struct ath_softc
*sc
);
260 u32
ath_calcrxfilter(struct ath_softc
*sc
);
261 int ath_rx_init(struct ath_softc
*sc
, int nbufs
);
262 void ath_rx_cleanup(struct ath_softc
*sc
);
263 int ath_rx_tasklet(struct ath_softc
*sc
, int flush
);
265 #define ATH_TXBUF 512
266 /* max number of transmit attempts (tries) */
267 #define ATH_TXMAXTRY 13
268 /* max number of 11n transmit attempts (tries) */
269 #define ATH_11N_TXMAXTRY 10
270 /* max number of tries for management and control frames */
271 #define ATH_MGT_TXMAXTRY 4
272 #define WME_BA_BMP_SIZE 64
273 #define WME_MAX_BA WME_BA_BMP_SIZE
274 #define ATH_TID_MAX_BUFS (2 * WME_MAX_BA)
275 #define TID_TO_WME_AC(_tid) \
276 ((((_tid) == 0) || ((_tid) == 3)) ? WME_AC_BE : \
277 (((_tid) == 1) || ((_tid) == 2)) ? WME_AC_BK : \
278 (((_tid) == 4) || ((_tid) == 5)) ? WME_AC_VI : \
282 /* Wireless Multimedia Extension Defines */
283 #define WME_AC_BE 0 /* best effort */
284 #define WME_AC_BK 1 /* background */
285 #define WME_AC_VI 2 /* video */
286 #define WME_AC_VO 3 /* voice */
290 * Data transmit queue state. One of these exists for each
291 * hardware transmit queue. Packets sent to us from above
292 * are assigned to queues based on their priority. Not all
293 * devices support a complete set of hardware transmit queues.
294 * For those devices the array sc_ac2q will map multiple
295 * priorities to fewer hardware queues (typically all to one
299 u32 axq_qnum
; /* hardware q number */
300 u32
*axq_link
; /* link ptr in last TX desc */
301 struct list_head axq_q
; /* transmit queue */
303 unsigned long axq_lockflags
; /* intr state when must cli */
304 u32 axq_depth
; /* queue depth */
305 u8 axq_aggr_depth
; /* aggregates queued */
306 u32 axq_totalqueued
; /* total ever queued */
308 bool stopped
; /* Is mac80211 queue stopped ? */
309 struct ath_buf
*axq_linkbuf
; /* virtual addr of last buffer*/
311 /* first desc of the last descriptor that contains CTS */
312 struct ath_desc
*axq_lastdsWithCTS
;
314 /* final desc of the gating desc that determines whether
315 lastdsWithCTS has been DMA'ed or not */
316 struct ath_desc
*axq_gatingds
;
318 struct list_head axq_acq
;
321 #define AGGR_CLEANUP BIT(1)
322 #define AGGR_ADDBA_COMPLETE BIT(2)
323 #define AGGR_ADDBA_PROGRESS BIT(3)
325 /* per TID aggregate tx state for a destination */
327 struct list_head list
; /* round-robin tid entry */
328 struct list_head buf_q
; /* pending buffers */
330 struct ath_atx_ac
*ac
;
331 struct ath_buf
*tx_buf
[ATH_TID_MAX_BUFS
]; /* active tx frames */
336 int baw_head
; /* first un-acked tx buffer */
337 int baw_tail
; /* next unused tx buffer slot */
341 int addba_exchangeattempts
;
344 /* per access-category aggregate tx state for a destination */
346 int sched
; /* dest-ac is scheduled */
347 int qnum
; /* H/W queue number associated
349 struct list_head list
; /* round-robin txq entry */
350 struct list_head tid_q
; /* queue of TIDs with buffers */
353 /* per dest tx state */
355 struct ath_atx_tid tid
[WME_NUM_TID
];
356 struct ath_atx_ac ac
[WME_NUM_AC
];
359 /* per-frame tx control block */
360 struct ath_tx_control
{
365 /* per frame tx status block */
366 struct ath_xmit_status
{
367 int retries
; /* number of retries to successufully
368 transmit this frame */
369 int flags
; /* status of transmit */
370 #define ATH_TX_ERROR 0x01
371 #define ATH_TX_XRETRY 0x02
372 #define ATH_TX_BAR 0x04
376 int rssi
; /* RSSI (noise floor ajusted) */
377 int rssictl
[ATH_MAX_ANTENNA
]; /* RSSI (noise floor ajusted) */
378 int rssiextn
[ATH_MAX_ANTENNA
]; /* RSSI (noise floor ajusted) */
379 int rateieee
; /* data rate xmitted (IEEE rate code) */
380 int rateKbps
; /* data rate xmitted (Kbps) */
381 int ratecode
; /* phy rate code */
382 int flags
; /* validity flags */
383 /* if any of ctl,extn chain rssis are valid */
384 #define ATH_TX_CHAIN_RSSI_VALID 0x01
385 /* if extn chain rssis are valid */
386 #define ATH_TX_RSSI_EXTN_VALID 0x02
387 u32 airtime
; /* time on air per final tx rate */
390 struct ath_txq
*ath_txq_setup(struct ath_softc
*sc
, int qtype
, int subtype
);
391 void ath_tx_cleanupq(struct ath_softc
*sc
, struct ath_txq
*txq
);
392 int ath_tx_setup(struct ath_softc
*sc
, int haltype
);
393 void ath_draintxq(struct ath_softc
*sc
, bool retry_tx
);
394 void ath_tx_draintxq(struct ath_softc
*sc
,
395 struct ath_txq
*txq
, bool retry_tx
);
396 void ath_tx_node_init(struct ath_softc
*sc
, struct ath_node
*an
);
397 void ath_tx_node_cleanup(struct ath_softc
*sc
, struct ath_node
*an
);
398 void ath_tx_node_free(struct ath_softc
*sc
, struct ath_node
*an
);
399 void ath_txq_schedule(struct ath_softc
*sc
, struct ath_txq
*txq
);
400 int ath_tx_init(struct ath_softc
*sc
, int nbufs
);
401 int ath_tx_cleanup(struct ath_softc
*sc
);
402 int ath_tx_get_qnum(struct ath_softc
*sc
, int qtype
, int haltype
);
403 struct ath_txq
*ath_test_get_txq(struct ath_softc
*sc
, struct sk_buff
*skb
);
404 int ath_txq_update(struct ath_softc
*sc
, int qnum
,
405 struct ath9k_tx_queue_info
*q
);
406 int ath_tx_start(struct ath_softc
*sc
, struct sk_buff
*skb
,
407 struct ath_tx_control
*txctl
);
408 void ath_tx_tasklet(struct ath_softc
*sc
);
409 u32
ath_txq_depth(struct ath_softc
*sc
, int qnum
);
410 u32
ath_txq_aggr_depth(struct ath_softc
*sc
, int qnum
);
411 void ath_tx_cabq(struct ath_softc
*sc
, struct sk_buff
*skb
);
413 /**********************/
414 /* Node / Aggregation */
415 /**********************/
417 #define ADDBA_EXCHANGE_ATTEMPTS 10
418 #define ATH_AGGR_DELIM_SZ 4 /* delimiter size */
419 #define ATH_AGGR_MINPLEN 256 /* in bytes, minimum packet length */
420 /* number of delimiters for encryption padding */
421 #define ATH_AGGR_ENCRYPTDELIM 10
422 /* minimum h/w qdepth to be sustained to maximize aggregation */
423 #define ATH_AGGR_MIN_QDEPTH 2
424 #define ATH_AMPDU_SUBFRAME_DEFAULT 32
425 #define IEEE80211_SEQ_SEQ_SHIFT 4
426 #define IEEE80211_SEQ_MAX 4096
427 #define IEEE80211_MIN_AMPDU_BUF 0x8
428 #define IEEE80211_HTCAP_MAXRXAMPDU_FACTOR 13
430 /* return whether a bit at index _n in bitmap _bm is set
431 * _sz is the size of the bitmap */
432 #define ATH_BA_ISSET(_bm, _n) (((_n) < (WME_BA_BMP_SIZE)) && \
433 ((_bm)[(_n) >> 5] & (1 << ((_n) & 31))))
435 /* return block-ack bitmap index given sequence and starting sequence */
436 #define ATH_BA_INDEX(_st, _seq) (((_seq) - (_st)) & (IEEE80211_SEQ_MAX - 1))
438 /* returns delimiter padding required given the packet length */
439 #define ATH_AGGR_GET_NDELIM(_len) \
440 (((((_len) + ATH_AGGR_DELIM_SZ) < ATH_AGGR_MINPLEN) ? \
441 (ATH_AGGR_MINPLEN - (_len) - ATH_AGGR_DELIM_SZ) : 0) >> 2)
443 #define BAW_WITHIN(_start, _bawsz, _seqno) \
444 ((((_seqno) - (_start)) & 4095) < (_bawsz))
446 #define ATH_DS_BA_SEQ(_ds) ((_ds)->ds_us.tx.ts_seqnum)
447 #define ATH_DS_BA_BITMAP(_ds) (&(_ds)->ds_us.tx.ba_low)
448 #define ATH_DS_TX_BA(_ds) ((_ds)->ds_us.tx.ts_flags & ATH9K_TX_BA)
449 #define ATH_AN_2_TID(_an, _tidno) (&(_an)->an_aggr.tx.tid[(_tidno)])
451 enum ATH_AGGR_STATUS
{
459 struct aggr_rifs_param
{
460 int param_max_frames
;
464 struct ath_rc_series
*param_rcs
;
467 /* Per-node aggregation state */
468 struct ath_node_aggr
{
469 struct ath_atx tx
; /* node transmit state */
472 /* driver-specific node state */
474 struct ath_softc
*an_sc
;
475 struct ath_node_aggr an_aggr
;
480 void ath_tx_resume_tid(struct ath_softc
*sc
, struct ath_atx_tid
*tid
);
481 bool ath_tx_aggr_check(struct ath_softc
*sc
, struct ath_node
*an
, u8 tidno
);
482 void ath_tx_aggr_teardown(struct ath_softc
*sc
, struct ath_node
*an
, u8 tidno
);
483 int ath_tx_aggr_start(struct ath_softc
*sc
, struct ieee80211_sta
*sta
,
485 int ath_tx_aggr_stop(struct ath_softc
*sc
, struct ieee80211_sta
*sta
, u16 tid
);
486 void ath_tx_aggr_resume(struct ath_softc
*sc
, struct ieee80211_sta
*sta
, u16 tid
);
493 * Define the scheme that we select MAC address for multiple
494 * BSS on the same radio. The very first VAP will just use the MAC
495 * address from the EEPROM. For the next 3 VAPs, we set the
496 * U/L bit (bit 1) in MAC address, and use the next two bits as the
500 #define ATH_SET_VAP_BSSID_MASK(bssid_mask) \
501 ((bssid_mask)[0] &= ~(((ATH_BCBUF-1)<<2)|0x02))
503 /* driver-specific vap state */
505 int av_bslot
; /* beacon slot index */
506 enum ath9k_opmode av_opmode
; /* VAP operational mode */
507 struct ath_buf
*av_bcbuf
; /* beacon buffer */
508 struct ath_tx_control av_btxctl
; /* txctl information for beacon */
511 /*******************/
512 /* Beacon Handling */
513 /*******************/
516 * Regardless of the number of beacons we stagger, (i.e. regardless of the
517 * number of BSSIDs) if a given beacon does not go out even after waiting this
518 * number of beacon intervals, the game's up.
520 #define BSTUCK_THRESH (9 * ATH_BCBUF)
521 #define ATH_BCBUF 4 /* number of beacon buffers */
522 #define ATH_DEFAULT_BINTVAL 100 /* default beacon interval in TU */
523 #define ATH_DEFAULT_BMISS_LIMIT 10
524 #define IEEE80211_MS_TO_TU(x) (((x) * 1000) / 1024)
526 /* beacon configuration */
527 struct ath_beacon_config
{
537 } u
; /* last received beacon/probe response timestamp of this BSS. */
540 void ath9k_beacon_tasklet(unsigned long data
);
541 void ath_beacon_config(struct ath_softc
*sc
, int if_id
);
542 int ath_beaconq_setup(struct ath_hal
*ah
);
543 int ath_beacon_alloc(struct ath_softc
*sc
, int if_id
);
544 void ath_beacon_return(struct ath_softc
*sc
, struct ath_vap
*avp
);
545 void ath_beacon_sync(struct ath_softc
*sc
, int if_id
);
551 /* ANI values for STA only.
552 FIXME: Add appropriate values for AP later */
554 #define ATH_ANI_POLLINTERVAL 100 /* 100 milliseconds between ANI poll */
555 #define ATH_SHORT_CALINTERVAL 1000 /* 1 second between calibrations */
556 #define ATH_LONG_CALINTERVAL 30000 /* 30 seconds between calibrations */
557 #define ATH_RESTART_CALINTERVAL 1200000 /* 20 minutes between calibrations */
561 int16_t sc_noise_floor
;
562 unsigned int sc_longcal_timer
;
563 unsigned int sc_shortcal_timer
;
564 unsigned int sc_resetcal_timer
;
565 unsigned int sc_checkani_timer
;
566 struct timer_list timer
;
569 /********************/
571 /********************/
573 #define ATH_LED_PIN 1
583 struct ath_softc
*sc
;
584 struct led_classdev led_cdev
;
585 enum ath_led_type led_type
;
591 #define ATH_RFKILL_POLL_INTERVAL 2000 /* msecs */
594 struct rfkill
*rfkill
;
595 struct delayed_work rfkill_poll
;
596 char rfkill_name
[32];
599 /********************/
600 /* Main driver core */
601 /********************/
604 * Default cache line size, in bytes.
605 * Used when PCI device not fully initialized by bootrom/BIOS
607 #define DEFAULT_CACHELINE 32
608 #define ATH_DEFAULT_NOISE_FLOOR -95
609 #define ATH_REGCLASSIDS_MAX 10
610 #define ATH_CABQ_READY_TIME 80 /* % of beacon interval */
611 #define ATH_MAX_SW_RETRIES 10
612 #define ATH_CHAN_MAX 255
613 #define IEEE80211_WEP_NKID 4 /* number of key ids */
614 #define IEEE80211_RATE_VAL 0x7f
616 * The key cache is used for h/w cipher state and also for
617 * tracking station state such as the current tx antenna.
618 * We also setup a mapping table between key cache slot indices
619 * and station state to short-circuit node lookups on rx.
620 * Different parts have different size key caches. We handle
621 * up to ATH_KEYMAX entries (could dynamically allocate state).
623 #define ATH_KEYMAX 128 /* max key cache size we handle */
625 #define ATH_IF_ID_ANY 0xff
626 #define ATH_TXPOWER_MAX 100 /* .5 dBm units */
627 #define ATH_RSSI_DUMMY_MARKER 0x127
628 #define ATH_RATE_DUMMY_MARKER 0
636 #define SC_OP_INVALID BIT(0)
637 #define SC_OP_BEACONS BIT(1)
638 #define SC_OP_RXAGGR BIT(2)
639 #define SC_OP_TXAGGR BIT(3)
640 #define SC_OP_CHAINMASK_UPDATE BIT(4)
641 #define SC_OP_FULL_RESET BIT(5)
642 #define SC_OP_NO_RESET BIT(6)
643 #define SC_OP_PREAMBLE_SHORT BIT(7)
644 #define SC_OP_PROTECT_ENABLE BIT(8)
645 #define SC_OP_RXFLUSH BIT(9)
646 #define SC_OP_LED_ASSOCIATED BIT(10)
647 #define SC_OP_RFKILL_REGISTERED BIT(11)
648 #define SC_OP_RFKILL_SW_BLOCKED BIT(12)
649 #define SC_OP_RFKILL_HW_BLOCKED BIT(13)
652 struct ieee80211_hw
*hw
;
653 struct pci_dev
*pdev
;
654 struct tasklet_struct intr_tq
;
655 struct tasklet_struct bcon_tasklet
;
656 struct ath_config sc_config
;
657 struct ath_hal
*sc_ah
;
660 u8 sc_curbssid
[ETH_ALEN
];
661 u8 sc_myaddr
[ETH_ALEN
];
662 u8 sc_bssidmask
[ETH_ALEN
];
666 u32 sc_flags
; /* SC_OP_* */
667 unsigned int rx_filter
;
671 int sc_slotupdate
; /* slot to next advance fsm */
673 int sc_bslot
[ATH_BCBUF
];
676 enum ath9k_int sc_imask
;
677 enum wireless_mode sc_curmode
; /* current phy mode */
678 enum PROT_MODE sc_protmode
;
680 u8 sc_nbcnvaps
; /* # of vaps sending beacons */
681 u16 sc_nvaps
; /* # of active virtual ap's */
682 struct ieee80211_vif
*sc_vaps
[ATH_BCBUF
];
685 u8 sc_defant
; /* current default antenna */
686 u8 sc_rxotherant
; /* rx's on non-default antenna */
688 struct ath9k_node_stats sc_halstats
; /* station-mode rssi stats */
689 enum ath9k_ht_extprotspacing sc_ht_extprotspacing
;
690 enum ath9k_ht_macmode tx_chan_width
;
692 #ifdef CONFIG_SLOW_ANT_DIV
693 struct ath_antdiv sc_antdiv
;
696 OK
, /* no change needed */
697 UPDATE
, /* update pending */
698 COMMIT
/* beacon sent, commit change */
699 } sc_updateslot
; /* slot time update fsm */
702 u32 sc_keymax
; /* size of key cache */
703 DECLARE_BITMAP(sc_keymap
, ATH_KEYMAX
); /* key use bit map */
704 u8 sc_splitmic
; /* split TKIP MIC keys */
707 struct list_head sc_rxbuf
;
708 struct ath_descdma sc_rxdma
;
709 int sc_rxbufsize
; /* rx size based on mtu */
710 u32
*sc_rxlink
; /* link ptr in last RX desc */
713 struct list_head sc_txbuf
;
714 struct ath_txq sc_txq
[ATH9K_NUM_TX_QUEUES
];
715 struct ath_descdma sc_txdma
;
717 int sc_haltype2q
[ATH9K_WME_AC_VO
+1]; /* HAL WME AC -> h/w qnum */
718 u16 seq_no
; /* TX sequence number */
721 struct ath9k_tx_queue_info sc_beacon_qi
;
722 struct ath_descdma sc_bdma
;
723 struct ath_txq
*sc_cabq
;
724 struct list_head sc_bbuf
;
727 u32 ast_be_xmit
; /* beacons transmitted */
731 struct ieee80211_rate rates
[IEEE80211_NUM_BANDS
][ATH_RATE_MAX
];
732 struct ath_rate_table
*hw_rate_table
[ATH9K_MODE_MAX
];
733 u8 sc_protrix
; /* protection rate index */
736 struct ieee80211_channel channels
[IEEE80211_NUM_BANDS
][ATH_CHAN_MAX
];
737 struct ieee80211_supported_band sbands
[IEEE80211_NUM_BANDS
];
740 spinlock_t sc_rxflushlock
;
741 spinlock_t sc_rxbuflock
;
742 spinlock_t sc_txbuflock
;
743 spinlock_t sc_resetlock
;
746 struct ath_led radio_led
;
747 struct ath_led assoc_led
;
748 struct ath_led tx_led
;
749 struct ath_led rx_led
;
752 struct ath_rfkill rf_kill
;
755 struct ath_ani sc_ani
;
758 int ath_reset(struct ath_softc
*sc
, bool retry_tx
);
759 int ath_get_hal_qnum(u16 queue
, struct ath_softc
*sc
);
760 int ath_get_mac80211_qnum(u32 queue
, struct ath_softc
*sc
);
761 int ath_cabq_update(struct ath_softc
*);