arch/arm/mach-davinci/board-dm365-evm.c

   1 /*
   2  * TI DaVinci DM365 EVM board support
   3  *
   4  * Copyright (C) 2009 Texas Instruments Incorporated
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation version 2.
   9  *
  10  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  11  * kind, whether express or implied; without even the implied warranty
  12  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15 #include <linux/kernel.h>
  16 #include <linux/init.h>
  17 #include <linux/err.h>
  18 #include <linux/i2c.h>
  19 #include <linux/io.h>
  20 #include <linux/clk.h>
  21 #include <linux/i2c/at24.h>
  22 #include <linux/leds.h>
  23 #include <linux/mtd/mtd.h>
  24 #include <linux/mtd/partitions.h>
  25 #include <linux/mtd/nand.h>
  26 #include <linux/input.h>
  27
  28 #include <asm/mach-types.h>
  29 #include <asm/mach/arch.h>
  30
  31 #include <mach/mux.h>
  32 #include <mach/dm365.h>
  33 #include <mach/common.h>
  34 #include <mach/i2c.h>
  35 #include <mach/serial.h>
  36 #include <mach/mmc.h>
  37 #include <mach/nand.h>
  38 #include <mach/keyscan.h>
  39
  40 static inline int have_imager(void)
  41 {
  42         /* REVISIT when it's supported, trigger via Kconfig */
  43         return 0;
  44 }
  45
  46 static inline int have_tvp7002(void)
  47 {
  48         /* REVISIT when it's supported, trigger via Kconfig */
  49         return 0;
  50 }
  51
  52
  53 #define DM365_ASYNC_EMIF_CONTROL_BASE   0x01d10000
  54 #define DM365_ASYNC_EMIF_DATA_CE0_BASE  0x02000000
  55 #define DM365_ASYNC_EMIF_DATA_CE1_BASE  0x04000000
  56
  57 #define DM365_EVM_PHY_MASK              (0x2)
  58 #define DM365_EVM_MDIO_FREQUENCY        (2200000) /* PHY bus frequency */
  59
  60 /*
  61  * A MAX-II CPLD is used for various board control functions.
  62  */
  63 #define CPLD_OFFSET(a13a8,a2a1)         (((a13a8) << 10) + ((a2a1) << 3))
  64
  65 #define CPLD_VERSION    CPLD_OFFSET(0,0)        /* r/o */
  66 #define CPLD_TEST       CPLD_OFFSET(0,1)
  67 #define CPLD_LEDS       CPLD_OFFSET(0,2)
  68 #define CPLD_MUX        CPLD_OFFSET(0,3)
  69 #define CPLD_SWITCH     CPLD_OFFSET(1,0)        /* r/o */
  70 #define CPLD_POWER      CPLD_OFFSET(1,1)
  71 #define CPLD_VIDEO      CPLD_OFFSET(1,2)
  72 #define CPLD_CARDSTAT   CPLD_OFFSET(1,3)        /* r/o */
  73
  74 #define CPLD_DILC_OUT   CPLD_OFFSET(2,0)
  75 #define CPLD_DILC_IN    CPLD_OFFSET(2,1)        /* r/o */
  76
  77 #define CPLD_IMG_DIR0   CPLD_OFFSET(2,2)
  78 #define CPLD_IMG_MUX0   CPLD_OFFSET(2,3)
  79 #define CPLD_IMG_MUX1   CPLD_OFFSET(3,0)
  80 #define CPLD_IMG_DIR1   CPLD_OFFSET(3,1)
  81 #define CPLD_IMG_MUX2   CPLD_OFFSET(3,2)
  82 #define CPLD_IMG_MUX3   CPLD_OFFSET(3,3)
  83 #define CPLD_IMG_DIR2   CPLD_OFFSET(4,0)
  84 #define CPLD_IMG_MUX4   CPLD_OFFSET(4,1)
  85 #define CPLD_IMG_MUX5   CPLD_OFFSET(4,2)
  86
  87 #define CPLD_RESETS     CPLD_OFFSET(4,3)
  88
  89 #define CPLD_CCD_DIR1   CPLD_OFFSET(0x3e,0)
  90 #define CPLD_CCD_IO1    CPLD_OFFSET(0x3e,1)
  91 #define CPLD_CCD_DIR2   CPLD_OFFSET(0x3e,2)
  92 #define CPLD_CCD_IO2    CPLD_OFFSET(0x3e,3)
  93 #define CPLD_CCD_DIR3   CPLD_OFFSET(0x3f,0)
  94 #define CPLD_CCD_IO3    CPLD_OFFSET(0x3f,1)
  95
  96 static void __iomem *cpld;
  97
  98
  99 /* NOTE:  this is geared for the standard config, with a socketed
 100  * 2 GByte Micron NAND (MT29F16G08FAA) using 128KB sectors.  If you
 101  * swap chips with a different block size, partitioning will
 102  * need to be changed. This NAND chip MT29F16G08FAA is the default
 103  * NAND shipped with the Spectrum Digital DM365 EVM
 104  */
 105 #define NAND_BLOCK_SIZE         SZ_128K
 106
 107 static struct mtd_partition davinci_nand_partitions[] = {
 108         {
 109                 /* UBL (a few copies) plus U-Boot */
 110                 .name           = "bootloader",
 111                 .offset         = 0,
 112                 .size           = 28 * NAND_BLOCK_SIZE,
 113                 .mask_flags     = MTD_WRITEABLE, /* force read-only */
 114         }, {
 115                 /* U-Boot environment */
 116                 .name           = "params",
 117                 .offset         = MTDPART_OFS_APPEND,
 118                 .size           = 2 * NAND_BLOCK_SIZE,
 119                 .mask_flags     = 0,
 120         }, {
 121                 .name           = "kernel",
 122                 .offset         = MTDPART_OFS_APPEND,
 123                 .size           = SZ_4M,
 124                 .mask_flags     = 0,
 125         }, {
 126                 .name           = "filesystem1",
 127                 .offset         = MTDPART_OFS_APPEND,
 128                 .size           = SZ_512M,
 129                 .mask_flags     = 0,
 130         }, {
 131                 .name           = "filesystem2",
 132                 .offset         = MTDPART_OFS_APPEND,
 133                 .size           = MTDPART_SIZ_FULL,
 134                 .mask_flags     = 0,
 135         }
 136         /* two blocks with bad block table (and mirror) at the end */
 137 };
 138
 139 static struct davinci_nand_pdata davinci_nand_data = {
 140         .mask_chipsel           = BIT(14),
 141         .parts                  = davinci_nand_partitions,
 142         .nr_parts               = ARRAY_SIZE(davinci_nand_partitions),
 143         .ecc_mode               = NAND_ECC_HW,
 144         .options                = NAND_USE_FLASH_BBT,
 145         .ecc_bits               = 4,
 146 };
 147
 148 static struct resource davinci_nand_resources[] = {
 149         {
 150                 .start          = DM365_ASYNC_EMIF_DATA_CE0_BASE,
 151                 .end            = DM365_ASYNC_EMIF_DATA_CE0_BASE + SZ_32M - 1,
 152                 .flags          = IORESOURCE_MEM,
 153         }, {
 154                 .start          = DM365_ASYNC_EMIF_CONTROL_BASE,
 155                 .end            = DM365_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
 156                 .flags          = IORESOURCE_MEM,
 157         },
 158 };
 159
 160 static struct platform_device davinci_nand_device = {
 161         .name                   = "davinci_nand",
 162         .id                     = 0,
 163         .num_resources          = ARRAY_SIZE(davinci_nand_resources),
 164         .resource               = davinci_nand_resources,
 165         .dev                    = {
 166                 .platform_data  = &davinci_nand_data,
 167         },
 168 };
 169
 170 static struct at24_platform_data eeprom_info = {
 171         .byte_len       = (256*1024) / 8,
 172         .page_size      = 64,
 173         .flags          = AT24_FLAG_ADDR16,
 174         .setup          = davinci_get_mac_addr,
 175         .context        = (void *)0x7f00,
 176 };
 177
 178 static struct snd_platform_data dm365_evm_snd_data;
 179
 180 static struct i2c_board_info i2c_info[] = {
 181         {
 182                 I2C_BOARD_INFO("24c256", 0x50),
 183                 .platform_data  = &eeprom_info,
 184         },
 185         {
 186                 I2C_BOARD_INFO("tlv320aic3x", 0x18),
 187         },
 188 };
 189
 190 static struct davinci_i2c_platform_data i2c_pdata = {
 191         .bus_freq       = 400   /* kHz */,
 192         .bus_delay      = 0     /* usec */,
 193 };
 194
 195 #ifdef CONFIG_KEYBOARD_DAVINCI
 196 static unsigned short dm365evm_keymap[] = {
 197         KEY_KP2,
 198         KEY_LEFT,
 199         KEY_EXIT,
 200         KEY_DOWN,
 201         KEY_ENTER,
 202         KEY_UP,
 203         KEY_KP1,
 204         KEY_RIGHT,
 205         KEY_MENU,
 206         KEY_RECORD,
 207         KEY_REWIND,
 208         KEY_KPMINUS,
 209         KEY_STOP,
 210         KEY_FASTFORWARD,
 211         KEY_KPPLUS,
 212         KEY_PLAYPAUSE,
 213         0
 214 };
 215
 216 static struct davinci_ks_platform_data dm365evm_ks_data = {
 217         .keymap         = dm365evm_keymap,
 218         .keymapsize     = ARRAY_SIZE(dm365evm_keymap),
 219         .rep            = 1,
 220         /* Scan period = strobe + interval */
 221         .strobe         = 0x5,
 222         .interval       = 0x2,
 223         .matrix_type    = DAVINCI_KEYSCAN_MATRIX_4X4,
 224 };
 225 #endif
 226
 227 static int cpld_mmc_get_cd(int module)
 228 {
 229         if (!cpld)
 230                 return -ENXIO;
 231
 232         /* low == card present */
 233         return !(__raw_readb(cpld + CPLD_CARDSTAT) & BIT(module ? 4 : 0));
 234 }
 235
 236 static int cpld_mmc_get_ro(int module)
 237 {
 238         if (!cpld)
 239                 return -ENXIO;
 240
 241         /* high == card's write protect switch active */
 242         return !!(__raw_readb(cpld + CPLD_CARDSTAT) & BIT(module ? 5 : 1));
 243 }
 244
 245 static struct davinci_mmc_config dm365evm_mmc_config = {
 246         .get_cd         = cpld_mmc_get_cd,
 247         .get_ro         = cpld_mmc_get_ro,
 248         .wires          = 4,
 249         .max_freq       = 50000000,
 250         .caps           = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
 251         .version        = MMC_CTLR_VERSION_2,
 252 };
 253
 254 static void dm365evm_emac_configure(void)
 255 {
 256         /*
 257          * EMAC pins are multiplexed with GPIO and UART
 258          * Further details are available at the DM365 ARM
 259          * Subsystem Users Guide(sprufg5.pdf) pages 125 - 127
 260          */
 261         davinci_cfg_reg(DM365_EMAC_TX_EN);
 262         davinci_cfg_reg(DM365_EMAC_TX_CLK);
 263         davinci_cfg_reg(DM365_EMAC_COL);
 264         davinci_cfg_reg(DM365_EMAC_TXD3);
 265         davinci_cfg_reg(DM365_EMAC_TXD2);
 266         davinci_cfg_reg(DM365_EMAC_TXD1);
 267         davinci_cfg_reg(DM365_EMAC_TXD0);
 268         davinci_cfg_reg(DM365_EMAC_RXD3);
 269         davinci_cfg_reg(DM365_EMAC_RXD2);
 270         davinci_cfg_reg(DM365_EMAC_RXD1);
 271         davinci_cfg_reg(DM365_EMAC_RXD0);
 272         davinci_cfg_reg(DM365_EMAC_RX_CLK);
 273         davinci_cfg_reg(DM365_EMAC_RX_DV);
 274         davinci_cfg_reg(DM365_EMAC_RX_ER);
 275         davinci_cfg_reg(DM365_EMAC_CRS);
 276         davinci_cfg_reg(DM365_EMAC_MDIO);
 277         davinci_cfg_reg(DM365_EMAC_MDCLK);
 278
 279         /*
 280          * EMAC interrupts are multiplexed with GPIO interrupts
 281          * Details are available at the DM365 ARM
 282          * Subsystem Users Guide(sprufg5.pdf) pages 133 - 134
 283          */
 284         davinci_cfg_reg(DM365_INT_EMAC_RXTHRESH);
 285         davinci_cfg_reg(DM365_INT_EMAC_RXPULSE);
 286         davinci_cfg_reg(DM365_INT_EMAC_TXPULSE);
 287         davinci_cfg_reg(DM365_INT_EMAC_MISCPULSE);
 288 }
 289
 290 static void dm365evm_mmc_configure(void)
 291 {
 292         /*
 293          * MMC/SD pins are multiplexed with GPIO and EMIF
 294          * Further details are available at the DM365 ARM
 295          * Subsystem Users Guide(sprufg5.pdf) pages 118, 128 - 131
 296          */
 297         davinci_cfg_reg(DM365_SD1_CLK);
 298         davinci_cfg_reg(DM365_SD1_CMD);
 299         davinci_cfg_reg(DM365_SD1_DATA3);
 300         davinci_cfg_reg(DM365_SD1_DATA2);
 301         davinci_cfg_reg(DM365_SD1_DATA1);
 302         davinci_cfg_reg(DM365_SD1_DATA0);
 303 }
 304
 305 static void __init evm_init_i2c(void)
 306 {
 307         davinci_init_i2c(&i2c_pdata);
 308         i2c_register_board_info(1, i2c_info, ARRAY_SIZE(i2c_info));
 309 }
 310
 311 static struct platform_device *dm365_evm_nand_devices[] __initdata = {
 312         &davinci_nand_device,
 313 };
 314
 315 static inline int have_leds(void)
 316 {
 317 #ifdef CONFIG_LEDS_CLASS
 318         return 1;
 319 #else
 320         return 0;
 321 #endif
 322 }
 323
 324 struct cpld_led {
 325         struct led_classdev     cdev;
 326         u8                      mask;
 327 };
 328
 329 static const struct {
 330         const char *name;
 331         const char *trigger;
 332 } cpld_leds[] = {
 333         { "dm365evm::ds2", },
 334         { "dm365evm::ds3", },
 335         { "dm365evm::ds4", },
 336         { "dm365evm::ds5", },
 337         { "dm365evm::ds6", "nand-disk", },
 338         { "dm365evm::ds7", "mmc1", },
 339         { "dm365evm::ds8", "mmc0", },
 340         { "dm365evm::ds9", "heartbeat", },
 341 };
 342
 343 static void cpld_led_set(struct led_classdev *cdev, enum led_brightness b)
 344 {
 345         struct cpld_led *led = container_of(cdev, struct cpld_led, cdev);
 346         u8 reg = __raw_readb(cpld + CPLD_LEDS);
 347
 348         if (b != LED_OFF)
 349                 reg &= ~led->mask;
 350         else
 351                 reg |= led->mask;
 352         __raw_writeb(reg, cpld + CPLD_LEDS);
 353 }
 354
 355 static enum led_brightness cpld_led_get(struct led_classdev *cdev)
 356 {
 357         struct cpld_led *led = container_of(cdev, struct cpld_led, cdev);
 358         u8 reg = __raw_readb(cpld + CPLD_LEDS);
 359
 360         return (reg & led->mask) ? LED_OFF : LED_FULL;
 361 }
 362
 363 static int __init cpld_leds_init(void)
 364 {
 365         int     i;
 366
 367         if (!have_leds() ||  !cpld)
 368                 return 0;
 369
 370         /* setup LEDs */
 371         __raw_writeb(0xff, cpld + CPLD_LEDS);
 372         for (i = 0; i < ARRAY_SIZE(cpld_leds); i++) {
 373                 struct cpld_led *led;
 374
 375                 led = kzalloc(sizeof(*led), GFP_KERNEL);
 376                 if (!led)
 377                         break;
 378
 379                 led->cdev.name = cpld_leds[i].name;
 380                 led->cdev.brightness_set = cpld_led_set;
 381                 led->cdev.brightness_get = cpld_led_get;
 382                 led->cdev.default_trigger = cpld_leds[i].trigger;
 383                 led->mask = BIT(i);
 384
 385                 if (led_classdev_register(NULL, &led->cdev) < 0) {
 386                         kfree(led);
 387                         break;
 388                 }
 389         }
 390
 391         return 0;
 392 }
 393 /* run after subsys_initcall() for LEDs */
 394 fs_initcall(cpld_leds_init);
 395
 396
 397 static void __init evm_init_cpld(void)
 398 {
 399         u8 mux, resets;
 400         const char *label;
 401         struct clk *aemif_clk;
 402
 403         /* Make sure we can configure the CPLD through CS1.  Then
 404          * leave it on for later access to MMC and LED registers.
 405          */
 406         aemif_clk = clk_get(NULL, "aemif");
 407         if (IS_ERR(aemif_clk))
 408                 return;
 409         clk_enable(aemif_clk);
 410
 411         if (request_mem_region(DM365_ASYNC_EMIF_DATA_CE1_BASE, SECTION_SIZE,
 412                         "cpld") == NULL)
 413                 goto fail;
 414         cpld = ioremap(DM365_ASYNC_EMIF_DATA_CE1_BASE, SECTION_SIZE);
 415         if (!cpld) {
 416                 release_mem_region(DM365_ASYNC_EMIF_DATA_CE1_BASE,
 417                                 SECTION_SIZE);
 418 fail:
 419                 pr_err("ERROR: can't map CPLD\n");
 420                 clk_disable(aemif_clk);
 421                 return;
 422         }
 423
 424         /* External muxing for some signals */
 425         mux = 0;
 426
 427         /* Read SW5 to set up NAND + keypad _or_ OneNAND (sync read).
 428          * NOTE:  SW4 bus width setting must match!
 429          */
 430         if ((__raw_readb(cpld + CPLD_SWITCH) & BIT(5)) == 0) {
 431                 /* external keypad mux */
 432                 mux |= BIT(7);
 433
 434                 platform_add_devices(dm365_evm_nand_devices,
 435                                 ARRAY_SIZE(dm365_evm_nand_devices));
 436         } else {
 437                 /* no OneNAND support yet */
 438         }
 439
 440         /* Leave external chips in reset when unused. */
 441         resets = BIT(3) | BIT(2) | BIT(1) | BIT(0);
 442
 443         /* Static video input config with SN74CBT16214 1-of-3 mux:
 444          *  - port b1 == tvp7002 (mux lowbits == 1 or 6)
 445          *  - port b2 == imager (mux lowbits == 2 or 7)
 446          *  - port b3 == tvp5146 (mux lowbits == 5)
 447          *
 448          * Runtime switching could work too, with limitations.
 449          */
 450         if (have_imager()) {
 451                 label = "HD imager";
 452                 mux |= 1;
 453
 454                 /* externally mux MMC1/ENET/AIC33 to imager */
 455                 mux |= BIT(6) | BIT(5) | BIT(3);
 456         } else {
 457                 struct davinci_soc_info *soc_info = &davinci_soc_info;
 458
 459                 /* we can use MMC1 ... */
 460                 dm365evm_mmc_configure();
 461                 davinci_setup_mmc(1, &dm365evm_mmc_config);
 462
 463                 /* ... and ENET ... */
 464                 dm365evm_emac_configure();
 465                 soc_info->emac_pdata->phy_mask = DM365_EVM_PHY_MASK;
 466                 soc_info->emac_pdata->mdio_max_freq = DM365_EVM_MDIO_FREQUENCY;
 467                 resets &= ~BIT(3);
 468
 469                 /* ... and AIC33 */
 470                 resets &= ~BIT(1);
 471
 472                 if (have_tvp7002()) {
 473                         mux |= 2;
 474                         resets &= ~BIT(2);
 475                         label = "tvp7002 HD";
 476                 } else {
 477                         /* default to tvp5146 */
 478                         mux |= 5;
 479                         resets &= ~BIT(0);
 480                         label = "tvp5146 SD";
 481                 }
 482         }
 483         __raw_writeb(mux, cpld + CPLD_MUX);
 484         __raw_writeb(resets, cpld + CPLD_RESETS);
 485         pr_info("EVM: %s video input\n", label);
 486
 487         /* REVISIT export switches: NTSC/PAL (SW5.6), EXTRA1 (SW5.2), etc */
 488 }
 489
 490 static struct davinci_uart_config uart_config __initdata = {
 491         .enabled_uarts = (1 << 0),
 492 };
 493
 494 static void __init dm365_evm_map_io(void)
 495 {
 496         dm365_init();
 497 }
 498
 499 static __init void dm365_evm_init(void)
 500 {
 501         evm_init_i2c();
 502         davinci_serial_init(&uart_config);
 503
 504         dm365evm_emac_configure();
 505         dm365evm_mmc_configure();
 506
 507         davinci_setup_mmc(0, &dm365evm_mmc_config);
 508
 509         /* maybe setup mmc1/etc ... _after_ mmc0 */
 510         evm_init_cpld();
 511
 512         dm365_init_asp(&dm365_evm_snd_data);
 513         dm365_init_rtc();
 514
 515 #ifdef CONFIG_KEYBOARD_DAVINCI
 516         dm365_init_ks(&dm365evm_ks_data);
 517 #endif
 518 }
 519
 520 static __init void dm365_evm_irq_init(void)
 521 {
 522         davinci_irq_init();
 523 }
 524
 525 MACHINE_START(DAVINCI_DM365_EVM, "DaVinci DM365 EVM")
 526         .phys_io        = IO_PHYS,
 527         .io_pg_offst    = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
 528         .boot_params    = (0x80000100),
 529         .map_io         = dm365_evm_map_io,
 530         .init_irq       = dm365_evm_irq_init,
 531         .timer          = &davinci_timer,
 532         .init_machine   = dm365_evm_init,
 533 MACHINE_END
 534