| blob | 782f23df7c85495714c85353ace0aca1d146a0cf |
1 /*
2 * PowerPC version
3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
4 *
5 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
6 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
7 * Adapted for Power Macintosh by Paul Mackerras.
8 * Low-level exception handlers and MMU support
9 * rewritten by Paul Mackerras.
10 * Copyright (C) 1996 Paul Mackerras.
11 *
12 * Adapted for 64bit PowerPC by Dave Engebretsen, Peter Bergner, and
13 * Mike Corrigan {engebret|bergner|mikejc}@us.ibm.com
14 *
15 * This file contains the entry point for the 64-bit kernel along
16 * with some early initialization code common to all 64-bit powerpc
17 * variants.
18 *
19 * This program is free software; you can redistribute it and/or
20 * modify it under the terms of the GNU General Public License
21 * as published by the Free Software Foundation; either version
22 * 2 of the License, or (at your option) any later version.
23 */
25 #include <linux/threads.h>
26 #include <asm/reg.h>
27 #include <asm/page.h>
28 #include <asm/mmu.h>
29 #include <asm/ppc_asm.h>
30 #include <asm/asm-offsets.h>
31 #include <asm/bug.h>
32 #include <asm/cputable.h>
33 #include <asm/setup.h>
34 #include <asm/hvcall.h>
35 #include <asm/iseries/lpar_map.h>
36 #include <asm/thread_info.h>
37 #include <asm/firmware.h>
38 #include <asm/page_64.h>
39 #include <asm/irqflags.h>
40 #include <asm/kvm_book3s_asm.h>
41 #include <asm/ptrace.h>
43 /* The physical memory is layed out such that the secondary processor
44 * spin code sits at 0x0000...0x00ff. On server, the vectors follow
45 * using the layout described in exceptions-64s.S
46 */
48 /*
49 * Entering into this code we make the following assumptions:
50 *
51 * For pSeries or server processors:
52 * 1. The MMU is off & open firmware is running in real mode.
53 * 2. The kernel is entered at __start
54 *
55 * For iSeries:
56 * 1. The MMU is on (as it always is for iSeries)
57 * 2. The kernel is entered at system_reset_iSeries
58 *
59 * For Book3E processors:
60 * 1. The MMU is on running in AS0 in a state defined in ePAPR
61 * 2. The kernel is entered at __start
62 */
64 .text
65 .globl _stext
66 _stext:
67 _GLOBAL(__start)
68 /* NOP this out unconditionally */
69 BEGIN_FTR_SECTION
70 b .__start_initialization_multiplatform
71 END_FTR_SECTION(0, 1)
73 /* Catch branch to 0 in real mode */
74 trap
76 /* Secondary processors spin on this value until it becomes nonzero.
77 * When it does it contains the real address of the descriptor
78 * of the function that the cpu should jump to to continue
79 * initialization.
80 */
81 .globl __secondary_hold_spinloop
82 __secondary_hold_spinloop:
83 .llong 0x0
85 /* Secondary processors write this value with their cpu # */
86 /* after they enter the spin loop immediately below. */
87 .globl __secondary_hold_acknowledge
88 __secondary_hold_acknowledge:
89 .llong 0x0
91 #ifdef CONFIG_PPC_ISERIES
92 /*
93 * At offset 0x20, there is a pointer to iSeries LPAR data.
94 * This is required by the hypervisor
95 */
96 . = 0x20
97 .llong hvReleaseData-KERNELBASE
98 #endif /* CONFIG_PPC_ISERIES */
100 #ifdef CONFIG_RELOCATABLE
101 /* This flag is set to 1 by a loader if the kernel should run
102 * at the loaded address instead of the linked address. This
103 * is used by kexec-tools to keep the the kdump kernel in the
104 * crash_kernel region. The loader is responsible for
105 * observing the alignment requirement.
106 */
107 /* Do not move this variable as kexec-tools knows about it. */
108 . = 0x5c
109 .globl __run_at_load
110 __run_at_load:
111 .long 0x72756e30 /* "run0" -- relocate to 0 by default */
112 #endif
114 . = 0x60
115 /*
116 * The following code is used to hold secondary processors
117 * in a spin loop after they have entered the kernel, but
118 * before the bulk of the kernel has been relocated. This code
119 * is relocated to physical address 0x60 before prom_init is run.
120 * All of it must fit below the first exception vector at 0x100.
121 * Use .globl here not _GLOBAL because we want __secondary_hold
122 * to be the actual text address, not a descriptor.
123 */
124 .globl __secondary_hold
125 __secondary_hold:
126 #ifndef CONFIG_PPC_BOOK3E
127 mfmsr r24
128 ori r24,r24,MSR_RI
129 mtmsrd r24 /* RI on */
130 #endif
131 /* Grab our physical cpu number */
132 mr r24,r3
134 /* Tell the master cpu we're here */
135 /* Relocation is off & we are located at an address less */
136 /* than 0x100, so only need to grab low order offset. */
137 std r24,__secondary_hold_acknowledge-_stext(0)
138 sync
140 /* All secondary cpus wait here until told to start. */
141 100: ld r4,__secondary_hold_spinloop-_stext(0)
142 cmpdi 0,r4,0
143 beq 100b
145 #if defined(CONFIG_SMP) || defined(CONFIG_KEXEC)
146 ld r4,0(r4) /* deref function descriptor */
147 mtctr r4
148 mr r3,r24
149 li r4,0
150 bctr
151 #else
152 BUG_OPCODE
153 #endif
155 /* This value is used to mark exception frames on the stack. */
156 .section ".toc","aw"
157 exception_marker:
158 .tc ID_72656773_68657265[TC],0x7265677368657265
159 .text
161 /*
162 * On server, we include the exception vectors code here as it
163 * relies on absolute addressing which is only possible within
164 * this compilation unit
165 */
166 #ifdef CONFIG_PPC_BOOK3S
167 #include "exceptions-64s.S"
168 #endif
170 _GLOBAL(generic_secondary_thread_init)
171 mr r24,r3
173 /* turn on 64-bit mode */
174 bl .enable_64b_mode
176 /* get a valid TOC pointer, wherever we're mapped at */
177 bl .relative_toc
179 #ifdef CONFIG_PPC_BOOK3E
180 /* Book3E initialization */
181 mr r3,r24
182 bl .book3e_secondary_thread_init
183 #endif
184 b generic_secondary_common_init
186 /*
187 * On pSeries and most other platforms, secondary processors spin
188 * in the following code.
189 * At entry, r3 = this processor's number (physical cpu id)
190 *
191 * On Book3E, r4 = 1 to indicate that the initial TLB entry for
192 * this core already exists (setup via some other mechanism such
193 * as SCOM before entry).
194 */
195 _GLOBAL(generic_secondary_smp_init)
196 mr r24,r3
197 mr r25,r4
199 /* turn on 64-bit mode */
200 bl .enable_64b_mode
202 /* get a valid TOC pointer, wherever we're mapped at */
203 bl .relative_toc
205 #ifdef CONFIG_PPC_BOOK3E
206 /* Book3E initialization */
207 mr r3,r24
208 mr r4,r25
209 bl .book3e_secondary_core_init
210 #endif
212 generic_secondary_common_init:
213 /* Set up a paca value for this processor. Since we have the
214 * physical cpu id in r24, we need to search the pacas to find
215 * which logical id maps to our physical one.
216 */
217 LOAD_REG_ADDR(r13, paca) /* Load paca pointer */
218 ld r13,0(r13) /* Get base vaddr of paca array */
219 li r5,0 /* logical cpu id */
220 1: lhz r6,PACAHWCPUID(r13) /* Load HW procid from paca */
221 cmpw r6,r24 /* Compare to our id */
222 beq 2f
223 addi r13,r13,PACA_SIZE /* Loop to next PACA on miss */
224 addi r5,r5,1
225 cmpwi r5,NR_CPUS
226 blt 1b
228 mr r3,r24 /* not found, copy phys to r3 */
229 b .kexec_wait /* next kernel might do better */
231 2: mtspr SPRN_SPRG_PACA,r13 /* Save vaddr of paca in an SPRG */
232 #ifdef CONFIG_PPC_BOOK3E
233 addi r12,r13,PACA_EXTLB /* and TLB exc frame in another */
234 mtspr SPRN_SPRG_TLB_EXFRAME,r12
235 #endif
237 /* From now on, r24 is expected to be logical cpuid */
238 mr r24,r5
239 3: HMT_LOW
240 lbz r23,PACAPROCSTART(r13) /* Test if this processor should */
241 /* start. */
243 #ifndef CONFIG_SMP
244 b 3b /* Never go on non-SMP */
245 #else
246 cmpwi 0,r23,0
247 beq 3b /* Loop until told to go */
249 sync /* order paca.run and cur_cpu_spec */
251 /* See if we need to call a cpu state restore handler */
252 LOAD_REG_ADDR(r23, cur_cpu_spec)
253 ld r23,0(r23)
254 ld r23,CPU_SPEC_RESTORE(r23)
255 cmpdi 0,r23,0
256 beq 4f
257 ld r23,0(r23)
258 mtctr r23
259 bctrl
261 4: /* Create a temp kernel stack for use before relocation is on. */
262 ld r1,PACAEMERGSP(r13)
263 subi r1,r1,STACK_FRAME_OVERHEAD
265 b __secondary_start
266 #endif
268 /*
269 * Turn the MMU off.
270 * Assumes we're mapped EA == RA if the MMU is on.
271 */
272 #ifdef CONFIG_PPC_BOOK3S
273 _STATIC(__mmu_off)
274 mfmsr r3
275 andi. r0,r3,MSR_IR|MSR_DR
276 beqlr
277 mflr r4
278 andc r3,r3,r0
279 mtspr SPRN_SRR0,r4
280 mtspr SPRN_SRR1,r3
281 sync
282 rfid
283 b . /* prevent speculative execution */
284 #endif
287 /*
288 * Here is our main kernel entry point. We support currently 2 kind of entries
289 * depending on the value of r5.
290 *
291 * r5 != NULL -> OF entry, we go to prom_init, "legacy" parameter content
292 * in r3...r7
293 *
294 * r5 == NULL -> kexec style entry. r3 is a physical pointer to the
295 * DT block, r4 is a physical pointer to the kernel itself
296 *
297 */
298 _GLOBAL(__start_initialization_multiplatform)
299 /* Make sure we are running in 64 bits mode */
300 bl .enable_64b_mode
302 /* Get TOC pointer (current runtime address) */
303 bl .relative_toc
305 /* find out where we are now */
306 bcl 20,31,$+4
307 0: mflr r26 /* r26 = runtime addr here */
308 addis r26,r26,(_stext - 0b)@ha
309 addi r26,r26,(_stext - 0b)@l /* current runtime base addr */
311 /*
312 * Are we booted from a PROM Of-type client-interface ?
313 */
314 cmpldi cr0,r5,0
315 beq 1f
316 b .__boot_from_prom /* yes -> prom */
317 1:
318 /* Save parameters */
319 mr r31,r3
320 mr r30,r4
322 #ifdef CONFIG_PPC_BOOK3E
323 bl .start_initialization_book3e
324 b .__after_prom_start
325 #else
326 /* Setup some critical 970 SPRs before switching MMU off */
327 mfspr r0,SPRN_PVR
328 srwi r0,r0,16
329 cmpwi r0,0x39 /* 970 */
330 beq 1f
331 cmpwi r0,0x3c /* 970FX */
332 beq 1f
333 cmpwi r0,0x44 /* 970MP */
334 beq 1f
335 cmpwi r0,0x45 /* 970GX */
336 bne 2f
337 1: bl .__cpu_preinit_ppc970
338 2:
340 /* Switch off MMU if not already off */
341 bl .__mmu_off
342 b .__after_prom_start
343 #endif /* CONFIG_PPC_BOOK3E */
345 _INIT_STATIC(__boot_from_prom)
346 #ifdef CONFIG_PPC_OF_BOOT_TRAMPOLINE
347 /* Save parameters */
348 mr r31,r3
349 mr r30,r4
350 mr r29,r5
351 mr r28,r6
352 mr r27,r7
354 /*
355 * Align the stack to 16-byte boundary
356 * Depending on the size and layout of the ELF sections in the initial
357 * boot binary, the stack pointer may be unaligned on PowerMac
358 */
359 rldicr r1,r1,0,59
361 #ifdef CONFIG_RELOCATABLE
362 /* Relocate code for where we are now */
363 mr r3,r26
364 bl .relocate
365 #endif
367 /* Restore parameters */
368 mr r3,r31
369 mr r4,r30
370 mr r5,r29
371 mr r6,r28
372 mr r7,r27
374 /* Do all of the interaction with OF client interface */
375 mr r8,r26
376 bl .prom_init
377 #endif /* #CONFIG_PPC_OF_BOOT_TRAMPOLINE */
379 /* We never return. We also hit that trap if trying to boot
380 * from OF while CONFIG_PPC_OF_BOOT_TRAMPOLINE isn't selected */
381 trap
383 _STATIC(__after_prom_start)
384 #ifdef CONFIG_RELOCATABLE
385 /* process relocations for the final address of the kernel */
386 lis r25,PAGE_OFFSET@highest /* compute virtual base of kernel */
387 sldi r25,r25,32
388 lwz r7,__run_at_load-_stext(r26)
389 cmplwi cr0,r7,1 /* flagged to stay where we are ? */
390 bne 1f
391 add r25,r25,r26
392 1: mr r3,r25
393 bl .relocate
394 #endif
396 /*
397 * We need to run with _stext at physical address PHYSICAL_START.
398 * This will leave some code in the first 256B of
399 * real memory, which are reserved for software use.
400 *
401 * Note: This process overwrites the OF exception vectors.
402 */
403 li r3,0 /* target addr */
404 #ifdef CONFIG_PPC_BOOK3E
405 tovirt(r3,r3) /* on booke, we already run at PAGE_OFFSET */
406 #endif
407 mr. r4,r26 /* In some cases the loader may */
408 beq 9f /* have already put us at zero */
409 li r6,0x100 /* Start offset, the first 0x100 */
410 /* bytes were copied earlier. */
411 #ifdef CONFIG_PPC_BOOK3E
412 tovirt(r6,r6) /* on booke, we already run at PAGE_OFFSET */
413 #endif
415 #ifdef CONFIG_CRASH_DUMP
416 /*
417 * Check if the kernel has to be running as relocatable kernel based on the
418 * variable __run_at_load, if it is set the kernel is treated as relocatable
419 * kernel, otherwise it will be moved to PHYSICAL_START
420 */
421 lwz r7,__run_at_load-_stext(r26)
422 cmplwi cr0,r7,1
423 bne 3f
425 li r5,__end_interrupts - _stext /* just copy interrupts */
426 b 5f
427 3:
428 #endif
429 lis r5,(copy_to_here - _stext)@ha
430 addi r5,r5,(copy_to_here - _stext)@l /* # bytes of memory to copy */
432 bl .copy_and_flush /* copy the first n bytes */
433 /* this includes the code being */
434 /* executed here. */
435 addis r8,r3,(4f - _stext)@ha /* Jump to the copy of this code */
436 addi r8,r8,(4f - _stext)@l /* that we just made */
437 mtctr r8
438 bctr
440 p_end: .llong _end - _stext
442 4: /* Now copy the rest of the kernel up to _end */
443 addis r5,r26,(p_end - _stext)@ha
444 ld r5,(p_end - _stext)@l(r5) /* get _end */
445 5: bl .copy_and_flush /* copy the rest */
447 9: b .start_here_multiplatform
449 /*
450 * Copy routine used to copy the kernel to start at physical address 0
451 * and flush and invalidate the caches as needed.
452 * r3 = dest addr, r4 = source addr, r5 = copy limit, r6 = start offset
453 * on exit, r3, r4, r5 are unchanged, r6 is updated to be >= r5.
454 *
455 * Note: this routine *only* clobbers r0, r6 and lr
456 */
457 _GLOBAL(copy_and_flush)
458 addi r5,r5,-8
459 addi r6,r6,-8
460 4: li r0,8 /* Use the smallest common */
461 /* denominator cache line */
462 /* size. This results in */
463 /* extra cache line flushes */
464 /* but operation is correct. */
465 /* Can't get cache line size */
466 /* from NACA as it is being */
467 /* moved too. */
469 mtctr r0 /* put # words/line in ctr */
470 3: addi r6,r6,8 /* copy a cache line */
471 ldx r0,r6,r4
472 stdx r0,r6,r3
473 bdnz 3b
474 dcbst r6,r3 /* write it to memory */
475 sync
476 icbi r6,r3 /* flush the icache line */
477 cmpld 0,r6,r5
478 blt 4b
479 sync
480 addi r5,r5,8
481 addi r6,r6,8
482 blr
484 .align 8
485 copy_to_here:
487 #ifdef CONFIG_SMP
488 #ifdef CONFIG_PPC_PMAC
489 /*
490 * On PowerMac, secondary processors starts from the reset vector, which
491 * is temporarily turned into a call to one of the functions below.
492 */
493 .section ".text";
494 .align 2 ;
496 .globl __secondary_start_pmac_0
497 __secondary_start_pmac_0:
498 /* NB the entries for cpus 0, 1, 2 must each occupy 8 bytes. */
499 li r24,0
500 b 1f
501 li r24,1
502 b 1f
503 li r24,2
504 b 1f
505 li r24,3
506 1:
508 _GLOBAL(pmac_secondary_start)
509 /* turn on 64-bit mode */
510 bl .enable_64b_mode
512 li r0,0
513 mfspr r3,SPRN_HID4
514 rldimi r3,r0,40,23 /* clear bit 23 (rm_ci) */
515 sync
516 mtspr SPRN_HID4,r3
517 isync
518 sync
519 slbia
521 /* get TOC pointer (real address) */
522 bl .relative_toc
524 /* Copy some CPU settings from CPU 0 */
525 bl .__restore_cpu_ppc970
527 /* pSeries do that early though I don't think we really need it */
528 mfmsr r3
529 ori r3,r3,MSR_RI
530 mtmsrd r3 /* RI on */
532 /* Set up a paca value for this processor. */
533 LOAD_REG_ADDR(r4,paca) /* Load paca pointer */
534 ld r4,0(r4) /* Get base vaddr of paca array */
535 mulli r13,r24,PACA_SIZE /* Calculate vaddr of right paca */
536 add r13,r13,r4 /* for this processor. */
537 mtspr SPRN_SPRG_PACA,r13 /* Save vaddr of paca in an SPRG*/
539 /* Create a temp kernel stack for use before relocation is on. */
540 ld r1,PACAEMERGSP(r13)
541 subi r1,r1,STACK_FRAME_OVERHEAD
543 b __secondary_start
545 #endif /* CONFIG_PPC_PMAC */
547 /*
548 * This function is called after the master CPU has released the
549 * secondary processors. The execution environment is relocation off.
550 * The paca for this processor has the following fields initialized at
551 * this point:
552 * 1. Processor number
553 * 2. Segment table pointer (virtual address)
554 * On entry the following are set:
555 * r1 = stack pointer. vaddr for iSeries, raddr (temp stack) for pSeries
556 * r24 = cpu# (in Linux terms)
557 * r13 = paca virtual address
558 * SPRG_PACA = paca virtual address
559 */
560 .section ".text";
561 .align 2 ;
563 .globl __secondary_start
564 __secondary_start:
565 /* Set thread priority to MEDIUM */
566 HMT_MEDIUM
568 /* Initialize the kernel stack. Just a repeat for iSeries. */
569 LOAD_REG_ADDR(r3, current_set)
570 sldi r28,r24,3 /* get current_set[cpu#] */
571 ldx r14,r3,r28
572 addi r14,r14,THREAD_SIZE-STACK_FRAME_OVERHEAD
573 std r14,PACAKSAVE(r13)
575 /* Do early setup for that CPU (stab, slb, hash table pointer) */
576 bl .early_setup_secondary
578 /*
579 * setup the new stack pointer, but *don't* use this until
580 * translation is on.
581 */
582 mr r1, r14
584 /* Clear backchain so we get nice backtraces */
585 li r7,0
586 mtlr r7
588 /* enable MMU and jump to start_secondary */
589 LOAD_REG_ADDR(r3, .start_secondary_prolog)
590 LOAD_REG_IMMEDIATE(r4, MSR_KERNEL)
591 #ifdef CONFIG_PPC_ISERIES
592 BEGIN_FW_FTR_SECTION
593 ori r4,r4,MSR_EE
594 li r8,1
595 stb r8,PACAHARDIRQEN(r13)
596 END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
597 #endif
598 BEGIN_FW_FTR_SECTION
599 stb r7,PACAHARDIRQEN(r13)
600 END_FW_FTR_SECTION_IFCLR(FW_FEATURE_ISERIES)
601 stb r7,PACASOFTIRQEN(r13)
603 mtspr SPRN_SRR0,r3
604 mtspr SPRN_SRR1,r4
605 RFI
606 b . /* prevent speculative execution */
608 /*
609 * Running with relocation on at this point. All we want to do is
610 * zero the stack back-chain pointer and get the TOC virtual address
611 * before going into C code.
612 */
613 _GLOBAL(start_secondary_prolog)
614 ld r2,PACATOC(r13)
615 li r3,0
616 std r3,0(r1) /* Zero the stack frame pointer */
617 bl .start_secondary
618 b .
619 /*
620 * Reset stack pointer and call start_secondary
621 * to continue with online operation when woken up
622 * from cede in cpu offline.
623 */
624 _GLOBAL(start_secondary_resume)
625 ld r1,PACAKSAVE(r13) /* Reload kernel stack pointer */
626 li r3,0
627 std r3,0(r1) /* Zero the stack frame pointer */
628 bl .start_secondary
629 b .
630 #endif
632 /*
633 * This subroutine clobbers r11 and r12
634 */
635 _GLOBAL(enable_64b_mode)
636 mfmsr r11 /* grab the current MSR */
637 #ifdef CONFIG_PPC_BOOK3E
638 oris r11,r11,0x8000 /* CM bit set, we'll set ICM later */
639 mtmsr r11
640 #else /* CONFIG_PPC_BOOK3E */
641 li r12,(MSR_SF | MSR_ISF)@highest
642 sldi r12,r12,48
643 or r11,r11,r12
644 mtmsrd r11
645 isync
646 #endif
647 blr
649 /*
650 * This puts the TOC pointer into r2, offset by 0x8000 (as expected
651 * by the toolchain). It computes the correct value for wherever we
652 * are running at the moment, using position-independent code.
653 */
654 _GLOBAL(relative_toc)
655 mflr r0
656 bcl 20,31,$+4
657 0: mflr r9
658 ld r2,(p_toc - 0b)(r9)
659 add r2,r2,r9
660 mtlr r0
661 blr
663 p_toc: .llong __toc_start + 0x8000 - 0b
665 /*
666 * This is where the main kernel code starts.
667 */
668 _INIT_STATIC(start_here_multiplatform)
669 /* set up the TOC (real address) */
670 bl .relative_toc
672 /* Clear out the BSS. It may have been done in prom_init,
673 * already but that's irrelevant since prom_init will soon
674 * be detached from the kernel completely. Besides, we need
675 * to clear it now for kexec-style entry.
676 */
677 LOAD_REG_ADDR(r11,__bss_stop)
678 LOAD_REG_ADDR(r8,__bss_start)
679 sub r11,r11,r8 /* bss size */
680 addi r11,r11,7 /* round up to an even double word */
681 srdi. r11,r11,3 /* shift right by 3 */
682 beq 4f
683 addi r8,r8,-8
684 li r0,0
685 mtctr r11 /* zero this many doublewords */
686 3: stdu r0,8(r8)
687 bdnz 3b
688 4:
690 #ifndef CONFIG_PPC_BOOK3E
691 mfmsr r6
692 ori r6,r6,MSR_RI
693 mtmsrd r6 /* RI on */
694 #endif
696 #ifdef CONFIG_RELOCATABLE
697 /* Save the physical address we're running at in kernstart_addr */
698 LOAD_REG_ADDR(r4, kernstart_addr)
699 clrldi r0,r25,2
700 std r0,0(r4)
701 #endif
703 /* The following gets the stack set up with the regs */
704 /* pointing to the real addr of the kernel stack. This is */
705 /* all done to support the C function call below which sets */
706 /* up the htab. This is done because we have relocated the */
707 /* kernel but are still running in real mode. */
709 LOAD_REG_ADDR(r3,init_thread_union)
711 /* set up a stack pointer */
712 addi r1,r3,THREAD_SIZE
713 li r0,0
714 stdu r0,-STACK_FRAME_OVERHEAD(r1)
716 /* Do very early kernel initializations, including initial hash table,
717 * stab and slb setup before we turn on relocation. */
719 /* Restore parameters passed from prom_init/kexec */
720 mr r3,r31
721 bl .early_setup /* also sets r13 and SPRG_PACA */
723 LOAD_REG_ADDR(r3, .start_here_common)
724 ld r4,PACAKMSR(r13)
725 mtspr SPRN_SRR0,r3
726 mtspr SPRN_SRR1,r4
727 RFI
728 b . /* prevent speculative execution */
730 /* This is where all platforms converge execution */
731 _INIT_GLOBAL(start_here_common)
732 /* relocation is on at this point */
733 std r1,PACAKSAVE(r13)
735 /* Load the TOC (virtual address) */
736 ld r2,PACATOC(r13)
738 bl .setup_system
740 /* Load up the kernel context */
741 5:
742 li r5,0
743 stb r5,PACASOFTIRQEN(r13) /* Soft Disabled */
744 #ifdef CONFIG_PPC_ISERIES
745 BEGIN_FW_FTR_SECTION
746 mfmsr r5
747 ori r5,r5,MSR_EE /* Hard Enabled on iSeries*/
748 mtmsrd r5
749 li r5,1
750 END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
751 #endif
752 stb r5,PACAHARDIRQEN(r13) /* Hard Disabled on others */
754 bl .start_kernel
756 /* Not reached */
757 BUG_OPCODE
759 /*
760 * We put a few things here that have to be page-aligned.
761 * This stuff goes at the beginning of the bss, which is page-aligned.
762 */
763 .section ".bss"
765 .align PAGE_SHIFT
767 .globl empty_zero_page
768 empty_zero_page:
769 .space PAGE_SIZE
771 .globl swapper_pg_dir
772 swapper_pg_dir:
773 .space PGD_TABLE_SIZE