2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/kernel_stat.h>
18 #include <linux/mc146818rtc.h>
19 #include <linux/acpi_pmtmr.h>
20 #include <linux/clockchips.h>
21 #include <linux/interrupt.h>
22 #include <linux/bootmem.h>
23 #include <linux/ftrace.h>
24 #include <linux/ioport.h>
25 #include <linux/module.h>
26 #include <linux/sysdev.h>
27 #include <linux/delay.h>
28 #include <linux/timex.h>
29 #include <linux/dmar.h>
30 #include <linux/init.h>
31 #include <linux/cpu.h>
32 #include <linux/dmi.h>
33 #include <linux/nmi.h>
34 #include <linux/smp.h>
37 #include <asm/arch_hooks.h>
38 #include <asm/pgalloc.h>
39 #include <asm/genapic.h>
40 #include <asm/atomic.h>
41 #include <asm/mpspec.h>
42 #include <asm/i8253.h>
43 #include <asm/i8259.h>
44 #include <asm/proto.h>
52 unsigned int num_processors
;
54 unsigned disabled_cpus __cpuinitdata
;
56 /* Processor that is doing the boot up */
57 unsigned int boot_cpu_physical_apicid
= -1U;
60 * The highest APIC ID seen during enumeration.
62 * This determines the messaging protocol we can use: if all APIC IDs
63 * are in the 0 ... 7 range, then we can use logical addressing which
64 * has some performance advantages (better broadcasting).
66 * If there's an APIC ID above 8, we use physical addressing.
68 unsigned int max_physical_apicid
;
71 * Bitmask of physically existing CPUs:
73 physid_mask_t phys_cpu_present_map
;
76 * Map cpu index to physical APIC ID
78 DEFINE_EARLY_PER_CPU(u16
, x86_cpu_to_apicid
, BAD_APICID
);
79 DEFINE_EARLY_PER_CPU(u16
, x86_bios_cpu_apicid
, BAD_APICID
);
80 EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid
);
81 EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid
);
85 * Knob to control our willingness to enable the local APIC.
89 static int force_enable_local_apic
;
91 * APIC command line parameters
93 static int __init
parse_lapic(char *arg
)
95 force_enable_local_apic
= 1;
98 early_param("lapic", parse_lapic
);
99 /* Local APIC was disabled by the BIOS and enabled by the kernel */
100 static int enabled_via_apicbase
;
105 static int apic_calibrate_pmtmr __initdata
;
106 static __init
int setup_apicpmtimer(char *s
)
108 apic_calibrate_pmtmr
= 1;
112 __setup("apicpmtimer", setup_apicpmtimer
);
121 /* x2apic enabled before OS handover */
122 static int x2apic_preenabled
;
123 static int disable_x2apic
;
124 static __init
int setup_nox2apic(char *str
)
127 setup_clear_cpu_cap(X86_FEATURE_X2APIC
);
130 early_param("nox2apic", setup_nox2apic
);
133 unsigned long mp_lapic_addr
;
135 /* Disable local APIC timer from the kernel commandline or via dmi quirk */
136 static int disable_apic_timer __cpuinitdata
;
137 /* Local APIC timer works in C2 */
138 int local_apic_timer_c2_ok
;
139 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok
);
141 int first_system_vector
= 0xfe;
144 * Debug level, exported for io_apic.c
146 unsigned int apic_verbosity
;
150 /* Have we found an MP table */
151 int smp_found_config
;
153 static struct resource lapic_resource
= {
154 .name
= "Local APIC",
155 .flags
= IORESOURCE_MEM
| IORESOURCE_BUSY
,
158 static unsigned int calibration_result
;
160 static int lapic_next_event(unsigned long delta
,
161 struct clock_event_device
*evt
);
162 static void lapic_timer_setup(enum clock_event_mode mode
,
163 struct clock_event_device
*evt
);
164 static void lapic_timer_broadcast(const struct cpumask
*mask
);
165 static void apic_pm_activate(void);
168 * The local apic timer can be used for any function which is CPU local.
170 static struct clock_event_device lapic_clockevent
= {
172 .features
= CLOCK_EVT_FEAT_PERIODIC
| CLOCK_EVT_FEAT_ONESHOT
173 | CLOCK_EVT_FEAT_C3STOP
| CLOCK_EVT_FEAT_DUMMY
,
175 .set_mode
= lapic_timer_setup
,
176 .set_next_event
= lapic_next_event
,
177 .broadcast
= lapic_timer_broadcast
,
181 static DEFINE_PER_CPU(struct clock_event_device
, lapic_events
);
183 static unsigned long apic_phys
;
186 * Get the LAPIC version
188 static inline int lapic_get_version(void)
190 return GET_APIC_VERSION(apic_read(APIC_LVR
));
194 * Check, if the APIC is integrated or a separate chip
196 static inline int lapic_is_integrated(void)
201 return APIC_INTEGRATED(lapic_get_version());
206 * Check, whether this is a modern or a first generation APIC
208 static int modern_apic(void)
210 /* AMD systems use old APIC versions, so check the CPU */
211 if (boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
&&
212 boot_cpu_data
.x86
>= 0xf)
214 return lapic_get_version() >= 0x14;
218 * Paravirt kernels also might be using these below ops. So we still
219 * use generic apic_read()/apic_write(), which might be pointing to different
220 * ops in PARAVIRT case.
222 void xapic_wait_icr_idle(void)
224 while (apic_read(APIC_ICR
) & APIC_ICR_BUSY
)
228 u32
safe_xapic_wait_icr_idle(void)
235 send_status
= apic_read(APIC_ICR
) & APIC_ICR_BUSY
;
239 } while (timeout
++ < 1000);
244 void xapic_icr_write(u32 low
, u32 id
)
246 apic_write(APIC_ICR2
, SET_APIC_DEST_FIELD(id
));
247 apic_write(APIC_ICR
, low
);
250 static u64
xapic_icr_read(void)
254 icr2
= apic_read(APIC_ICR2
);
255 icr1
= apic_read(APIC_ICR
);
257 return icr1
| ((u64
)icr2
<< 32);
260 static struct apic_ops xapic_ops
= {
261 .read
= native_apic_mem_read
,
262 .write
= native_apic_mem_write
,
263 .icr_read
= xapic_icr_read
,
264 .icr_write
= xapic_icr_write
,
265 .wait_icr_idle
= xapic_wait_icr_idle
,
266 .safe_wait_icr_idle
= safe_xapic_wait_icr_idle
,
269 struct apic_ops __read_mostly
*apic_ops
= &xapic_ops
;
270 EXPORT_SYMBOL_GPL(apic_ops
);
273 static void x2apic_wait_icr_idle(void)
275 /* no need to wait for icr idle in x2apic */
279 static u32
safe_x2apic_wait_icr_idle(void)
281 /* no need to wait for icr idle in x2apic */
285 void x2apic_icr_write(u32 low
, u32 id
)
287 wrmsrl(APIC_BASE_MSR
+ (APIC_ICR
>> 4), ((__u64
) id
) << 32 | low
);
290 static u64
x2apic_icr_read(void)
294 rdmsrl(APIC_BASE_MSR
+ (APIC_ICR
>> 4), val
);
298 static struct apic_ops x2apic_ops
= {
299 .read
= native_apic_msr_read
,
300 .write
= native_apic_msr_write
,
301 .icr_read
= x2apic_icr_read
,
302 .icr_write
= x2apic_icr_write
,
303 .wait_icr_idle
= x2apic_wait_icr_idle
,
304 .safe_wait_icr_idle
= safe_x2apic_wait_icr_idle
,
309 * enable_NMI_through_LVT0 - enable NMI through local vector table 0
311 void __cpuinit
enable_NMI_through_LVT0(void)
315 /* unmask and set to NMI */
318 /* Level triggered for 82489DX (32bit mode) */
319 if (!lapic_is_integrated())
320 v
|= APIC_LVT_LEVEL_TRIGGER
;
322 apic_write(APIC_LVT0
, v
);
327 * get_physical_broadcast - Get number of physical broadcast IDs
329 int get_physical_broadcast(void)
331 return modern_apic() ? 0xff : 0xf;
336 * lapic_get_maxlvt - get the maximum number of local vector table entries
338 int lapic_get_maxlvt(void)
342 v
= apic_read(APIC_LVR
);
344 * - we always have APIC integrated on 64bit mode
345 * - 82489DXs do not report # of LVT entries
347 return APIC_INTEGRATED(GET_APIC_VERSION(v
)) ? GET_APIC_MAXLVT(v
) : 2;
355 #define APIC_DIVISOR 16
358 * This function sets up the local APIC timer, with a timeout of
359 * 'clocks' APIC bus clock. During calibration we actually call
360 * this function twice on the boot CPU, once with a bogus timeout
361 * value, second time for real. The other (noncalibrating) CPUs
362 * call this function only once, with the real, calibrated value.
364 * We do reads before writes even if unnecessary, to get around the
365 * P5 APIC double write bug.
367 static void __setup_APIC_LVTT(unsigned int clocks
, int oneshot
, int irqen
)
369 unsigned int lvtt_value
, tmp_value
;
371 lvtt_value
= LOCAL_TIMER_VECTOR
;
373 lvtt_value
|= APIC_LVT_TIMER_PERIODIC
;
374 if (!lapic_is_integrated())
375 lvtt_value
|= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV
);
378 lvtt_value
|= APIC_LVT_MASKED
;
380 apic_write(APIC_LVTT
, lvtt_value
);
385 tmp_value
= apic_read(APIC_TDCR
);
386 apic_write(APIC_TDCR
,
387 (tmp_value
& ~(APIC_TDR_DIV_1
| APIC_TDR_DIV_TMBASE
)) |
391 apic_write(APIC_TMICT
, clocks
/ APIC_DIVISOR
);
395 * Setup extended LVT, AMD specific (K8, family 10h)
397 * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and
398 * MCE interrupts are supported. Thus MCE offset must be set to 0.
400 * If mask=1, the LVT entry does not generate interrupts while mask=0
401 * enables the vector. See also the BKDGs.
404 #define APIC_EILVT_LVTOFF_MCE 0
405 #define APIC_EILVT_LVTOFF_IBS 1
407 static void setup_APIC_eilvt(u8 lvt_off
, u8 vector
, u8 msg_type
, u8 mask
)
409 unsigned long reg
= (lvt_off
<< 4) + APIC_EILVT0
;
410 unsigned int v
= (mask
<< 16) | (msg_type
<< 8) | vector
;
415 u8
setup_APIC_eilvt_mce(u8 vector
, u8 msg_type
, u8 mask
)
417 setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE
, vector
, msg_type
, mask
);
418 return APIC_EILVT_LVTOFF_MCE
;
421 u8
setup_APIC_eilvt_ibs(u8 vector
, u8 msg_type
, u8 mask
)
423 setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS
, vector
, msg_type
, mask
);
424 return APIC_EILVT_LVTOFF_IBS
;
426 EXPORT_SYMBOL_GPL(setup_APIC_eilvt_ibs
);
429 * Program the next event, relative to now
431 static int lapic_next_event(unsigned long delta
,
432 struct clock_event_device
*evt
)
434 apic_write(APIC_TMICT
, delta
);
439 * Setup the lapic timer in periodic or oneshot mode
441 static void lapic_timer_setup(enum clock_event_mode mode
,
442 struct clock_event_device
*evt
)
447 /* Lapic used as dummy for broadcast ? */
448 if (evt
->features
& CLOCK_EVT_FEAT_DUMMY
)
451 local_irq_save(flags
);
454 case CLOCK_EVT_MODE_PERIODIC
:
455 case CLOCK_EVT_MODE_ONESHOT
:
456 __setup_APIC_LVTT(calibration_result
,
457 mode
!= CLOCK_EVT_MODE_PERIODIC
, 1);
459 case CLOCK_EVT_MODE_UNUSED
:
460 case CLOCK_EVT_MODE_SHUTDOWN
:
461 v
= apic_read(APIC_LVTT
);
462 v
|= (APIC_LVT_MASKED
| LOCAL_TIMER_VECTOR
);
463 apic_write(APIC_LVTT
, v
);
464 apic_write(APIC_TMICT
, 0xffffffff);
466 case CLOCK_EVT_MODE_RESUME
:
467 /* Nothing to do here */
471 local_irq_restore(flags
);
475 * Local APIC timer broadcast function
477 static void lapic_timer_broadcast(const struct cpumask
*mask
)
480 apic
->send_IPI_mask(mask
, LOCAL_TIMER_VECTOR
);
485 * Setup the local APIC timer for this CPU. Copy the initilized values
486 * of the boot CPU and register the clock event in the framework.
488 static void __cpuinit
setup_APIC_timer(void)
490 struct clock_event_device
*levt
= &__get_cpu_var(lapic_events
);
492 memcpy(levt
, &lapic_clockevent
, sizeof(*levt
));
493 levt
->cpumask
= cpumask_of(smp_processor_id());
495 clockevents_register_device(levt
);
499 * In this functions we calibrate APIC bus clocks to the external timer.
501 * We want to do the calibration only once since we want to have local timer
502 * irqs syncron. CPUs connected by the same APIC bus have the very same bus
505 * This was previously done by reading the PIT/HPET and waiting for a wrap
506 * around to find out, that a tick has elapsed. I have a box, where the PIT
507 * readout is broken, so it never gets out of the wait loop again. This was
508 * also reported by others.
510 * Monitoring the jiffies value is inaccurate and the clockevents
511 * infrastructure allows us to do a simple substitution of the interrupt
514 * The calibration routine also uses the pm_timer when possible, as the PIT
515 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes
516 * back to normal later in the boot process).
519 #define LAPIC_CAL_LOOPS (HZ/10)
521 static __initdata
int lapic_cal_loops
= -1;
522 static __initdata
long lapic_cal_t1
, lapic_cal_t2
;
523 static __initdata
unsigned long long lapic_cal_tsc1
, lapic_cal_tsc2
;
524 static __initdata
unsigned long lapic_cal_pm1
, lapic_cal_pm2
;
525 static __initdata
unsigned long lapic_cal_j1
, lapic_cal_j2
;
528 * Temporary interrupt handler.
530 static void __init
lapic_cal_handler(struct clock_event_device
*dev
)
532 unsigned long long tsc
= 0;
533 long tapic
= apic_read(APIC_TMCCT
);
534 unsigned long pm
= acpi_pm_read_early();
539 switch (lapic_cal_loops
++) {
541 lapic_cal_t1
= tapic
;
542 lapic_cal_tsc1
= tsc
;
544 lapic_cal_j1
= jiffies
;
547 case LAPIC_CAL_LOOPS
:
548 lapic_cal_t2
= tapic
;
549 lapic_cal_tsc2
= tsc
;
550 if (pm
< lapic_cal_pm1
)
551 pm
+= ACPI_PM_OVRRUN
;
553 lapic_cal_j2
= jiffies
;
558 static int __init
calibrate_by_pmtimer(long deltapm
, long *delta
)
560 const long pm_100ms
= PMTMR_TICKS_PER_SEC
/ 10;
561 const long pm_thresh
= pm_100ms
/ 100;
565 #ifndef CONFIG_X86_PM_TIMER
569 apic_printk(APIC_VERBOSE
, "... PM timer delta = %ld\n", deltapm
);
571 /* Check, if the PM timer is available */
575 mult
= clocksource_hz2mult(PMTMR_TICKS_PER_SEC
, 22);
577 if (deltapm
> (pm_100ms
- pm_thresh
) &&
578 deltapm
< (pm_100ms
+ pm_thresh
)) {
579 apic_printk(APIC_VERBOSE
, "... PM timer result ok\n");
581 res
= (((u64
)deltapm
) * mult
) >> 22;
582 do_div(res
, 1000000);
583 pr_warning("APIC calibration not consistent "
584 "with PM Timer: %ldms instead of 100ms\n",
586 /* Correct the lapic counter value */
587 res
= (((u64
)(*delta
)) * pm_100ms
);
588 do_div(res
, deltapm
);
589 pr_info("APIC delta adjusted to PM-Timer: "
590 "%lu (%ld)\n", (unsigned long)res
, *delta
);
597 static int __init
calibrate_APIC_clock(void)
599 struct clock_event_device
*levt
= &__get_cpu_var(lapic_events
);
600 void (*real_handler
)(struct clock_event_device
*dev
);
601 unsigned long deltaj
;
603 int pm_referenced
= 0;
607 /* Replace the global interrupt handler */
608 real_handler
= global_clock_event
->event_handler
;
609 global_clock_event
->event_handler
= lapic_cal_handler
;
612 * Setup the APIC counter to maximum. There is no way the lapic
613 * can underflow in the 100ms detection time frame
615 __setup_APIC_LVTT(0xffffffff, 0, 0);
617 /* Let the interrupts run */
620 while (lapic_cal_loops
<= LAPIC_CAL_LOOPS
)
625 /* Restore the real event handler */
626 global_clock_event
->event_handler
= real_handler
;
628 /* Build delta t1-t2 as apic timer counts down */
629 delta
= lapic_cal_t1
- lapic_cal_t2
;
630 apic_printk(APIC_VERBOSE
, "... lapic delta = %ld\n", delta
);
632 /* we trust the PM based calibration if possible */
633 pm_referenced
= !calibrate_by_pmtimer(lapic_cal_pm2
- lapic_cal_pm1
,
636 /* Calculate the scaled math multiplication factor */
637 lapic_clockevent
.mult
= div_sc(delta
, TICK_NSEC
* LAPIC_CAL_LOOPS
,
638 lapic_clockevent
.shift
);
639 lapic_clockevent
.max_delta_ns
=
640 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent
);
641 lapic_clockevent
.min_delta_ns
=
642 clockevent_delta2ns(0xF, &lapic_clockevent
);
644 calibration_result
= (delta
* APIC_DIVISOR
) / LAPIC_CAL_LOOPS
;
646 apic_printk(APIC_VERBOSE
, "..... delta %ld\n", delta
);
647 apic_printk(APIC_VERBOSE
, "..... mult: %ld\n", lapic_clockevent
.mult
);
648 apic_printk(APIC_VERBOSE
, "..... calibration result: %u\n",
652 delta
= (long)(lapic_cal_tsc2
- lapic_cal_tsc1
);
653 apic_printk(APIC_VERBOSE
, "..... CPU clock speed is "
655 (delta
/ LAPIC_CAL_LOOPS
) / (1000000 / HZ
),
656 (delta
/ LAPIC_CAL_LOOPS
) % (1000000 / HZ
));
659 apic_printk(APIC_VERBOSE
, "..... host bus clock speed is "
661 calibration_result
/ (1000000 / HZ
),
662 calibration_result
% (1000000 / HZ
));
665 * Do a sanity check on the APIC calibration result
667 if (calibration_result
< (1000000 / HZ
)) {
669 pr_warning("APIC frequency too slow, disabling apic timer\n");
673 levt
->features
&= ~CLOCK_EVT_FEAT_DUMMY
;
676 * PM timer calibration failed or not turned on
677 * so lets try APIC timer based calibration
679 if (!pm_referenced
) {
680 apic_printk(APIC_VERBOSE
, "... verify APIC timer\n");
683 * Setup the apic timer manually
685 levt
->event_handler
= lapic_cal_handler
;
686 lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC
, levt
);
687 lapic_cal_loops
= -1;
689 /* Let the interrupts run */
692 while (lapic_cal_loops
<= LAPIC_CAL_LOOPS
)
695 /* Stop the lapic timer */
696 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN
, levt
);
699 deltaj
= lapic_cal_j2
- lapic_cal_j1
;
700 apic_printk(APIC_VERBOSE
, "... jiffies delta = %lu\n", deltaj
);
702 /* Check, if the jiffies result is consistent */
703 if (deltaj
>= LAPIC_CAL_LOOPS
-2 && deltaj
<= LAPIC_CAL_LOOPS
+2)
704 apic_printk(APIC_VERBOSE
, "... jiffies result ok\n");
706 levt
->features
|= CLOCK_EVT_FEAT_DUMMY
;
710 if (levt
->features
& CLOCK_EVT_FEAT_DUMMY
) {
711 pr_warning("APIC timer disabled due to verification failure\n");
719 * Setup the boot APIC
721 * Calibrate and verify the result.
723 void __init
setup_boot_APIC_clock(void)
726 * The local apic timer can be disabled via the kernel
727 * commandline or from the CPU detection code. Register the lapic
728 * timer as a dummy clock event source on SMP systems, so the
729 * broadcast mechanism is used. On UP systems simply ignore it.
731 if (disable_apic_timer
) {
732 pr_info("Disabling APIC timer\n");
733 /* No broadcast on UP ! */
734 if (num_possible_cpus() > 1) {
735 lapic_clockevent
.mult
= 1;
741 apic_printk(APIC_VERBOSE
, "Using local APIC timer interrupts.\n"
742 "calibrating APIC timer ...\n");
744 if (calibrate_APIC_clock()) {
745 /* No broadcast on UP ! */
746 if (num_possible_cpus() > 1)
752 * If nmi_watchdog is set to IO_APIC, we need the
753 * PIT/HPET going. Otherwise register lapic as a dummy
756 if (nmi_watchdog
!= NMI_IO_APIC
)
757 lapic_clockevent
.features
&= ~CLOCK_EVT_FEAT_DUMMY
;
759 pr_warning("APIC timer registered as dummy,"
760 " due to nmi_watchdog=%d!\n", nmi_watchdog
);
762 /* Setup the lapic or request the broadcast */
766 void __cpuinit
setup_secondary_APIC_clock(void)
772 * The guts of the apic timer interrupt
774 static void local_apic_timer_interrupt(void)
776 int cpu
= smp_processor_id();
777 struct clock_event_device
*evt
= &per_cpu(lapic_events
, cpu
);
780 * Normally we should not be here till LAPIC has been initialized but
781 * in some cases like kdump, its possible that there is a pending LAPIC
782 * timer interrupt from previous kernel's context and is delivered in
783 * new kernel the moment interrupts are enabled.
785 * Interrupts are enabled early and LAPIC is setup much later, hence
786 * its possible that when we get here evt->event_handler is NULL.
787 * Check for event_handler being NULL and discard the interrupt as
790 if (!evt
->event_handler
) {
791 pr_warning("Spurious LAPIC timer interrupt on cpu %d\n", cpu
);
793 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN
, evt
);
798 * the NMI deadlock-detector uses this.
800 inc_irq_stat(apic_timer_irqs
);
802 evt
->event_handler(evt
);
806 * Local APIC timer interrupt. This is the most natural way for doing
807 * local interrupts, but local timer interrupts can be emulated by
808 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
810 * [ if a single-CPU system runs an SMP kernel then we call the local
811 * interrupt as well. Thus we cannot inline the local irq ... ]
813 void __irq_entry
smp_apic_timer_interrupt(struct pt_regs
*regs
)
815 struct pt_regs
*old_regs
= set_irq_regs(regs
);
818 * NOTE! We'd better ACK the irq immediately,
819 * because timer handling can be slow.
823 * update_process_times() expects us to have done irq_enter().
824 * Besides, if we don't timer interrupts ignore the global
825 * interrupt lock, which is the WrongThing (tm) to do.
829 local_apic_timer_interrupt();
832 set_irq_regs(old_regs
);
835 int setup_profiling_timer(unsigned int multiplier
)
841 * Local APIC start and shutdown
845 * clear_local_APIC - shutdown the local APIC
847 * This is called, when a CPU is disabled and before rebooting, so the state of
848 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
849 * leftovers during boot.
851 void clear_local_APIC(void)
856 /* APIC hasn't been mapped yet */
860 maxlvt
= lapic_get_maxlvt();
862 * Masking an LVT entry can trigger a local APIC error
863 * if the vector is zero. Mask LVTERR first to prevent this.
866 v
= ERROR_APIC_VECTOR
; /* any non-zero vector will do */
867 apic_write(APIC_LVTERR
, v
| APIC_LVT_MASKED
);
870 * Careful: we have to set masks only first to deassert
871 * any level-triggered sources.
873 v
= apic_read(APIC_LVTT
);
874 apic_write(APIC_LVTT
, v
| APIC_LVT_MASKED
);
875 v
= apic_read(APIC_LVT0
);
876 apic_write(APIC_LVT0
, v
| APIC_LVT_MASKED
);
877 v
= apic_read(APIC_LVT1
);
878 apic_write(APIC_LVT1
, v
| APIC_LVT_MASKED
);
880 v
= apic_read(APIC_LVTPC
);
881 apic_write(APIC_LVTPC
, v
| APIC_LVT_MASKED
);
884 /* lets not touch this if we didn't frob it */
885 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(X86_MCE_INTEL)
887 v
= apic_read(APIC_LVTTHMR
);
888 apic_write(APIC_LVTTHMR
, v
| APIC_LVT_MASKED
);
892 * Clean APIC state for other OSs:
894 apic_write(APIC_LVTT
, APIC_LVT_MASKED
);
895 apic_write(APIC_LVT0
, APIC_LVT_MASKED
);
896 apic_write(APIC_LVT1
, APIC_LVT_MASKED
);
898 apic_write(APIC_LVTERR
, APIC_LVT_MASKED
);
900 apic_write(APIC_LVTPC
, APIC_LVT_MASKED
);
902 /* Integrated APIC (!82489DX) ? */
903 if (lapic_is_integrated()) {
905 /* Clear ESR due to Pentium errata 3AP and 11AP */
906 apic_write(APIC_ESR
, 0);
912 * disable_local_APIC - clear and disable the local APIC
914 void disable_local_APIC(void)
918 /* APIC hasn't been mapped yet */
925 * Disable APIC (implies clearing of registers
928 value
= apic_read(APIC_SPIV
);
929 value
&= ~APIC_SPIV_APIC_ENABLED
;
930 apic_write(APIC_SPIV
, value
);
934 * When LAPIC was disabled by the BIOS and enabled by the kernel,
935 * restore the disabled state.
937 if (enabled_via_apicbase
) {
940 rdmsr(MSR_IA32_APICBASE
, l
, h
);
941 l
&= ~MSR_IA32_APICBASE_ENABLE
;
942 wrmsr(MSR_IA32_APICBASE
, l
, h
);
948 * If Linux enabled the LAPIC against the BIOS default disable it down before
949 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and
950 * not power-off. Additionally clear all LVT entries before disable_local_APIC
951 * for the case where Linux didn't enable the LAPIC.
953 void lapic_shutdown(void)
960 local_irq_save(flags
);
963 if (!enabled_via_apicbase
)
967 disable_local_APIC();
970 local_irq_restore(flags
);
974 * This is to verify that we're looking at a real local APIC.
975 * Check these against your board if the CPUs aren't getting
976 * started for no apparent reason.
978 int __init
verify_local_APIC(void)
980 unsigned int reg0
, reg1
;
983 * The version register is read-only in a real APIC.
985 reg0
= apic_read(APIC_LVR
);
986 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg0
);
987 apic_write(APIC_LVR
, reg0
^ APIC_LVR_MASK
);
988 reg1
= apic_read(APIC_LVR
);
989 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg1
);
992 * The two version reads above should print the same
993 * numbers. If the second one is different, then we
994 * poke at a non-APIC.
1000 * Check if the version looks reasonably.
1002 reg1
= GET_APIC_VERSION(reg0
);
1003 if (reg1
== 0x00 || reg1
== 0xff)
1005 reg1
= lapic_get_maxlvt();
1006 if (reg1
< 0x02 || reg1
== 0xff)
1010 * The ID register is read/write in a real APIC.
1012 reg0
= apic_read(APIC_ID
);
1013 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg0
);
1014 apic_write(APIC_ID
, reg0
^ apic
->apic_id_mask
);
1015 reg1
= apic_read(APIC_ID
);
1016 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg1
);
1017 apic_write(APIC_ID
, reg0
);
1018 if (reg1
!= (reg0
^ apic
->apic_id_mask
))
1022 * The next two are just to see if we have sane values.
1023 * They're only really relevant if we're in Virtual Wire
1024 * compatibility mode, but most boxes are anymore.
1026 reg0
= apic_read(APIC_LVT0
);
1027 apic_printk(APIC_DEBUG
, "Getting LVT0: %x\n", reg0
);
1028 reg1
= apic_read(APIC_LVT1
);
1029 apic_printk(APIC_DEBUG
, "Getting LVT1: %x\n", reg1
);
1035 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
1037 void __init
sync_Arb_IDs(void)
1040 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
1043 if (modern_apic() || boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
)
1049 apic_wait_icr_idle();
1051 apic_printk(APIC_DEBUG
, "Synchronizing Arb IDs.\n");
1052 apic_write(APIC_ICR
, APIC_DEST_ALLINC
|
1053 APIC_INT_LEVELTRIG
| APIC_DM_INIT
);
1057 * An initial setup of the virtual wire mode.
1059 void __init
init_bsp_APIC(void)
1064 * Don't do the setup now if we have a SMP BIOS as the
1065 * through-I/O-APIC virtual wire mode might be active.
1067 if (smp_found_config
|| !cpu_has_apic
)
1071 * Do not trust the local APIC being empty at bootup.
1078 value
= apic_read(APIC_SPIV
);
1079 value
&= ~APIC_VECTOR_MASK
;
1080 value
|= APIC_SPIV_APIC_ENABLED
;
1082 #ifdef CONFIG_X86_32
1083 /* This bit is reserved on P4/Xeon and should be cleared */
1084 if ((boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
) &&
1085 (boot_cpu_data
.x86
== 15))
1086 value
&= ~APIC_SPIV_FOCUS_DISABLED
;
1089 value
|= APIC_SPIV_FOCUS_DISABLED
;
1090 value
|= SPURIOUS_APIC_VECTOR
;
1091 apic_write(APIC_SPIV
, value
);
1094 * Set up the virtual wire mode.
1096 apic_write(APIC_LVT0
, APIC_DM_EXTINT
);
1097 value
= APIC_DM_NMI
;
1098 if (!lapic_is_integrated()) /* 82489DX */
1099 value
|= APIC_LVT_LEVEL_TRIGGER
;
1100 apic_write(APIC_LVT1
, value
);
1103 static void __cpuinit
lapic_setup_esr(void)
1105 unsigned int oldvalue
, value
, maxlvt
;
1107 if (!lapic_is_integrated()) {
1108 pr_info("No ESR for 82489DX.\n");
1112 if (apic
->disable_esr
) {
1114 * Something untraceable is creating bad interrupts on
1115 * secondary quads ... for the moment, just leave the
1116 * ESR disabled - we can't do anything useful with the
1117 * errors anyway - mbligh
1119 pr_info("Leaving ESR disabled.\n");
1123 maxlvt
= lapic_get_maxlvt();
1124 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
1125 apic_write(APIC_ESR
, 0);
1126 oldvalue
= apic_read(APIC_ESR
);
1128 /* enables sending errors */
1129 value
= ERROR_APIC_VECTOR
;
1130 apic_write(APIC_LVTERR
, value
);
1133 * spec says clear errors after enabling vector.
1136 apic_write(APIC_ESR
, 0);
1137 value
= apic_read(APIC_ESR
);
1138 if (value
!= oldvalue
)
1139 apic_printk(APIC_VERBOSE
, "ESR value before enabling "
1140 "vector: 0x%08x after: 0x%08x\n",
1146 * setup_local_APIC - setup the local APIC
1148 void __cpuinit
setup_local_APIC(void)
1154 arch_disable_smp_support();
1158 #ifdef CONFIG_X86_32
1159 /* Pound the ESR really hard over the head with a big hammer - mbligh */
1160 if (lapic_is_integrated() && apic
->disable_esr
) {
1161 apic_write(APIC_ESR
, 0);
1162 apic_write(APIC_ESR
, 0);
1163 apic_write(APIC_ESR
, 0);
1164 apic_write(APIC_ESR
, 0);
1171 * Double-check whether this APIC is really registered.
1172 * This is meaningless in clustered apic mode, so we skip it.
1174 if (!apic
->apic_id_registered())
1178 * Intel recommends to set DFR, LDR and TPR before enabling
1179 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
1180 * document number 292116). So here it goes...
1182 apic
->init_apic_ldr();
1185 * Set Task Priority to 'accept all'. We never change this
1188 value
= apic_read(APIC_TASKPRI
);
1189 value
&= ~APIC_TPRI_MASK
;
1190 apic_write(APIC_TASKPRI
, value
);
1193 * After a crash, we no longer service the interrupts and a pending
1194 * interrupt from previous kernel might still have ISR bit set.
1196 * Most probably by now CPU has serviced that pending interrupt and
1197 * it might not have done the ack_APIC_irq() because it thought,
1198 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
1199 * does not clear the ISR bit and cpu thinks it has already serivced
1200 * the interrupt. Hence a vector might get locked. It was noticed
1201 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
1203 for (i
= APIC_ISR_NR
- 1; i
>= 0; i
--) {
1204 value
= apic_read(APIC_ISR
+ i
*0x10);
1205 for (j
= 31; j
>= 0; j
--) {
1212 * Now that we are all set up, enable the APIC
1214 value
= apic_read(APIC_SPIV
);
1215 value
&= ~APIC_VECTOR_MASK
;
1219 value
|= APIC_SPIV_APIC_ENABLED
;
1221 #ifdef CONFIG_X86_32
1223 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
1224 * certain networking cards. If high frequency interrupts are
1225 * happening on a particular IOAPIC pin, plus the IOAPIC routing
1226 * entry is masked/unmasked at a high rate as well then sooner or
1227 * later IOAPIC line gets 'stuck', no more interrupts are received
1228 * from the device. If focus CPU is disabled then the hang goes
1231 * [ This bug can be reproduced easily with a level-triggered
1232 * PCI Ne2000 networking cards and PII/PIII processors, dual
1236 * Actually disabling the focus CPU check just makes the hang less
1237 * frequent as it makes the interrupt distributon model be more
1238 * like LRU than MRU (the short-term load is more even across CPUs).
1239 * See also the comment in end_level_ioapic_irq(). --macro
1243 * - enable focus processor (bit==0)
1244 * - 64bit mode always use processor focus
1245 * so no need to set it
1247 value
&= ~APIC_SPIV_FOCUS_DISABLED
;
1251 * Set spurious IRQ vector
1253 value
|= SPURIOUS_APIC_VECTOR
;
1254 apic_write(APIC_SPIV
, value
);
1257 * Set up LVT0, LVT1:
1259 * set up through-local-APIC on the BP's LINT0. This is not
1260 * strictly necessary in pure symmetric-IO mode, but sometimes
1261 * we delegate interrupts to the 8259A.
1264 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
1266 value
= apic_read(APIC_LVT0
) & APIC_LVT_MASKED
;
1267 if (!smp_processor_id() && (pic_mode
|| !value
)) {
1268 value
= APIC_DM_EXTINT
;
1269 apic_printk(APIC_VERBOSE
, "enabled ExtINT on CPU#%d\n",
1270 smp_processor_id());
1272 value
= APIC_DM_EXTINT
| APIC_LVT_MASKED
;
1273 apic_printk(APIC_VERBOSE
, "masked ExtINT on CPU#%d\n",
1274 smp_processor_id());
1276 apic_write(APIC_LVT0
, value
);
1279 * only the BP should see the LINT1 NMI signal, obviously.
1281 if (!smp_processor_id())
1282 value
= APIC_DM_NMI
;
1284 value
= APIC_DM_NMI
| APIC_LVT_MASKED
;
1285 if (!lapic_is_integrated()) /* 82489DX */
1286 value
|= APIC_LVT_LEVEL_TRIGGER
;
1287 apic_write(APIC_LVT1
, value
);
1292 void __cpuinit
end_local_APIC_setup(void)
1296 #ifdef CONFIG_X86_32
1299 /* Disable the local apic timer */
1300 value
= apic_read(APIC_LVTT
);
1301 value
|= (APIC_LVT_MASKED
| LOCAL_TIMER_VECTOR
);
1302 apic_write(APIC_LVTT
, value
);
1306 setup_apic_nmi_watchdog(NULL
);
1311 void check_x2apic(void)
1315 rdmsr(MSR_IA32_APICBASE
, msr
, msr2
);
1317 if (msr
& X2APIC_ENABLE
) {
1318 pr_info("x2apic enabled by BIOS, switching to x2apic ops\n");
1319 x2apic_preenabled
= x2apic
= 1;
1320 apic_ops
= &x2apic_ops
;
1324 void enable_x2apic(void)
1328 rdmsr(MSR_IA32_APICBASE
, msr
, msr2
);
1329 if (!(msr
& X2APIC_ENABLE
)) {
1330 pr_info("Enabling x2apic\n");
1331 wrmsr(MSR_IA32_APICBASE
, msr
| X2APIC_ENABLE
, 0);
1335 void __init
enable_IR_x2apic(void)
1337 #ifdef CONFIG_INTR_REMAP
1339 unsigned long flags
;
1341 if (!cpu_has_x2apic
)
1344 if (!x2apic_preenabled
&& disable_x2apic
) {
1345 pr_info("Skipped enabling x2apic and Interrupt-remapping "
1346 "because of nox2apic\n");
1350 if (x2apic_preenabled
&& disable_x2apic
)
1351 panic("Bios already enabled x2apic, can't enforce nox2apic");
1353 if (!x2apic_preenabled
&& skip_ioapic_setup
) {
1354 pr_info("Skipped enabling x2apic and Interrupt-remapping "
1355 "because of skipping io-apic setup\n");
1359 ret
= dmar_table_init();
1361 pr_info("dmar_table_init() failed with %d:\n", ret
);
1363 if (x2apic_preenabled
)
1364 panic("x2apic enabled by bios. But IR enabling failed");
1366 pr_info("Not enabling x2apic,Intr-remapping\n");
1370 local_irq_save(flags
);
1373 ret
= save_mask_IO_APIC_setup();
1375 pr_info("Saving IO-APIC state failed: %d\n", ret
);
1379 ret
= enable_intr_remapping(1);
1381 if (ret
&& x2apic_preenabled
) {
1382 local_irq_restore(flags
);
1383 panic("x2apic enabled by bios. But IR enabling failed");
1391 apic_ops
= &x2apic_ops
;
1398 * IR enabling failed
1400 restore_IO_APIC_setup();
1402 reinit_intr_remapped_IO_APIC(x2apic_preenabled
);
1406 local_irq_restore(flags
);
1409 if (!x2apic_preenabled
)
1410 pr_info("Enabled x2apic and interrupt-remapping\n");
1412 pr_info("Enabled Interrupt-remapping\n");
1414 pr_err("Failed to enable Interrupt-remapping and x2apic\n");
1416 if (!cpu_has_x2apic
)
1419 if (x2apic_preenabled
)
1420 panic("x2apic enabled prior OS handover,"
1421 " enable CONFIG_INTR_REMAP");
1423 pr_info("Enable CONFIG_INTR_REMAP for enabling intr-remapping "
1429 #endif /* HAVE_X2APIC */
1431 #ifdef CONFIG_X86_64
1433 * Detect and enable local APICs on non-SMP boards.
1434 * Original code written by Keir Fraser.
1435 * On AMD64 we trust the BIOS - if it says no APIC it is likely
1436 * not correctly set up (usually the APIC timer won't work etc.)
1438 static int __init
detect_init_APIC(void)
1440 if (!cpu_has_apic
) {
1441 pr_info("No local APIC present\n");
1445 mp_lapic_addr
= APIC_DEFAULT_PHYS_BASE
;
1446 boot_cpu_physical_apicid
= 0;
1451 * Detect and initialize APIC
1453 static int __init
detect_init_APIC(void)
1457 /* Disabled by kernel option? */
1461 switch (boot_cpu_data
.x86_vendor
) {
1462 case X86_VENDOR_AMD
:
1463 if ((boot_cpu_data
.x86
== 6 && boot_cpu_data
.x86_model
> 1) ||
1464 (boot_cpu_data
.x86
>= 15))
1467 case X86_VENDOR_INTEL
:
1468 if (boot_cpu_data
.x86
== 6 || boot_cpu_data
.x86
== 15 ||
1469 (boot_cpu_data
.x86
== 5 && cpu_has_apic
))
1476 if (!cpu_has_apic
) {
1478 * Over-ride BIOS and try to enable the local APIC only if
1479 * "lapic" specified.
1481 if (!force_enable_local_apic
) {
1482 pr_info("Local APIC disabled by BIOS -- "
1483 "you can enable it with \"lapic\"\n");
1487 * Some BIOSes disable the local APIC in the APIC_BASE
1488 * MSR. This can only be done in software for Intel P6 or later
1489 * and AMD K7 (Model > 1) or later.
1491 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1492 if (!(l
& MSR_IA32_APICBASE_ENABLE
)) {
1493 pr_info("Local APIC disabled by BIOS -- reenabling.\n");
1494 l
&= ~MSR_IA32_APICBASE_BASE
;
1495 l
|= MSR_IA32_APICBASE_ENABLE
| APIC_DEFAULT_PHYS_BASE
;
1496 wrmsr(MSR_IA32_APICBASE
, l
, h
);
1497 enabled_via_apicbase
= 1;
1501 * The APIC feature bit should now be enabled
1504 features
= cpuid_edx(1);
1505 if (!(features
& (1 << X86_FEATURE_APIC
))) {
1506 pr_warning("Could not enable APIC!\n");
1509 set_cpu_cap(&boot_cpu_data
, X86_FEATURE_APIC
);
1510 mp_lapic_addr
= APIC_DEFAULT_PHYS_BASE
;
1512 /* The BIOS may have set up the APIC at some other address */
1513 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1514 if (l
& MSR_IA32_APICBASE_ENABLE
)
1515 mp_lapic_addr
= l
& MSR_IA32_APICBASE_BASE
;
1517 pr_info("Found and enabled local APIC!\n");
1524 pr_info("No local APIC present or hardware disabled\n");
1529 #ifdef CONFIG_X86_64
1530 void __init
early_init_lapic_mapping(void)
1532 unsigned long phys_addr
;
1535 * If no local APIC can be found then go out
1536 * : it means there is no mpatable and MADT
1538 if (!smp_found_config
)
1541 phys_addr
= mp_lapic_addr
;
1543 set_fixmap_nocache(FIX_APIC_BASE
, phys_addr
);
1544 apic_printk(APIC_VERBOSE
, "mapped APIC to %16lx (%16lx)\n",
1545 APIC_BASE
, phys_addr
);
1548 * Fetch the APIC ID of the BSP in case we have a
1549 * default configuration (or the MP table is broken).
1551 boot_cpu_physical_apicid
= read_apic_id();
1556 * init_apic_mappings - initialize APIC mappings
1558 void __init
init_apic_mappings(void)
1562 boot_cpu_physical_apicid
= read_apic_id();
1568 * If no local APIC can be found then set up a fake all
1569 * zeroes page to simulate the local APIC and another
1570 * one for the IO-APIC.
1572 if (!smp_found_config
&& detect_init_APIC()) {
1573 apic_phys
= (unsigned long) alloc_bootmem_pages(PAGE_SIZE
);
1574 apic_phys
= __pa(apic_phys
);
1576 apic_phys
= mp_lapic_addr
;
1578 set_fixmap_nocache(FIX_APIC_BASE
, apic_phys
);
1579 apic_printk(APIC_VERBOSE
, "mapped APIC to %08lx (%08lx)\n",
1580 APIC_BASE
, apic_phys
);
1583 * Fetch the APIC ID of the BSP in case we have a
1584 * default configuration (or the MP table is broken).
1586 if (boot_cpu_physical_apicid
== -1U)
1587 boot_cpu_physical_apicid
= read_apic_id();
1591 * This initializes the IO-APIC and APIC hardware if this is
1594 int apic_version
[MAX_APICS
];
1596 int __init
APIC_init_uniprocessor(void)
1599 pr_info("Apic disabled\n");
1602 #ifdef CONFIG_X86_64
1603 if (!cpu_has_apic
) {
1605 pr_info("Apic disabled by BIOS\n");
1609 if (!smp_found_config
&& !cpu_has_apic
)
1613 * Complain if the BIOS pretends there is one.
1615 if (!cpu_has_apic
&&
1616 APIC_INTEGRATED(apic_version
[boot_cpu_physical_apicid
])) {
1617 pr_err("BIOS bug, local APIC 0x%x not detected!...\n",
1618 boot_cpu_physical_apicid
);
1619 clear_cpu_cap(&boot_cpu_data
, X86_FEATURE_APIC
);
1627 #ifdef CONFIG_X86_64
1628 default_setup_apic_routing();
1631 verify_local_APIC();
1634 #ifdef CONFIG_X86_64
1635 apic_write(APIC_ID
, SET_APIC_ID(boot_cpu_physical_apicid
));
1638 * Hack: In case of kdump, after a crash, kernel might be booting
1639 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid
1640 * might be zero if read from MP tables. Get it from LAPIC.
1642 # ifdef CONFIG_CRASH_DUMP
1643 boot_cpu_physical_apicid
= read_apic_id();
1646 physid_set_mask_of_physid(boot_cpu_physical_apicid
, &phys_cpu_present_map
);
1649 #ifdef CONFIG_X86_IO_APIC
1651 * Now enable IO-APICs, actually call clear_IO_APIC
1652 * We need clear_IO_APIC before enabling error vector
1654 if (!skip_ioapic_setup
&& nr_ioapics
)
1658 end_local_APIC_setup();
1660 #ifdef CONFIG_X86_IO_APIC
1661 if (smp_found_config
&& !skip_ioapic_setup
&& nr_ioapics
)
1665 localise_nmi_watchdog();
1668 localise_nmi_watchdog();
1672 #ifdef CONFIG_X86_64
1673 check_nmi_watchdog();
1680 * Local APIC interrupts
1684 * This interrupt should _never_ happen with our APIC/SMP architecture
1686 void smp_spurious_interrupt(struct pt_regs
*regs
)
1693 * Check if this really is a spurious interrupt and ACK it
1694 * if it is a vectored one. Just in case...
1695 * Spurious interrupts should not be ACKed.
1697 v
= apic_read(APIC_ISR
+ ((SPURIOUS_APIC_VECTOR
& ~0x1f) >> 1));
1698 if (v
& (1 << (SPURIOUS_APIC_VECTOR
& 0x1f)))
1701 inc_irq_stat(irq_spurious_count
);
1703 /* see sw-dev-man vol 3, chapter 7.4.13.5 */
1704 pr_info("spurious APIC interrupt on CPU#%d, "
1705 "should never happen.\n", smp_processor_id());
1710 * This interrupt should never happen with our APIC/SMP architecture
1712 void smp_error_interrupt(struct pt_regs
*regs
)
1718 /* First tickle the hardware, only then report what went on. -- REW */
1719 v
= apic_read(APIC_ESR
);
1720 apic_write(APIC_ESR
, 0);
1721 v1
= apic_read(APIC_ESR
);
1723 atomic_inc(&irq_err_count
);
1726 * Here is what the APIC error bits mean:
1728 * 1: Receive CS error
1729 * 2: Send accept error
1730 * 3: Receive accept error
1732 * 5: Send illegal vector
1733 * 6: Received illegal vector
1734 * 7: Illegal register address
1736 pr_debug("APIC error on CPU%d: %02x(%02x)\n",
1737 smp_processor_id(), v
, v1
);
1742 * connect_bsp_APIC - attach the APIC to the interrupt system
1744 void __init
connect_bsp_APIC(void)
1746 #ifdef CONFIG_X86_32
1749 * Do not trust the local APIC being empty at bootup.
1753 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's
1754 * local APIC to INT and NMI lines.
1756 apic_printk(APIC_VERBOSE
, "leaving PIC mode, "
1757 "enabling APIC mode.\n");
1762 if (apic
->enable_apic_mode
)
1763 apic
->enable_apic_mode();
1767 * disconnect_bsp_APIC - detach the APIC from the interrupt system
1768 * @virt_wire_setup: indicates, whether virtual wire mode is selected
1770 * Virtual wire mode is necessary to deliver legacy interrupts even when the
1773 void disconnect_bsp_APIC(int virt_wire_setup
)
1777 #ifdef CONFIG_X86_32
1780 * Put the board back into PIC mode (has an effect only on
1781 * certain older boards). Note that APIC interrupts, including
1782 * IPIs, won't work beyond this point! The only exception are
1785 apic_printk(APIC_VERBOSE
, "disabling APIC mode, "
1786 "entering PIC mode.\n");
1793 /* Go back to Virtual Wire compatibility mode */
1795 /* For the spurious interrupt use vector F, and enable it */
1796 value
= apic_read(APIC_SPIV
);
1797 value
&= ~APIC_VECTOR_MASK
;
1798 value
|= APIC_SPIV_APIC_ENABLED
;
1800 apic_write(APIC_SPIV
, value
);
1802 if (!virt_wire_setup
) {
1804 * For LVT0 make it edge triggered, active high,
1805 * external and enabled
1807 value
= apic_read(APIC_LVT0
);
1808 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
1809 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
1810 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
1811 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
1812 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_EXTINT
);
1813 apic_write(APIC_LVT0
, value
);
1816 apic_write(APIC_LVT0
, APIC_LVT_MASKED
);
1820 * For LVT1 make it edge triggered, active high,
1823 value
= apic_read(APIC_LVT1
);
1824 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
1825 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
1826 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
1827 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
1828 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_NMI
);
1829 apic_write(APIC_LVT1
, value
);
1832 void __cpuinit
generic_processor_info(int apicid
, int version
)
1839 if (version
== 0x0) {
1840 pr_warning("BIOS bug, APIC version is 0 for CPU#%d! "
1841 "fixing up to 0x10. (tell your hw vendor)\n",
1845 apic_version
[apicid
] = version
;
1847 if (num_processors
>= nr_cpu_ids
) {
1848 int max
= nr_cpu_ids
;
1849 int thiscpu
= max
+ disabled_cpus
;
1852 "ACPI: NR_CPUS/possible_cpus limit of %i reached."
1853 " Processor %d/0x%x ignored.\n", max
, thiscpu
, apicid
);
1860 cpu
= cpumask_next_zero(-1, cpu_present_mask
);
1862 if (version
!= apic_version
[boot_cpu_physical_apicid
])
1864 "ACPI: apic version mismatch, bootcpu: %x cpu %d: %x\n",
1865 apic_version
[boot_cpu_physical_apicid
], cpu
, version
);
1867 physid_set(apicid
, phys_cpu_present_map
);
1868 if (apicid
== boot_cpu_physical_apicid
) {
1870 * x86_bios_cpu_apicid is required to have processors listed
1871 * in same order as logical cpu numbers. Hence the first
1872 * entry is BSP, and so on.
1876 if (apicid
> max_physical_apicid
)
1877 max_physical_apicid
= apicid
;
1879 #ifdef CONFIG_X86_32
1881 * Would be preferable to switch to bigsmp when CONFIG_HOTPLUG_CPU=y
1882 * but we need to work other dependencies like SMP_SUSPEND etc
1883 * before this can be done without some confusion.
1884 * if (CPU_HOTPLUG_ENABLED || num_processors > 8)
1885 * - Ashok Raj <ashok.raj@intel.com>
1887 if (max_physical_apicid
>= 8) {
1888 switch (boot_cpu_data
.x86_vendor
) {
1889 case X86_VENDOR_INTEL
:
1890 if (!APIC_XAPIC(version
)) {
1894 /* If P4 and above fall through */
1895 case X86_VENDOR_AMD
:
1901 #if defined(CONFIG_SMP) || defined(CONFIG_X86_64)
1902 early_per_cpu(x86_cpu_to_apicid
, cpu
) = apicid
;
1903 early_per_cpu(x86_bios_cpu_apicid
, cpu
) = apicid
;
1906 set_cpu_possible(cpu
, true);
1907 set_cpu_present(cpu
, true);
1910 int hard_smp_processor_id(void)
1912 return read_apic_id();
1915 void default_init_apic_ldr(void)
1919 apic_write(APIC_DFR
, APIC_DFR_VALUE
);
1920 val
= apic_read(APIC_LDR
) & ~APIC_LDR_MASK
;
1921 val
|= SET_APIC_LOGICAL_ID(1UL << smp_processor_id());
1922 apic_write(APIC_LDR
, val
);
1925 #ifdef CONFIG_X86_32
1926 int default_apicid_to_node(int logical_apicid
)
1929 return apicid_2_node
[hard_smp_processor_id()];
1943 * 'active' is true if the local APIC was enabled by us and
1944 * not the BIOS; this signifies that we are also responsible
1945 * for disabling it before entering apm/acpi suspend
1948 /* r/w apic fields */
1949 unsigned int apic_id
;
1950 unsigned int apic_taskpri
;
1951 unsigned int apic_ldr
;
1952 unsigned int apic_dfr
;
1953 unsigned int apic_spiv
;
1954 unsigned int apic_lvtt
;
1955 unsigned int apic_lvtpc
;
1956 unsigned int apic_lvt0
;
1957 unsigned int apic_lvt1
;
1958 unsigned int apic_lvterr
;
1959 unsigned int apic_tmict
;
1960 unsigned int apic_tdcr
;
1961 unsigned int apic_thmr
;
1964 static int lapic_suspend(struct sys_device
*dev
, pm_message_t state
)
1966 unsigned long flags
;
1969 if (!apic_pm_state
.active
)
1972 maxlvt
= lapic_get_maxlvt();
1974 apic_pm_state
.apic_id
= apic_read(APIC_ID
);
1975 apic_pm_state
.apic_taskpri
= apic_read(APIC_TASKPRI
);
1976 apic_pm_state
.apic_ldr
= apic_read(APIC_LDR
);
1977 apic_pm_state
.apic_dfr
= apic_read(APIC_DFR
);
1978 apic_pm_state
.apic_spiv
= apic_read(APIC_SPIV
);
1979 apic_pm_state
.apic_lvtt
= apic_read(APIC_LVTT
);
1981 apic_pm_state
.apic_lvtpc
= apic_read(APIC_LVTPC
);
1982 apic_pm_state
.apic_lvt0
= apic_read(APIC_LVT0
);
1983 apic_pm_state
.apic_lvt1
= apic_read(APIC_LVT1
);
1984 apic_pm_state
.apic_lvterr
= apic_read(APIC_LVTERR
);
1985 apic_pm_state
.apic_tmict
= apic_read(APIC_TMICT
);
1986 apic_pm_state
.apic_tdcr
= apic_read(APIC_TDCR
);
1987 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
1989 apic_pm_state
.apic_thmr
= apic_read(APIC_LVTTHMR
);
1992 local_irq_save(flags
);
1993 disable_local_APIC();
1994 local_irq_restore(flags
);
1998 static int lapic_resume(struct sys_device
*dev
)
2001 unsigned long flags
;
2004 if (!apic_pm_state
.active
)
2007 maxlvt
= lapic_get_maxlvt();
2009 local_irq_save(flags
);
2018 * Make sure the APICBASE points to the right address
2020 * FIXME! This will be wrong if we ever support suspend on
2021 * SMP! We'll need to do this as part of the CPU restore!
2023 rdmsr(MSR_IA32_APICBASE
, l
, h
);
2024 l
&= ~MSR_IA32_APICBASE_BASE
;
2025 l
|= MSR_IA32_APICBASE_ENABLE
| mp_lapic_addr
;
2026 wrmsr(MSR_IA32_APICBASE
, l
, h
);
2029 apic_write(APIC_LVTERR
, ERROR_APIC_VECTOR
| APIC_LVT_MASKED
);
2030 apic_write(APIC_ID
, apic_pm_state
.apic_id
);
2031 apic_write(APIC_DFR
, apic_pm_state
.apic_dfr
);
2032 apic_write(APIC_LDR
, apic_pm_state
.apic_ldr
);
2033 apic_write(APIC_TASKPRI
, apic_pm_state
.apic_taskpri
);
2034 apic_write(APIC_SPIV
, apic_pm_state
.apic_spiv
);
2035 apic_write(APIC_LVT0
, apic_pm_state
.apic_lvt0
);
2036 apic_write(APIC_LVT1
, apic_pm_state
.apic_lvt1
);
2037 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
2039 apic_write(APIC_LVTTHMR
, apic_pm_state
.apic_thmr
);
2042 apic_write(APIC_LVTPC
, apic_pm_state
.apic_lvtpc
);
2043 apic_write(APIC_LVTT
, apic_pm_state
.apic_lvtt
);
2044 apic_write(APIC_TDCR
, apic_pm_state
.apic_tdcr
);
2045 apic_write(APIC_TMICT
, apic_pm_state
.apic_tmict
);
2046 apic_write(APIC_ESR
, 0);
2047 apic_read(APIC_ESR
);
2048 apic_write(APIC_LVTERR
, apic_pm_state
.apic_lvterr
);
2049 apic_write(APIC_ESR
, 0);
2050 apic_read(APIC_ESR
);
2052 local_irq_restore(flags
);
2058 * This device has no shutdown method - fully functioning local APICs
2059 * are needed on every CPU up until machine_halt/restart/poweroff.
2062 static struct sysdev_class lapic_sysclass
= {
2064 .resume
= lapic_resume
,
2065 .suspend
= lapic_suspend
,
2068 static struct sys_device device_lapic
= {
2070 .cls
= &lapic_sysclass
,
2073 static void __cpuinit
apic_pm_activate(void)
2075 apic_pm_state
.active
= 1;
2078 static int __init
init_lapic_sysfs(void)
2084 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
2086 error
= sysdev_class_register(&lapic_sysclass
);
2088 error
= sysdev_register(&device_lapic
);
2091 device_initcall(init_lapic_sysfs
);
2093 #else /* CONFIG_PM */
2095 static void apic_pm_activate(void) { }
2097 #endif /* CONFIG_PM */
2099 #ifdef CONFIG_X86_64
2101 * apic_is_clustered_box() -- Check if we can expect good TSC
2103 * Thus far, the major user of this is IBM's Summit2 series:
2105 * Clustered boxes may have unsynced TSC problems if they are
2106 * multi-chassis. Use available data to take a good guess.
2107 * If in doubt, go HPET.
2109 __cpuinit
int apic_is_clustered_box(void)
2111 int i
, clusters
, zeros
;
2113 u16
*bios_cpu_apicid
;
2114 DECLARE_BITMAP(clustermap
, NUM_APIC_CLUSTERS
);
2117 * there is not this kind of box with AMD CPU yet.
2118 * Some AMD box with quadcore cpu and 8 sockets apicid
2119 * will be [4, 0x23] or [8, 0x27] could be thought to
2120 * vsmp box still need checking...
2122 if ((boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
) && !is_vsmp_box())
2125 bios_cpu_apicid
= early_per_cpu_ptr(x86_bios_cpu_apicid
);
2126 bitmap_zero(clustermap
, NUM_APIC_CLUSTERS
);
2128 for (i
= 0; i
< nr_cpu_ids
; i
++) {
2129 /* are we being called early in kernel startup? */
2130 if (bios_cpu_apicid
) {
2131 id
= bios_cpu_apicid
[i
];
2132 } else if (i
< nr_cpu_ids
) {
2134 id
= per_cpu(x86_bios_cpu_apicid
, i
);
2140 if (id
!= BAD_APICID
)
2141 __set_bit(APIC_CLUSTERID(id
), clustermap
);
2144 /* Problem: Partially populated chassis may not have CPUs in some of
2145 * the APIC clusters they have been allocated. Only present CPUs have
2146 * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap.
2147 * Since clusters are allocated sequentially, count zeros only if
2148 * they are bounded by ones.
2152 for (i
= 0; i
< NUM_APIC_CLUSTERS
; i
++) {
2153 if (test_bit(i
, clustermap
)) {
2154 clusters
+= 1 + zeros
;
2160 /* ScaleMP vSMPowered boxes have one cluster per board and TSCs are
2161 * not guaranteed to be synced between boards
2163 if (is_vsmp_box() && clusters
> 1)
2167 * If clusters > 2, then should be multi-chassis.
2168 * May have to revisit this when multi-core + hyperthreaded CPUs come
2169 * out, but AFAIK this will work even for them.
2171 return (clusters
> 2);
2176 * APIC command line parameters
2178 static int __init
setup_disableapic(char *arg
)
2181 setup_clear_cpu_cap(X86_FEATURE_APIC
);
2184 early_param("disableapic", setup_disableapic
);
2186 /* same as disableapic, for compatibility */
2187 static int __init
setup_nolapic(char *arg
)
2189 return setup_disableapic(arg
);
2191 early_param("nolapic", setup_nolapic
);
2193 static int __init
parse_lapic_timer_c2_ok(char *arg
)
2195 local_apic_timer_c2_ok
= 1;
2198 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok
);
2200 static int __init
parse_disable_apic_timer(char *arg
)
2202 disable_apic_timer
= 1;
2205 early_param("noapictimer", parse_disable_apic_timer
);
2207 static int __init
parse_nolapic_timer(char *arg
)
2209 disable_apic_timer
= 1;
2212 early_param("nolapic_timer", parse_nolapic_timer
);
2214 static int __init
apic_set_verbosity(char *arg
)
2217 #ifdef CONFIG_X86_64
2218 skip_ioapic_setup
= 0;
2224 if (strcmp("debug", arg
) == 0)
2225 apic_verbosity
= APIC_DEBUG
;
2226 else if (strcmp("verbose", arg
) == 0)
2227 apic_verbosity
= APIC_VERBOSE
;
2229 pr_warning("APIC Verbosity level %s not recognised"
2230 " use apic=verbose or apic=debug\n", arg
);
2236 early_param("apic", apic_set_verbosity
);
2238 static int __init
lapic_insert_resource(void)
2243 /* Put local APIC into the resource map. */
2244 lapic_resource
.start
= apic_phys
;
2245 lapic_resource
.end
= lapic_resource
.start
+ PAGE_SIZE
- 1;
2246 insert_resource(&iomem_resource
, &lapic_resource
);
2252 * need call insert after e820_reserve_resources()
2253 * that is using request_resource
2255 late_initcall(lapic_insert_resource
);