arch/arm/plat-mxc/include/mach/mx27.h

   1 /*
   2  * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
   3  * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
   4  *
   5  * This contains i.MX27-specific hardware definitions. For those
   6  * hardware pieces that are common between i.MX21 and i.MX27, have a
   7  * look at mx2x.h.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License
  11  * as published by the Free Software Foundation; either version 2
  12  * of the License, or (at your option) any later version.
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
  21  * MA  02110-1301, USA.
  22  */
  23
  24 #ifndef __MACH_MX27_H__
  25 #define __MACH_MX27_H__
  26
  27 #ifndef __ASSEMBLER__
  28 #include <linux/io.h>
  29 #endif
  30
  31 #define MX27_AIPI_BASE_ADDR             0x10000000
  32 #define MX27_AIPI_SIZE                  SZ_1M
  33 #define MX27_DMA_BASE_ADDR                      (MX27_AIPI_BASE_ADDR + 0x01000)
  34 #define MX27_WDOG_BASE_ADDR                     (MX27_AIPI_BASE_ADDR + 0x02000)
  35 #define MX27_GPT1_BASE_ADDR                     (MX27_AIPI_BASE_ADDR + 0x03000)
  36 #define MX27_GPT2_BASE_ADDR                     (MX27_AIPI_BASE_ADDR + 0x04000)
  37 #define MX27_GPT3_BASE_ADDR                     (MX27_AIPI_BASE_ADDR + 0x05000)
  38 #define MX27_PWM_BASE_ADDR                      (MX27_AIPI_BASE_ADDR + 0x06000)
  39 #define MX27_RTC_BASE_ADDR                      (MX27_AIPI_BASE_ADDR + 0x07000)
  40 #define MX27_KPP_BASE_ADDR                      (MX27_AIPI_BASE_ADDR + 0x08000)
  41 #define MX27_OWIRE_BASE_ADDR                    (MX27_AIPI_BASE_ADDR + 0x09000)
  42 #define MX27_UART1_BASE_ADDR                    (MX27_AIPI_BASE_ADDR + 0x0a000)
  43 #define MX27_UART2_BASE_ADDR                    (MX27_AIPI_BASE_ADDR + 0x0b000)
  44 #define MX27_UART3_BASE_ADDR                    (MX27_AIPI_BASE_ADDR + 0x0c000)
  45 #define MX27_UART4_BASE_ADDR                    (MX27_AIPI_BASE_ADDR + 0x0d000)
  46 #define MX27_CSPI1_BASE_ADDR                    (MX27_AIPI_BASE_ADDR + 0x0e000)
  47 #define MX27_CSPI2_BASE_ADDR                    (MX27_AIPI_BASE_ADDR + 0x0f000)
  48 #define MX27_SSI1_BASE_ADDR                     (MX27_AIPI_BASE_ADDR + 0x10000)
  49 #define MX27_SSI2_BASE_ADDR                     (MX27_AIPI_BASE_ADDR + 0x11000)
  50 #define MX27_I2C1_BASE_ADDR                     (MX27_AIPI_BASE_ADDR + 0x12000)
  51 #define MX27_SDHC1_BASE_ADDR                    (MX27_AIPI_BASE_ADDR + 0x13000)
  52 #define MX27_SDHC2_BASE_ADDR                    (MX27_AIPI_BASE_ADDR + 0x14000)
  53 #define MX27_GPIO_BASE_ADDR                     (MX27_AIPI_BASE_ADDR + 0x15000)
  54 #define MX27_GPIO1_BASE_ADDR                    (MX27_GPIO_BASE_ADDR + 0x000)
  55 #define MX27_GPIO2_BASE_ADDR                    (MX27_GPIO_BASE_ADDR + 0x100)
  56 #define MX27_GPIO3_BASE_ADDR                    (MX27_GPIO_BASE_ADDR + 0x200)
  57 #define MX27_GPIO4_BASE_ADDR                    (MX27_GPIO_BASE_ADDR + 0x300)
  58 #define MX27_GPIO5_BASE_ADDR                    (MX27_GPIO_BASE_ADDR + 0x400)
  59 #define MX27_GPIO6_BASE_ADDR                    (MX27_GPIO_BASE_ADDR + 0x500)
  60 #define MX27_AUDMUX_BASE_ADDR                   (MX27_AIPI_BASE_ADDR + 0x16000)
  61 #define MX27_CSPI3_BASE_ADDR                    (MX27_AIPI_BASE_ADDR + 0x17000)
  62 #define MX27_MSHC_BASE_ADDR                     (MX27_AIPI_BASE_ADDR + 0x18000)
  63 #define MX27_GPT4_BASE_ADDR                     (MX27_AIPI_BASE_ADDR + 0x19000)
  64 #define MX27_GPT5_BASE_ADDR                     (MX27_AIPI_BASE_ADDR + 0x1a000)
  65 #define MX27_UART5_BASE_ADDR                    (MX27_AIPI_BASE_ADDR + 0x1b000)
  66 #define MX27_UART6_BASE_ADDR                    (MX27_AIPI_BASE_ADDR + 0x1c000)
  67 #define MX27_I2C2_BASE_ADDR                     (MX27_AIPI_BASE_ADDR + 0x1d000)
  68 #define MX27_SDHC3_BASE_ADDR                    (MX27_AIPI_BASE_ADDR + 0x1e000)
  69 #define MX27_GPT6_BASE_ADDR                     (MX27_AIPI_BASE_ADDR + 0x1f000)
  70 #define MX27_LCDC_BASE_ADDR                     (MX27_AIPI_BASE_ADDR + 0x21000)
  71 #define MX27_SLCDC_BASE_ADDR                    (MX27_AIPI_BASE_ADDR + 0x22000)
  72 #define MX27_VPU_BASE_ADDR                      (MX27_AIPI_BASE_ADDR + 0x23000)
  73 #define MX27_USB_BASE_ADDR                      (MX27_AIPI_BASE_ADDR + 0x24000)
  74 #define MX27_USB_OTG_BASE_ADDR                  (MX27_USB_BASE_ADDR + 0x0000)
  75 #define MX27_USB_HS1_BASE_ADDR                  (MX27_USB_BASE_ADDR + 0x0200)
  76 #define MX27_USB_HS2_BASE_ADDR                  (MX27_USB_BASE_ADDR + 0x0400)
  77 #define MX27_SAHARA_BASE_ADDR                   (MX27_AIPI_BASE_ADDR + 0x25000)
  78 #define MX27_EMMAPP_BASE_ADDR                   (MX27_AIPI_BASE_ADDR + 0x26000)
  79 #define MX27_EMMAPRP_BASE_ADDR                  (MX27_AIPI_BASE_ADDR + 0x26400)
  80 #define MX27_CCM_BASE_ADDR                      (MX27_AIPI_BASE_ADDR + 0x27000)
  81 #define MX27_SYSCTRL_BASE_ADDR                  (MX27_AIPI_BASE_ADDR + 0x27800)
  82 #define MX27_IIM_BASE_ADDR                      (MX27_AIPI_BASE_ADDR + 0x28000)
  83 #define MX27_RTIC_BASE_ADDR                     (MX27_AIPI_BASE_ADDR + 0x2a000)
  84 #define MX27_FEC_BASE_ADDR                      (MX27_AIPI_BASE_ADDR + 0x2b000)
  85 #define MX27_SCC_BASE_ADDR                      (MX27_AIPI_BASE_ADDR + 0x2c000)
  86 #define MX27_ETB_BASE_ADDR                      (MX27_AIPI_BASE_ADDR + 0x3b000)
  87 #define MX27_ETB_RAM_BASE_ADDR                  (MX27_AIPI_BASE_ADDR + 0x3c000)
  88 #define MX27_JAM_BASE_ADDR                      (MX27_AIPI_BASE_ADDR + 0x3e000)
  89 #define MX27_MAX_BASE_ADDR                      (MX27_AIPI_BASE_ADDR + 0x3f000)
  90
  91 #define MX27_AVIC_BASE_ADDR             0x10040000
  92
  93 /* ROM patch */
  94 #define MX27_ROMP_BASE_ADDR             0x10041000
  95
  96 #define MX27_SAHB1_BASE_ADDR            0x80000000
  97 #define MX27_SAHB1_SIZE                 SZ_1M
  98 #define MX27_CSI_BASE_ADDR                      (MX27_SAHB1_BASE_ADDR + 0x0000)
  99 #define MX27_ATA_BASE_ADDR                      (MX27_SAHB1_BASE_ADDR + 0x1000)
 100
 101 /* Memory regions and CS */
 102 #define MX27_SDRAM_BASE_ADDR            0xa0000000
 103 #define MX27_CSD1_BASE_ADDR             0xb0000000
 104
 105 #define MX27_CS0_BASE_ADDR              0xc0000000
 106 #define MX27_CS1_BASE_ADDR              0xc8000000
 107 #define MX27_CS2_BASE_ADDR              0xd0000000
 108 #define MX27_CS3_BASE_ADDR              0xd2000000
 109 #define MX27_CS4_BASE_ADDR              0xd4000000
 110 #define MX27_CS5_BASE_ADDR              0xd6000000
 111
 112 /* NAND, SDRAM, WEIM, M3IF, EMI controllers */
 113 #define MX27_X_MEMC_BASE_ADDR           0xd8000000
 114 #define MX27_X_MEMC_SIZE                SZ_1M
 115 #define MX27_NFC_BASE_ADDR                      (MX27_X_MEMC_BASE_ADDR)
 116 #define MX27_SDRAMC_BASE_ADDR                   (MX27_X_MEMC_BASE_ADDR + 0x1000)
 117 #define MX27_WEIM_BASE_ADDR                     (MX27_X_MEMC_BASE_ADDR + 0x2000)
 118 #define MX27_M3IF_BASE_ADDR                     (MX27_X_MEMC_BASE_ADDR + 0x3000)
 119 #define MX27_PCMCIA_CTL_BASE_ADDR               (MX27_X_MEMC_BASE_ADDR + 0x4000)
 120
 121 #define MX27_WEIM_CSCRx_BASE_ADDR(cs)   (MX27_WEIM_BASE_ADDR + (cs) * 0x10)
 122 #define MX27_WEIM_CSCRxU(cs)                    (MX27_WEIM_CSCRx_BASE_ADDR(cs))
 123 #define MX27_WEIM_CSCRxL(cs)                    (MX27_WEIM_CSCRx_BASE_ADDR(cs) + 0x4)
 124 #define MX27_WEIM_CSCRxA(cs)                    (MX27_WEIM_CSCRx_BASE_ADDR(cs) + 0x8)
 125
 126 #define MX27_PCMCIA_MEM_BASE_ADDR       0xdc000000
 127
 128 /* IRAM */
 129 #define MX27_IRAM_BASE_ADDR             0xffff4c00      /* internal ram */
 130
 131 #define MX27_IO_P2V(x)                  IMX_IO_P2V(x)
 132 #define MX27_IO_ADDRESS(x)              IOMEM(MX27_IO_P2V(x))
 133
 134 #ifndef __ASSEMBLER__
 135 static inline void mx27_setup_weimcs(size_t cs,
 136                 unsigned upper, unsigned lower, unsigned addional)
 137 {
 138         __raw_writel(upper, MX27_IO_ADDRESS(MX27_WEIM_CSCRxU(cs)));
 139         __raw_writel(lower, MX27_IO_ADDRESS(MX27_WEIM_CSCRxL(cs)));
 140         __raw_writel(addional, MX27_IO_ADDRESS(MX27_WEIM_CSCRxA(cs)));
 141 }
 142 #endif
 143
 144 /* fixed interrupt numbers */
 145 #define MX27_INT_I2C2           1
 146 #define MX27_INT_GPT6           2
 147 #define MX27_INT_GPT5           3
 148 #define MX27_INT_GPT4           4
 149 #define MX27_INT_RTIC           5
 150 #define MX27_INT_CSPI3          6
 151 #define MX27_INT_SDHC           7
 152 #define MX27_INT_GPIO           8
 153 #define MX27_INT_SDHC3          9
 154 #define MX27_INT_SDHC2          10
 155 #define MX27_INT_SDHC1          11
 156 #define MX27_INT_I2C1           12
 157 #define MX27_INT_SSI2           13
 158 #define MX27_INT_SSI1           14
 159 #define MX27_INT_CSPI2          15
 160 #define MX27_INT_CSPI1          16
 161 #define MX27_INT_UART4          17
 162 #define MX27_INT_UART3          18
 163 #define MX27_INT_UART2          19
 164 #define MX27_INT_UART1          20
 165 #define MX27_INT_KPP            21
 166 #define MX27_INT_RTC            22
 167 #define MX27_INT_PWM            23
 168 #define MX27_INT_GPT3           24
 169 #define MX27_INT_GPT2           25
 170 #define MX27_INT_GPT1           26
 171 #define MX27_INT_WDOG           27
 172 #define MX27_INT_PCMCIA         28
 173 #define MX27_INT_NFC            29
 174 #define MX27_INT_ATA            30
 175 #define MX27_INT_CSI            31
 176 #define MX27_INT_DMACH0         32
 177 #define MX27_INT_DMACH1         33
 178 #define MX27_INT_DMACH2         34
 179 #define MX27_INT_DMACH3         35
 180 #define MX27_INT_DMACH4         36
 181 #define MX27_INT_DMACH5         37
 182 #define MX27_INT_DMACH6         38
 183 #define MX27_INT_DMACH7         39
 184 #define MX27_INT_DMACH8         40
 185 #define MX27_INT_DMACH9         41
 186 #define MX27_INT_DMACH10        42
 187 #define MX27_INT_DMACH11        43
 188 #define MX27_INT_DMACH12        44
 189 #define MX27_INT_DMACH13        45
 190 #define MX27_INT_DMACH14        46
 191 #define MX27_INT_DMACH15        47
 192 #define MX27_INT_UART6          48
 193 #define MX27_INT_UART5          49
 194 #define MX27_INT_FEC            50
 195 #define MX27_INT_EMMAPRP        51
 196 #define MX27_INT_EMMAPP         52
 197 #define MX27_INT_VPU            53
 198 #define MX27_INT_USB_HS1        54
 199 #define MX27_INT_USB_HS2        55
 200 #define MX27_INT_USB_OTG        56
 201 #define MX27_INT_SCC_SMN        57
 202 #define MX27_INT_SCC_SCM        58
 203 #define MX27_INT_SAHARA         59
 204 #define MX27_INT_SLCDC          60
 205 #define MX27_INT_LCDC           61
 206 #define MX27_INT_IIM            62
 207 #define MX27_INT_CCM            63
 208
 209 /* fixed DMA request numbers */
 210 #define MX27_DMA_REQ_CSPI3_RX   1
 211 #define MX27_DMA_REQ_CSPI3_TX   2
 212 #define MX27_DMA_REQ_EXT        3
 213 #define MX27_DMA_REQ_MSHC       4
 214 #define MX27_DMA_REQ_SDHC2      6
 215 #define MX27_DMA_REQ_SDHC1      7
 216 #define MX27_DMA_REQ_SSI2_RX0   8
 217 #define MX27_DMA_REQ_SSI2_TX0   9
 218 #define MX27_DMA_REQ_SSI2_RX1   10
 219 #define MX27_DMA_REQ_SSI2_TX1   11
 220 #define MX27_DMA_REQ_SSI1_RX0   12
 221 #define MX27_DMA_REQ_SSI1_TX0   13
 222 #define MX27_DMA_REQ_SSI1_RX1   14
 223 #define MX27_DMA_REQ_SSI1_TX1   15
 224 #define MX27_DMA_REQ_CSPI2_RX   16
 225 #define MX27_DMA_REQ_CSPI2_TX   17
 226 #define MX27_DMA_REQ_CSPI1_RX   18
 227 #define MX27_DMA_REQ_CSPI1_TX   19
 228 #define MX27_DMA_REQ_UART4_RX   20
 229 #define MX27_DMA_REQ_UART4_TX   21
 230 #define MX27_DMA_REQ_UART3_RX   22
 231 #define MX27_DMA_REQ_UART3_TX   23
 232 #define MX27_DMA_REQ_UART2_RX   24
 233 #define MX27_DMA_REQ_UART2_TX   25
 234 #define MX27_DMA_REQ_UART1_RX   26
 235 #define MX27_DMA_REQ_UART1_TX   27
 236 #define MX27_DMA_REQ_ATA_TX     28
 237 #define MX27_DMA_REQ_ATA_RCV    29
 238 #define MX27_DMA_REQ_CSI_STAT   30
 239 #define MX27_DMA_REQ_CSI_RX     31
 240 #define MX27_DMA_REQ_UART5_TX   32
 241 #define MX27_DMA_REQ_UART5_RX   33
 242 #define MX27_DMA_REQ_UART6_TX   34
 243 #define MX27_DMA_REQ_UART6_RX   35
 244 #define MX27_DMA_REQ_SDHC3      36
 245 #define MX27_DMA_REQ_NFC        37
 246
 247 #ifndef __ASSEMBLY__
 248 extern int mx27_revision(void);
 249 #endif
 250
 251 #endif /* ifndef __MACH_MX27_H__ */