arch/arm/mach-omap2/omap_hwmod_2420_data.c

   1 /*
   2  * omap_hwmod_2420_data.c - hardware modules present on the OMAP2420 chips
   3  *
   4  * Copyright (C) 2009-2010 Nokia Corporation
   5  * Paul Walmsley
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  *
  11  * XXX handle crossbar/shared link difference for L3?
  12  * XXX these should be marked initdata for multi-OMAP kernels
  13  */
  14 #include <plat/omap_hwmod.h>
  15 #include <mach/irqs.h>
  16 #include <plat/cpu.h>
  17 #include <plat/dma.h>
  18 #include <plat/serial.h>
  19
  20 #include "omap_hwmod_common_data.h"
  21
  22 #include "prm-regbits-24xx.h"
  23 #include "cm-regbits-24xx.h"
  24
  25 /*
  26  * OMAP2420 hardware module integration data
  27  *
  28  * ALl of the data in this section should be autogeneratable from the
  29  * TI hardware database or other technical documentation.  Data that
  30  * is driver-specific or driver-kernel integration-specific belongs
  31  * elsewhere.
  32  */
  33
  34 static struct omap_hwmod omap2420_mpu_hwmod;
  35 static struct omap_hwmod omap2420_iva_hwmod;
  36 static struct omap_hwmod omap2420_l3_main_hwmod;
  37 static struct omap_hwmod omap2420_l4_core_hwmod;
  38 static struct omap_hwmod omap2420_wd_timer2_hwmod;
  39
  40 /* L3 -> L4_CORE interface */
  41 static struct omap_hwmod_ocp_if omap2420_l3_main__l4_core = {
  42         .master = &omap2420_l3_main_hwmod,
  43         .slave  = &omap2420_l4_core_hwmod,
  44         .user   = OCP_USER_MPU | OCP_USER_SDMA,
  45 };
  46
  47 /* MPU -> L3 interface */
  48 static struct omap_hwmod_ocp_if omap2420_mpu__l3_main = {
  49         .master = &omap2420_mpu_hwmod,
  50         .slave  = &omap2420_l3_main_hwmod,
  51         .user   = OCP_USER_MPU,
  52 };
  53
  54 /* Slave interfaces on the L3 interconnect */
  55 static struct omap_hwmod_ocp_if *omap2420_l3_main_slaves[] = {
  56         &omap2420_mpu__l3_main,
  57 };
  58
  59 /* Master interfaces on the L3 interconnect */
  60 static struct omap_hwmod_ocp_if *omap2420_l3_main_masters[] = {
  61         &omap2420_l3_main__l4_core,
  62 };
  63
  64 /* L3 */
  65 static struct omap_hwmod omap2420_l3_main_hwmod = {
  66         .name           = "l3_main",
  67         .class          = &l3_hwmod_class,
  68         .masters        = omap2420_l3_main_masters,
  69         .masters_cnt    = ARRAY_SIZE(omap2420_l3_main_masters),
  70         .slaves         = omap2420_l3_main_slaves,
  71         .slaves_cnt     = ARRAY_SIZE(omap2420_l3_main_slaves),
  72         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
  73         .flags          = HWMOD_NO_IDLEST,
  74 };
  75
  76 static struct omap_hwmod omap2420_l4_wkup_hwmod;
  77 static struct omap_hwmod omap2420_uart1_hwmod;
  78 static struct omap_hwmod omap2420_uart2_hwmod;
  79 static struct omap_hwmod omap2420_uart3_hwmod;
  80
  81 /* L4_CORE -> L4_WKUP interface */
  82 static struct omap_hwmod_ocp_if omap2420_l4_core__l4_wkup = {
  83         .master = &omap2420_l4_core_hwmod,
  84         .slave  = &omap2420_l4_wkup_hwmod,
  85         .user   = OCP_USER_MPU | OCP_USER_SDMA,
  86 };
  87
  88 /* L4 CORE -> UART1 interface */
  89 static struct omap_hwmod_addr_space omap2420_uart1_addr_space[] = {
  90         {
  91                 .pa_start       = OMAP2_UART1_BASE,
  92                 .pa_end         = OMAP2_UART1_BASE + SZ_8K - 1,
  93                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
  94         },
  95 };
  96
  97 static struct omap_hwmod_ocp_if omap2_l4_core__uart1 = {
  98         .master         = &omap2420_l4_core_hwmod,
  99         .slave          = &omap2420_uart1_hwmod,
 100         .clk            = "uart1_ick",
 101         .addr           = omap2420_uart1_addr_space,
 102         .addr_cnt       = ARRAY_SIZE(omap2420_uart1_addr_space),
 103         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 104 };
 105
 106 /* L4 CORE -> UART2 interface */
 107 static struct omap_hwmod_addr_space omap2420_uart2_addr_space[] = {
 108         {
 109                 .pa_start       = OMAP2_UART2_BASE,
 110                 .pa_end         = OMAP2_UART2_BASE + SZ_1K - 1,
 111                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
 112         },
 113 };
 114
 115 static struct omap_hwmod_ocp_if omap2_l4_core__uart2 = {
 116         .master         = &omap2420_l4_core_hwmod,
 117         .slave          = &omap2420_uart2_hwmod,
 118         .clk            = "uart2_ick",
 119         .addr           = omap2420_uart2_addr_space,
 120         .addr_cnt       = ARRAY_SIZE(omap2420_uart2_addr_space),
 121         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 122 };
 123
 124 /* L4 PER -> UART3 interface */
 125 static struct omap_hwmod_addr_space omap2420_uart3_addr_space[] = {
 126         {
 127                 .pa_start       = OMAP2_UART3_BASE,
 128                 .pa_end         = OMAP2_UART3_BASE + SZ_1K - 1,
 129                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
 130         },
 131 };
 132
 133 static struct omap_hwmod_ocp_if omap2_l4_core__uart3 = {
 134         .master         = &omap2420_l4_core_hwmod,
 135         .slave          = &omap2420_uart3_hwmod,
 136         .clk            = "uart3_ick",
 137         .addr           = omap2420_uart3_addr_space,
 138         .addr_cnt       = ARRAY_SIZE(omap2420_uart3_addr_space),
 139         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 140 };
 141
 142 /* Slave interfaces on the L4_CORE interconnect */
 143 static struct omap_hwmod_ocp_if *omap2420_l4_core_slaves[] = {
 144         &omap2420_l3_main__l4_core,
 145 };
 146
 147 /* Master interfaces on the L4_CORE interconnect */
 148 static struct omap_hwmod_ocp_if *omap2420_l4_core_masters[] = {
 149         &omap2420_l4_core__l4_wkup,
 150         &omap2_l4_core__uart1,
 151         &omap2_l4_core__uart2,
 152         &omap2_l4_core__uart3,
 153 };
 154
 155 /* L4 CORE */
 156 static struct omap_hwmod omap2420_l4_core_hwmod = {
 157         .name           = "l4_core",
 158         .class          = &l4_hwmod_class,
 159         .masters        = omap2420_l4_core_masters,
 160         .masters_cnt    = ARRAY_SIZE(omap2420_l4_core_masters),
 161         .slaves         = omap2420_l4_core_slaves,
 162         .slaves_cnt     = ARRAY_SIZE(omap2420_l4_core_slaves),
 163         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 164         .flags          = HWMOD_NO_IDLEST,
 165 };
 166
 167 /* Slave interfaces on the L4_WKUP interconnect */
 168 static struct omap_hwmod_ocp_if *omap2420_l4_wkup_slaves[] = {
 169         &omap2420_l4_core__l4_wkup,
 170 };
 171
 172 /* Master interfaces on the L4_WKUP interconnect */
 173 static struct omap_hwmod_ocp_if *omap2420_l4_wkup_masters[] = {
 174 };
 175
 176 /* L4 WKUP */
 177 static struct omap_hwmod omap2420_l4_wkup_hwmod = {
 178         .name           = "l4_wkup",
 179         .class          = &l4_hwmod_class,
 180         .masters        = omap2420_l4_wkup_masters,
 181         .masters_cnt    = ARRAY_SIZE(omap2420_l4_wkup_masters),
 182         .slaves         = omap2420_l4_wkup_slaves,
 183         .slaves_cnt     = ARRAY_SIZE(omap2420_l4_wkup_slaves),
 184         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 185         .flags          = HWMOD_NO_IDLEST,
 186 };
 187
 188 /* Master interfaces on the MPU device */
 189 static struct omap_hwmod_ocp_if *omap2420_mpu_masters[] = {
 190         &omap2420_mpu__l3_main,
 191 };
 192
 193 /* MPU */
 194 static struct omap_hwmod omap2420_mpu_hwmod = {
 195         .name           = "mpu",
 196         .class          = &mpu_hwmod_class,
 197         .main_clk       = "mpu_ck",
 198         .masters        = omap2420_mpu_masters,
 199         .masters_cnt    = ARRAY_SIZE(omap2420_mpu_masters),
 200         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 201 };
 202
 203 /*
 204  * IVA1 interface data
 205  */
 206
 207 /* IVA <- L3 interface */
 208 static struct omap_hwmod_ocp_if omap2420_l3__iva = {
 209         .master         = &omap2420_l3_main_hwmod,
 210         .slave          = &omap2420_iva_hwmod,
 211         .clk            = "iva1_ifck",
 212         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 213 };
 214
 215 static struct omap_hwmod_ocp_if *omap2420_iva_masters[] = {
 216         &omap2420_l3__iva,
 217 };
 218
 219 /*
 220  * IVA2 (IVA2)
 221  */
 222
 223 static struct omap_hwmod omap2420_iva_hwmod = {
 224         .name           = "iva",
 225         .class          = &iva_hwmod_class,
 226         .masters        = omap2420_iva_masters,
 227         .masters_cnt    = ARRAY_SIZE(omap2420_iva_masters),
 228         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
 229 };
 230
 231 /* l4_wkup -> wd_timer2 */
 232 static struct omap_hwmod_addr_space omap2420_wd_timer2_addrs[] = {
 233         {
 234                 .pa_start       = 0x48022000,
 235                 .pa_end         = 0x4802207f,
 236                 .flags          = ADDR_TYPE_RT
 237         },
 238 };
 239
 240 static struct omap_hwmod_ocp_if omap2420_l4_wkup__wd_timer2 = {
 241         .master         = &omap2420_l4_wkup_hwmod,
 242         .slave          = &omap2420_wd_timer2_hwmod,
 243         .clk            = "mpu_wdt_ick",
 244         .addr           = omap2420_wd_timer2_addrs,
 245         .addr_cnt       = ARRAY_SIZE(omap2420_wd_timer2_addrs),
 246         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 247 };
 248
 249 /*
 250  * 'wd_timer' class
 251  * 32-bit watchdog upward counter that generates a pulse on the reset pin on
 252  * overflow condition
 253  */
 254
 255 static struct omap_hwmod_class_sysconfig omap2420_wd_timer_sysc = {
 256         .rev_offs       = 0x0000,
 257         .sysc_offs      = 0x0010,
 258         .syss_offs      = 0x0014,
 259         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET |
 260                            SYSC_HAS_AUTOIDLE),
 261         .sysc_fields    = &omap_hwmod_sysc_type1,
 262 };
 263
 264 static struct omap_hwmod_class omap2420_wd_timer_hwmod_class = {
 265         .name = "wd_timer",
 266         .sysc = &omap2420_wd_timer_sysc,
 267 };
 268
 269 /* wd_timer2 */
 270 static struct omap_hwmod_ocp_if *omap2420_wd_timer2_slaves[] = {
 271         &omap2420_l4_wkup__wd_timer2,
 272 };
 273
 274 static struct omap_hwmod omap2420_wd_timer2_hwmod = {
 275         .name           = "wd_timer2",
 276         .class          = &omap2420_wd_timer_hwmod_class,
 277         .main_clk       = "mpu_wdt_fck",
 278         .prcm           = {
 279                 .omap2 = {
 280                         .prcm_reg_id = 1,
 281                         .module_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
 282                         .module_offs = WKUP_MOD,
 283                         .idlest_reg_id = 1,
 284                         .idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT,
 285                 },
 286         },
 287         .slaves         = omap2420_wd_timer2_slaves,
 288         .slaves_cnt     = ARRAY_SIZE(omap2420_wd_timer2_slaves),
 289         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 290 };
 291
 292 /* UART */
 293
 294 static struct omap_hwmod_class_sysconfig uart_sysc = {
 295         .rev_offs       = 0x50,
 296         .sysc_offs      = 0x54,
 297         .syss_offs      = 0x58,
 298         .sysc_flags     = (SYSC_HAS_SIDLEMODE |
 299                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 300                            SYSC_HAS_AUTOIDLE),
 301         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 302         .sysc_fields    = &omap_hwmod_sysc_type1,
 303 };
 304
 305 static struct omap_hwmod_class uart_class = {
 306         .name = "uart",
 307         .sysc = &uart_sysc,
 308 };
 309
 310 /* UART1 */
 311
 312 static struct omap_hwmod_irq_info uart1_mpu_irqs[] = {
 313         { .irq = INT_24XX_UART1_IRQ, },
 314 };
 315
 316 static struct omap_hwmod_dma_info uart1_sdma_reqs[] = {
 317         { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, },
 318         { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, },
 319 };
 320
 321 static struct omap_hwmod_ocp_if *omap2420_uart1_slaves[] = {
 322         &omap2_l4_core__uart1,
 323 };
 324
 325 static struct omap_hwmod omap2420_uart1_hwmod = {
 326         .name           = "uart1",
 327         .mpu_irqs       = uart1_mpu_irqs,
 328         .mpu_irqs_cnt   = ARRAY_SIZE(uart1_mpu_irqs),
 329         .sdma_reqs      = uart1_sdma_reqs,
 330         .sdma_reqs_cnt  = ARRAY_SIZE(uart1_sdma_reqs),
 331         .main_clk       = "uart1_fck",
 332         .prcm           = {
 333                 .omap2 = {
 334                         .module_offs = CORE_MOD,
 335                         .prcm_reg_id = 1,
 336                         .module_bit = OMAP24XX_EN_UART1_SHIFT,
 337                         .idlest_reg_id = 1,
 338                         .idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT,
 339                 },
 340         },
 341         .slaves         = omap2420_uart1_slaves,
 342         .slaves_cnt     = ARRAY_SIZE(omap2420_uart1_slaves),
 343         .class          = &uart_class,
 344         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 345 };
 346
 347 /* UART2 */
 348
 349 static struct omap_hwmod_irq_info uart2_mpu_irqs[] = {
 350         { .irq = INT_24XX_UART2_IRQ, },
 351 };
 352
 353 static struct omap_hwmod_dma_info uart2_sdma_reqs[] = {
 354         { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, },
 355         { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, },
 356 };
 357
 358 static struct omap_hwmod_ocp_if *omap2420_uart2_slaves[] = {
 359         &omap2_l4_core__uart2,
 360 };
 361
 362 static struct omap_hwmod omap2420_uart2_hwmod = {
 363         .name           = "uart2",
 364         .mpu_irqs       = uart2_mpu_irqs,
 365         .mpu_irqs_cnt   = ARRAY_SIZE(uart2_mpu_irqs),
 366         .sdma_reqs      = uart2_sdma_reqs,
 367         .sdma_reqs_cnt  = ARRAY_SIZE(uart2_sdma_reqs),
 368         .main_clk       = "uart2_fck",
 369         .prcm           = {
 370                 .omap2 = {
 371                         .module_offs = CORE_MOD,
 372                         .prcm_reg_id = 1,
 373                         .module_bit = OMAP24XX_EN_UART2_SHIFT,
 374                         .idlest_reg_id = 1,
 375                         .idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT,
 376                 },
 377         },
 378         .slaves         = omap2420_uart2_slaves,
 379         .slaves_cnt     = ARRAY_SIZE(omap2420_uart2_slaves),
 380         .class          = &uart_class,
 381         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 382 };
 383
 384 /* UART3 */
 385
 386 static struct omap_hwmod_irq_info uart3_mpu_irqs[] = {
 387         { .irq = INT_24XX_UART3_IRQ, },
 388 };
 389
 390 static struct omap_hwmod_dma_info uart3_sdma_reqs[] = {
 391         { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, },
 392         { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, },
 393 };
 394
 395 static struct omap_hwmod_ocp_if *omap2420_uart3_slaves[] = {
 396         &omap2_l4_core__uart3,
 397 };
 398
 399 static struct omap_hwmod omap2420_uart3_hwmod = {
 400         .name           = "uart3",
 401         .mpu_irqs       = uart3_mpu_irqs,
 402         .mpu_irqs_cnt   = ARRAY_SIZE(uart3_mpu_irqs),
 403         .sdma_reqs      = uart3_sdma_reqs,
 404         .sdma_reqs_cnt  = ARRAY_SIZE(uart3_sdma_reqs),
 405         .main_clk       = "uart3_fck",
 406         .prcm           = {
 407                 .omap2 = {
 408                         .module_offs = CORE_MOD,
 409                         .prcm_reg_id = 2,
 410                         .module_bit = OMAP24XX_EN_UART3_SHIFT,
 411                         .idlest_reg_id = 2,
 412                         .idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT,
 413                 },
 414         },
 415         .slaves         = omap2420_uart3_slaves,
 416         .slaves_cnt     = ARRAY_SIZE(omap2420_uart3_slaves),
 417         .class          = &uart_class,
 418         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 419 };
 420
 421 static __initdata struct omap_hwmod *omap2420_hwmods[] = {
 422         &omap2420_l3_main_hwmod,
 423         &omap2420_l4_core_hwmod,
 424         &omap2420_l4_wkup_hwmod,
 425         &omap2420_mpu_hwmod,
 426         &omap2420_iva_hwmod,
 427         &omap2420_wd_timer2_hwmod,
 428         &omap2420_uart1_hwmod,
 429         &omap2420_uart2_hwmod,
 430         &omap2420_uart3_hwmod,
 431         NULL,
 432 };
 433
 434 int __init omap2420_hwmod_init(void)
 435 {
 436         return omap_hwmod_init(omap2420_hwmods);
 437 }
 438
 439