arch/blackfin/mach-bf518/boards/ezbrd.c

   1 /*
   2  * Copyright 2004-2009 Analog Devices Inc.
   3  *                2005 National ICT Australia (NICTA)
   4  *                      Aidan Williams <aidan@nicta.com.au>
   5  *
   6  * Licensed under the GPL-2 or later.
   7  */
   8
   9 #include <linux/device.h>
  10 #include <linux/platform_device.h>
  11 #include <linux/mtd/mtd.h>
  12 #include <linux/mtd/partitions.h>
  13 #include <linux/mtd/physmap.h>
  14 #include <linux/spi/spi.h>
  15 #include <linux/spi/flash.h>
  16
  17 #include <linux/i2c.h>
  18 #include <linux/irq.h>
  19 #include <linux/interrupt.h>
  20 #include <asm/dma.h>
  21 #include <asm/bfin5xx_spi.h>
  22 #include <asm/reboot.h>
  23 #include <asm/portmux.h>
  24 #include <asm/dpmc.h>
  25 #include <asm/bfin_sdh.h>
  26 #include <linux/spi/ad7877.h>
  27 #include <net/dsa.h>
  28
  29 /*
  30  * Name the Board for the /proc/cpuinfo
  31  */
  32 const char bfin_board_name[] = "ADI BF518F-EZBRD";
  33
  34 /*
  35  *  Driver needs to know address, irq and flag pin.
  36  */
  37
  38 #if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
  39 static struct mtd_partition ezbrd_partitions[] = {
  40         {
  41                 .name       = "bootloader(nor)",
  42                 .size       = 0x40000,
  43                 .offset     = 0,
  44         }, {
  45                 .name       = "linux kernel(nor)",
  46                 .size       = 0x1C0000,
  47                 .offset     = MTDPART_OFS_APPEND,
  48         }, {
  49                 .name       = "file system(nor)",
  50                 .size       = MTDPART_SIZ_FULL,
  51                 .offset     = MTDPART_OFS_APPEND,
  52         }
  53 };
  54
  55 static struct physmap_flash_data ezbrd_flash_data = {
  56         .width      = 2,
  57         .parts      = ezbrd_partitions,
  58         .nr_parts   = ARRAY_SIZE(ezbrd_partitions),
  59 };
  60
  61 static struct resource ezbrd_flash_resource = {
  62         .start = 0x20000000,
  63 #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
  64         .end   = 0x202fffff,
  65 #else
  66         .end   = 0x203fffff,
  67 #endif
  68         .flags = IORESOURCE_MEM,
  69 };
  70
  71 static struct platform_device ezbrd_flash_device = {
  72         .name          = "physmap-flash",
  73         .id            = 0,
  74         .dev = {
  75                 .platform_data = &ezbrd_flash_data,
  76         },
  77         .num_resources = 1,
  78         .resource      = &ezbrd_flash_resource,
  79 };
  80 #endif
  81
  82 #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
  83 static struct platform_device rtc_device = {
  84         .name = "rtc-bfin",
  85         .id   = -1,
  86 };
  87 #endif
  88
  89 #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
  90 static struct platform_device bfin_mii_bus = {
  91         .name = "bfin_mii_bus",
  92 };
  93
  94 static struct platform_device bfin_mac_device = {
  95         .name = "bfin_mac",
  96         .dev.platform_data = &bfin_mii_bus,
  97 };
  98
  99 #if defined(CONFIG_NET_DSA_KSZ8893M) || defined(CONFIG_NET_DSA_KSZ8893M_MODULE)
 100 static struct dsa_chip_data ksz8893m_switch_chip_data = {
 101         .mii_bus = &bfin_mii_bus.dev,
 102         .port_names = {
 103                 NULL,
 104                 "eth%d",
 105                 "eth%d",
 106                 "cpu",
 107         },
 108 };
 109 static struct dsa_platform_data ksz8893m_switch_data = {
 110         .nr_chips = 1,
 111         .netdev = &bfin_mac_device.dev,
 112         .chip = &ksz8893m_switch_chip_data,
 113 };
 114
 115 static struct platform_device ksz8893m_switch_device = {
 116         .name           = "dsa",
 117         .id             = 0,
 118         .num_resources  = 0,
 119         .dev.platform_data = &ksz8893m_switch_data,
 120 };
 121 #endif
 122 #endif
 123
 124 #if defined(CONFIG_MTD_M25P80) \
 125         || defined(CONFIG_MTD_M25P80_MODULE)
 126 static struct mtd_partition bfin_spi_flash_partitions[] = {
 127         {
 128                 .name = "bootloader(spi)",
 129                 .size = 0x00040000,
 130                 .offset = 0,
 131                 .mask_flags = MTD_CAP_ROM
 132         }, {
 133                 .name = "linux kernel(spi)",
 134                 .size = MTDPART_SIZ_FULL,
 135                 .offset = MTDPART_OFS_APPEND,
 136         }
 137 };
 138
 139 static struct flash_platform_data bfin_spi_flash_data = {
 140         .name = "m25p80",
 141         .parts = bfin_spi_flash_partitions,
 142         .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
 143         .type = "m25p16",
 144 };
 145
 146 /* SPI flash chip (m25p64) */
 147 static struct bfin5xx_spi_chip spi_flash_chip_info = {
 148         .enable_dma = 0,         /* use dma transfer with this chip*/
 149         .bits_per_word = 8,
 150 };
 151 #endif
 152
 153 #if defined(CONFIG_BFIN_SPI_ADC) \
 154         || defined(CONFIG_BFIN_SPI_ADC_MODULE)
 155 /* SPI ADC chip */
 156 static struct bfin5xx_spi_chip spi_adc_chip_info = {
 157         .enable_dma = 1,         /* use dma transfer with this chip*/
 158         .bits_per_word = 16,
 159 };
 160 #endif
 161
 162 #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
 163 #if defined(CONFIG_NET_DSA_KSZ8893M) \
 164         || defined(CONFIG_NET_DSA_KSZ8893M_MODULE)
 165 /* SPI SWITCH CHIP */
 166 static struct bfin5xx_spi_chip spi_switch_info = {
 167         .enable_dma = 0,
 168         .bits_per_word = 8,
 169 };
 170 #endif
 171 #endif
 172
 173 #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
 174 static struct bfin5xx_spi_chip mmc_spi_chip_info = {
 175         .enable_dma = 0,
 176         .bits_per_word = 8,
 177 };
 178 #endif
 179
 180 #if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
 181 static struct bfin5xx_spi_chip spi_ad7877_chip_info = {
 182         .enable_dma = 0,
 183         .bits_per_word = 16,
 184 };
 185
 186 static const struct ad7877_platform_data bfin_ad7877_ts_info = {
 187         .model                  = 7877,
 188         .vref_delay_usecs       = 50,   /* internal, no capacitor */
 189         .x_plate_ohms           = 419,
 190         .y_plate_ohms           = 486,
 191         .pressure_max           = 1000,
 192         .pressure_min           = 0,
 193         .stopacq_polarity       = 1,
 194         .first_conversion_delay = 3,
 195         .acquisition_time       = 1,
 196         .averaging              = 1,
 197         .pen_down_acc_interval  = 1,
 198 };
 199 #endif
 200
 201 #if defined(CONFIG_SND_SOC_WM8731) || defined(CONFIG_SND_SOC_WM8731_MODULE) \
 202          && defined(CONFIG_SND_SOC_WM8731_SPI)
 203 static struct bfin5xx_spi_chip spi_wm8731_chip_info = {
 204         .enable_dma = 0,
 205         .bits_per_word = 16,
 206 };
 207 #endif
 208
 209 #if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
 210 static struct bfin5xx_spi_chip spidev_chip_info = {
 211         .enable_dma = 0,
 212         .bits_per_word = 8,
 213 };
 214 #endif
 215
 216 static struct spi_board_info bfin_spi_board_info[] __initdata = {
 217 #if defined(CONFIG_MTD_M25P80) \
 218         || defined(CONFIG_MTD_M25P80_MODULE)
 219         {
 220                 /* the modalias must be the same as spi device driver name */
 221                 .modalias = "m25p80", /* Name of spi_driver for this device */
 222                 .max_speed_hz = 25000000,     /* max spi clock (SCK) speed in HZ */
 223                 .bus_num = 0, /* Framework bus number */
 224                 .chip_select = 2, /* On BF518F-EZBRD it's SPI0_SSEL2 */
 225                 .platform_data = &bfin_spi_flash_data,
 226                 .controller_data = &spi_flash_chip_info,
 227                 .mode = SPI_MODE_3,
 228         },
 229 #endif
 230
 231 #if defined(CONFIG_BFIN_SPI_ADC) \
 232         || defined(CONFIG_BFIN_SPI_ADC_MODULE)
 233         {
 234                 .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
 235                 .max_speed_hz = 6250000,     /* max spi clock (SCK) speed in HZ */
 236                 .bus_num = 0, /* Framework bus number */
 237                 .chip_select = 1, /* Framework chip select. */
 238                 .platform_data = NULL, /* No spi_driver specific config */
 239                 .controller_data = &spi_adc_chip_info,
 240         },
 241 #endif
 242
 243 #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
 244 #if defined(CONFIG_NET_DSA_KSZ8893M) \
 245         || defined(CONFIG_NET_DSA_KSZ8893M_MODULE)
 246         {
 247                 .modalias = "ksz8893m",
 248                 .max_speed_hz = 5000000,
 249                 .bus_num = 0,
 250                 .chip_select = 1,
 251                 .platform_data = NULL,
 252                 .controller_data = &spi_switch_info,
 253                 .mode = SPI_MODE_3,
 254         },
 255 #endif
 256 #endif
 257
 258 #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
 259         {
 260                 .modalias = "mmc_spi",
 261                 .max_speed_hz = 25000000,     /* max spi clock (SCK) speed in HZ */
 262                 .bus_num = 0,
 263                 .chip_select = 5,
 264                 .controller_data = &mmc_spi_chip_info,
 265                 .mode = SPI_MODE_3,
 266         },
 267 #endif
 268 #if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
 269         {
 270                 .modalias               = "ad7877",
 271                 .platform_data          = &bfin_ad7877_ts_info,
 272                 .irq                    = IRQ_PF8,
 273                 .max_speed_hz   = 12500000,     /* max spi clock (SCK) speed in HZ */
 274                 .bus_num        = 0,
 275                 .chip_select  = 2,
 276                 .controller_data = &spi_ad7877_chip_info,
 277         },
 278 #endif
 279 #if defined(CONFIG_SND_SOC_WM8731) || defined(CONFIG_SND_SOC_WM8731_MODULE) \
 280          && defined(CONFIG_SND_SOC_WM8731_SPI)
 281         {
 282                 .modalias       = "wm8731",
 283                 .max_speed_hz   = 3125000,     /* max spi clock (SCK) speed in HZ */
 284                 .bus_num        = 0,
 285                 .chip_select    = 5,
 286                 .controller_data = &spi_wm8731_chip_info,
 287                 .mode = SPI_MODE_0,
 288         },
 289 #endif
 290 #if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
 291         {
 292                 .modalias = "spidev",
 293                 .max_speed_hz = 3125000,     /* max spi clock (SCK) speed in HZ */
 294                 .bus_num = 0,
 295                 .chip_select = 1,
 296                 .controller_data = &spidev_chip_info,
 297         },
 298 #endif
 299 #if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
 300         {
 301                 .modalias = "bfin-lq035q1-spi",
 302                 .max_speed_hz = 20000000,     /* max spi clock (SCK) speed in HZ */
 303                 .bus_num = 0,
 304                 .chip_select = 1,
 305                 .controller_data = &lq035q1_spi_chip_info,
 306                 .mode = SPI_CPHA | SPI_CPOL,
 307         },
 308 #endif
 309 };
 310
 311 /* SPI controller data */
 312 #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
 313 /* SPI (0) */
 314 static struct bfin5xx_spi_master bfin_spi0_info = {
 315         .num_chipselect = 6,
 316         .enable_dma = 1,  /* master has the ability to do dma transfer */
 317         .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
 318 };
 319
 320 static struct resource bfin_spi0_resource[] = {
 321         [0] = {
 322                 .start = SPI0_REGBASE,
 323                 .end   = SPI0_REGBASE + 0xFF,
 324                 .flags = IORESOURCE_MEM,
 325                 },
 326         [1] = {
 327                 .start = CH_SPI0,
 328                 .end   = CH_SPI0,
 329                 .flags = IORESOURCE_DMA,
 330         },
 331         [2] = {
 332                 .start = IRQ_SPI0,
 333                 .end   = IRQ_SPI0,
 334                 .flags = IORESOURCE_IRQ,
 335         },
 336 };
 337
 338 static struct platform_device bfin_spi0_device = {
 339         .name = "bfin-spi",
 340         .id = 0, /* Bus number */
 341         .num_resources = ARRAY_SIZE(bfin_spi0_resource),
 342         .resource = bfin_spi0_resource,
 343         .dev = {
 344                 .platform_data = &bfin_spi0_info, /* Passed to driver */
 345         },
 346 };
 347
 348 /* SPI (1) */
 349 static struct bfin5xx_spi_master bfin_spi1_info = {
 350         .num_chipselect = 6,
 351         .enable_dma = 1,  /* master has the ability to do dma transfer */
 352         .pin_req = {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0},
 353 };
 354
 355 static struct resource bfin_spi1_resource[] = {
 356         [0] = {
 357                 .start = SPI1_REGBASE,
 358                 .end   = SPI1_REGBASE + 0xFF,
 359                 .flags = IORESOURCE_MEM,
 360                 },
 361         [1] = {
 362                 .start = CH_SPI1,
 363                 .end   = CH_SPI1,
 364                 .flags = IORESOURCE_DMA,
 365         },
 366         [2] = {
 367                 .start = IRQ_SPI1,
 368                 .end   = IRQ_SPI1,
 369                 .flags = IORESOURCE_IRQ,
 370         },
 371 };
 372
 373 static struct platform_device bfin_spi1_device = {
 374         .name = "bfin-spi",
 375         .id = 1, /* Bus number */
 376         .num_resources = ARRAY_SIZE(bfin_spi1_resource),
 377         .resource = bfin_spi1_resource,
 378         .dev = {
 379                 .platform_data = &bfin_spi1_info, /* Passed to driver */
 380         },
 381 };
 382 #endif  /* spi master and devices */
 383
 384 #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
 385 #ifdef CONFIG_SERIAL_BFIN_UART0
 386 static struct resource bfin_uart0_resources[] = {
 387         {
 388                 .start = UART0_THR,
 389                 .end = UART0_GCTL+2,
 390                 .flags = IORESOURCE_MEM,
 391         },
 392         {
 393                 .start = IRQ_UART0_RX,
 394                 .end = IRQ_UART0_RX+1,
 395                 .flags = IORESOURCE_IRQ,
 396         },
 397         {
 398                 .start = IRQ_UART0_ERROR,
 399                 .end = IRQ_UART0_ERROR,
 400                 .flags = IORESOURCE_IRQ,
 401         },
 402         {
 403                 .start = CH_UART0_TX,
 404                 .end = CH_UART0_TX,
 405                 .flags = IORESOURCE_DMA,
 406         },
 407         {
 408                 .start = CH_UART0_RX,
 409                 .end = CH_UART0_RX,
 410                 .flags = IORESOURCE_DMA,
 411         },
 412 };
 413
 414 unsigned short bfin_uart0_peripherals[] = {
 415         P_UART0_TX, P_UART0_RX, 0
 416 };
 417
 418 static struct platform_device bfin_uart0_device = {
 419         .name = "bfin-uart",
 420         .id = 0,
 421         .num_resources = ARRAY_SIZE(bfin_uart0_resources),
 422         .resource = bfin_uart0_resources,
 423         .dev = {
 424                 .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
 425         },
 426 };
 427 #endif
 428 #ifdef CONFIG_SERIAL_BFIN_UART1
 429 static struct resource bfin_uart1_resources[] = {
 430         {
 431                 .start = UART1_THR,
 432                 .end = UART1_GCTL+2,
 433                 .flags = IORESOURCE_MEM,
 434         },
 435         {
 436                 .start = IRQ_UART1_RX,
 437                 .end = IRQ_UART1_RX+1,
 438                 .flags = IORESOURCE_IRQ,
 439         },
 440         {
 441                 .start = IRQ_UART1_ERROR,
 442                 .end = IRQ_UART1_ERROR,
 443                 .flags = IORESOURCE_IRQ,
 444         },
 445         {
 446                 .start = CH_UART1_TX,
 447                 .end = CH_UART1_TX,
 448                 .flags = IORESOURCE_DMA,
 449         },
 450         {
 451                 .start = CH_UART1_RX,
 452                 .end = CH_UART1_RX,
 453                 .flags = IORESOURCE_DMA,
 454         },
 455 };
 456
 457 unsigned short bfin_uart1_peripherals[] = {
 458         P_UART1_TX, P_UART1_RX, 0
 459 };
 460
 461 static struct platform_device bfin_uart1_device = {
 462         .name = "bfin-uart",
 463         .id = 1,
 464         .num_resources = ARRAY_SIZE(bfin_uart1_resources),
 465         .resource = bfin_uart1_resources,
 466         .dev = {
 467                 .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
 468         },
 469 };
 470 #endif
 471 #endif
 472
 473 #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
 474 #ifdef CONFIG_BFIN_SIR0
 475 static struct resource bfin_sir0_resources[] = {
 476         {
 477                 .start = 0xFFC00400,
 478                 .end = 0xFFC004FF,
 479                 .flags = IORESOURCE_MEM,
 480         },
 481         {
 482                 .start = IRQ_UART0_RX,
 483                 .end = IRQ_UART0_RX+1,
 484                 .flags = IORESOURCE_IRQ,
 485         },
 486         {
 487                 .start = CH_UART0_RX,
 488                 .end = CH_UART0_RX+1,
 489                 .flags = IORESOURCE_DMA,
 490         },
 491 };
 492
 493 static struct platform_device bfin_sir0_device = {
 494         .name = "bfin_sir",
 495         .id = 0,
 496         .num_resources = ARRAY_SIZE(bfin_sir0_resources),
 497         .resource = bfin_sir0_resources,
 498 };
 499 #endif
 500 #ifdef CONFIG_BFIN_SIR1
 501 static struct resource bfin_sir1_resources[] = {
 502         {
 503                 .start = 0xFFC02000,
 504                 .end = 0xFFC020FF,
 505                 .flags = IORESOURCE_MEM,
 506         },
 507         {
 508                 .start = IRQ_UART1_RX,
 509                 .end = IRQ_UART1_RX+1,
 510                 .flags = IORESOURCE_IRQ,
 511         },
 512         {
 513                 .start = CH_UART1_RX,
 514                 .end = CH_UART1_RX+1,
 515                 .flags = IORESOURCE_DMA,
 516         },
 517 };
 518
 519 static struct platform_device bfin_sir1_device = {
 520         .name = "bfin_sir",
 521         .id = 1,
 522         .num_resources = ARRAY_SIZE(bfin_sir1_resources),
 523         .resource = bfin_sir1_resources,
 524 };
 525 #endif
 526 #endif
 527
 528 #if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
 529 static struct platform_device bfin_i2s = {
 530         .name = "bfin-i2s",
 531         .id = CONFIG_SND_BF5XX_SPORT_NUM,
 532         /* TODO: add platform data here */
 533 };
 534 #endif
 535
 536 #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
 537 static struct resource bfin_twi0_resource[] = {
 538         [0] = {
 539                 .start = TWI0_REGBASE,
 540                 .end   = TWI0_REGBASE,
 541                 .flags = IORESOURCE_MEM,
 542         },
 543         [1] = {
 544                 .start = IRQ_TWI,
 545                 .end   = IRQ_TWI,
 546                 .flags = IORESOURCE_IRQ,
 547         },
 548 };
 549
 550 static struct platform_device i2c_bfin_twi_device = {
 551         .name = "i2c-bfin-twi",
 552         .id = 0,
 553         .num_resources = ARRAY_SIZE(bfin_twi0_resource),
 554         .resource = bfin_twi0_resource,
 555 };
 556 #endif
 557
 558 static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
 559 #if defined(CONFIG_BFIN_TWI_LCD) || defined(CONFIG_BFIN_TWI_LCD_MODULE)
 560         {
 561                 I2C_BOARD_INFO("pcf8574_lcd", 0x22),
 562         },
 563 #endif
 564 #if defined(CONFIG_INPUT_PCF8574) || defined(CONFIG_INPUT_PCF8574_MODULE)
 565         {
 566                 I2C_BOARD_INFO("pcf8574_keypad", 0x27),
 567                 .irq = IRQ_PF8,
 568         },
 569 #endif
 570 #if defined(CONFIG_SND_SOC_SSM2602) || defined(CONFIG_SND_SOC_SSM2602_MODULE)
 571         {
 572                 I2C_BOARD_INFO("ssm2602", 0x1b),
 573         },
 574 #endif
 575 };
 576
 577 #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
 578 #ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
 579 static struct resource bfin_sport0_uart_resources[] = {
 580         {
 581                 .start = SPORT0_TCR1,
 582                 .end = SPORT0_MRCS3+4,
 583                 .flags = IORESOURCE_MEM,
 584         },
 585         {
 586                 .start = IRQ_SPORT0_RX,
 587                 .end = IRQ_SPORT0_RX+1,
 588                 .flags = IORESOURCE_IRQ,
 589         },
 590         {
 591                 .start = IRQ_SPORT0_ERROR,
 592                 .end = IRQ_SPORT0_ERROR,
 593                 .flags = IORESOURCE_IRQ,
 594         },
 595 };
 596
 597 unsigned short bfin_sport0_peripherals[] = {
 598         P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
 599         P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0
 600 };
 601
 602 static struct platform_device bfin_sport0_uart_device = {
 603         .name = "bfin-sport-uart",
 604         .id = 0,
 605         .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
 606         .resource = bfin_sport0_uart_resources,
 607         .dev = {
 608                 .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
 609         },
 610 };
 611 #endif
 612 #ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
 613 static struct resource bfin_sport1_uart_resources[] = {
 614         {
 615                 .start = SPORT1_TCR1,
 616                 .end = SPORT1_MRCS3+4,
 617                 .flags = IORESOURCE_MEM,
 618         },
 619         {
 620                 .start = IRQ_SPORT1_RX,
 621                 .end = IRQ_SPORT1_RX+1,
 622                 .flags = IORESOURCE_IRQ,
 623         },
 624         {
 625                 .start = IRQ_SPORT1_ERROR,
 626                 .end = IRQ_SPORT1_ERROR,
 627                 .flags = IORESOURCE_IRQ,
 628         },
 629 };
 630
 631 unsigned short bfin_sport1_peripherals[] = {
 632         P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
 633         P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_DRSEC, P_SPORT1_DTSEC, 0
 634 };
 635
 636 static struct platform_device bfin_sport1_uart_device = {
 637         .name = "bfin-sport-uart",
 638         .id = 1,
 639         .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
 640         .resource = bfin_sport1_uart_resources,
 641         .dev = {
 642                 .platform_data = &bfin_sport1_peripherals, /* Passed to driver */
 643         },
 644 };
 645 #endif
 646 #endif
 647
 648 #if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
 649 #include <linux/input.h>
 650 #include <linux/gpio_keys.h>
 651
 652 static struct gpio_keys_button bfin_gpio_keys_table[] = {
 653         {BTN_0, GPIO_PG0, 1, "gpio-keys: BTN0"},
 654         {BTN_1, GPIO_PG13, 1, "gpio-keys: BTN1"},
 655 };
 656
 657 static struct gpio_keys_platform_data bfin_gpio_keys_data = {
 658         .buttons        = bfin_gpio_keys_table,
 659         .nbuttons       = ARRAY_SIZE(bfin_gpio_keys_table),
 660 };
 661
 662 static struct platform_device bfin_device_gpiokeys = {
 663         .name      = "gpio-keys",
 664         .dev = {
 665                 .platform_data = &bfin_gpio_keys_data,
 666         },
 667 };
 668 #endif
 669
 670 #if defined(CONFIG_SDH_BFIN) || defined(CONFIG_SDH_BFIN_MODULE)
 671
 672 static struct bfin_sd_host bfin_sdh_data = {
 673         .dma_chan = CH_RSI,
 674         .irq_int0 = IRQ_RSI_INT0,
 675         .pin_req = {P_RSI_DATA0, P_RSI_DATA1, P_RSI_DATA2, P_RSI_DATA3, P_RSI_CMD, P_RSI_CLK, 0},
 676 };
 677
 678 static struct platform_device bf51x_sdh_device = {
 679         .name = "bfin-sdh",
 680         .id = 0,
 681         .dev = {
 682                 .platform_data = &bfin_sdh_data,
 683         },
 684 };
 685 #endif
 686
 687 static const unsigned int cclk_vlev_datasheet[] =
 688 {
 689         VRPAIR(VLEV_100, 400000000),
 690         VRPAIR(VLEV_105, 426000000),
 691         VRPAIR(VLEV_110, 500000000),
 692         VRPAIR(VLEV_115, 533000000),
 693         VRPAIR(VLEV_120, 600000000),
 694 };
 695
 696 static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
 697         .tuple_tab = cclk_vlev_datasheet,
 698         .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
 699         .vr_settling_time = 25 /* us */,
 700 };
 701
 702 static struct platform_device bfin_dpmc = {
 703         .name = "bfin dpmc",
 704         .dev = {
 705                 .platform_data = &bfin_dmpc_vreg_data,
 706         },
 707 };
 708
 709 static struct platform_device *stamp_devices[] __initdata = {
 710
 711         &bfin_dpmc,
 712
 713 #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
 714         &rtc_device,
 715 #endif
 716
 717 #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
 718         &bfin_mii_bus,
 719         &bfin_mac_device,
 720 #if defined(CONFIG_NET_DSA_KSZ8893M) || defined(CONFIG_NET_DSA_KSZ8893M_MODULE)
 721         &ksz8893m_switch_device,
 722 #endif
 723 #endif
 724
 725 #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
 726         &bfin_spi0_device,
 727         &bfin_spi1_device,
 728 #endif
 729
 730 #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
 731 #ifdef CONFIG_SERIAL_BFIN_UART0
 732         &bfin_uart0_device,
 733 #endif
 734 #ifdef CONFIG_SERIAL_BFIN_UART1
 735         &bfin_uart1_device,
 736 #endif
 737 #endif
 738
 739 #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
 740 #ifdef CONFIG_BFIN_SIR0
 741         &bfin_sir0_device,
 742 #endif
 743 #ifdef CONFIG_BFIN_SIR1
 744         &bfin_sir1_device,
 745 #endif
 746 #endif
 747
 748 #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
 749         &i2c_bfin_twi_device,
 750 #endif
 751
 752 #if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
 753         &bfin_i2s,
 754 #endif
 755
 756 #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
 757 #ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
 758         &bfin_sport0_uart_device,
 759 #endif
 760 #ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
 761         &bfin_sport1_uart_device,
 762 #endif
 763 #endif
 764
 765 #if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
 766         &bfin_device_gpiokeys,
 767 #endif
 768
 769 #if defined(CONFIG_SDH_BFIN) || defined(CONFIG_SDH_BFIN_MODULE)
 770         &bf51x_sdh_device,
 771 #endif
 772
 773 #if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
 774         &ezbrd_flash_device,
 775 #endif
 776 };
 777
 778 static int __init ezbrd_init(void)
 779 {
 780         printk(KERN_INFO "%s(): registering device resources\n", __func__);
 781         i2c_register_board_info(0, bfin_i2c_board_info,
 782                                 ARRAY_SIZE(bfin_i2c_board_info));
 783         platform_add_devices(stamp_devices, ARRAY_SIZE(stamp_devices));
 784         spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
 785         /* setup BF518-EZBRD GPIO pin PG11 to AMS2, PG15 to AMS3. */
 786         peripheral_request(P_AMS2, "ParaFlash");
 787 #if !defined(CONFIG_SPI_BFIN) && !defined(CONFIG_SPI_BFIN_MODULE)
 788         peripheral_request(P_AMS3, "ParaFlash");
 789 #endif
 790         return 0;
 791 }
 792
 793 arch_initcall(ezbrd_init);
 794
 795 static struct platform_device *ezbrd_early_devices[] __initdata = {
 796 #if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
 797 #ifdef CONFIG_SERIAL_BFIN_UART0
 798         &bfin_uart0_device,
 799 #endif
 800 #ifdef CONFIG_SERIAL_BFIN_UART1
 801         &bfin_uart1_device,
 802 #endif
 803 #endif
 804
 805 #if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE)
 806 #ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
 807         &bfin_sport0_uart_device,
 808 #endif
 809 #ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
 810         &bfin_sport1_uart_device,
 811 #endif
 812 #endif
 813 };
 814
 815 void __init native_machine_early_platform_add_devices(void)
 816 {
 817         printk(KERN_INFO "register early platform devices\n");
 818         early_platform_add_devices(ezbrd_early_devices,
 819                 ARRAY_SIZE(ezbrd_early_devices));
 820 }
 821
 822 void native_machine_restart(char *cmd)
 823 {
 824         /* workaround reboot hang when booting from SPI */
 825         if ((bfin_read_SYSCR() & 0x7) == 0x3)
 826                 bfin_reset_boot_spi_cs(P_DEFAULT_BOOT_SPI_CS);
 827 }
 828
 829 void bfin_get_ether_addr(char *addr)
 830 {
 831         /* the MAC is stored in OTP memory page 0xDF */
 832         u32 ret;
 833         u64 otp_mac;
 834         u32 (*otp_read)(u32 page, u32 flags, u64 *page_content) = (void *)0xEF00001A;
 835
 836         ret = otp_read(0xDF, 0x00, &otp_mac);
 837         if (!(ret & 0x1)) {
 838                 char *otp_mac_p = (char *)&otp_mac;
 839                 for (ret = 0; ret < 6; ++ret)
 840                         addr[ret] = otp_mac_p[5 - ret];
 841         }
 842 }
 843 EXPORT_SYMBOL(bfin_get_ether_addr);