2 * Hardware modules present on the OMAP44xx chips
4 * Copyright (C) 2009-2012 Texas Instruments, Inc.
5 * Copyright (C) 2009-2010 Nokia Corporation
10 * This file is automatically generated from the OMAP hardware databases.
11 * We respectfully ask that any modifications to this file be coordinated
12 * with the public linux-omap@vger.kernel.org mailing list and the
13 * authors above to ensure that the autogeneration scripts are kept
14 * up-to-date with the file contents.
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation.
22 #include <linux/platform_data/gpio-omap.h>
23 #include <linux/power/smartreflex.h>
25 #include <plat/omap_hwmod.h>
28 #include <linux/platform_data/spi-omap2-mcspi.h>
29 #include <linux/platform_data/asoc-ti-mcbsp.h>
31 #include <plat/dmtimer.h>
32 #include <plat/common.h>
33 #include <plat/iommu.h>
35 #include "omap_hwmod_common_data.h"
39 #include "prm-regbits-44xx.h"
42 /* Base offset for all OMAP4 interrupts external to MPUSS */
43 #define OMAP44XX_IRQ_GIC_START 32
45 /* Base offset for all OMAP4 dma requests */
46 #define OMAP44XX_DMA_REQ_START 1
53 * 'c2c_target_fw' class
54 * instance(s): c2c_target_fw
56 static struct omap_hwmod_class omap44xx_c2c_target_fw_hwmod_class
= {
57 .name
= "c2c_target_fw",
61 static struct omap_hwmod omap44xx_c2c_target_fw_hwmod
= {
62 .name
= "c2c_target_fw",
63 .class = &omap44xx_c2c_target_fw_hwmod_class
,
64 .clkdm_name
= "d2d_clkdm",
67 .clkctrl_offs
= OMAP4_CM_D2D_SAD2D_FW_CLKCTRL_OFFSET
,
68 .context_offs
= OMAP4_RM_D2D_SAD2D_FW_CONTEXT_OFFSET
,
77 static struct omap_hwmod_class omap44xx_dmm_hwmod_class
= {
82 static struct omap_hwmod_irq_info omap44xx_dmm_irqs
[] = {
83 { .irq
= 113 + OMAP44XX_IRQ_GIC_START
},
87 static struct omap_hwmod omap44xx_dmm_hwmod
= {
89 .class = &omap44xx_dmm_hwmod_class
,
90 .clkdm_name
= "l3_emif_clkdm",
91 .mpu_irqs
= omap44xx_dmm_irqs
,
94 .clkctrl_offs
= OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET
,
95 .context_offs
= OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET
,
102 * instance(s): emif_fw
104 static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class
= {
109 static struct omap_hwmod omap44xx_emif_fw_hwmod
= {
111 .class = &omap44xx_emif_fw_hwmod_class
,
112 .clkdm_name
= "l3_emif_clkdm",
115 .clkctrl_offs
= OMAP4_CM_MEMIF_EMIF_FW_CLKCTRL_OFFSET
,
116 .context_offs
= OMAP4_RM_MEMIF_EMIF_FW_CONTEXT_OFFSET
,
123 * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
125 static struct omap_hwmod_class omap44xx_l3_hwmod_class
= {
130 static struct omap_hwmod omap44xx_l3_instr_hwmod
= {
132 .class = &omap44xx_l3_hwmod_class
,
133 .clkdm_name
= "l3_instr_clkdm",
136 .clkctrl_offs
= OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET
,
137 .context_offs
= OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET
,
138 .modulemode
= MODULEMODE_HWCTRL
,
144 static struct omap_hwmod_irq_info omap44xx_l3_main_1_irqs
[] = {
145 { .name
= "dbg_err", .irq
= 9 + OMAP44XX_IRQ_GIC_START
},
146 { .name
= "app_err", .irq
= 10 + OMAP44XX_IRQ_GIC_START
},
150 static struct omap_hwmod omap44xx_l3_main_1_hwmod
= {
152 .class = &omap44xx_l3_hwmod_class
,
153 .clkdm_name
= "l3_1_clkdm",
154 .mpu_irqs
= omap44xx_l3_main_1_irqs
,
157 .clkctrl_offs
= OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET
,
158 .context_offs
= OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET
,
164 static struct omap_hwmod omap44xx_l3_main_2_hwmod
= {
166 .class = &omap44xx_l3_hwmod_class
,
167 .clkdm_name
= "l3_2_clkdm",
170 .clkctrl_offs
= OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET
,
171 .context_offs
= OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET
,
177 static struct omap_hwmod omap44xx_l3_main_3_hwmod
= {
179 .class = &omap44xx_l3_hwmod_class
,
180 .clkdm_name
= "l3_instr_clkdm",
183 .clkctrl_offs
= OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET
,
184 .context_offs
= OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET
,
185 .modulemode
= MODULEMODE_HWCTRL
,
192 * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
194 static struct omap_hwmod_class omap44xx_l4_hwmod_class
= {
199 static struct omap_hwmod omap44xx_l4_abe_hwmod
= {
201 .class = &omap44xx_l4_hwmod_class
,
202 .clkdm_name
= "abe_clkdm",
205 .clkctrl_offs
= OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET
,
206 .context_offs
= OMAP4_RM_ABE_AESS_CONTEXT_OFFSET
,
207 .lostcontext_mask
= OMAP4430_LOSTMEM_AESSMEM_MASK
,
208 .flags
= HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT
,
214 static struct omap_hwmod omap44xx_l4_cfg_hwmod
= {
216 .class = &omap44xx_l4_hwmod_class
,
217 .clkdm_name
= "l4_cfg_clkdm",
220 .clkctrl_offs
= OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET
,
221 .context_offs
= OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET
,
227 static struct omap_hwmod omap44xx_l4_per_hwmod
= {
229 .class = &omap44xx_l4_hwmod_class
,
230 .clkdm_name
= "l4_per_clkdm",
233 .clkctrl_offs
= OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET
,
234 .context_offs
= OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET
,
240 static struct omap_hwmod omap44xx_l4_wkup_hwmod
= {
242 .class = &omap44xx_l4_hwmod_class
,
243 .clkdm_name
= "l4_wkup_clkdm",
246 .clkctrl_offs
= OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET
,
247 .context_offs
= OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET
,
254 * instance(s): mpu_private
256 static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class
= {
261 static struct omap_hwmod omap44xx_mpu_private_hwmod
= {
262 .name
= "mpu_private",
263 .class = &omap44xx_mpu_bus_hwmod_class
,
264 .clkdm_name
= "mpuss_clkdm",
267 .flags
= HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT
,
274 * instance(s): ocp_wp_noc
276 static struct omap_hwmod_class omap44xx_ocp_wp_noc_hwmod_class
= {
277 .name
= "ocp_wp_noc",
281 static struct omap_hwmod omap44xx_ocp_wp_noc_hwmod
= {
282 .name
= "ocp_wp_noc",
283 .class = &omap44xx_ocp_wp_noc_hwmod_class
,
284 .clkdm_name
= "l3_instr_clkdm",
287 .clkctrl_offs
= OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_OFFSET
,
288 .context_offs
= OMAP4_RM_L3INSTR_OCP_WP1_CONTEXT_OFFSET
,
289 .modulemode
= MODULEMODE_HWCTRL
,
295 * Modules omap_hwmod structures
297 * The following IPs are excluded for the moment because:
298 * - They do not need an explicit SW control using omap_hwmod API.
299 * - They still need to be validated with the driver
300 * properly adapted to omap_hwmod / omap_device
307 * audio engine sub system
310 static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc
= {
313 .sysc_flags
= (SYSC_HAS_MIDLEMODE
| SYSC_HAS_SIDLEMODE
),
314 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
315 MSTANDBY_FORCE
| MSTANDBY_NO
| MSTANDBY_SMART
|
316 MSTANDBY_SMART_WKUP
),
317 .sysc_fields
= &omap_hwmod_sysc_type2
,
320 static struct omap_hwmod_class omap44xx_aess_hwmod_class
= {
322 .sysc
= &omap44xx_aess_sysc
,
326 static struct omap_hwmod_irq_info omap44xx_aess_irqs
[] = {
327 { .irq
= 99 + OMAP44XX_IRQ_GIC_START
},
331 static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs
[] = {
332 { .name
= "fifo0", .dma_req
= 100 + OMAP44XX_DMA_REQ_START
},
333 { .name
= "fifo1", .dma_req
= 101 + OMAP44XX_DMA_REQ_START
},
334 { .name
= "fifo2", .dma_req
= 102 + OMAP44XX_DMA_REQ_START
},
335 { .name
= "fifo3", .dma_req
= 103 + OMAP44XX_DMA_REQ_START
},
336 { .name
= "fifo4", .dma_req
= 104 + OMAP44XX_DMA_REQ_START
},
337 { .name
= "fifo5", .dma_req
= 105 + OMAP44XX_DMA_REQ_START
},
338 { .name
= "fifo6", .dma_req
= 106 + OMAP44XX_DMA_REQ_START
},
339 { .name
= "fifo7", .dma_req
= 107 + OMAP44XX_DMA_REQ_START
},
343 static struct omap_hwmod omap44xx_aess_hwmod
= {
345 .class = &omap44xx_aess_hwmod_class
,
346 .clkdm_name
= "abe_clkdm",
347 .mpu_irqs
= omap44xx_aess_irqs
,
348 .sdma_reqs
= omap44xx_aess_sdma_reqs
,
349 .main_clk
= "aess_fck",
352 .clkctrl_offs
= OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET
,
353 .context_offs
= OMAP4_RM_ABE_AESS_CONTEXT_OFFSET
,
354 .lostcontext_mask
= OMAP4430_LOSTCONTEXT_DFF_MASK
,
355 .modulemode
= MODULEMODE_SWCTRL
,
362 * chip 2 chip interface used to plug the ape soc (omap) with an external modem
366 static struct omap_hwmod_class omap44xx_c2c_hwmod_class
= {
371 static struct omap_hwmod_irq_info omap44xx_c2c_irqs
[] = {
372 { .irq
= 88 + OMAP44XX_IRQ_GIC_START
},
376 static struct omap_hwmod_dma_info omap44xx_c2c_sdma_reqs
[] = {
377 { .dma_req
= 68 + OMAP44XX_DMA_REQ_START
},
381 static struct omap_hwmod omap44xx_c2c_hwmod
= {
383 .class = &omap44xx_c2c_hwmod_class
,
384 .clkdm_name
= "d2d_clkdm",
385 .mpu_irqs
= omap44xx_c2c_irqs
,
386 .sdma_reqs
= omap44xx_c2c_sdma_reqs
,
389 .clkctrl_offs
= OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET
,
390 .context_offs
= OMAP4_RM_D2D_SAD2D_CONTEXT_OFFSET
,
397 * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
400 static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc
= {
403 .sysc_flags
= SYSC_HAS_SIDLEMODE
,
404 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
),
405 .sysc_fields
= &omap_hwmod_sysc_type1
,
408 static struct omap_hwmod_class omap44xx_counter_hwmod_class
= {
410 .sysc
= &omap44xx_counter_sysc
,
414 static struct omap_hwmod omap44xx_counter_32k_hwmod
= {
415 .name
= "counter_32k",
416 .class = &omap44xx_counter_hwmod_class
,
417 .clkdm_name
= "l4_wkup_clkdm",
418 .flags
= HWMOD_SWSUP_SIDLE
,
419 .main_clk
= "sys_32k_ck",
422 .clkctrl_offs
= OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET
,
423 .context_offs
= OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET
,
429 * 'ctrl_module' class
430 * attila core control module + core pad control module + wkup pad control
431 * module + attila wkup control module
434 static struct omap_hwmod_class_sysconfig omap44xx_ctrl_module_sysc
= {
437 .sysc_flags
= SYSC_HAS_SIDLEMODE
,
438 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
440 .sysc_fields
= &omap_hwmod_sysc_type2
,
443 static struct omap_hwmod_class omap44xx_ctrl_module_hwmod_class
= {
444 .name
= "ctrl_module",
445 .sysc
= &omap44xx_ctrl_module_sysc
,
448 /* ctrl_module_core */
449 static struct omap_hwmod_irq_info omap44xx_ctrl_module_core_irqs
[] = {
450 { .irq
= 8 + OMAP44XX_IRQ_GIC_START
},
454 static struct omap_hwmod omap44xx_ctrl_module_core_hwmod
= {
455 .name
= "ctrl_module_core",
456 .class = &omap44xx_ctrl_module_hwmod_class
,
457 .clkdm_name
= "l4_cfg_clkdm",
458 .mpu_irqs
= omap44xx_ctrl_module_core_irqs
,
461 .flags
= HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT
,
466 /* ctrl_module_pad_core */
467 static struct omap_hwmod omap44xx_ctrl_module_pad_core_hwmod
= {
468 .name
= "ctrl_module_pad_core",
469 .class = &omap44xx_ctrl_module_hwmod_class
,
470 .clkdm_name
= "l4_cfg_clkdm",
473 .flags
= HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT
,
478 /* ctrl_module_wkup */
479 static struct omap_hwmod omap44xx_ctrl_module_wkup_hwmod
= {
480 .name
= "ctrl_module_wkup",
481 .class = &omap44xx_ctrl_module_hwmod_class
,
482 .clkdm_name
= "l4_wkup_clkdm",
485 .flags
= HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT
,
490 /* ctrl_module_pad_wkup */
491 static struct omap_hwmod omap44xx_ctrl_module_pad_wkup_hwmod
= {
492 .name
= "ctrl_module_pad_wkup",
493 .class = &omap44xx_ctrl_module_hwmod_class
,
494 .clkdm_name
= "l4_wkup_clkdm",
497 .flags
= HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT
,
504 * debug and emulation sub system
507 static struct omap_hwmod_class omap44xx_debugss_hwmod_class
= {
512 static struct omap_hwmod omap44xx_debugss_hwmod
= {
514 .class = &omap44xx_debugss_hwmod_class
,
515 .clkdm_name
= "emu_sys_clkdm",
516 .main_clk
= "trace_clk_div_ck",
519 .clkctrl_offs
= OMAP4_CM_EMU_DEBUGSS_CLKCTRL_OFFSET
,
520 .context_offs
= OMAP4_RM_EMU_DEBUGSS_CONTEXT_OFFSET
,
527 * dma controller for data exchange between memory to memory (i.e. internal or
528 * external memory) and gp peripherals to memory or memory to gp peripherals
531 static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc
= {
535 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_CLOCKACTIVITY
|
536 SYSC_HAS_EMUFREE
| SYSC_HAS_MIDLEMODE
|
537 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
|
538 SYSS_HAS_RESET_STATUS
),
539 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
540 MSTANDBY_FORCE
| MSTANDBY_NO
| MSTANDBY_SMART
),
541 .sysc_fields
= &omap_hwmod_sysc_type1
,
544 static struct omap_hwmod_class omap44xx_dma_hwmod_class
= {
546 .sysc
= &omap44xx_dma_sysc
,
550 static struct omap_dma_dev_attr dma_dev_attr
= {
551 .dev_caps
= RESERVE_CHANNEL
| DMA_LINKED_LCH
| GLOBAL_PRIORITY
|
552 IS_CSSA_32
| IS_CDSA_32
| IS_RW_PRIORITY
,
557 static struct omap_hwmod_irq_info omap44xx_dma_system_irqs
[] = {
558 { .name
= "0", .irq
= 12 + OMAP44XX_IRQ_GIC_START
},
559 { .name
= "1", .irq
= 13 + OMAP44XX_IRQ_GIC_START
},
560 { .name
= "2", .irq
= 14 + OMAP44XX_IRQ_GIC_START
},
561 { .name
= "3", .irq
= 15 + OMAP44XX_IRQ_GIC_START
},
565 static struct omap_hwmod omap44xx_dma_system_hwmod
= {
566 .name
= "dma_system",
567 .class = &omap44xx_dma_hwmod_class
,
568 .clkdm_name
= "l3_dma_clkdm",
569 .mpu_irqs
= omap44xx_dma_system_irqs
,
570 .main_clk
= "l3_div_ck",
573 .clkctrl_offs
= OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET
,
574 .context_offs
= OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET
,
577 .dev_attr
= &dma_dev_attr
,
582 * digital microphone controller
585 static struct omap_hwmod_class_sysconfig omap44xx_dmic_sysc
= {
588 .sysc_flags
= (SYSC_HAS_EMUFREE
| SYSC_HAS_RESET_STATUS
|
589 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
),
590 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
592 .sysc_fields
= &omap_hwmod_sysc_type2
,
595 static struct omap_hwmod_class omap44xx_dmic_hwmod_class
= {
597 .sysc
= &omap44xx_dmic_sysc
,
601 static struct omap_hwmod_irq_info omap44xx_dmic_irqs
[] = {
602 { .irq
= 114 + OMAP44XX_IRQ_GIC_START
},
606 static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs
[] = {
607 { .dma_req
= 66 + OMAP44XX_DMA_REQ_START
},
611 static struct omap_hwmod omap44xx_dmic_hwmod
= {
613 .class = &omap44xx_dmic_hwmod_class
,
614 .clkdm_name
= "abe_clkdm",
615 .mpu_irqs
= omap44xx_dmic_irqs
,
616 .sdma_reqs
= omap44xx_dmic_sdma_reqs
,
617 .main_clk
= "dmic_fck",
620 .clkctrl_offs
= OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET
,
621 .context_offs
= OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET
,
622 .modulemode
= MODULEMODE_SWCTRL
,
632 static struct omap_hwmod_class omap44xx_dsp_hwmod_class
= {
637 static struct omap_hwmod_irq_info omap44xx_dsp_irqs
[] = {
638 { .irq
= 28 + OMAP44XX_IRQ_GIC_START
},
642 static struct omap_hwmod_rst_info omap44xx_dsp_resets
[] = {
643 { .name
= "dsp", .rst_shift
= 0 },
646 static struct omap_hwmod omap44xx_dsp_hwmod
= {
648 .class = &omap44xx_dsp_hwmod_class
,
649 .clkdm_name
= "tesla_clkdm",
650 .mpu_irqs
= omap44xx_dsp_irqs
,
651 .rst_lines
= omap44xx_dsp_resets
,
652 .rst_lines_cnt
= ARRAY_SIZE(omap44xx_dsp_resets
),
653 .main_clk
= "dsp_fck",
656 .clkctrl_offs
= OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET
,
657 .rstctrl_offs
= OMAP4_RM_TESLA_RSTCTRL_OFFSET
,
658 .context_offs
= OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET
,
659 .modulemode
= MODULEMODE_HWCTRL
,
669 static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc
= {
672 .sysc_flags
= SYSS_HAS_RESET_STATUS
,
675 static struct omap_hwmod_class omap44xx_dss_hwmod_class
= {
677 .sysc
= &omap44xx_dss_sysc
,
678 .reset
= omap_dss_reset
,
682 static struct omap_hwmod_opt_clk dss_opt_clks
[] = {
683 { .role
= "sys_clk", .clk
= "dss_sys_clk" },
684 { .role
= "tv_clk", .clk
= "dss_tv_clk" },
685 { .role
= "hdmi_clk", .clk
= "dss_48mhz_clk" },
688 static struct omap_hwmod omap44xx_dss_hwmod
= {
690 .flags
= HWMOD_CONTROL_OPT_CLKS_IN_RESET
,
691 .class = &omap44xx_dss_hwmod_class
,
692 .clkdm_name
= "l3_dss_clkdm",
693 .main_clk
= "dss_dss_clk",
696 .clkctrl_offs
= OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET
,
697 .context_offs
= OMAP4_RM_DSS_DSS_CONTEXT_OFFSET
,
700 .opt_clks
= dss_opt_clks
,
701 .opt_clks_cnt
= ARRAY_SIZE(dss_opt_clks
),
709 static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc
= {
713 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_CLOCKACTIVITY
|
714 SYSC_HAS_ENAWAKEUP
| SYSC_HAS_MIDLEMODE
|
715 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
|
716 SYSS_HAS_RESET_STATUS
),
717 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
718 MSTANDBY_FORCE
| MSTANDBY_NO
| MSTANDBY_SMART
),
719 .sysc_fields
= &omap_hwmod_sysc_type1
,
722 static struct omap_hwmod_class omap44xx_dispc_hwmod_class
= {
724 .sysc
= &omap44xx_dispc_sysc
,
728 static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs
[] = {
729 { .irq
= 25 + OMAP44XX_IRQ_GIC_START
},
733 static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs
[] = {
734 { .dma_req
= 5 + OMAP44XX_DMA_REQ_START
},
738 static struct omap_dss_dispc_dev_attr omap44xx_dss_dispc_dev_attr
= {
740 .has_framedonetv_irq
= 1
743 static struct omap_hwmod omap44xx_dss_dispc_hwmod
= {
745 .class = &omap44xx_dispc_hwmod_class
,
746 .clkdm_name
= "l3_dss_clkdm",
747 .mpu_irqs
= omap44xx_dss_dispc_irqs
,
748 .sdma_reqs
= omap44xx_dss_dispc_sdma_reqs
,
749 .main_clk
= "dss_dss_clk",
752 .clkctrl_offs
= OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET
,
753 .context_offs
= OMAP4_RM_DSS_DSS_CONTEXT_OFFSET
,
756 .dev_attr
= &omap44xx_dss_dispc_dev_attr
761 * display serial interface controller
764 static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc
= {
768 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_CLOCKACTIVITY
|
769 SYSC_HAS_ENAWAKEUP
| SYSC_HAS_SIDLEMODE
|
770 SYSC_HAS_SOFTRESET
| SYSS_HAS_RESET_STATUS
),
771 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
772 .sysc_fields
= &omap_hwmod_sysc_type1
,
775 static struct omap_hwmod_class omap44xx_dsi_hwmod_class
= {
777 .sysc
= &omap44xx_dsi_sysc
,
781 static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs
[] = {
782 { .irq
= 53 + OMAP44XX_IRQ_GIC_START
},
786 static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs
[] = {
787 { .dma_req
= 74 + OMAP44XX_DMA_REQ_START
},
791 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks
[] = {
792 { .role
= "sys_clk", .clk
= "dss_sys_clk" },
795 static struct omap_hwmod omap44xx_dss_dsi1_hwmod
= {
797 .class = &omap44xx_dsi_hwmod_class
,
798 .clkdm_name
= "l3_dss_clkdm",
799 .mpu_irqs
= omap44xx_dss_dsi1_irqs
,
800 .sdma_reqs
= omap44xx_dss_dsi1_sdma_reqs
,
801 .main_clk
= "dss_dss_clk",
804 .clkctrl_offs
= OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET
,
805 .context_offs
= OMAP4_RM_DSS_DSS_CONTEXT_OFFSET
,
808 .opt_clks
= dss_dsi1_opt_clks
,
809 .opt_clks_cnt
= ARRAY_SIZE(dss_dsi1_opt_clks
),
813 static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs
[] = {
814 { .irq
= 84 + OMAP44XX_IRQ_GIC_START
},
818 static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs
[] = {
819 { .dma_req
= 83 + OMAP44XX_DMA_REQ_START
},
823 static struct omap_hwmod_opt_clk dss_dsi2_opt_clks
[] = {
824 { .role
= "sys_clk", .clk
= "dss_sys_clk" },
827 static struct omap_hwmod omap44xx_dss_dsi2_hwmod
= {
829 .class = &omap44xx_dsi_hwmod_class
,
830 .clkdm_name
= "l3_dss_clkdm",
831 .mpu_irqs
= omap44xx_dss_dsi2_irqs
,
832 .sdma_reqs
= omap44xx_dss_dsi2_sdma_reqs
,
833 .main_clk
= "dss_dss_clk",
836 .clkctrl_offs
= OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET
,
837 .context_offs
= OMAP4_RM_DSS_DSS_CONTEXT_OFFSET
,
840 .opt_clks
= dss_dsi2_opt_clks
,
841 .opt_clks_cnt
= ARRAY_SIZE(dss_dsi2_opt_clks
),
849 static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc
= {
852 .sysc_flags
= (SYSC_HAS_RESET_STATUS
| SYSC_HAS_SIDLEMODE
|
854 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
856 .sysc_fields
= &omap_hwmod_sysc_type2
,
859 static struct omap_hwmod_class omap44xx_hdmi_hwmod_class
= {
861 .sysc
= &omap44xx_hdmi_sysc
,
865 static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs
[] = {
866 { .irq
= 101 + OMAP44XX_IRQ_GIC_START
},
870 static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs
[] = {
871 { .dma_req
= 75 + OMAP44XX_DMA_REQ_START
},
875 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks
[] = {
876 { .role
= "sys_clk", .clk
= "dss_sys_clk" },
879 static struct omap_hwmod omap44xx_dss_hdmi_hwmod
= {
881 .class = &omap44xx_hdmi_hwmod_class
,
882 .clkdm_name
= "l3_dss_clkdm",
884 * HDMI audio requires to use no-idle mode. Hence,
885 * set idle mode by software.
887 .flags
= HWMOD_SWSUP_SIDLE
,
888 .mpu_irqs
= omap44xx_dss_hdmi_irqs
,
889 .sdma_reqs
= omap44xx_dss_hdmi_sdma_reqs
,
890 .main_clk
= "dss_48mhz_clk",
893 .clkctrl_offs
= OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET
,
894 .context_offs
= OMAP4_RM_DSS_DSS_CONTEXT_OFFSET
,
897 .opt_clks
= dss_hdmi_opt_clks
,
898 .opt_clks_cnt
= ARRAY_SIZE(dss_hdmi_opt_clks
),
903 * remote frame buffer interface
906 static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc
= {
910 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_SIDLEMODE
|
911 SYSC_HAS_SOFTRESET
| SYSS_HAS_RESET_STATUS
),
912 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
913 .sysc_fields
= &omap_hwmod_sysc_type1
,
916 static struct omap_hwmod_class omap44xx_rfbi_hwmod_class
= {
918 .sysc
= &omap44xx_rfbi_sysc
,
922 static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs
[] = {
923 { .dma_req
= 13 + OMAP44XX_DMA_REQ_START
},
927 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks
[] = {
928 { .role
= "ick", .clk
= "dss_fck" },
931 static struct omap_hwmod omap44xx_dss_rfbi_hwmod
= {
933 .class = &omap44xx_rfbi_hwmod_class
,
934 .clkdm_name
= "l3_dss_clkdm",
935 .sdma_reqs
= omap44xx_dss_rfbi_sdma_reqs
,
936 .main_clk
= "dss_dss_clk",
939 .clkctrl_offs
= OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET
,
940 .context_offs
= OMAP4_RM_DSS_DSS_CONTEXT_OFFSET
,
943 .opt_clks
= dss_rfbi_opt_clks
,
944 .opt_clks_cnt
= ARRAY_SIZE(dss_rfbi_opt_clks
),
952 static struct omap_hwmod_class omap44xx_venc_hwmod_class
= {
957 static struct omap_hwmod omap44xx_dss_venc_hwmod
= {
959 .class = &omap44xx_venc_hwmod_class
,
960 .clkdm_name
= "l3_dss_clkdm",
961 .main_clk
= "dss_tv_clk",
964 .clkctrl_offs
= OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET
,
965 .context_offs
= OMAP4_RM_DSS_DSS_CONTEXT_OFFSET
,
972 * bch error location module
975 static struct omap_hwmod_class_sysconfig omap44xx_elm_sysc
= {
979 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_CLOCKACTIVITY
|
980 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
|
981 SYSS_HAS_RESET_STATUS
),
982 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
983 .sysc_fields
= &omap_hwmod_sysc_type1
,
986 static struct omap_hwmod_class omap44xx_elm_hwmod_class
= {
988 .sysc
= &omap44xx_elm_sysc
,
992 static struct omap_hwmod_irq_info omap44xx_elm_irqs
[] = {
993 { .irq
= 4 + OMAP44XX_IRQ_GIC_START
},
997 static struct omap_hwmod omap44xx_elm_hwmod
= {
999 .class = &omap44xx_elm_hwmod_class
,
1000 .clkdm_name
= "l4_per_clkdm",
1001 .mpu_irqs
= omap44xx_elm_irqs
,
1004 .clkctrl_offs
= OMAP4_CM_L4PER_ELM_CLKCTRL_OFFSET
,
1005 .context_offs
= OMAP4_RM_L4PER_ELM_CONTEXT_OFFSET
,
1012 * external memory interface no1
1015 static struct omap_hwmod_class_sysconfig omap44xx_emif_sysc
= {
1019 static struct omap_hwmod_class omap44xx_emif_hwmod_class
= {
1021 .sysc
= &omap44xx_emif_sysc
,
1025 static struct omap_hwmod_irq_info omap44xx_emif1_irqs
[] = {
1026 { .irq
= 110 + OMAP44XX_IRQ_GIC_START
},
1030 static struct omap_hwmod omap44xx_emif1_hwmod
= {
1032 .class = &omap44xx_emif_hwmod_class
,
1033 .clkdm_name
= "l3_emif_clkdm",
1034 .flags
= HWMOD_INIT_NO_IDLE
| HWMOD_INIT_NO_RESET
,
1035 .mpu_irqs
= omap44xx_emif1_irqs
,
1036 .main_clk
= "ddrphy_ck",
1039 .clkctrl_offs
= OMAP4_CM_MEMIF_EMIF_1_CLKCTRL_OFFSET
,
1040 .context_offs
= OMAP4_RM_MEMIF_EMIF_1_CONTEXT_OFFSET
,
1041 .modulemode
= MODULEMODE_HWCTRL
,
1047 static struct omap_hwmod_irq_info omap44xx_emif2_irqs
[] = {
1048 { .irq
= 111 + OMAP44XX_IRQ_GIC_START
},
1052 static struct omap_hwmod omap44xx_emif2_hwmod
= {
1054 .class = &omap44xx_emif_hwmod_class
,
1055 .clkdm_name
= "l3_emif_clkdm",
1056 .flags
= HWMOD_INIT_NO_IDLE
| HWMOD_INIT_NO_RESET
,
1057 .mpu_irqs
= omap44xx_emif2_irqs
,
1058 .main_clk
= "ddrphy_ck",
1061 .clkctrl_offs
= OMAP4_CM_MEMIF_EMIF_2_CLKCTRL_OFFSET
,
1062 .context_offs
= OMAP4_RM_MEMIF_EMIF_2_CONTEXT_OFFSET
,
1063 .modulemode
= MODULEMODE_HWCTRL
,
1070 * face detection hw accelerator module
1073 static struct omap_hwmod_class_sysconfig omap44xx_fdif_sysc
= {
1075 .sysc_offs
= 0x0010,
1077 * FDIF needs 100 OCP clk cycles delay after a softreset before
1078 * accessing sysconfig again.
1079 * The lowest frequency at the moment for L3 bus is 100 MHz, so
1080 * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
1082 * TODO: Indicate errata when available.
1085 .sysc_flags
= (SYSC_HAS_MIDLEMODE
| SYSC_HAS_RESET_STATUS
|
1086 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
),
1087 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
1088 MSTANDBY_FORCE
| MSTANDBY_NO
| MSTANDBY_SMART
),
1089 .sysc_fields
= &omap_hwmod_sysc_type2
,
1092 static struct omap_hwmod_class omap44xx_fdif_hwmod_class
= {
1094 .sysc
= &omap44xx_fdif_sysc
,
1098 static struct omap_hwmod_irq_info omap44xx_fdif_irqs
[] = {
1099 { .irq
= 69 + OMAP44XX_IRQ_GIC_START
},
1103 static struct omap_hwmod omap44xx_fdif_hwmod
= {
1105 .class = &omap44xx_fdif_hwmod_class
,
1106 .clkdm_name
= "iss_clkdm",
1107 .mpu_irqs
= omap44xx_fdif_irqs
,
1108 .main_clk
= "fdif_fck",
1111 .clkctrl_offs
= OMAP4_CM_CAM_FDIF_CLKCTRL_OFFSET
,
1112 .context_offs
= OMAP4_RM_CAM_FDIF_CONTEXT_OFFSET
,
1113 .modulemode
= MODULEMODE_SWCTRL
,
1120 * general purpose io module
1123 static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc
= {
1125 .sysc_offs
= 0x0010,
1126 .syss_offs
= 0x0114,
1127 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_ENAWAKEUP
|
1128 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
|
1129 SYSS_HAS_RESET_STATUS
),
1130 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
1132 .sysc_fields
= &omap_hwmod_sysc_type1
,
1135 static struct omap_hwmod_class omap44xx_gpio_hwmod_class
= {
1137 .sysc
= &omap44xx_gpio_sysc
,
1142 static struct omap_gpio_dev_attr gpio_dev_attr
= {
1148 static struct omap_hwmod_irq_info omap44xx_gpio1_irqs
[] = {
1149 { .irq
= 29 + OMAP44XX_IRQ_GIC_START
},
1153 static struct omap_hwmod_opt_clk gpio1_opt_clks
[] = {
1154 { .role
= "dbclk", .clk
= "gpio1_dbclk" },
1157 static struct omap_hwmod omap44xx_gpio1_hwmod
= {
1159 .class = &omap44xx_gpio_hwmod_class
,
1160 .clkdm_name
= "l4_wkup_clkdm",
1161 .mpu_irqs
= omap44xx_gpio1_irqs
,
1162 .main_clk
= "gpio1_ick",
1165 .clkctrl_offs
= OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET
,
1166 .context_offs
= OMAP4_RM_WKUP_GPIO1_CONTEXT_OFFSET
,
1167 .modulemode
= MODULEMODE_HWCTRL
,
1170 .opt_clks
= gpio1_opt_clks
,
1171 .opt_clks_cnt
= ARRAY_SIZE(gpio1_opt_clks
),
1172 .dev_attr
= &gpio_dev_attr
,
1176 static struct omap_hwmod_irq_info omap44xx_gpio2_irqs
[] = {
1177 { .irq
= 30 + OMAP44XX_IRQ_GIC_START
},
1181 static struct omap_hwmod_opt_clk gpio2_opt_clks
[] = {
1182 { .role
= "dbclk", .clk
= "gpio2_dbclk" },
1185 static struct omap_hwmod omap44xx_gpio2_hwmod
= {
1187 .class = &omap44xx_gpio_hwmod_class
,
1188 .clkdm_name
= "l4_per_clkdm",
1189 .flags
= HWMOD_CONTROL_OPT_CLKS_IN_RESET
,
1190 .mpu_irqs
= omap44xx_gpio2_irqs
,
1191 .main_clk
= "gpio2_ick",
1194 .clkctrl_offs
= OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET
,
1195 .context_offs
= OMAP4_RM_L4PER_GPIO2_CONTEXT_OFFSET
,
1196 .modulemode
= MODULEMODE_HWCTRL
,
1199 .opt_clks
= gpio2_opt_clks
,
1200 .opt_clks_cnt
= ARRAY_SIZE(gpio2_opt_clks
),
1201 .dev_attr
= &gpio_dev_attr
,
1205 static struct omap_hwmod_irq_info omap44xx_gpio3_irqs
[] = {
1206 { .irq
= 31 + OMAP44XX_IRQ_GIC_START
},
1210 static struct omap_hwmod_opt_clk gpio3_opt_clks
[] = {
1211 { .role
= "dbclk", .clk
= "gpio3_dbclk" },
1214 static struct omap_hwmod omap44xx_gpio3_hwmod
= {
1216 .class = &omap44xx_gpio_hwmod_class
,
1217 .clkdm_name
= "l4_per_clkdm",
1218 .flags
= HWMOD_CONTROL_OPT_CLKS_IN_RESET
,
1219 .mpu_irqs
= omap44xx_gpio3_irqs
,
1220 .main_clk
= "gpio3_ick",
1223 .clkctrl_offs
= OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET
,
1224 .context_offs
= OMAP4_RM_L4PER_GPIO3_CONTEXT_OFFSET
,
1225 .modulemode
= MODULEMODE_HWCTRL
,
1228 .opt_clks
= gpio3_opt_clks
,
1229 .opt_clks_cnt
= ARRAY_SIZE(gpio3_opt_clks
),
1230 .dev_attr
= &gpio_dev_attr
,
1234 static struct omap_hwmod_irq_info omap44xx_gpio4_irqs
[] = {
1235 { .irq
= 32 + OMAP44XX_IRQ_GIC_START
},
1239 static struct omap_hwmod_opt_clk gpio4_opt_clks
[] = {
1240 { .role
= "dbclk", .clk
= "gpio4_dbclk" },
1243 static struct omap_hwmod omap44xx_gpio4_hwmod
= {
1245 .class = &omap44xx_gpio_hwmod_class
,
1246 .clkdm_name
= "l4_per_clkdm",
1247 .flags
= HWMOD_CONTROL_OPT_CLKS_IN_RESET
,
1248 .mpu_irqs
= omap44xx_gpio4_irqs
,
1249 .main_clk
= "gpio4_ick",
1252 .clkctrl_offs
= OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET
,
1253 .context_offs
= OMAP4_RM_L4PER_GPIO4_CONTEXT_OFFSET
,
1254 .modulemode
= MODULEMODE_HWCTRL
,
1257 .opt_clks
= gpio4_opt_clks
,
1258 .opt_clks_cnt
= ARRAY_SIZE(gpio4_opt_clks
),
1259 .dev_attr
= &gpio_dev_attr
,
1263 static struct omap_hwmod_irq_info omap44xx_gpio5_irqs
[] = {
1264 { .irq
= 33 + OMAP44XX_IRQ_GIC_START
},
1268 static struct omap_hwmod_opt_clk gpio5_opt_clks
[] = {
1269 { .role
= "dbclk", .clk
= "gpio5_dbclk" },
1272 static struct omap_hwmod omap44xx_gpio5_hwmod
= {
1274 .class = &omap44xx_gpio_hwmod_class
,
1275 .clkdm_name
= "l4_per_clkdm",
1276 .flags
= HWMOD_CONTROL_OPT_CLKS_IN_RESET
,
1277 .mpu_irqs
= omap44xx_gpio5_irqs
,
1278 .main_clk
= "gpio5_ick",
1281 .clkctrl_offs
= OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET
,
1282 .context_offs
= OMAP4_RM_L4PER_GPIO5_CONTEXT_OFFSET
,
1283 .modulemode
= MODULEMODE_HWCTRL
,
1286 .opt_clks
= gpio5_opt_clks
,
1287 .opt_clks_cnt
= ARRAY_SIZE(gpio5_opt_clks
),
1288 .dev_attr
= &gpio_dev_attr
,
1292 static struct omap_hwmod_irq_info omap44xx_gpio6_irqs
[] = {
1293 { .irq
= 34 + OMAP44XX_IRQ_GIC_START
},
1297 static struct omap_hwmod_opt_clk gpio6_opt_clks
[] = {
1298 { .role
= "dbclk", .clk
= "gpio6_dbclk" },
1301 static struct omap_hwmod omap44xx_gpio6_hwmod
= {
1303 .class = &omap44xx_gpio_hwmod_class
,
1304 .clkdm_name
= "l4_per_clkdm",
1305 .flags
= HWMOD_CONTROL_OPT_CLKS_IN_RESET
,
1306 .mpu_irqs
= omap44xx_gpio6_irqs
,
1307 .main_clk
= "gpio6_ick",
1310 .clkctrl_offs
= OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET
,
1311 .context_offs
= OMAP4_RM_L4PER_GPIO6_CONTEXT_OFFSET
,
1312 .modulemode
= MODULEMODE_HWCTRL
,
1315 .opt_clks
= gpio6_opt_clks
,
1316 .opt_clks_cnt
= ARRAY_SIZE(gpio6_opt_clks
),
1317 .dev_attr
= &gpio_dev_attr
,
1322 * general purpose memory controller
1325 static struct omap_hwmod_class_sysconfig omap44xx_gpmc_sysc
= {
1327 .sysc_offs
= 0x0010,
1328 .syss_offs
= 0x0014,
1329 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_SIDLEMODE
|
1330 SYSC_HAS_SOFTRESET
| SYSS_HAS_RESET_STATUS
),
1331 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
1332 .sysc_fields
= &omap_hwmod_sysc_type1
,
1335 static struct omap_hwmod_class omap44xx_gpmc_hwmod_class
= {
1337 .sysc
= &omap44xx_gpmc_sysc
,
1341 static struct omap_hwmod_irq_info omap44xx_gpmc_irqs
[] = {
1342 { .irq
= 20 + OMAP44XX_IRQ_GIC_START
},
1346 static struct omap_hwmod_dma_info omap44xx_gpmc_sdma_reqs
[] = {
1347 { .dma_req
= 3 + OMAP44XX_DMA_REQ_START
},
1351 static struct omap_hwmod omap44xx_gpmc_hwmod
= {
1353 .class = &omap44xx_gpmc_hwmod_class
,
1354 .clkdm_name
= "l3_2_clkdm",
1356 * XXX HWMOD_INIT_NO_RESET should not be needed for this IP
1357 * block. It is not being added due to any known bugs with
1358 * resetting the GPMC IP block, but rather because any timings
1359 * set by the bootloader are not being correctly programmed by
1360 * the kernel from the board file or DT data.
1361 * HWMOD_INIT_NO_RESET should be removed ASAP.
1363 .flags
= HWMOD_INIT_NO_IDLE
| HWMOD_INIT_NO_RESET
,
1364 .mpu_irqs
= omap44xx_gpmc_irqs
,
1365 .sdma_reqs
= omap44xx_gpmc_sdma_reqs
,
1368 .clkctrl_offs
= OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET
,
1369 .context_offs
= OMAP4_RM_L3_2_GPMC_CONTEXT_OFFSET
,
1370 .modulemode
= MODULEMODE_HWCTRL
,
1377 * 2d/3d graphics accelerator
1380 static struct omap_hwmod_class_sysconfig omap44xx_gpu_sysc
= {
1381 .rev_offs
= 0x1fc00,
1382 .sysc_offs
= 0x1fc10,
1383 .sysc_flags
= (SYSC_HAS_MIDLEMODE
| SYSC_HAS_SIDLEMODE
),
1384 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
1385 SIDLE_SMART_WKUP
| MSTANDBY_FORCE
| MSTANDBY_NO
|
1386 MSTANDBY_SMART
| MSTANDBY_SMART_WKUP
),
1387 .sysc_fields
= &omap_hwmod_sysc_type2
,
1390 static struct omap_hwmod_class omap44xx_gpu_hwmod_class
= {
1392 .sysc
= &omap44xx_gpu_sysc
,
1396 static struct omap_hwmod_irq_info omap44xx_gpu_irqs
[] = {
1397 { .irq
= 21 + OMAP44XX_IRQ_GIC_START
},
1401 static struct omap_hwmod omap44xx_gpu_hwmod
= {
1403 .class = &omap44xx_gpu_hwmod_class
,
1404 .clkdm_name
= "l3_gfx_clkdm",
1405 .mpu_irqs
= omap44xx_gpu_irqs
,
1406 .main_clk
= "gpu_fck",
1409 .clkctrl_offs
= OMAP4_CM_GFX_GFX_CLKCTRL_OFFSET
,
1410 .context_offs
= OMAP4_RM_GFX_GFX_CONTEXT_OFFSET
,
1411 .modulemode
= MODULEMODE_SWCTRL
,
1418 * hdq / 1-wire serial interface controller
1421 static struct omap_hwmod_class_sysconfig omap44xx_hdq1w_sysc
= {
1423 .sysc_offs
= 0x0014,
1424 .syss_offs
= 0x0018,
1425 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_SOFTRESET
|
1426 SYSS_HAS_RESET_STATUS
),
1427 .sysc_fields
= &omap_hwmod_sysc_type1
,
1430 static struct omap_hwmod_class omap44xx_hdq1w_hwmod_class
= {
1432 .sysc
= &omap44xx_hdq1w_sysc
,
1436 static struct omap_hwmod_irq_info omap44xx_hdq1w_irqs
[] = {
1437 { .irq
= 58 + OMAP44XX_IRQ_GIC_START
},
1441 static struct omap_hwmod omap44xx_hdq1w_hwmod
= {
1443 .class = &omap44xx_hdq1w_hwmod_class
,
1444 .clkdm_name
= "l4_per_clkdm",
1445 .flags
= HWMOD_INIT_NO_RESET
, /* XXX temporary */
1446 .mpu_irqs
= omap44xx_hdq1w_irqs
,
1447 .main_clk
= "hdq1w_fck",
1450 .clkctrl_offs
= OMAP4_CM_L4PER_HDQ1W_CLKCTRL_OFFSET
,
1451 .context_offs
= OMAP4_RM_L4PER_HDQ1W_CONTEXT_OFFSET
,
1452 .modulemode
= MODULEMODE_SWCTRL
,
1459 * mipi high-speed synchronous serial interface (multichannel and full-duplex
1463 static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc
= {
1465 .sysc_offs
= 0x0010,
1466 .syss_offs
= 0x0014,
1467 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_EMUFREE
|
1468 SYSC_HAS_MIDLEMODE
| SYSC_HAS_SIDLEMODE
|
1469 SYSC_HAS_SOFTRESET
| SYSS_HAS_RESET_STATUS
),
1470 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
1471 SIDLE_SMART_WKUP
| MSTANDBY_FORCE
| MSTANDBY_NO
|
1472 MSTANDBY_SMART
| MSTANDBY_SMART_WKUP
),
1473 .sysc_fields
= &omap_hwmod_sysc_type1
,
1476 static struct omap_hwmod_class omap44xx_hsi_hwmod_class
= {
1478 .sysc
= &omap44xx_hsi_sysc
,
1482 static struct omap_hwmod_irq_info omap44xx_hsi_irqs
[] = {
1483 { .name
= "mpu_p1", .irq
= 67 + OMAP44XX_IRQ_GIC_START
},
1484 { .name
= "mpu_p2", .irq
= 68 + OMAP44XX_IRQ_GIC_START
},
1485 { .name
= "mpu_dma", .irq
= 71 + OMAP44XX_IRQ_GIC_START
},
1489 static struct omap_hwmod omap44xx_hsi_hwmod
= {
1491 .class = &omap44xx_hsi_hwmod_class
,
1492 .clkdm_name
= "l3_init_clkdm",
1493 .mpu_irqs
= omap44xx_hsi_irqs
,
1494 .main_clk
= "hsi_fck",
1497 .clkctrl_offs
= OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET
,
1498 .context_offs
= OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET
,
1499 .modulemode
= MODULEMODE_HWCTRL
,
1506 * multimaster high-speed i2c controller
1509 static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc
= {
1510 .sysc_offs
= 0x0010,
1511 .syss_offs
= 0x0090,
1512 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_CLOCKACTIVITY
|
1513 SYSC_HAS_ENAWAKEUP
| SYSC_HAS_SIDLEMODE
|
1514 SYSC_HAS_SOFTRESET
| SYSS_HAS_RESET_STATUS
),
1515 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
1517 .clockact
= CLOCKACT_TEST_ICLK
,
1518 .sysc_fields
= &omap_hwmod_sysc_type1
,
1521 static struct omap_hwmod_class omap44xx_i2c_hwmod_class
= {
1523 .sysc
= &omap44xx_i2c_sysc
,
1524 .rev
= OMAP_I2C_IP_VERSION_2
,
1525 .reset
= &omap_i2c_reset
,
1528 static struct omap_i2c_dev_attr i2c_dev_attr
= {
1529 .flags
= OMAP_I2C_FLAG_BUS_SHIFT_NONE
,
1533 static struct omap_hwmod_irq_info omap44xx_i2c1_irqs
[] = {
1534 { .irq
= 56 + OMAP44XX_IRQ_GIC_START
},
1538 static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs
[] = {
1539 { .name
= "tx", .dma_req
= 26 + OMAP44XX_DMA_REQ_START
},
1540 { .name
= "rx", .dma_req
= 27 + OMAP44XX_DMA_REQ_START
},
1544 static struct omap_hwmod omap44xx_i2c1_hwmod
= {
1546 .class = &omap44xx_i2c_hwmod_class
,
1547 .clkdm_name
= "l4_per_clkdm",
1548 .flags
= HWMOD_16BIT_REG
| HWMOD_SET_DEFAULT_CLOCKACT
,
1549 .mpu_irqs
= omap44xx_i2c1_irqs
,
1550 .sdma_reqs
= omap44xx_i2c1_sdma_reqs
,
1551 .main_clk
= "i2c1_fck",
1554 .clkctrl_offs
= OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET
,
1555 .context_offs
= OMAP4_RM_L4PER_I2C1_CONTEXT_OFFSET
,
1556 .modulemode
= MODULEMODE_SWCTRL
,
1559 .dev_attr
= &i2c_dev_attr
,
1563 static struct omap_hwmod_irq_info omap44xx_i2c2_irqs
[] = {
1564 { .irq
= 57 + OMAP44XX_IRQ_GIC_START
},
1568 static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs
[] = {
1569 { .name
= "tx", .dma_req
= 28 + OMAP44XX_DMA_REQ_START
},
1570 { .name
= "rx", .dma_req
= 29 + OMAP44XX_DMA_REQ_START
},
1574 static struct omap_hwmod omap44xx_i2c2_hwmod
= {
1576 .class = &omap44xx_i2c_hwmod_class
,
1577 .clkdm_name
= "l4_per_clkdm",
1578 .flags
= HWMOD_16BIT_REG
| HWMOD_SET_DEFAULT_CLOCKACT
,
1579 .mpu_irqs
= omap44xx_i2c2_irqs
,
1580 .sdma_reqs
= omap44xx_i2c2_sdma_reqs
,
1581 .main_clk
= "i2c2_fck",
1584 .clkctrl_offs
= OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET
,
1585 .context_offs
= OMAP4_RM_L4PER_I2C2_CONTEXT_OFFSET
,
1586 .modulemode
= MODULEMODE_SWCTRL
,
1589 .dev_attr
= &i2c_dev_attr
,
1593 static struct omap_hwmod_irq_info omap44xx_i2c3_irqs
[] = {
1594 { .irq
= 61 + OMAP44XX_IRQ_GIC_START
},
1598 static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs
[] = {
1599 { .name
= "tx", .dma_req
= 24 + OMAP44XX_DMA_REQ_START
},
1600 { .name
= "rx", .dma_req
= 25 + OMAP44XX_DMA_REQ_START
},
1604 static struct omap_hwmod omap44xx_i2c3_hwmod
= {
1606 .class = &omap44xx_i2c_hwmod_class
,
1607 .clkdm_name
= "l4_per_clkdm",
1608 .flags
= HWMOD_16BIT_REG
| HWMOD_SET_DEFAULT_CLOCKACT
,
1609 .mpu_irqs
= omap44xx_i2c3_irqs
,
1610 .sdma_reqs
= omap44xx_i2c3_sdma_reqs
,
1611 .main_clk
= "i2c3_fck",
1614 .clkctrl_offs
= OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET
,
1615 .context_offs
= OMAP4_RM_L4PER_I2C3_CONTEXT_OFFSET
,
1616 .modulemode
= MODULEMODE_SWCTRL
,
1619 .dev_attr
= &i2c_dev_attr
,
1623 static struct omap_hwmod_irq_info omap44xx_i2c4_irqs
[] = {
1624 { .irq
= 62 + OMAP44XX_IRQ_GIC_START
},
1628 static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs
[] = {
1629 { .name
= "tx", .dma_req
= 123 + OMAP44XX_DMA_REQ_START
},
1630 { .name
= "rx", .dma_req
= 124 + OMAP44XX_DMA_REQ_START
},
1634 static struct omap_hwmod omap44xx_i2c4_hwmod
= {
1636 .class = &omap44xx_i2c_hwmod_class
,
1637 .clkdm_name
= "l4_per_clkdm",
1638 .flags
= HWMOD_16BIT_REG
| HWMOD_SET_DEFAULT_CLOCKACT
,
1639 .mpu_irqs
= omap44xx_i2c4_irqs
,
1640 .sdma_reqs
= omap44xx_i2c4_sdma_reqs
,
1641 .main_clk
= "i2c4_fck",
1644 .clkctrl_offs
= OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET
,
1645 .context_offs
= OMAP4_RM_L4PER_I2C4_CONTEXT_OFFSET
,
1646 .modulemode
= MODULEMODE_SWCTRL
,
1649 .dev_attr
= &i2c_dev_attr
,
1654 * imaging processor unit
1657 static struct omap_hwmod_class omap44xx_ipu_hwmod_class
= {
1662 static struct omap_hwmod_irq_info omap44xx_ipu_irqs
[] = {
1663 { .irq
= 100 + OMAP44XX_IRQ_GIC_START
},
1667 static struct omap_hwmod_rst_info omap44xx_ipu_resets
[] = {
1668 { .name
= "cpu0", .rst_shift
= 0 },
1669 { .name
= "cpu1", .rst_shift
= 1 },
1672 static struct omap_hwmod omap44xx_ipu_hwmod
= {
1674 .class = &omap44xx_ipu_hwmod_class
,
1675 .clkdm_name
= "ducati_clkdm",
1676 .mpu_irqs
= omap44xx_ipu_irqs
,
1677 .rst_lines
= omap44xx_ipu_resets
,
1678 .rst_lines_cnt
= ARRAY_SIZE(omap44xx_ipu_resets
),
1679 .main_clk
= "ipu_fck",
1682 .clkctrl_offs
= OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET
,
1683 .rstctrl_offs
= OMAP4_RM_DUCATI_RSTCTRL_OFFSET
,
1684 .context_offs
= OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET
,
1685 .modulemode
= MODULEMODE_HWCTRL
,
1692 * external images sensor pixel data processor
1695 static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc
= {
1697 .sysc_offs
= 0x0010,
1699 * ISS needs 100 OCP clk cycles delay after a softreset before
1700 * accessing sysconfig again.
1701 * The lowest frequency at the moment for L3 bus is 100 MHz, so
1702 * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
1704 * TODO: Indicate errata when available.
1707 .sysc_flags
= (SYSC_HAS_MIDLEMODE
| SYSC_HAS_RESET_STATUS
|
1708 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
),
1709 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
1710 SIDLE_SMART_WKUP
| MSTANDBY_FORCE
| MSTANDBY_NO
|
1711 MSTANDBY_SMART
| MSTANDBY_SMART_WKUP
),
1712 .sysc_fields
= &omap_hwmod_sysc_type2
,
1715 static struct omap_hwmod_class omap44xx_iss_hwmod_class
= {
1717 .sysc
= &omap44xx_iss_sysc
,
1721 static struct omap_hwmod_irq_info omap44xx_iss_irqs
[] = {
1722 { .irq
= 24 + OMAP44XX_IRQ_GIC_START
},
1726 static struct omap_hwmod_dma_info omap44xx_iss_sdma_reqs
[] = {
1727 { .name
= "1", .dma_req
= 8 + OMAP44XX_DMA_REQ_START
},
1728 { .name
= "2", .dma_req
= 9 + OMAP44XX_DMA_REQ_START
},
1729 { .name
= "3", .dma_req
= 11 + OMAP44XX_DMA_REQ_START
},
1730 { .name
= "4", .dma_req
= 12 + OMAP44XX_DMA_REQ_START
},
1734 static struct omap_hwmod_opt_clk iss_opt_clks
[] = {
1735 { .role
= "ctrlclk", .clk
= "iss_ctrlclk" },
1738 static struct omap_hwmod omap44xx_iss_hwmod
= {
1740 .class = &omap44xx_iss_hwmod_class
,
1741 .clkdm_name
= "iss_clkdm",
1742 .mpu_irqs
= omap44xx_iss_irqs
,
1743 .sdma_reqs
= omap44xx_iss_sdma_reqs
,
1744 .main_clk
= "iss_fck",
1747 .clkctrl_offs
= OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET
,
1748 .context_offs
= OMAP4_RM_CAM_ISS_CONTEXT_OFFSET
,
1749 .modulemode
= MODULEMODE_SWCTRL
,
1752 .opt_clks
= iss_opt_clks
,
1753 .opt_clks_cnt
= ARRAY_SIZE(iss_opt_clks
),
1758 * multi-standard video encoder/decoder hardware accelerator
1761 static struct omap_hwmod_class omap44xx_iva_hwmod_class
= {
1766 static struct omap_hwmod_irq_info omap44xx_iva_irqs
[] = {
1767 { .name
= "sync_1", .irq
= 103 + OMAP44XX_IRQ_GIC_START
},
1768 { .name
= "sync_0", .irq
= 104 + OMAP44XX_IRQ_GIC_START
},
1769 { .name
= "mailbox_0", .irq
= 107 + OMAP44XX_IRQ_GIC_START
},
1773 static struct omap_hwmod_rst_info omap44xx_iva_resets
[] = {
1774 { .name
= "seq0", .rst_shift
= 0 },
1775 { .name
= "seq1", .rst_shift
= 1 },
1776 { .name
= "logic", .rst_shift
= 2 },
1779 static struct omap_hwmod omap44xx_iva_hwmod
= {
1781 .class = &omap44xx_iva_hwmod_class
,
1782 .clkdm_name
= "ivahd_clkdm",
1783 .mpu_irqs
= omap44xx_iva_irqs
,
1784 .rst_lines
= omap44xx_iva_resets
,
1785 .rst_lines_cnt
= ARRAY_SIZE(omap44xx_iva_resets
),
1786 .main_clk
= "iva_fck",
1789 .clkctrl_offs
= OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET
,
1790 .rstctrl_offs
= OMAP4_RM_IVAHD_RSTCTRL_OFFSET
,
1791 .context_offs
= OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET
,
1792 .modulemode
= MODULEMODE_HWCTRL
,
1799 * keyboard controller
1802 static struct omap_hwmod_class_sysconfig omap44xx_kbd_sysc
= {
1804 .sysc_offs
= 0x0010,
1805 .syss_offs
= 0x0014,
1806 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_CLOCKACTIVITY
|
1807 SYSC_HAS_EMUFREE
| SYSC_HAS_ENAWAKEUP
|
1808 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
|
1809 SYSS_HAS_RESET_STATUS
),
1810 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
1811 .sysc_fields
= &omap_hwmod_sysc_type1
,
1814 static struct omap_hwmod_class omap44xx_kbd_hwmod_class
= {
1816 .sysc
= &omap44xx_kbd_sysc
,
1820 static struct omap_hwmod_irq_info omap44xx_kbd_irqs
[] = {
1821 { .irq
= 120 + OMAP44XX_IRQ_GIC_START
},
1825 static struct omap_hwmod omap44xx_kbd_hwmod
= {
1827 .class = &omap44xx_kbd_hwmod_class
,
1828 .clkdm_name
= "l4_wkup_clkdm",
1829 .mpu_irqs
= omap44xx_kbd_irqs
,
1830 .main_clk
= "kbd_fck",
1833 .clkctrl_offs
= OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET
,
1834 .context_offs
= OMAP4_RM_WKUP_KEYBOARD_CONTEXT_OFFSET
,
1835 .modulemode
= MODULEMODE_SWCTRL
,
1842 * mailbox module allowing communication between the on-chip processors using a
1843 * queued mailbox-interrupt mechanism.
1846 static struct omap_hwmod_class_sysconfig omap44xx_mailbox_sysc
= {
1848 .sysc_offs
= 0x0010,
1849 .sysc_flags
= (SYSC_HAS_RESET_STATUS
| SYSC_HAS_SIDLEMODE
|
1850 SYSC_HAS_SOFTRESET
),
1851 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
1852 .sysc_fields
= &omap_hwmod_sysc_type2
,
1855 static struct omap_hwmod_class omap44xx_mailbox_hwmod_class
= {
1857 .sysc
= &omap44xx_mailbox_sysc
,
1861 static struct omap_hwmod_irq_info omap44xx_mailbox_irqs
[] = {
1862 { .irq
= 26 + OMAP44XX_IRQ_GIC_START
},
1866 static struct omap_hwmod omap44xx_mailbox_hwmod
= {
1868 .class = &omap44xx_mailbox_hwmod_class
,
1869 .clkdm_name
= "l4_cfg_clkdm",
1870 .mpu_irqs
= omap44xx_mailbox_irqs
,
1873 .clkctrl_offs
= OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET
,
1874 .context_offs
= OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET
,
1881 * multi-channel audio serial port controller
1884 /* The IP is not compliant to type1 / type2 scheme */
1885 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_mcasp
= {
1889 static struct omap_hwmod_class_sysconfig omap44xx_mcasp_sysc
= {
1890 .sysc_offs
= 0x0004,
1891 .sysc_flags
= SYSC_HAS_SIDLEMODE
,
1892 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
1894 .sysc_fields
= &omap_hwmod_sysc_type_mcasp
,
1897 static struct omap_hwmod_class omap44xx_mcasp_hwmod_class
= {
1899 .sysc
= &omap44xx_mcasp_sysc
,
1903 static struct omap_hwmod_irq_info omap44xx_mcasp_irqs
[] = {
1904 { .name
= "arevt", .irq
= 108 + OMAP44XX_IRQ_GIC_START
},
1905 { .name
= "axevt", .irq
= 109 + OMAP44XX_IRQ_GIC_START
},
1909 static struct omap_hwmod_dma_info omap44xx_mcasp_sdma_reqs
[] = {
1910 { .name
= "axevt", .dma_req
= 7 + OMAP44XX_DMA_REQ_START
},
1911 { .name
= "arevt", .dma_req
= 10 + OMAP44XX_DMA_REQ_START
},
1915 static struct omap_hwmod omap44xx_mcasp_hwmod
= {
1917 .class = &omap44xx_mcasp_hwmod_class
,
1918 .clkdm_name
= "abe_clkdm",
1919 .mpu_irqs
= omap44xx_mcasp_irqs
,
1920 .sdma_reqs
= omap44xx_mcasp_sdma_reqs
,
1921 .main_clk
= "mcasp_fck",
1924 .clkctrl_offs
= OMAP4_CM1_ABE_MCASP_CLKCTRL_OFFSET
,
1925 .context_offs
= OMAP4_RM_ABE_MCASP_CONTEXT_OFFSET
,
1926 .modulemode
= MODULEMODE_SWCTRL
,
1933 * multi channel buffered serial port controller
1936 static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc
= {
1937 .sysc_offs
= 0x008c,
1938 .sysc_flags
= (SYSC_HAS_CLOCKACTIVITY
| SYSC_HAS_ENAWAKEUP
|
1939 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
),
1940 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
1941 .sysc_fields
= &omap_hwmod_sysc_type1
,
1944 static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class
= {
1946 .sysc
= &omap44xx_mcbsp_sysc
,
1947 .rev
= MCBSP_CONFIG_TYPE4
,
1951 static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs
[] = {
1952 { .name
= "common", .irq
= 17 + OMAP44XX_IRQ_GIC_START
},
1956 static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs
[] = {
1957 { .name
= "tx", .dma_req
= 32 + OMAP44XX_DMA_REQ_START
},
1958 { .name
= "rx", .dma_req
= 33 + OMAP44XX_DMA_REQ_START
},
1962 static struct omap_hwmod_opt_clk mcbsp1_opt_clks
[] = {
1963 { .role
= "pad_fck", .clk
= "pad_clks_ck" },
1964 { .role
= "prcm_fck", .clk
= "mcbsp1_sync_mux_ck" },
1967 static struct omap_hwmod omap44xx_mcbsp1_hwmod
= {
1969 .class = &omap44xx_mcbsp_hwmod_class
,
1970 .clkdm_name
= "abe_clkdm",
1971 .mpu_irqs
= omap44xx_mcbsp1_irqs
,
1972 .sdma_reqs
= omap44xx_mcbsp1_sdma_reqs
,
1973 .main_clk
= "mcbsp1_fck",
1976 .clkctrl_offs
= OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET
,
1977 .context_offs
= OMAP4_RM_ABE_MCBSP1_CONTEXT_OFFSET
,
1978 .modulemode
= MODULEMODE_SWCTRL
,
1981 .opt_clks
= mcbsp1_opt_clks
,
1982 .opt_clks_cnt
= ARRAY_SIZE(mcbsp1_opt_clks
),
1986 static struct omap_hwmod_irq_info omap44xx_mcbsp2_irqs
[] = {
1987 { .name
= "common", .irq
= 22 + OMAP44XX_IRQ_GIC_START
},
1991 static struct omap_hwmod_dma_info omap44xx_mcbsp2_sdma_reqs
[] = {
1992 { .name
= "tx", .dma_req
= 16 + OMAP44XX_DMA_REQ_START
},
1993 { .name
= "rx", .dma_req
= 17 + OMAP44XX_DMA_REQ_START
},
1997 static struct omap_hwmod_opt_clk mcbsp2_opt_clks
[] = {
1998 { .role
= "pad_fck", .clk
= "pad_clks_ck" },
1999 { .role
= "prcm_fck", .clk
= "mcbsp2_sync_mux_ck" },
2002 static struct omap_hwmod omap44xx_mcbsp2_hwmod
= {
2004 .class = &omap44xx_mcbsp_hwmod_class
,
2005 .clkdm_name
= "abe_clkdm",
2006 .mpu_irqs
= omap44xx_mcbsp2_irqs
,
2007 .sdma_reqs
= omap44xx_mcbsp2_sdma_reqs
,
2008 .main_clk
= "mcbsp2_fck",
2011 .clkctrl_offs
= OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET
,
2012 .context_offs
= OMAP4_RM_ABE_MCBSP2_CONTEXT_OFFSET
,
2013 .modulemode
= MODULEMODE_SWCTRL
,
2016 .opt_clks
= mcbsp2_opt_clks
,
2017 .opt_clks_cnt
= ARRAY_SIZE(mcbsp2_opt_clks
),
2021 static struct omap_hwmod_irq_info omap44xx_mcbsp3_irqs
[] = {
2022 { .name
= "common", .irq
= 23 + OMAP44XX_IRQ_GIC_START
},
2026 static struct omap_hwmod_dma_info omap44xx_mcbsp3_sdma_reqs
[] = {
2027 { .name
= "tx", .dma_req
= 18 + OMAP44XX_DMA_REQ_START
},
2028 { .name
= "rx", .dma_req
= 19 + OMAP44XX_DMA_REQ_START
},
2032 static struct omap_hwmod_opt_clk mcbsp3_opt_clks
[] = {
2033 { .role
= "pad_fck", .clk
= "pad_clks_ck" },
2034 { .role
= "prcm_fck", .clk
= "mcbsp3_sync_mux_ck" },
2037 static struct omap_hwmod omap44xx_mcbsp3_hwmod
= {
2039 .class = &omap44xx_mcbsp_hwmod_class
,
2040 .clkdm_name
= "abe_clkdm",
2041 .mpu_irqs
= omap44xx_mcbsp3_irqs
,
2042 .sdma_reqs
= omap44xx_mcbsp3_sdma_reqs
,
2043 .main_clk
= "mcbsp3_fck",
2046 .clkctrl_offs
= OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET
,
2047 .context_offs
= OMAP4_RM_ABE_MCBSP3_CONTEXT_OFFSET
,
2048 .modulemode
= MODULEMODE_SWCTRL
,
2051 .opt_clks
= mcbsp3_opt_clks
,
2052 .opt_clks_cnt
= ARRAY_SIZE(mcbsp3_opt_clks
),
2056 static struct omap_hwmod_irq_info omap44xx_mcbsp4_irqs
[] = {
2057 { .name
= "common", .irq
= 16 + OMAP44XX_IRQ_GIC_START
},
2061 static struct omap_hwmod_dma_info omap44xx_mcbsp4_sdma_reqs
[] = {
2062 { .name
= "tx", .dma_req
= 30 + OMAP44XX_DMA_REQ_START
},
2063 { .name
= "rx", .dma_req
= 31 + OMAP44XX_DMA_REQ_START
},
2067 static struct omap_hwmod_opt_clk mcbsp4_opt_clks
[] = {
2068 { .role
= "pad_fck", .clk
= "pad_clks_ck" },
2069 { .role
= "prcm_fck", .clk
= "mcbsp4_sync_mux_ck" },
2072 static struct omap_hwmod omap44xx_mcbsp4_hwmod
= {
2074 .class = &omap44xx_mcbsp_hwmod_class
,
2075 .clkdm_name
= "l4_per_clkdm",
2076 .mpu_irqs
= omap44xx_mcbsp4_irqs
,
2077 .sdma_reqs
= omap44xx_mcbsp4_sdma_reqs
,
2078 .main_clk
= "mcbsp4_fck",
2081 .clkctrl_offs
= OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET
,
2082 .context_offs
= OMAP4_RM_L4PER_MCBSP4_CONTEXT_OFFSET
,
2083 .modulemode
= MODULEMODE_SWCTRL
,
2086 .opt_clks
= mcbsp4_opt_clks
,
2087 .opt_clks_cnt
= ARRAY_SIZE(mcbsp4_opt_clks
),
2092 * multi channel pdm controller (proprietary interface with phoenix power
2096 static struct omap_hwmod_class_sysconfig omap44xx_mcpdm_sysc
= {
2098 .sysc_offs
= 0x0010,
2099 .sysc_flags
= (SYSC_HAS_EMUFREE
| SYSC_HAS_RESET_STATUS
|
2100 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
),
2101 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
2103 .sysc_fields
= &omap_hwmod_sysc_type2
,
2106 static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class
= {
2108 .sysc
= &omap44xx_mcpdm_sysc
,
2112 static struct omap_hwmod_irq_info omap44xx_mcpdm_irqs
[] = {
2113 { .irq
= 112 + OMAP44XX_IRQ_GIC_START
},
2117 static struct omap_hwmod_dma_info omap44xx_mcpdm_sdma_reqs
[] = {
2118 { .name
= "up_link", .dma_req
= 64 + OMAP44XX_DMA_REQ_START
},
2119 { .name
= "dn_link", .dma_req
= 65 + OMAP44XX_DMA_REQ_START
},
2123 static struct omap_hwmod omap44xx_mcpdm_hwmod
= {
2125 .class = &omap44xx_mcpdm_hwmod_class
,
2126 .clkdm_name
= "abe_clkdm",
2127 .mpu_irqs
= omap44xx_mcpdm_irqs
,
2128 .sdma_reqs
= omap44xx_mcpdm_sdma_reqs
,
2129 .main_clk
= "mcpdm_fck",
2132 .clkctrl_offs
= OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET
,
2133 .context_offs
= OMAP4_RM_ABE_PDM_CONTEXT_OFFSET
,
2134 .modulemode
= MODULEMODE_SWCTRL
,
2141 * multichannel serial port interface (mcspi) / master/slave synchronous serial
2145 static struct omap_hwmod_class_sysconfig omap44xx_mcspi_sysc
= {
2147 .sysc_offs
= 0x0010,
2148 .sysc_flags
= (SYSC_HAS_EMUFREE
| SYSC_HAS_RESET_STATUS
|
2149 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
),
2150 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
2152 .sysc_fields
= &omap_hwmod_sysc_type2
,
2155 static struct omap_hwmod_class omap44xx_mcspi_hwmod_class
= {
2157 .sysc
= &omap44xx_mcspi_sysc
,
2158 .rev
= OMAP4_MCSPI_REV
,
2162 static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs
[] = {
2163 { .irq
= 65 + OMAP44XX_IRQ_GIC_START
},
2167 static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs
[] = {
2168 { .name
= "tx0", .dma_req
= 34 + OMAP44XX_DMA_REQ_START
},
2169 { .name
= "rx0", .dma_req
= 35 + OMAP44XX_DMA_REQ_START
},
2170 { .name
= "tx1", .dma_req
= 36 + OMAP44XX_DMA_REQ_START
},
2171 { .name
= "rx1", .dma_req
= 37 + OMAP44XX_DMA_REQ_START
},
2172 { .name
= "tx2", .dma_req
= 38 + OMAP44XX_DMA_REQ_START
},
2173 { .name
= "rx2", .dma_req
= 39 + OMAP44XX_DMA_REQ_START
},
2174 { .name
= "tx3", .dma_req
= 40 + OMAP44XX_DMA_REQ_START
},
2175 { .name
= "rx3", .dma_req
= 41 + OMAP44XX_DMA_REQ_START
},
2179 /* mcspi1 dev_attr */
2180 static struct omap2_mcspi_dev_attr mcspi1_dev_attr
= {
2181 .num_chipselect
= 4,
2184 static struct omap_hwmod omap44xx_mcspi1_hwmod
= {
2186 .class = &omap44xx_mcspi_hwmod_class
,
2187 .clkdm_name
= "l4_per_clkdm",
2188 .mpu_irqs
= omap44xx_mcspi1_irqs
,
2189 .sdma_reqs
= omap44xx_mcspi1_sdma_reqs
,
2190 .main_clk
= "mcspi1_fck",
2193 .clkctrl_offs
= OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET
,
2194 .context_offs
= OMAP4_RM_L4PER_MCSPI1_CONTEXT_OFFSET
,
2195 .modulemode
= MODULEMODE_SWCTRL
,
2198 .dev_attr
= &mcspi1_dev_attr
,
2202 static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs
[] = {
2203 { .irq
= 66 + OMAP44XX_IRQ_GIC_START
},
2207 static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs
[] = {
2208 { .name
= "tx0", .dma_req
= 42 + OMAP44XX_DMA_REQ_START
},
2209 { .name
= "rx0", .dma_req
= 43 + OMAP44XX_DMA_REQ_START
},
2210 { .name
= "tx1", .dma_req
= 44 + OMAP44XX_DMA_REQ_START
},
2211 { .name
= "rx1", .dma_req
= 45 + OMAP44XX_DMA_REQ_START
},
2215 /* mcspi2 dev_attr */
2216 static struct omap2_mcspi_dev_attr mcspi2_dev_attr
= {
2217 .num_chipselect
= 2,
2220 static struct omap_hwmod omap44xx_mcspi2_hwmod
= {
2222 .class = &omap44xx_mcspi_hwmod_class
,
2223 .clkdm_name
= "l4_per_clkdm",
2224 .mpu_irqs
= omap44xx_mcspi2_irqs
,
2225 .sdma_reqs
= omap44xx_mcspi2_sdma_reqs
,
2226 .main_clk
= "mcspi2_fck",
2229 .clkctrl_offs
= OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET
,
2230 .context_offs
= OMAP4_RM_L4PER_MCSPI2_CONTEXT_OFFSET
,
2231 .modulemode
= MODULEMODE_SWCTRL
,
2234 .dev_attr
= &mcspi2_dev_attr
,
2238 static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs
[] = {
2239 { .irq
= 91 + OMAP44XX_IRQ_GIC_START
},
2243 static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs
[] = {
2244 { .name
= "tx0", .dma_req
= 14 + OMAP44XX_DMA_REQ_START
},
2245 { .name
= "rx0", .dma_req
= 15 + OMAP44XX_DMA_REQ_START
},
2246 { .name
= "tx1", .dma_req
= 22 + OMAP44XX_DMA_REQ_START
},
2247 { .name
= "rx1", .dma_req
= 23 + OMAP44XX_DMA_REQ_START
},
2251 /* mcspi3 dev_attr */
2252 static struct omap2_mcspi_dev_attr mcspi3_dev_attr
= {
2253 .num_chipselect
= 2,
2256 static struct omap_hwmod omap44xx_mcspi3_hwmod
= {
2258 .class = &omap44xx_mcspi_hwmod_class
,
2259 .clkdm_name
= "l4_per_clkdm",
2260 .mpu_irqs
= omap44xx_mcspi3_irqs
,
2261 .sdma_reqs
= omap44xx_mcspi3_sdma_reqs
,
2262 .main_clk
= "mcspi3_fck",
2265 .clkctrl_offs
= OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET
,
2266 .context_offs
= OMAP4_RM_L4PER_MCSPI3_CONTEXT_OFFSET
,
2267 .modulemode
= MODULEMODE_SWCTRL
,
2270 .dev_attr
= &mcspi3_dev_attr
,
2274 static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs
[] = {
2275 { .irq
= 48 + OMAP44XX_IRQ_GIC_START
},
2279 static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs
[] = {
2280 { .name
= "tx0", .dma_req
= 69 + OMAP44XX_DMA_REQ_START
},
2281 { .name
= "rx0", .dma_req
= 70 + OMAP44XX_DMA_REQ_START
},
2285 /* mcspi4 dev_attr */
2286 static struct omap2_mcspi_dev_attr mcspi4_dev_attr
= {
2287 .num_chipselect
= 1,
2290 static struct omap_hwmod omap44xx_mcspi4_hwmod
= {
2292 .class = &omap44xx_mcspi_hwmod_class
,
2293 .clkdm_name
= "l4_per_clkdm",
2294 .mpu_irqs
= omap44xx_mcspi4_irqs
,
2295 .sdma_reqs
= omap44xx_mcspi4_sdma_reqs
,
2296 .main_clk
= "mcspi4_fck",
2299 .clkctrl_offs
= OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET
,
2300 .context_offs
= OMAP4_RM_L4PER_MCSPI4_CONTEXT_OFFSET
,
2301 .modulemode
= MODULEMODE_SWCTRL
,
2304 .dev_attr
= &mcspi4_dev_attr
,
2309 * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller
2312 static struct omap_hwmod_class_sysconfig omap44xx_mmc_sysc
= {
2314 .sysc_offs
= 0x0010,
2315 .sysc_flags
= (SYSC_HAS_EMUFREE
| SYSC_HAS_MIDLEMODE
|
2316 SYSC_HAS_RESET_STATUS
| SYSC_HAS_SIDLEMODE
|
2317 SYSC_HAS_SOFTRESET
),
2318 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
2319 SIDLE_SMART_WKUP
| MSTANDBY_FORCE
| MSTANDBY_NO
|
2320 MSTANDBY_SMART
| MSTANDBY_SMART_WKUP
),
2321 .sysc_fields
= &omap_hwmod_sysc_type2
,
2324 static struct omap_hwmod_class omap44xx_mmc_hwmod_class
= {
2326 .sysc
= &omap44xx_mmc_sysc
,
2330 static struct omap_hwmod_irq_info omap44xx_mmc1_irqs
[] = {
2331 { .irq
= 83 + OMAP44XX_IRQ_GIC_START
},
2335 static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs
[] = {
2336 { .name
= "tx", .dma_req
= 60 + OMAP44XX_DMA_REQ_START
},
2337 { .name
= "rx", .dma_req
= 61 + OMAP44XX_DMA_REQ_START
},
2342 static struct omap_mmc_dev_attr mmc1_dev_attr
= {
2343 .flags
= OMAP_HSMMC_SUPPORTS_DUAL_VOLT
,
2346 static struct omap_hwmod omap44xx_mmc1_hwmod
= {
2348 .class = &omap44xx_mmc_hwmod_class
,
2349 .clkdm_name
= "l3_init_clkdm",
2350 .mpu_irqs
= omap44xx_mmc1_irqs
,
2351 .sdma_reqs
= omap44xx_mmc1_sdma_reqs
,
2352 .main_clk
= "mmc1_fck",
2355 .clkctrl_offs
= OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET
,
2356 .context_offs
= OMAP4_RM_L3INIT_MMC1_CONTEXT_OFFSET
,
2357 .modulemode
= MODULEMODE_SWCTRL
,
2360 .dev_attr
= &mmc1_dev_attr
,
2364 static struct omap_hwmod_irq_info omap44xx_mmc2_irqs
[] = {
2365 { .irq
= 86 + OMAP44XX_IRQ_GIC_START
},
2369 static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs
[] = {
2370 { .name
= "tx", .dma_req
= 46 + OMAP44XX_DMA_REQ_START
},
2371 { .name
= "rx", .dma_req
= 47 + OMAP44XX_DMA_REQ_START
},
2375 static struct omap_hwmod omap44xx_mmc2_hwmod
= {
2377 .class = &omap44xx_mmc_hwmod_class
,
2378 .clkdm_name
= "l3_init_clkdm",
2379 .mpu_irqs
= omap44xx_mmc2_irqs
,
2380 .sdma_reqs
= omap44xx_mmc2_sdma_reqs
,
2381 .main_clk
= "mmc2_fck",
2384 .clkctrl_offs
= OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET
,
2385 .context_offs
= OMAP4_RM_L3INIT_MMC2_CONTEXT_OFFSET
,
2386 .modulemode
= MODULEMODE_SWCTRL
,
2392 static struct omap_hwmod_irq_info omap44xx_mmc3_irqs
[] = {
2393 { .irq
= 94 + OMAP44XX_IRQ_GIC_START
},
2397 static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs
[] = {
2398 { .name
= "tx", .dma_req
= 76 + OMAP44XX_DMA_REQ_START
},
2399 { .name
= "rx", .dma_req
= 77 + OMAP44XX_DMA_REQ_START
},
2403 static struct omap_hwmod omap44xx_mmc3_hwmod
= {
2405 .class = &omap44xx_mmc_hwmod_class
,
2406 .clkdm_name
= "l4_per_clkdm",
2407 .mpu_irqs
= omap44xx_mmc3_irqs
,
2408 .sdma_reqs
= omap44xx_mmc3_sdma_reqs
,
2409 .main_clk
= "mmc3_fck",
2412 .clkctrl_offs
= OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET
,
2413 .context_offs
= OMAP4_RM_L4PER_MMCSD3_CONTEXT_OFFSET
,
2414 .modulemode
= MODULEMODE_SWCTRL
,
2420 static struct omap_hwmod_irq_info omap44xx_mmc4_irqs
[] = {
2421 { .irq
= 96 + OMAP44XX_IRQ_GIC_START
},
2425 static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs
[] = {
2426 { .name
= "tx", .dma_req
= 56 + OMAP44XX_DMA_REQ_START
},
2427 { .name
= "rx", .dma_req
= 57 + OMAP44XX_DMA_REQ_START
},
2431 static struct omap_hwmod omap44xx_mmc4_hwmod
= {
2433 .class = &omap44xx_mmc_hwmod_class
,
2434 .clkdm_name
= "l4_per_clkdm",
2435 .mpu_irqs
= omap44xx_mmc4_irqs
,
2436 .sdma_reqs
= omap44xx_mmc4_sdma_reqs
,
2437 .main_clk
= "mmc4_fck",
2440 .clkctrl_offs
= OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET
,
2441 .context_offs
= OMAP4_RM_L4PER_MMCSD4_CONTEXT_OFFSET
,
2442 .modulemode
= MODULEMODE_SWCTRL
,
2448 static struct omap_hwmod_irq_info omap44xx_mmc5_irqs
[] = {
2449 { .irq
= 59 + OMAP44XX_IRQ_GIC_START
},
2453 static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs
[] = {
2454 { .name
= "tx", .dma_req
= 58 + OMAP44XX_DMA_REQ_START
},
2455 { .name
= "rx", .dma_req
= 59 + OMAP44XX_DMA_REQ_START
},
2459 static struct omap_hwmod omap44xx_mmc5_hwmod
= {
2461 .class = &omap44xx_mmc_hwmod_class
,
2462 .clkdm_name
= "l4_per_clkdm",
2463 .mpu_irqs
= omap44xx_mmc5_irqs
,
2464 .sdma_reqs
= omap44xx_mmc5_sdma_reqs
,
2465 .main_clk
= "mmc5_fck",
2468 .clkctrl_offs
= OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET
,
2469 .context_offs
= OMAP4_RM_L4PER_MMCSD5_CONTEXT_OFFSET
,
2470 .modulemode
= MODULEMODE_SWCTRL
,
2477 * The memory management unit performs virtual to physical address translation
2478 * for its requestors.
2481 static struct omap_hwmod_class_sysconfig mmu_sysc
= {
2485 .sysc_flags
= (SYSC_HAS_CLOCKACTIVITY
| SYSC_HAS_SIDLEMODE
|
2486 SYSC_HAS_SOFTRESET
| SYSC_HAS_AUTOIDLE
),
2487 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
2488 .sysc_fields
= &omap_hwmod_sysc_type1
,
2491 static struct omap_hwmod_class omap44xx_mmu_hwmod_class
= {
2498 static struct omap_mmu_dev_attr mmu_ipu_dev_attr
= {
2500 .da_end
= 0xfffff000,
2501 .nr_tlb_entries
= 32,
2504 static struct omap_hwmod omap44xx_mmu_ipu_hwmod
;
2505 static struct omap_hwmod_irq_info omap44xx_mmu_ipu_irqs
[] = {
2506 { .irq
= 100 + OMAP44XX_IRQ_GIC_START
, },
2510 static struct omap_hwmod_rst_info omap44xx_mmu_ipu_resets
[] = {
2511 { .name
= "mmu_cache", .rst_shift
= 2 },
2514 static struct omap_hwmod_addr_space omap44xx_mmu_ipu_addrs
[] = {
2516 .pa_start
= 0x55082000,
2517 .pa_end
= 0x550820ff,
2518 .flags
= ADDR_TYPE_RT
,
2523 /* l3_main_2 -> mmu_ipu */
2524 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__mmu_ipu
= {
2525 .master
= &omap44xx_l3_main_2_hwmod
,
2526 .slave
= &omap44xx_mmu_ipu_hwmod
,
2528 .addr
= omap44xx_mmu_ipu_addrs
,
2529 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2532 static struct omap_hwmod omap44xx_mmu_ipu_hwmod
= {
2534 .class = &omap44xx_mmu_hwmod_class
,
2535 .clkdm_name
= "ducati_clkdm",
2536 .mpu_irqs
= omap44xx_mmu_ipu_irqs
,
2537 .rst_lines
= omap44xx_mmu_ipu_resets
,
2538 .rst_lines_cnt
= ARRAY_SIZE(omap44xx_mmu_ipu_resets
),
2539 .main_clk
= "ducati_clk_mux_ck",
2542 .clkctrl_offs
= OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET
,
2543 .rstctrl_offs
= OMAP4_RM_DUCATI_RSTCTRL_OFFSET
,
2544 .context_offs
= OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET
,
2545 .modulemode
= MODULEMODE_HWCTRL
,
2548 .dev_attr
= &mmu_ipu_dev_attr
,
2553 static struct omap_mmu_dev_attr mmu_dsp_dev_attr
= {
2555 .da_end
= 0xfffff000,
2556 .nr_tlb_entries
= 32,
2559 static struct omap_hwmod omap44xx_mmu_dsp_hwmod
;
2560 static struct omap_hwmod_irq_info omap44xx_mmu_dsp_irqs
[] = {
2561 { .irq
= 28 + OMAP44XX_IRQ_GIC_START
},
2565 static struct omap_hwmod_rst_info omap44xx_mmu_dsp_resets
[] = {
2566 { .name
= "mmu_cache", .rst_shift
= 1 },
2569 static struct omap_hwmod_addr_space omap44xx_mmu_dsp_addrs
[] = {
2571 .pa_start
= 0x4a066000,
2572 .pa_end
= 0x4a0660ff,
2573 .flags
= ADDR_TYPE_RT
,
2579 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mmu_dsp
= {
2580 .master
= &omap44xx_l4_cfg_hwmod
,
2581 .slave
= &omap44xx_mmu_dsp_hwmod
,
2583 .addr
= omap44xx_mmu_dsp_addrs
,
2584 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2587 static struct omap_hwmod omap44xx_mmu_dsp_hwmod
= {
2589 .class = &omap44xx_mmu_hwmod_class
,
2590 .clkdm_name
= "tesla_clkdm",
2591 .mpu_irqs
= omap44xx_mmu_dsp_irqs
,
2592 .rst_lines
= omap44xx_mmu_dsp_resets
,
2593 .rst_lines_cnt
= ARRAY_SIZE(omap44xx_mmu_dsp_resets
),
2594 .main_clk
= "dpll_iva_m4x2_ck",
2597 .clkctrl_offs
= OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET
,
2598 .rstctrl_offs
= OMAP4_RM_TESLA_RSTCTRL_OFFSET
,
2599 .context_offs
= OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET
,
2600 .modulemode
= MODULEMODE_HWCTRL
,
2603 .dev_attr
= &mmu_dsp_dev_attr
,
2611 static struct omap_hwmod_class omap44xx_mpu_hwmod_class
= {
2616 static struct omap_hwmod_irq_info omap44xx_mpu_irqs
[] = {
2617 { .name
= "pmu0", .irq
= 54 + OMAP44XX_IRQ_GIC_START
},
2618 { .name
= "pmu1", .irq
= 55 + OMAP44XX_IRQ_GIC_START
},
2619 { .name
= "pl310", .irq
= 0 + OMAP44XX_IRQ_GIC_START
},
2620 { .name
= "cti0", .irq
= 1 + OMAP44XX_IRQ_GIC_START
},
2621 { .name
= "cti1", .irq
= 2 + OMAP44XX_IRQ_GIC_START
},
2625 static struct omap_hwmod omap44xx_mpu_hwmod
= {
2627 .class = &omap44xx_mpu_hwmod_class
,
2628 .clkdm_name
= "mpuss_clkdm",
2629 .flags
= HWMOD_INIT_NO_IDLE
| HWMOD_INIT_NO_RESET
,
2630 .mpu_irqs
= omap44xx_mpu_irqs
,
2631 .main_clk
= "dpll_mpu_m2_ck",
2634 .clkctrl_offs
= OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET
,
2635 .context_offs
= OMAP4_RM_MPU_MPU_CONTEXT_OFFSET
,
2642 * top-level core on-chip ram
2645 static struct omap_hwmod_class omap44xx_ocmc_ram_hwmod_class
= {
2650 static struct omap_hwmod omap44xx_ocmc_ram_hwmod
= {
2652 .class = &omap44xx_ocmc_ram_hwmod_class
,
2653 .clkdm_name
= "l3_2_clkdm",
2656 .clkctrl_offs
= OMAP4_CM_L3_2_OCMC_RAM_CLKCTRL_OFFSET
,
2657 .context_offs
= OMAP4_RM_L3_2_OCMC_RAM_CONTEXT_OFFSET
,
2664 * bridge to transform ocp interface protocol to scp (serial control port)
2668 static struct omap_hwmod_class_sysconfig omap44xx_ocp2scp_sysc
= {
2670 .sysc_offs
= 0x0010,
2671 .syss_offs
= 0x0014,
2672 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_SIDLEMODE
|
2673 SYSC_HAS_SOFTRESET
| SYSS_HAS_RESET_STATUS
),
2674 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
2675 .sysc_fields
= &omap_hwmod_sysc_type1
,
2678 static struct omap_hwmod_class omap44xx_ocp2scp_hwmod_class
= {
2680 .sysc
= &omap44xx_ocp2scp_sysc
,
2683 /* ocp2scp_usb_phy */
2684 static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod
= {
2685 .name
= "ocp2scp_usb_phy",
2686 .class = &omap44xx_ocp2scp_hwmod_class
,
2687 .clkdm_name
= "l3_init_clkdm",
2688 .main_clk
= "ocp2scp_usb_phy_phy_48m",
2691 .clkctrl_offs
= OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET
,
2692 .context_offs
= OMAP4_RM_L3INIT_USBPHYOCP2SCP_CONTEXT_OFFSET
,
2693 .modulemode
= MODULEMODE_HWCTRL
,
2700 * power and reset manager (part of the prcm infrastructure) + clock manager 2
2701 * + clock manager 1 (in always on power domain) + local prm in mpu
2704 static struct omap_hwmod_class omap44xx_prcm_hwmod_class
= {
2709 static struct omap_hwmod omap44xx_prcm_mpu_hwmod
= {
2711 .class = &omap44xx_prcm_hwmod_class
,
2712 .clkdm_name
= "l4_wkup_clkdm",
2713 .flags
= HWMOD_NO_IDLEST
,
2716 .flags
= HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT
,
2722 static struct omap_hwmod omap44xx_cm_core_aon_hwmod
= {
2723 .name
= "cm_core_aon",
2724 .class = &omap44xx_prcm_hwmod_class
,
2725 .flags
= HWMOD_NO_IDLEST
,
2728 .flags
= HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT
,
2734 static struct omap_hwmod omap44xx_cm_core_hwmod
= {
2736 .class = &omap44xx_prcm_hwmod_class
,
2737 .flags
= HWMOD_NO_IDLEST
,
2740 .flags
= HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT
,
2746 static struct omap_hwmod_irq_info omap44xx_prm_irqs
[] = {
2747 { .irq
= 11 + OMAP44XX_IRQ_GIC_START
},
2751 static struct omap_hwmod_rst_info omap44xx_prm_resets
[] = {
2752 { .name
= "rst_global_warm_sw", .rst_shift
= 0 },
2753 { .name
= "rst_global_cold_sw", .rst_shift
= 1 },
2756 static struct omap_hwmod omap44xx_prm_hwmod
= {
2758 .class = &omap44xx_prcm_hwmod_class
,
2759 .mpu_irqs
= omap44xx_prm_irqs
,
2760 .rst_lines
= omap44xx_prm_resets
,
2761 .rst_lines_cnt
= ARRAY_SIZE(omap44xx_prm_resets
),
2766 * system clock and reset manager
2769 static struct omap_hwmod_class omap44xx_scrm_hwmod_class
= {
2774 static struct omap_hwmod omap44xx_scrm_hwmod
= {
2776 .class = &omap44xx_scrm_hwmod_class
,
2777 .clkdm_name
= "l4_wkup_clkdm",
2780 .flags
= HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT
,
2787 * shared level 2 memory interface
2790 static struct omap_hwmod_class omap44xx_sl2if_hwmod_class
= {
2795 static struct omap_hwmod omap44xx_sl2if_hwmod
= {
2797 .class = &omap44xx_sl2if_hwmod_class
,
2798 .clkdm_name
= "ivahd_clkdm",
2801 .clkctrl_offs
= OMAP4_CM_IVAHD_SL2_CLKCTRL_OFFSET
,
2802 .context_offs
= OMAP4_RM_IVAHD_SL2_CONTEXT_OFFSET
,
2803 .modulemode
= MODULEMODE_HWCTRL
,
2810 * bidirectional, multi-drop, multi-channel two-line serial interface between
2811 * the device and external components
2814 static struct omap_hwmod_class_sysconfig omap44xx_slimbus_sysc
= {
2816 .sysc_offs
= 0x0010,
2817 .sysc_flags
= (SYSC_HAS_RESET_STATUS
| SYSC_HAS_SIDLEMODE
|
2818 SYSC_HAS_SOFTRESET
),
2819 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
2821 .sysc_fields
= &omap_hwmod_sysc_type2
,
2824 static struct omap_hwmod_class omap44xx_slimbus_hwmod_class
= {
2826 .sysc
= &omap44xx_slimbus_sysc
,
2830 static struct omap_hwmod_irq_info omap44xx_slimbus1_irqs
[] = {
2831 { .irq
= 97 + OMAP44XX_IRQ_GIC_START
},
2835 static struct omap_hwmod_dma_info omap44xx_slimbus1_sdma_reqs
[] = {
2836 { .name
= "tx0", .dma_req
= 84 + OMAP44XX_DMA_REQ_START
},
2837 { .name
= "tx1", .dma_req
= 85 + OMAP44XX_DMA_REQ_START
},
2838 { .name
= "tx2", .dma_req
= 86 + OMAP44XX_DMA_REQ_START
},
2839 { .name
= "tx3", .dma_req
= 87 + OMAP44XX_DMA_REQ_START
},
2840 { .name
= "rx0", .dma_req
= 88 + OMAP44XX_DMA_REQ_START
},
2841 { .name
= "rx1", .dma_req
= 89 + OMAP44XX_DMA_REQ_START
},
2842 { .name
= "rx2", .dma_req
= 90 + OMAP44XX_DMA_REQ_START
},
2843 { .name
= "rx3", .dma_req
= 91 + OMAP44XX_DMA_REQ_START
},
2847 static struct omap_hwmod_opt_clk slimbus1_opt_clks
[] = {
2848 { .role
= "fclk_1", .clk
= "slimbus1_fclk_1" },
2849 { .role
= "fclk_0", .clk
= "slimbus1_fclk_0" },
2850 { .role
= "fclk_2", .clk
= "slimbus1_fclk_2" },
2851 { .role
= "slimbus_clk", .clk
= "slimbus1_slimbus_clk" },
2854 static struct omap_hwmod omap44xx_slimbus1_hwmod
= {
2856 .class = &omap44xx_slimbus_hwmod_class
,
2857 .clkdm_name
= "abe_clkdm",
2858 .mpu_irqs
= omap44xx_slimbus1_irqs
,
2859 .sdma_reqs
= omap44xx_slimbus1_sdma_reqs
,
2862 .clkctrl_offs
= OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET
,
2863 .context_offs
= OMAP4_RM_ABE_SLIMBUS_CONTEXT_OFFSET
,
2864 .modulemode
= MODULEMODE_SWCTRL
,
2867 .opt_clks
= slimbus1_opt_clks
,
2868 .opt_clks_cnt
= ARRAY_SIZE(slimbus1_opt_clks
),
2872 static struct omap_hwmod_irq_info omap44xx_slimbus2_irqs
[] = {
2873 { .irq
= 98 + OMAP44XX_IRQ_GIC_START
},
2877 static struct omap_hwmod_dma_info omap44xx_slimbus2_sdma_reqs
[] = {
2878 { .name
= "tx0", .dma_req
= 92 + OMAP44XX_DMA_REQ_START
},
2879 { .name
= "tx1", .dma_req
= 93 + OMAP44XX_DMA_REQ_START
},
2880 { .name
= "tx2", .dma_req
= 94 + OMAP44XX_DMA_REQ_START
},
2881 { .name
= "tx3", .dma_req
= 95 + OMAP44XX_DMA_REQ_START
},
2882 { .name
= "rx0", .dma_req
= 96 + OMAP44XX_DMA_REQ_START
},
2883 { .name
= "rx1", .dma_req
= 97 + OMAP44XX_DMA_REQ_START
},
2884 { .name
= "rx2", .dma_req
= 98 + OMAP44XX_DMA_REQ_START
},
2885 { .name
= "rx3", .dma_req
= 99 + OMAP44XX_DMA_REQ_START
},
2889 static struct omap_hwmod_opt_clk slimbus2_opt_clks
[] = {
2890 { .role
= "fclk_1", .clk
= "slimbus2_fclk_1" },
2891 { .role
= "fclk_0", .clk
= "slimbus2_fclk_0" },
2892 { .role
= "slimbus_clk", .clk
= "slimbus2_slimbus_clk" },
2895 static struct omap_hwmod omap44xx_slimbus2_hwmod
= {
2897 .class = &omap44xx_slimbus_hwmod_class
,
2898 .clkdm_name
= "l4_per_clkdm",
2899 .mpu_irqs
= omap44xx_slimbus2_irqs
,
2900 .sdma_reqs
= omap44xx_slimbus2_sdma_reqs
,
2903 .clkctrl_offs
= OMAP4_CM_L4PER_SLIMBUS2_CLKCTRL_OFFSET
,
2904 .context_offs
= OMAP4_RM_L4PER_SLIMBUS2_CONTEXT_OFFSET
,
2905 .modulemode
= MODULEMODE_SWCTRL
,
2908 .opt_clks
= slimbus2_opt_clks
,
2909 .opt_clks_cnt
= ARRAY_SIZE(slimbus2_opt_clks
),
2913 * 'smartreflex' class
2914 * smartreflex module (monitor silicon performance and outputs a measure of
2915 * performance error)
2918 /* The IP is not compliant to type1 / type2 scheme */
2919 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex
= {
2924 static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc
= {
2925 .sysc_offs
= 0x0038,
2926 .sysc_flags
= (SYSC_HAS_ENAWAKEUP
| SYSC_HAS_SIDLEMODE
),
2927 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
2929 .sysc_fields
= &omap_hwmod_sysc_type_smartreflex
,
2932 static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class
= {
2933 .name
= "smartreflex",
2934 .sysc
= &omap44xx_smartreflex_sysc
,
2938 /* smartreflex_core */
2939 static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr
= {
2940 .sensor_voltdm_name
= "core",
2943 static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs
[] = {
2944 { .irq
= 19 + OMAP44XX_IRQ_GIC_START
},
2948 static struct omap_hwmod omap44xx_smartreflex_core_hwmod
= {
2949 .name
= "smartreflex_core",
2950 .class = &omap44xx_smartreflex_hwmod_class
,
2951 .clkdm_name
= "l4_ao_clkdm",
2952 .mpu_irqs
= omap44xx_smartreflex_core_irqs
,
2954 .main_clk
= "smartreflex_core_fck",
2957 .clkctrl_offs
= OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET
,
2958 .context_offs
= OMAP4_RM_ALWON_SR_CORE_CONTEXT_OFFSET
,
2959 .modulemode
= MODULEMODE_SWCTRL
,
2962 .dev_attr
= &smartreflex_core_dev_attr
,
2965 /* smartreflex_iva */
2966 static struct omap_smartreflex_dev_attr smartreflex_iva_dev_attr
= {
2967 .sensor_voltdm_name
= "iva",
2970 static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs
[] = {
2971 { .irq
= 102 + OMAP44XX_IRQ_GIC_START
},
2975 static struct omap_hwmod omap44xx_smartreflex_iva_hwmod
= {
2976 .name
= "smartreflex_iva",
2977 .class = &omap44xx_smartreflex_hwmod_class
,
2978 .clkdm_name
= "l4_ao_clkdm",
2979 .mpu_irqs
= omap44xx_smartreflex_iva_irqs
,
2980 .main_clk
= "smartreflex_iva_fck",
2983 .clkctrl_offs
= OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET
,
2984 .context_offs
= OMAP4_RM_ALWON_SR_IVA_CONTEXT_OFFSET
,
2985 .modulemode
= MODULEMODE_SWCTRL
,
2988 .dev_attr
= &smartreflex_iva_dev_attr
,
2991 /* smartreflex_mpu */
2992 static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr
= {
2993 .sensor_voltdm_name
= "mpu",
2996 static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs
[] = {
2997 { .irq
= 18 + OMAP44XX_IRQ_GIC_START
},
3001 static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod
= {
3002 .name
= "smartreflex_mpu",
3003 .class = &omap44xx_smartreflex_hwmod_class
,
3004 .clkdm_name
= "l4_ao_clkdm",
3005 .mpu_irqs
= omap44xx_smartreflex_mpu_irqs
,
3006 .main_clk
= "smartreflex_mpu_fck",
3009 .clkctrl_offs
= OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET
,
3010 .context_offs
= OMAP4_RM_ALWON_SR_MPU_CONTEXT_OFFSET
,
3011 .modulemode
= MODULEMODE_SWCTRL
,
3014 .dev_attr
= &smartreflex_mpu_dev_attr
,
3019 * spinlock provides hardware assistance for synchronizing the processes
3020 * running on multiple processors
3023 static struct omap_hwmod_class_sysconfig omap44xx_spinlock_sysc
= {
3025 .sysc_offs
= 0x0010,
3026 .syss_offs
= 0x0014,
3027 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_CLOCKACTIVITY
|
3028 SYSC_HAS_ENAWAKEUP
| SYSC_HAS_SIDLEMODE
|
3029 SYSC_HAS_SOFTRESET
| SYSS_HAS_RESET_STATUS
),
3030 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
3032 .sysc_fields
= &omap_hwmod_sysc_type1
,
3035 static struct omap_hwmod_class omap44xx_spinlock_hwmod_class
= {
3037 .sysc
= &omap44xx_spinlock_sysc
,
3041 static struct omap_hwmod omap44xx_spinlock_hwmod
= {
3043 .class = &omap44xx_spinlock_hwmod_class
,
3044 .clkdm_name
= "l4_cfg_clkdm",
3047 .clkctrl_offs
= OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET
,
3048 .context_offs
= OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET
,
3055 * general purpose timer module with accurate 1ms tick
3056 * This class contains several variants: ['timer_1ms', 'timer']
3059 static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc
= {
3061 .sysc_offs
= 0x0010,
3062 .syss_offs
= 0x0014,
3063 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_CLOCKACTIVITY
|
3064 SYSC_HAS_EMUFREE
| SYSC_HAS_ENAWAKEUP
|
3065 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
|
3066 SYSS_HAS_RESET_STATUS
),
3067 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
3068 .sysc_fields
= &omap_hwmod_sysc_type1
,
3071 static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class
= {
3073 .sysc
= &omap44xx_timer_1ms_sysc
,
3076 static struct omap_hwmod_class_sysconfig omap44xx_timer_sysc
= {
3078 .sysc_offs
= 0x0010,
3079 .sysc_flags
= (SYSC_HAS_EMUFREE
| SYSC_HAS_RESET_STATUS
|
3080 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
),
3081 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
3083 .sysc_fields
= &omap_hwmod_sysc_type2
,
3086 static struct omap_hwmod_class omap44xx_timer_hwmod_class
= {
3088 .sysc
= &omap44xx_timer_sysc
,
3091 /* always-on timers dev attribute */
3092 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr
= {
3093 .timer_capability
= OMAP_TIMER_ALWON
,
3096 /* pwm timers dev attribute */
3097 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr
= {
3098 .timer_capability
= OMAP_TIMER_HAS_PWM
,
3101 /* timers with DSP interrupt dev attribute */
3102 static struct omap_timer_capability_dev_attr capability_dsp_dev_attr
= {
3103 .timer_capability
= OMAP_TIMER_HAS_DSP_IRQ
,
3106 /* pwm timers with DSP interrupt dev attribute */
3107 static struct omap_timer_capability_dev_attr capability_dsp_pwm_dev_attr
= {
3108 .timer_capability
= OMAP_TIMER_HAS_DSP_IRQ
| OMAP_TIMER_HAS_PWM
,
3112 static struct omap_hwmod_irq_info omap44xx_timer1_irqs
[] = {
3113 { .irq
= 37 + OMAP44XX_IRQ_GIC_START
},
3117 static struct omap_hwmod omap44xx_timer1_hwmod
= {
3119 .class = &omap44xx_timer_1ms_hwmod_class
,
3120 .clkdm_name
= "l4_wkup_clkdm",
3121 .mpu_irqs
= omap44xx_timer1_irqs
,
3122 .main_clk
= "timer1_fck",
3125 .clkctrl_offs
= OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET
,
3126 .context_offs
= OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET
,
3127 .modulemode
= MODULEMODE_SWCTRL
,
3130 .dev_attr
= &capability_alwon_dev_attr
,
3134 static struct omap_hwmod_irq_info omap44xx_timer2_irqs
[] = {
3135 { .irq
= 38 + OMAP44XX_IRQ_GIC_START
},
3139 static struct omap_hwmod omap44xx_timer2_hwmod
= {
3141 .class = &omap44xx_timer_1ms_hwmod_class
,
3142 .clkdm_name
= "l4_per_clkdm",
3143 .mpu_irqs
= omap44xx_timer2_irqs
,
3144 .main_clk
= "timer2_fck",
3147 .clkctrl_offs
= OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET
,
3148 .context_offs
= OMAP4_RM_L4PER_DMTIMER2_CONTEXT_OFFSET
,
3149 .modulemode
= MODULEMODE_SWCTRL
,
3155 static struct omap_hwmod_irq_info omap44xx_timer3_irqs
[] = {
3156 { .irq
= 39 + OMAP44XX_IRQ_GIC_START
},
3160 static struct omap_hwmod omap44xx_timer3_hwmod
= {
3162 .class = &omap44xx_timer_hwmod_class
,
3163 .clkdm_name
= "l4_per_clkdm",
3164 .mpu_irqs
= omap44xx_timer3_irqs
,
3165 .main_clk
= "timer3_fck",
3168 .clkctrl_offs
= OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET
,
3169 .context_offs
= OMAP4_RM_L4PER_DMTIMER3_CONTEXT_OFFSET
,
3170 .modulemode
= MODULEMODE_SWCTRL
,
3176 static struct omap_hwmod_irq_info omap44xx_timer4_irqs
[] = {
3177 { .irq
= 40 + OMAP44XX_IRQ_GIC_START
},
3181 static struct omap_hwmod omap44xx_timer4_hwmod
= {
3183 .class = &omap44xx_timer_hwmod_class
,
3184 .clkdm_name
= "l4_per_clkdm",
3185 .mpu_irqs
= omap44xx_timer4_irqs
,
3186 .main_clk
= "timer4_fck",
3189 .clkctrl_offs
= OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET
,
3190 .context_offs
= OMAP4_RM_L4PER_DMTIMER4_CONTEXT_OFFSET
,
3191 .modulemode
= MODULEMODE_SWCTRL
,
3197 static struct omap_hwmod_irq_info omap44xx_timer5_irqs
[] = {
3198 { .irq
= 41 + OMAP44XX_IRQ_GIC_START
},
3202 static struct omap_hwmod omap44xx_timer5_hwmod
= {
3204 .class = &omap44xx_timer_hwmod_class
,
3205 .clkdm_name
= "abe_clkdm",
3206 .mpu_irqs
= omap44xx_timer5_irqs
,
3207 .main_clk
= "timer5_fck",
3210 .clkctrl_offs
= OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET
,
3211 .context_offs
= OMAP4_RM_ABE_TIMER5_CONTEXT_OFFSET
,
3212 .modulemode
= MODULEMODE_SWCTRL
,
3215 .dev_attr
= &capability_dsp_dev_attr
,
3219 static struct omap_hwmod_irq_info omap44xx_timer6_irqs
[] = {
3220 { .irq
= 42 + OMAP44XX_IRQ_GIC_START
},
3224 static struct omap_hwmod omap44xx_timer6_hwmod
= {
3226 .class = &omap44xx_timer_hwmod_class
,
3227 .clkdm_name
= "abe_clkdm",
3228 .mpu_irqs
= omap44xx_timer6_irqs
,
3230 .main_clk
= "timer6_fck",
3233 .clkctrl_offs
= OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET
,
3234 .context_offs
= OMAP4_RM_ABE_TIMER6_CONTEXT_OFFSET
,
3235 .modulemode
= MODULEMODE_SWCTRL
,
3238 .dev_attr
= &capability_dsp_dev_attr
,
3242 static struct omap_hwmod_irq_info omap44xx_timer7_irqs
[] = {
3243 { .irq
= 43 + OMAP44XX_IRQ_GIC_START
},
3247 static struct omap_hwmod omap44xx_timer7_hwmod
= {
3249 .class = &omap44xx_timer_hwmod_class
,
3250 .clkdm_name
= "abe_clkdm",
3251 .mpu_irqs
= omap44xx_timer7_irqs
,
3252 .main_clk
= "timer7_fck",
3255 .clkctrl_offs
= OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET
,
3256 .context_offs
= OMAP4_RM_ABE_TIMER7_CONTEXT_OFFSET
,
3257 .modulemode
= MODULEMODE_SWCTRL
,
3260 .dev_attr
= &capability_dsp_dev_attr
,
3264 static struct omap_hwmod_irq_info omap44xx_timer8_irqs
[] = {
3265 { .irq
= 44 + OMAP44XX_IRQ_GIC_START
},
3269 static struct omap_hwmod omap44xx_timer8_hwmod
= {
3271 .class = &omap44xx_timer_hwmod_class
,
3272 .clkdm_name
= "abe_clkdm",
3273 .mpu_irqs
= omap44xx_timer8_irqs
,
3274 .main_clk
= "timer8_fck",
3277 .clkctrl_offs
= OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET
,
3278 .context_offs
= OMAP4_RM_ABE_TIMER8_CONTEXT_OFFSET
,
3279 .modulemode
= MODULEMODE_SWCTRL
,
3282 .dev_attr
= &capability_dsp_pwm_dev_attr
,
3286 static struct omap_hwmod_irq_info omap44xx_timer9_irqs
[] = {
3287 { .irq
= 45 + OMAP44XX_IRQ_GIC_START
},
3291 static struct omap_hwmod omap44xx_timer9_hwmod
= {
3293 .class = &omap44xx_timer_hwmod_class
,
3294 .clkdm_name
= "l4_per_clkdm",
3295 .mpu_irqs
= omap44xx_timer9_irqs
,
3296 .main_clk
= "timer9_fck",
3299 .clkctrl_offs
= OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET
,
3300 .context_offs
= OMAP4_RM_L4PER_DMTIMER9_CONTEXT_OFFSET
,
3301 .modulemode
= MODULEMODE_SWCTRL
,
3304 .dev_attr
= &capability_pwm_dev_attr
,
3308 static struct omap_hwmod_irq_info omap44xx_timer10_irqs
[] = {
3309 { .irq
= 46 + OMAP44XX_IRQ_GIC_START
},
3313 static struct omap_hwmod omap44xx_timer10_hwmod
= {
3315 .class = &omap44xx_timer_1ms_hwmod_class
,
3316 .clkdm_name
= "l4_per_clkdm",
3317 .mpu_irqs
= omap44xx_timer10_irqs
,
3318 .main_clk
= "timer10_fck",
3321 .clkctrl_offs
= OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET
,
3322 .context_offs
= OMAP4_RM_L4PER_DMTIMER10_CONTEXT_OFFSET
,
3323 .modulemode
= MODULEMODE_SWCTRL
,
3326 .dev_attr
= &capability_pwm_dev_attr
,
3330 static struct omap_hwmod_irq_info omap44xx_timer11_irqs
[] = {
3331 { .irq
= 47 + OMAP44XX_IRQ_GIC_START
},
3335 static struct omap_hwmod omap44xx_timer11_hwmod
= {
3337 .class = &omap44xx_timer_hwmod_class
,
3338 .clkdm_name
= "l4_per_clkdm",
3339 .mpu_irqs
= omap44xx_timer11_irqs
,
3340 .main_clk
= "timer11_fck",
3343 .clkctrl_offs
= OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET
,
3344 .context_offs
= OMAP4_RM_L4PER_DMTIMER11_CONTEXT_OFFSET
,
3345 .modulemode
= MODULEMODE_SWCTRL
,
3348 .dev_attr
= &capability_pwm_dev_attr
,
3353 * universal asynchronous receiver/transmitter (uart)
3356 static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc
= {
3358 .sysc_offs
= 0x0054,
3359 .syss_offs
= 0x0058,
3360 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_ENAWAKEUP
|
3361 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
|
3362 SYSS_HAS_RESET_STATUS
),
3363 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
3365 .sysc_fields
= &omap_hwmod_sysc_type1
,
3368 static struct omap_hwmod_class omap44xx_uart_hwmod_class
= {
3370 .sysc
= &omap44xx_uart_sysc
,
3374 static struct omap_hwmod_irq_info omap44xx_uart1_irqs
[] = {
3375 { .irq
= 72 + OMAP44XX_IRQ_GIC_START
},
3379 static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs
[] = {
3380 { .name
= "tx", .dma_req
= 48 + OMAP44XX_DMA_REQ_START
},
3381 { .name
= "rx", .dma_req
= 49 + OMAP44XX_DMA_REQ_START
},
3385 static struct omap_hwmod omap44xx_uart1_hwmod
= {
3387 .class = &omap44xx_uart_hwmod_class
,
3388 .clkdm_name
= "l4_per_clkdm",
3389 .mpu_irqs
= omap44xx_uart1_irqs
,
3390 .sdma_reqs
= omap44xx_uart1_sdma_reqs
,
3391 .main_clk
= "uart1_fck",
3394 .clkctrl_offs
= OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET
,
3395 .context_offs
= OMAP4_RM_L4PER_UART1_CONTEXT_OFFSET
,
3396 .modulemode
= MODULEMODE_SWCTRL
,
3402 static struct omap_hwmod_irq_info omap44xx_uart2_irqs
[] = {
3403 { .irq
= 73 + OMAP44XX_IRQ_GIC_START
},
3407 static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs
[] = {
3408 { .name
= "tx", .dma_req
= 50 + OMAP44XX_DMA_REQ_START
},
3409 { .name
= "rx", .dma_req
= 51 + OMAP44XX_DMA_REQ_START
},
3413 static struct omap_hwmod omap44xx_uart2_hwmod
= {
3415 .class = &omap44xx_uart_hwmod_class
,
3416 .clkdm_name
= "l4_per_clkdm",
3417 .mpu_irqs
= omap44xx_uart2_irqs
,
3418 .sdma_reqs
= omap44xx_uart2_sdma_reqs
,
3419 .main_clk
= "uart2_fck",
3422 .clkctrl_offs
= OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET
,
3423 .context_offs
= OMAP4_RM_L4PER_UART2_CONTEXT_OFFSET
,
3424 .modulemode
= MODULEMODE_SWCTRL
,
3430 static struct omap_hwmod_irq_info omap44xx_uart3_irqs
[] = {
3431 { .irq
= 74 + OMAP44XX_IRQ_GIC_START
},
3435 static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs
[] = {
3436 { .name
= "tx", .dma_req
= 52 + OMAP44XX_DMA_REQ_START
},
3437 { .name
= "rx", .dma_req
= 53 + OMAP44XX_DMA_REQ_START
},
3441 static struct omap_hwmod omap44xx_uart3_hwmod
= {
3443 .class = &omap44xx_uart_hwmod_class
,
3444 .clkdm_name
= "l4_per_clkdm",
3445 .flags
= HWMOD_INIT_NO_IDLE
| HWMOD_INIT_NO_RESET
,
3446 .mpu_irqs
= omap44xx_uart3_irqs
,
3447 .sdma_reqs
= omap44xx_uart3_sdma_reqs
,
3448 .main_clk
= "uart3_fck",
3451 .clkctrl_offs
= OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET
,
3452 .context_offs
= OMAP4_RM_L4PER_UART3_CONTEXT_OFFSET
,
3453 .modulemode
= MODULEMODE_SWCTRL
,
3459 static struct omap_hwmod_irq_info omap44xx_uart4_irqs
[] = {
3460 { .irq
= 70 + OMAP44XX_IRQ_GIC_START
},
3464 static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs
[] = {
3465 { .name
= "tx", .dma_req
= 54 + OMAP44XX_DMA_REQ_START
},
3466 { .name
= "rx", .dma_req
= 55 + OMAP44XX_DMA_REQ_START
},
3470 static struct omap_hwmod omap44xx_uart4_hwmod
= {
3472 .class = &omap44xx_uart_hwmod_class
,
3473 .clkdm_name
= "l4_per_clkdm",
3474 .mpu_irqs
= omap44xx_uart4_irqs
,
3475 .sdma_reqs
= omap44xx_uart4_sdma_reqs
,
3476 .main_clk
= "uart4_fck",
3479 .clkctrl_offs
= OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET
,
3480 .context_offs
= OMAP4_RM_L4PER_UART4_CONTEXT_OFFSET
,
3481 .modulemode
= MODULEMODE_SWCTRL
,
3487 * 'usb_host_fs' class
3488 * full-speed usb host controller
3491 /* The IP is not compliant to type1 / type2 scheme */
3492 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_usb_host_fs
= {
3498 static struct omap_hwmod_class_sysconfig omap44xx_usb_host_fs_sysc
= {
3500 .sysc_offs
= 0x0210,
3501 .sysc_flags
= (SYSC_HAS_MIDLEMODE
| SYSC_HAS_SIDLEMODE
|
3502 SYSC_HAS_SOFTRESET
),
3503 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
3505 .sysc_fields
= &omap_hwmod_sysc_type_usb_host_fs
,
3508 static struct omap_hwmod_class omap44xx_usb_host_fs_hwmod_class
= {
3509 .name
= "usb_host_fs",
3510 .sysc
= &omap44xx_usb_host_fs_sysc
,
3514 static struct omap_hwmod_irq_info omap44xx_usb_host_fs_irqs
[] = {
3515 { .name
= "std", .irq
= 89 + OMAP44XX_IRQ_GIC_START
},
3516 { .name
= "smi", .irq
= 90 + OMAP44XX_IRQ_GIC_START
},
3520 static struct omap_hwmod omap44xx_usb_host_fs_hwmod
= {
3521 .name
= "usb_host_fs",
3522 .class = &omap44xx_usb_host_fs_hwmod_class
,
3523 .clkdm_name
= "l3_init_clkdm",
3524 .mpu_irqs
= omap44xx_usb_host_fs_irqs
,
3525 .main_clk
= "usb_host_fs_fck",
3528 .clkctrl_offs
= OMAP4_CM_L3INIT_USB_HOST_FS_CLKCTRL_OFFSET
,
3529 .context_offs
= OMAP4_RM_L3INIT_USB_HOST_FS_CONTEXT_OFFSET
,
3530 .modulemode
= MODULEMODE_SWCTRL
,
3536 * 'usb_host_hs' class
3537 * high-speed multi-port usb host controller
3540 static struct omap_hwmod_class_sysconfig omap44xx_usb_host_hs_sysc
= {
3542 .sysc_offs
= 0x0010,
3543 .syss_offs
= 0x0014,
3544 .sysc_flags
= (SYSC_HAS_MIDLEMODE
| SYSC_HAS_SIDLEMODE
|
3545 SYSC_HAS_SOFTRESET
),
3546 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
3547 SIDLE_SMART_WKUP
| MSTANDBY_FORCE
| MSTANDBY_NO
|
3548 MSTANDBY_SMART
| MSTANDBY_SMART_WKUP
),
3549 .sysc_fields
= &omap_hwmod_sysc_type2
,
3552 static struct omap_hwmod_class omap44xx_usb_host_hs_hwmod_class
= {
3553 .name
= "usb_host_hs",
3554 .sysc
= &omap44xx_usb_host_hs_sysc
,
3558 static struct omap_hwmod_irq_info omap44xx_usb_host_hs_irqs
[] = {
3559 { .name
= "ohci-irq", .irq
= 76 + OMAP44XX_IRQ_GIC_START
},
3560 { .name
= "ehci-irq", .irq
= 77 + OMAP44XX_IRQ_GIC_START
},
3564 static struct omap_hwmod omap44xx_usb_host_hs_hwmod
= {
3565 .name
= "usb_host_hs",
3566 .class = &omap44xx_usb_host_hs_hwmod_class
,
3567 .clkdm_name
= "l3_init_clkdm",
3568 .main_clk
= "usb_host_hs_fck",
3571 .clkctrl_offs
= OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET
,
3572 .context_offs
= OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET
,
3573 .modulemode
= MODULEMODE_SWCTRL
,
3576 .mpu_irqs
= omap44xx_usb_host_hs_irqs
,
3579 * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
3583 * In the following configuration :
3584 * - USBHOST module is set to smart-idle mode
3585 * - PRCM asserts idle_req to the USBHOST module ( This typically
3586 * happens when the system is going to a low power mode : all ports
3587 * have been suspended, the master part of the USBHOST module has
3588 * entered the standby state, and SW has cut the functional clocks)
3589 * - an USBHOST interrupt occurs before the module is able to answer
3590 * idle_ack, typically a remote wakeup IRQ.
3591 * Then the USB HOST module will enter a deadlock situation where it
3592 * is no more accessible nor functional.
3595 * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
3599 * Errata: USB host EHCI may stall when entering smart-standby mode
3603 * When the USBHOST module is set to smart-standby mode, and when it is
3604 * ready to enter the standby state (i.e. all ports are suspended and
3605 * all attached devices are in suspend mode), then it can wrongly assert
3606 * the Mstandby signal too early while there are still some residual OCP
3607 * transactions ongoing. If this condition occurs, the internal state
3608 * machine may go to an undefined state and the USB link may be stuck
3609 * upon the next resume.
3612 * Don't use smart standby; use only force standby,
3613 * hence HWMOD_SWSUP_MSTANDBY
3617 * During system boot; If the hwmod framework resets the module
3618 * the module will have smart idle settings; which can lead to deadlock
3619 * (above Errata Id:i660); so, dont reset the module during boot;
3620 * Use HWMOD_INIT_NO_RESET.
3623 .flags
= HWMOD_SWSUP_SIDLE
| HWMOD_SWSUP_MSTANDBY
|
3624 HWMOD_INIT_NO_RESET
,
3628 * 'usb_otg_hs' class
3629 * high-speed on-the-go universal serial bus (usb_otg_hs) controller
3632 static struct omap_hwmod_class_sysconfig omap44xx_usb_otg_hs_sysc
= {
3634 .sysc_offs
= 0x0404,
3635 .syss_offs
= 0x0408,
3636 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_ENAWAKEUP
|
3637 SYSC_HAS_MIDLEMODE
| SYSC_HAS_SIDLEMODE
|
3638 SYSC_HAS_SOFTRESET
| SYSS_HAS_RESET_STATUS
),
3639 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
3640 SIDLE_SMART_WKUP
| MSTANDBY_FORCE
| MSTANDBY_NO
|
3642 .sysc_fields
= &omap_hwmod_sysc_type1
,
3645 static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class
= {
3646 .name
= "usb_otg_hs",
3647 .sysc
= &omap44xx_usb_otg_hs_sysc
,
3651 static struct omap_hwmod_irq_info omap44xx_usb_otg_hs_irqs
[] = {
3652 { .name
= "mc", .irq
= 92 + OMAP44XX_IRQ_GIC_START
},
3653 { .name
= "dma", .irq
= 93 + OMAP44XX_IRQ_GIC_START
},
3657 static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks
[] = {
3658 { .role
= "xclk", .clk
= "usb_otg_hs_xclk" },
3661 static struct omap_hwmod omap44xx_usb_otg_hs_hwmod
= {
3662 .name
= "usb_otg_hs",
3663 .class = &omap44xx_usb_otg_hs_hwmod_class
,
3664 .clkdm_name
= "l3_init_clkdm",
3665 .flags
= HWMOD_SWSUP_SIDLE
| HWMOD_SWSUP_MSTANDBY
,
3666 .mpu_irqs
= omap44xx_usb_otg_hs_irqs
,
3667 .main_clk
= "usb_otg_hs_ick",
3670 .clkctrl_offs
= OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET
,
3671 .context_offs
= OMAP4_RM_L3INIT_USB_OTG_CONTEXT_OFFSET
,
3672 .modulemode
= MODULEMODE_HWCTRL
,
3675 .opt_clks
= usb_otg_hs_opt_clks
,
3676 .opt_clks_cnt
= ARRAY_SIZE(usb_otg_hs_opt_clks
),
3680 * 'usb_tll_hs' class
3681 * usb_tll_hs module is the adapter on the usb_host_hs ports
3684 static struct omap_hwmod_class_sysconfig omap44xx_usb_tll_hs_sysc
= {
3686 .sysc_offs
= 0x0010,
3687 .syss_offs
= 0x0014,
3688 .sysc_flags
= (SYSC_HAS_CLOCKACTIVITY
| SYSC_HAS_SIDLEMODE
|
3689 SYSC_HAS_ENAWAKEUP
| SYSC_HAS_SOFTRESET
|
3691 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
3692 .sysc_fields
= &omap_hwmod_sysc_type1
,
3695 static struct omap_hwmod_class omap44xx_usb_tll_hs_hwmod_class
= {
3696 .name
= "usb_tll_hs",
3697 .sysc
= &omap44xx_usb_tll_hs_sysc
,
3700 static struct omap_hwmod_irq_info omap44xx_usb_tll_hs_irqs
[] = {
3701 { .name
= "tll-irq", .irq
= 78 + OMAP44XX_IRQ_GIC_START
},
3705 static struct omap_hwmod omap44xx_usb_tll_hs_hwmod
= {
3706 .name
= "usb_tll_hs",
3707 .class = &omap44xx_usb_tll_hs_hwmod_class
,
3708 .clkdm_name
= "l3_init_clkdm",
3709 .mpu_irqs
= omap44xx_usb_tll_hs_irqs
,
3710 .main_clk
= "usb_tll_hs_ick",
3713 .clkctrl_offs
= OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET
,
3714 .context_offs
= OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET
,
3715 .modulemode
= MODULEMODE_HWCTRL
,
3722 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
3723 * overflow condition
3726 static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc
= {
3728 .sysc_offs
= 0x0010,
3729 .syss_offs
= 0x0014,
3730 .sysc_flags
= (SYSC_HAS_EMUFREE
| SYSC_HAS_SIDLEMODE
|
3731 SYSC_HAS_SOFTRESET
| SYSS_HAS_RESET_STATUS
),
3732 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
3734 .sysc_fields
= &omap_hwmod_sysc_type1
,
3737 static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class
= {
3739 .sysc
= &omap44xx_wd_timer_sysc
,
3740 .pre_shutdown
= &omap2_wd_timer_disable
,
3741 .reset
= &omap2_wd_timer_reset
,
3745 static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs
[] = {
3746 { .irq
= 80 + OMAP44XX_IRQ_GIC_START
},
3750 static struct omap_hwmod omap44xx_wd_timer2_hwmod
= {
3751 .name
= "wd_timer2",
3752 .class = &omap44xx_wd_timer_hwmod_class
,
3753 .clkdm_name
= "l4_wkup_clkdm",
3754 .mpu_irqs
= omap44xx_wd_timer2_irqs
,
3755 .main_clk
= "wd_timer2_fck",
3758 .clkctrl_offs
= OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET
,
3759 .context_offs
= OMAP4_RM_WKUP_WDT2_CONTEXT_OFFSET
,
3760 .modulemode
= MODULEMODE_SWCTRL
,
3766 static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs
[] = {
3767 { .irq
= 36 + OMAP44XX_IRQ_GIC_START
},
3771 static struct omap_hwmod omap44xx_wd_timer3_hwmod
= {
3772 .name
= "wd_timer3",
3773 .class = &omap44xx_wd_timer_hwmod_class
,
3774 .clkdm_name
= "abe_clkdm",
3775 .mpu_irqs
= omap44xx_wd_timer3_irqs
,
3776 .main_clk
= "wd_timer3_fck",
3779 .clkctrl_offs
= OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET
,
3780 .context_offs
= OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET
,
3781 .modulemode
= MODULEMODE_SWCTRL
,
3791 static struct omap_hwmod_addr_space omap44xx_c2c_target_fw_addrs
[] = {
3793 .pa_start
= 0x4a204000,
3794 .pa_end
= 0x4a2040ff,
3795 .flags
= ADDR_TYPE_RT
3800 /* c2c -> c2c_target_fw */
3801 static struct omap_hwmod_ocp_if omap44xx_c2c__c2c_target_fw
= {
3802 .master
= &omap44xx_c2c_hwmod
,
3803 .slave
= &omap44xx_c2c_target_fw_hwmod
,
3804 .clk
= "div_core_ck",
3805 .addr
= omap44xx_c2c_target_fw_addrs
,
3806 .user
= OCP_USER_MPU
,
3809 /* l4_cfg -> c2c_target_fw */
3810 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__c2c_target_fw
= {
3811 .master
= &omap44xx_l4_cfg_hwmod
,
3812 .slave
= &omap44xx_c2c_target_fw_hwmod
,
3814 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3817 /* l3_main_1 -> dmm */
3818 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm
= {
3819 .master
= &omap44xx_l3_main_1_hwmod
,
3820 .slave
= &omap44xx_dmm_hwmod
,
3822 .user
= OCP_USER_SDMA
,
3825 static struct omap_hwmod_addr_space omap44xx_dmm_addrs
[] = {
3827 .pa_start
= 0x4e000000,
3828 .pa_end
= 0x4e0007ff,
3829 .flags
= ADDR_TYPE_RT
3835 static struct omap_hwmod_ocp_if omap44xx_mpu__dmm
= {
3836 .master
= &omap44xx_mpu_hwmod
,
3837 .slave
= &omap44xx_dmm_hwmod
,
3839 .addr
= omap44xx_dmm_addrs
,
3840 .user
= OCP_USER_MPU
,
3843 /* c2c -> emif_fw */
3844 static struct omap_hwmod_ocp_if omap44xx_c2c__emif_fw
= {
3845 .master
= &omap44xx_c2c_hwmod
,
3846 .slave
= &omap44xx_emif_fw_hwmod
,
3847 .clk
= "div_core_ck",
3848 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3851 /* dmm -> emif_fw */
3852 static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw
= {
3853 .master
= &omap44xx_dmm_hwmod
,
3854 .slave
= &omap44xx_emif_fw_hwmod
,
3856 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3859 static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs
[] = {
3861 .pa_start
= 0x4a20c000,
3862 .pa_end
= 0x4a20c0ff,
3863 .flags
= ADDR_TYPE_RT
3868 /* l4_cfg -> emif_fw */
3869 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw
= {
3870 .master
= &omap44xx_l4_cfg_hwmod
,
3871 .slave
= &omap44xx_emif_fw_hwmod
,
3873 .addr
= omap44xx_emif_fw_addrs
,
3874 .user
= OCP_USER_MPU
,
3877 /* iva -> l3_instr */
3878 static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr
= {
3879 .master
= &omap44xx_iva_hwmod
,
3880 .slave
= &omap44xx_l3_instr_hwmod
,
3882 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3885 /* l3_main_3 -> l3_instr */
3886 static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr
= {
3887 .master
= &omap44xx_l3_main_3_hwmod
,
3888 .slave
= &omap44xx_l3_instr_hwmod
,
3890 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3893 /* ocp_wp_noc -> l3_instr */
3894 static struct omap_hwmod_ocp_if omap44xx_ocp_wp_noc__l3_instr
= {
3895 .master
= &omap44xx_ocp_wp_noc_hwmod
,
3896 .slave
= &omap44xx_l3_instr_hwmod
,
3898 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3901 /* dsp -> l3_main_1 */
3902 static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1
= {
3903 .master
= &omap44xx_dsp_hwmod
,
3904 .slave
= &omap44xx_l3_main_1_hwmod
,
3906 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3909 /* dss -> l3_main_1 */
3910 static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1
= {
3911 .master
= &omap44xx_dss_hwmod
,
3912 .slave
= &omap44xx_l3_main_1_hwmod
,
3914 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3917 /* l3_main_2 -> l3_main_1 */
3918 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1
= {
3919 .master
= &omap44xx_l3_main_2_hwmod
,
3920 .slave
= &omap44xx_l3_main_1_hwmod
,
3922 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3925 /* l4_cfg -> l3_main_1 */
3926 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1
= {
3927 .master
= &omap44xx_l4_cfg_hwmod
,
3928 .slave
= &omap44xx_l3_main_1_hwmod
,
3930 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3933 /* mmc1 -> l3_main_1 */
3934 static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1
= {
3935 .master
= &omap44xx_mmc1_hwmod
,
3936 .slave
= &omap44xx_l3_main_1_hwmod
,
3938 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3941 /* mmc2 -> l3_main_1 */
3942 static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1
= {
3943 .master
= &omap44xx_mmc2_hwmod
,
3944 .slave
= &omap44xx_l3_main_1_hwmod
,
3946 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3949 static struct omap_hwmod_addr_space omap44xx_l3_main_1_addrs
[] = {
3951 .pa_start
= 0x44000000,
3952 .pa_end
= 0x44000fff,
3953 .flags
= ADDR_TYPE_RT
3958 /* mpu -> l3_main_1 */
3959 static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1
= {
3960 .master
= &omap44xx_mpu_hwmod
,
3961 .slave
= &omap44xx_l3_main_1_hwmod
,
3963 .addr
= omap44xx_l3_main_1_addrs
,
3964 .user
= OCP_USER_MPU
,
3967 /* c2c_target_fw -> l3_main_2 */
3968 static struct omap_hwmod_ocp_if omap44xx_c2c_target_fw__l3_main_2
= {
3969 .master
= &omap44xx_c2c_target_fw_hwmod
,
3970 .slave
= &omap44xx_l3_main_2_hwmod
,
3972 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3975 /* debugss -> l3_main_2 */
3976 static struct omap_hwmod_ocp_if omap44xx_debugss__l3_main_2
= {
3977 .master
= &omap44xx_debugss_hwmod
,
3978 .slave
= &omap44xx_l3_main_2_hwmod
,
3979 .clk
= "dbgclk_mux_ck",
3980 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3983 /* dma_system -> l3_main_2 */
3984 static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2
= {
3985 .master
= &omap44xx_dma_system_hwmod
,
3986 .slave
= &omap44xx_l3_main_2_hwmod
,
3988 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3991 /* fdif -> l3_main_2 */
3992 static struct omap_hwmod_ocp_if omap44xx_fdif__l3_main_2
= {
3993 .master
= &omap44xx_fdif_hwmod
,
3994 .slave
= &omap44xx_l3_main_2_hwmod
,
3996 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3999 /* gpu -> l3_main_2 */
4000 static struct omap_hwmod_ocp_if omap44xx_gpu__l3_main_2
= {
4001 .master
= &omap44xx_gpu_hwmod
,
4002 .slave
= &omap44xx_l3_main_2_hwmod
,
4004 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4007 /* hsi -> l3_main_2 */
4008 static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2
= {
4009 .master
= &omap44xx_hsi_hwmod
,
4010 .slave
= &omap44xx_l3_main_2_hwmod
,
4012 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4015 /* ipu -> l3_main_2 */
4016 static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2
= {
4017 .master
= &omap44xx_ipu_hwmod
,
4018 .slave
= &omap44xx_l3_main_2_hwmod
,
4020 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4023 /* iss -> l3_main_2 */
4024 static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2
= {
4025 .master
= &omap44xx_iss_hwmod
,
4026 .slave
= &omap44xx_l3_main_2_hwmod
,
4028 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4031 /* iva -> l3_main_2 */
4032 static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2
= {
4033 .master
= &omap44xx_iva_hwmod
,
4034 .slave
= &omap44xx_l3_main_2_hwmod
,
4036 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4039 static struct omap_hwmod_addr_space omap44xx_l3_main_2_addrs
[] = {
4041 .pa_start
= 0x44800000,
4042 .pa_end
= 0x44801fff,
4043 .flags
= ADDR_TYPE_RT
4048 /* l3_main_1 -> l3_main_2 */
4049 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2
= {
4050 .master
= &omap44xx_l3_main_1_hwmod
,
4051 .slave
= &omap44xx_l3_main_2_hwmod
,
4053 .addr
= omap44xx_l3_main_2_addrs
,
4054 .user
= OCP_USER_MPU
,
4057 /* l4_cfg -> l3_main_2 */
4058 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2
= {
4059 .master
= &omap44xx_l4_cfg_hwmod
,
4060 .slave
= &omap44xx_l3_main_2_hwmod
,
4062 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4065 /* usb_host_fs -> l3_main_2 */
4066 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_usb_host_fs__l3_main_2
= {
4067 .master
= &omap44xx_usb_host_fs_hwmod
,
4068 .slave
= &omap44xx_l3_main_2_hwmod
,
4070 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4073 /* usb_host_hs -> l3_main_2 */
4074 static struct omap_hwmod_ocp_if omap44xx_usb_host_hs__l3_main_2
= {
4075 .master
= &omap44xx_usb_host_hs_hwmod
,
4076 .slave
= &omap44xx_l3_main_2_hwmod
,
4078 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4081 /* usb_otg_hs -> l3_main_2 */
4082 static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2
= {
4083 .master
= &omap44xx_usb_otg_hs_hwmod
,
4084 .slave
= &omap44xx_l3_main_2_hwmod
,
4086 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4089 static struct omap_hwmod_addr_space omap44xx_l3_main_3_addrs
[] = {
4091 .pa_start
= 0x45000000,
4092 .pa_end
= 0x45000fff,
4093 .flags
= ADDR_TYPE_RT
4098 /* l3_main_1 -> l3_main_3 */
4099 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3
= {
4100 .master
= &omap44xx_l3_main_1_hwmod
,
4101 .slave
= &omap44xx_l3_main_3_hwmod
,
4103 .addr
= omap44xx_l3_main_3_addrs
,
4104 .user
= OCP_USER_MPU
,
4107 /* l3_main_2 -> l3_main_3 */
4108 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3
= {
4109 .master
= &omap44xx_l3_main_2_hwmod
,
4110 .slave
= &omap44xx_l3_main_3_hwmod
,
4112 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4115 /* l4_cfg -> l3_main_3 */
4116 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3
= {
4117 .master
= &omap44xx_l4_cfg_hwmod
,
4118 .slave
= &omap44xx_l3_main_3_hwmod
,
4120 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4123 /* aess -> l4_abe */
4124 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_aess__l4_abe
= {
4125 .master
= &omap44xx_aess_hwmod
,
4126 .slave
= &omap44xx_l4_abe_hwmod
,
4127 .clk
= "ocp_abe_iclk",
4128 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4132 static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe
= {
4133 .master
= &omap44xx_dsp_hwmod
,
4134 .slave
= &omap44xx_l4_abe_hwmod
,
4135 .clk
= "ocp_abe_iclk",
4136 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4139 /* l3_main_1 -> l4_abe */
4140 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe
= {
4141 .master
= &omap44xx_l3_main_1_hwmod
,
4142 .slave
= &omap44xx_l4_abe_hwmod
,
4144 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4148 static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe
= {
4149 .master
= &omap44xx_mpu_hwmod
,
4150 .slave
= &omap44xx_l4_abe_hwmod
,
4151 .clk
= "ocp_abe_iclk",
4152 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4155 /* l3_main_1 -> l4_cfg */
4156 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg
= {
4157 .master
= &omap44xx_l3_main_1_hwmod
,
4158 .slave
= &omap44xx_l4_cfg_hwmod
,
4160 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4163 /* l3_main_2 -> l4_per */
4164 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per
= {
4165 .master
= &omap44xx_l3_main_2_hwmod
,
4166 .slave
= &omap44xx_l4_per_hwmod
,
4168 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4171 /* l4_cfg -> l4_wkup */
4172 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup
= {
4173 .master
= &omap44xx_l4_cfg_hwmod
,
4174 .slave
= &omap44xx_l4_wkup_hwmod
,
4176 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4179 /* mpu -> mpu_private */
4180 static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private
= {
4181 .master
= &omap44xx_mpu_hwmod
,
4182 .slave
= &omap44xx_mpu_private_hwmod
,
4184 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4187 static struct omap_hwmod_addr_space omap44xx_ocp_wp_noc_addrs
[] = {
4189 .pa_start
= 0x4a102000,
4190 .pa_end
= 0x4a10207f,
4191 .flags
= ADDR_TYPE_RT
4196 /* l4_cfg -> ocp_wp_noc */
4197 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp_wp_noc
= {
4198 .master
= &omap44xx_l4_cfg_hwmod
,
4199 .slave
= &omap44xx_ocp_wp_noc_hwmod
,
4201 .addr
= omap44xx_ocp_wp_noc_addrs
,
4202 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4205 static struct omap_hwmod_addr_space omap44xx_aess_addrs
[] = {
4207 .pa_start
= 0x401f1000,
4208 .pa_end
= 0x401f13ff,
4209 .flags
= ADDR_TYPE_RT
4214 /* l4_abe -> aess */
4215 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess
= {
4216 .master
= &omap44xx_l4_abe_hwmod
,
4217 .slave
= &omap44xx_aess_hwmod
,
4218 .clk
= "ocp_abe_iclk",
4219 .addr
= omap44xx_aess_addrs
,
4220 .user
= OCP_USER_MPU
,
4223 static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs
[] = {
4225 .pa_start
= 0x490f1000,
4226 .pa_end
= 0x490f13ff,
4227 .flags
= ADDR_TYPE_RT
4232 /* l4_abe -> aess (dma) */
4233 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess_dma
= {
4234 .master
= &omap44xx_l4_abe_hwmod
,
4235 .slave
= &omap44xx_aess_hwmod
,
4236 .clk
= "ocp_abe_iclk",
4237 .addr
= omap44xx_aess_dma_addrs
,
4238 .user
= OCP_USER_SDMA
,
4241 /* l3_main_2 -> c2c */
4242 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__c2c
= {
4243 .master
= &omap44xx_l3_main_2_hwmod
,
4244 .slave
= &omap44xx_c2c_hwmod
,
4246 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4249 static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs
[] = {
4251 .pa_start
= 0x4a304000,
4252 .pa_end
= 0x4a30401f,
4253 .flags
= ADDR_TYPE_RT
4258 /* l4_wkup -> counter_32k */
4259 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k
= {
4260 .master
= &omap44xx_l4_wkup_hwmod
,
4261 .slave
= &omap44xx_counter_32k_hwmod
,
4262 .clk
= "l4_wkup_clk_mux_ck",
4263 .addr
= omap44xx_counter_32k_addrs
,
4264 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4267 static struct omap_hwmod_addr_space omap44xx_ctrl_module_core_addrs
[] = {
4269 .pa_start
= 0x4a002000,
4270 .pa_end
= 0x4a0027ff,
4271 .flags
= ADDR_TYPE_RT
4276 /* l4_cfg -> ctrl_module_core */
4277 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_core
= {
4278 .master
= &omap44xx_l4_cfg_hwmod
,
4279 .slave
= &omap44xx_ctrl_module_core_hwmod
,
4281 .addr
= omap44xx_ctrl_module_core_addrs
,
4282 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4285 static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_core_addrs
[] = {
4287 .pa_start
= 0x4a100000,
4288 .pa_end
= 0x4a1007ff,
4289 .flags
= ADDR_TYPE_RT
4294 /* l4_cfg -> ctrl_module_pad_core */
4295 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_pad_core
= {
4296 .master
= &omap44xx_l4_cfg_hwmod
,
4297 .slave
= &omap44xx_ctrl_module_pad_core_hwmod
,
4299 .addr
= omap44xx_ctrl_module_pad_core_addrs
,
4300 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4303 static struct omap_hwmod_addr_space omap44xx_ctrl_module_wkup_addrs
[] = {
4305 .pa_start
= 0x4a30c000,
4306 .pa_end
= 0x4a30c7ff,
4307 .flags
= ADDR_TYPE_RT
4312 /* l4_wkup -> ctrl_module_wkup */
4313 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_wkup
= {
4314 .master
= &omap44xx_l4_wkup_hwmod
,
4315 .slave
= &omap44xx_ctrl_module_wkup_hwmod
,
4316 .clk
= "l4_wkup_clk_mux_ck",
4317 .addr
= omap44xx_ctrl_module_wkup_addrs
,
4318 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4321 static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_wkup_addrs
[] = {
4323 .pa_start
= 0x4a31e000,
4324 .pa_end
= 0x4a31e7ff,
4325 .flags
= ADDR_TYPE_RT
4330 /* l4_wkup -> ctrl_module_pad_wkup */
4331 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_pad_wkup
= {
4332 .master
= &omap44xx_l4_wkup_hwmod
,
4333 .slave
= &omap44xx_ctrl_module_pad_wkup_hwmod
,
4334 .clk
= "l4_wkup_clk_mux_ck",
4335 .addr
= omap44xx_ctrl_module_pad_wkup_addrs
,
4336 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4339 static struct omap_hwmod_addr_space omap44xx_debugss_addrs
[] = {
4341 .pa_start
= 0x54160000,
4342 .pa_end
= 0x54167fff,
4343 .flags
= ADDR_TYPE_RT
4348 /* l3_instr -> debugss */
4349 static struct omap_hwmod_ocp_if omap44xx_l3_instr__debugss
= {
4350 .master
= &omap44xx_l3_instr_hwmod
,
4351 .slave
= &omap44xx_debugss_hwmod
,
4353 .addr
= omap44xx_debugss_addrs
,
4354 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4357 static struct omap_hwmod_addr_space omap44xx_dma_system_addrs
[] = {
4359 .pa_start
= 0x4a056000,
4360 .pa_end
= 0x4a056fff,
4361 .flags
= ADDR_TYPE_RT
4366 /* l4_cfg -> dma_system */
4367 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system
= {
4368 .master
= &omap44xx_l4_cfg_hwmod
,
4369 .slave
= &omap44xx_dma_system_hwmod
,
4371 .addr
= omap44xx_dma_system_addrs
,
4372 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4375 static struct omap_hwmod_addr_space omap44xx_dmic_addrs
[] = {
4378 .pa_start
= 0x4012e000,
4379 .pa_end
= 0x4012e07f,
4380 .flags
= ADDR_TYPE_RT
4385 /* l4_abe -> dmic */
4386 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic
= {
4387 .master
= &omap44xx_l4_abe_hwmod
,
4388 .slave
= &omap44xx_dmic_hwmod
,
4389 .clk
= "ocp_abe_iclk",
4390 .addr
= omap44xx_dmic_addrs
,
4391 .user
= OCP_USER_MPU
,
4394 static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs
[] = {
4397 .pa_start
= 0x4902e000,
4398 .pa_end
= 0x4902e07f,
4399 .flags
= ADDR_TYPE_RT
4404 /* l4_abe -> dmic (dma) */
4405 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma
= {
4406 .master
= &omap44xx_l4_abe_hwmod
,
4407 .slave
= &omap44xx_dmic_hwmod
,
4408 .clk
= "ocp_abe_iclk",
4409 .addr
= omap44xx_dmic_dma_addrs
,
4410 .user
= OCP_USER_SDMA
,
4414 static struct omap_hwmod_ocp_if omap44xx_dsp__iva
= {
4415 .master
= &omap44xx_dsp_hwmod
,
4416 .slave
= &omap44xx_iva_hwmod
,
4417 .clk
= "dpll_iva_m5x2_ck",
4418 .user
= OCP_USER_DSP
,
4422 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_dsp__sl2if
= {
4423 .master
= &omap44xx_dsp_hwmod
,
4424 .slave
= &omap44xx_sl2if_hwmod
,
4425 .clk
= "dpll_iva_m5x2_ck",
4426 .user
= OCP_USER_DSP
,
4430 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp
= {
4431 .master
= &omap44xx_l4_cfg_hwmod
,
4432 .slave
= &omap44xx_dsp_hwmod
,
4434 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4437 static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs
[] = {
4439 .pa_start
= 0x58000000,
4440 .pa_end
= 0x5800007f,
4441 .flags
= ADDR_TYPE_RT
4446 /* l3_main_2 -> dss */
4447 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss
= {
4448 .master
= &omap44xx_l3_main_2_hwmod
,
4449 .slave
= &omap44xx_dss_hwmod
,
4451 .addr
= omap44xx_dss_dma_addrs
,
4452 .user
= OCP_USER_SDMA
,
4455 static struct omap_hwmod_addr_space omap44xx_dss_addrs
[] = {
4457 .pa_start
= 0x48040000,
4458 .pa_end
= 0x4804007f,
4459 .flags
= ADDR_TYPE_RT
4465 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss
= {
4466 .master
= &omap44xx_l4_per_hwmod
,
4467 .slave
= &omap44xx_dss_hwmod
,
4469 .addr
= omap44xx_dss_addrs
,
4470 .user
= OCP_USER_MPU
,
4473 static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs
[] = {
4475 .pa_start
= 0x58001000,
4476 .pa_end
= 0x58001fff,
4477 .flags
= ADDR_TYPE_RT
4482 /* l3_main_2 -> dss_dispc */
4483 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc
= {
4484 .master
= &omap44xx_l3_main_2_hwmod
,
4485 .slave
= &omap44xx_dss_dispc_hwmod
,
4487 .addr
= omap44xx_dss_dispc_dma_addrs
,
4488 .user
= OCP_USER_SDMA
,
4491 static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs
[] = {
4493 .pa_start
= 0x48041000,
4494 .pa_end
= 0x48041fff,
4495 .flags
= ADDR_TYPE_RT
4500 /* l4_per -> dss_dispc */
4501 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc
= {
4502 .master
= &omap44xx_l4_per_hwmod
,
4503 .slave
= &omap44xx_dss_dispc_hwmod
,
4505 .addr
= omap44xx_dss_dispc_addrs
,
4506 .user
= OCP_USER_MPU
,
4509 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs
[] = {
4511 .pa_start
= 0x58004000,
4512 .pa_end
= 0x580041ff,
4513 .flags
= ADDR_TYPE_RT
4518 /* l3_main_2 -> dss_dsi1 */
4519 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1
= {
4520 .master
= &omap44xx_l3_main_2_hwmod
,
4521 .slave
= &omap44xx_dss_dsi1_hwmod
,
4523 .addr
= omap44xx_dss_dsi1_dma_addrs
,
4524 .user
= OCP_USER_SDMA
,
4527 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs
[] = {
4529 .pa_start
= 0x48044000,
4530 .pa_end
= 0x480441ff,
4531 .flags
= ADDR_TYPE_RT
4536 /* l4_per -> dss_dsi1 */
4537 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1
= {
4538 .master
= &omap44xx_l4_per_hwmod
,
4539 .slave
= &omap44xx_dss_dsi1_hwmod
,
4541 .addr
= omap44xx_dss_dsi1_addrs
,
4542 .user
= OCP_USER_MPU
,
4545 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs
[] = {
4547 .pa_start
= 0x58005000,
4548 .pa_end
= 0x580051ff,
4549 .flags
= ADDR_TYPE_RT
4554 /* l3_main_2 -> dss_dsi2 */
4555 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2
= {
4556 .master
= &omap44xx_l3_main_2_hwmod
,
4557 .slave
= &omap44xx_dss_dsi2_hwmod
,
4559 .addr
= omap44xx_dss_dsi2_dma_addrs
,
4560 .user
= OCP_USER_SDMA
,
4563 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs
[] = {
4565 .pa_start
= 0x48045000,
4566 .pa_end
= 0x480451ff,
4567 .flags
= ADDR_TYPE_RT
4572 /* l4_per -> dss_dsi2 */
4573 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2
= {
4574 .master
= &omap44xx_l4_per_hwmod
,
4575 .slave
= &omap44xx_dss_dsi2_hwmod
,
4577 .addr
= omap44xx_dss_dsi2_addrs
,
4578 .user
= OCP_USER_MPU
,
4581 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs
[] = {
4583 .pa_start
= 0x58006000,
4584 .pa_end
= 0x58006fff,
4585 .flags
= ADDR_TYPE_RT
4590 /* l3_main_2 -> dss_hdmi */
4591 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi
= {
4592 .master
= &omap44xx_l3_main_2_hwmod
,
4593 .slave
= &omap44xx_dss_hdmi_hwmod
,
4595 .addr
= omap44xx_dss_hdmi_dma_addrs
,
4596 .user
= OCP_USER_SDMA
,
4599 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs
[] = {
4601 .pa_start
= 0x48046000,
4602 .pa_end
= 0x48046fff,
4603 .flags
= ADDR_TYPE_RT
4608 /* l4_per -> dss_hdmi */
4609 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi
= {
4610 .master
= &omap44xx_l4_per_hwmod
,
4611 .slave
= &omap44xx_dss_hdmi_hwmod
,
4613 .addr
= omap44xx_dss_hdmi_addrs
,
4614 .user
= OCP_USER_MPU
,
4617 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs
[] = {
4619 .pa_start
= 0x58002000,
4620 .pa_end
= 0x580020ff,
4621 .flags
= ADDR_TYPE_RT
4626 /* l3_main_2 -> dss_rfbi */
4627 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi
= {
4628 .master
= &omap44xx_l3_main_2_hwmod
,
4629 .slave
= &omap44xx_dss_rfbi_hwmod
,
4631 .addr
= omap44xx_dss_rfbi_dma_addrs
,
4632 .user
= OCP_USER_SDMA
,
4635 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs
[] = {
4637 .pa_start
= 0x48042000,
4638 .pa_end
= 0x480420ff,
4639 .flags
= ADDR_TYPE_RT
4644 /* l4_per -> dss_rfbi */
4645 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi
= {
4646 .master
= &omap44xx_l4_per_hwmod
,
4647 .slave
= &omap44xx_dss_rfbi_hwmod
,
4649 .addr
= omap44xx_dss_rfbi_addrs
,
4650 .user
= OCP_USER_MPU
,
4653 static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs
[] = {
4655 .pa_start
= 0x58003000,
4656 .pa_end
= 0x580030ff,
4657 .flags
= ADDR_TYPE_RT
4662 /* l3_main_2 -> dss_venc */
4663 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc
= {
4664 .master
= &omap44xx_l3_main_2_hwmod
,
4665 .slave
= &omap44xx_dss_venc_hwmod
,
4667 .addr
= omap44xx_dss_venc_dma_addrs
,
4668 .user
= OCP_USER_SDMA
,
4671 static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs
[] = {
4673 .pa_start
= 0x48043000,
4674 .pa_end
= 0x480430ff,
4675 .flags
= ADDR_TYPE_RT
4680 /* l4_per -> dss_venc */
4681 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc
= {
4682 .master
= &omap44xx_l4_per_hwmod
,
4683 .slave
= &omap44xx_dss_venc_hwmod
,
4685 .addr
= omap44xx_dss_venc_addrs
,
4686 .user
= OCP_USER_MPU
,
4689 static struct omap_hwmod_addr_space omap44xx_elm_addrs
[] = {
4691 .pa_start
= 0x48078000,
4692 .pa_end
= 0x48078fff,
4693 .flags
= ADDR_TYPE_RT
4699 static struct omap_hwmod_ocp_if omap44xx_l4_per__elm
= {
4700 .master
= &omap44xx_l4_per_hwmod
,
4701 .slave
= &omap44xx_elm_hwmod
,
4703 .addr
= omap44xx_elm_addrs
,
4704 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4707 static struct omap_hwmod_addr_space omap44xx_emif1_addrs
[] = {
4709 .pa_start
= 0x4c000000,
4710 .pa_end
= 0x4c0000ff,
4711 .flags
= ADDR_TYPE_RT
4716 /* emif_fw -> emif1 */
4717 static struct omap_hwmod_ocp_if omap44xx_emif_fw__emif1
= {
4718 .master
= &omap44xx_emif_fw_hwmod
,
4719 .slave
= &omap44xx_emif1_hwmod
,
4721 .addr
= omap44xx_emif1_addrs
,
4722 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4725 static struct omap_hwmod_addr_space omap44xx_emif2_addrs
[] = {
4727 .pa_start
= 0x4d000000,
4728 .pa_end
= 0x4d0000ff,
4729 .flags
= ADDR_TYPE_RT
4734 /* emif_fw -> emif2 */
4735 static struct omap_hwmod_ocp_if omap44xx_emif_fw__emif2
= {
4736 .master
= &omap44xx_emif_fw_hwmod
,
4737 .slave
= &omap44xx_emif2_hwmod
,
4739 .addr
= omap44xx_emif2_addrs
,
4740 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4743 static struct omap_hwmod_addr_space omap44xx_fdif_addrs
[] = {
4745 .pa_start
= 0x4a10a000,
4746 .pa_end
= 0x4a10a1ff,
4747 .flags
= ADDR_TYPE_RT
4752 /* l4_cfg -> fdif */
4753 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__fdif
= {
4754 .master
= &omap44xx_l4_cfg_hwmod
,
4755 .slave
= &omap44xx_fdif_hwmod
,
4757 .addr
= omap44xx_fdif_addrs
,
4758 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4761 static struct omap_hwmod_addr_space omap44xx_gpio1_addrs
[] = {
4763 .pa_start
= 0x4a310000,
4764 .pa_end
= 0x4a3101ff,
4765 .flags
= ADDR_TYPE_RT
4770 /* l4_wkup -> gpio1 */
4771 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1
= {
4772 .master
= &omap44xx_l4_wkup_hwmod
,
4773 .slave
= &omap44xx_gpio1_hwmod
,
4774 .clk
= "l4_wkup_clk_mux_ck",
4775 .addr
= omap44xx_gpio1_addrs
,
4776 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4779 static struct omap_hwmod_addr_space omap44xx_gpio2_addrs
[] = {
4781 .pa_start
= 0x48055000,
4782 .pa_end
= 0x480551ff,
4783 .flags
= ADDR_TYPE_RT
4788 /* l4_per -> gpio2 */
4789 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2
= {
4790 .master
= &omap44xx_l4_per_hwmod
,
4791 .slave
= &omap44xx_gpio2_hwmod
,
4793 .addr
= omap44xx_gpio2_addrs
,
4794 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4797 static struct omap_hwmod_addr_space omap44xx_gpio3_addrs
[] = {
4799 .pa_start
= 0x48057000,
4800 .pa_end
= 0x480571ff,
4801 .flags
= ADDR_TYPE_RT
4806 /* l4_per -> gpio3 */
4807 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3
= {
4808 .master
= &omap44xx_l4_per_hwmod
,
4809 .slave
= &omap44xx_gpio3_hwmod
,
4811 .addr
= omap44xx_gpio3_addrs
,
4812 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4815 static struct omap_hwmod_addr_space omap44xx_gpio4_addrs
[] = {
4817 .pa_start
= 0x48059000,
4818 .pa_end
= 0x480591ff,
4819 .flags
= ADDR_TYPE_RT
4824 /* l4_per -> gpio4 */
4825 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4
= {
4826 .master
= &omap44xx_l4_per_hwmod
,
4827 .slave
= &omap44xx_gpio4_hwmod
,
4829 .addr
= omap44xx_gpio4_addrs
,
4830 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4833 static struct omap_hwmod_addr_space omap44xx_gpio5_addrs
[] = {
4835 .pa_start
= 0x4805b000,
4836 .pa_end
= 0x4805b1ff,
4837 .flags
= ADDR_TYPE_RT
4842 /* l4_per -> gpio5 */
4843 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5
= {
4844 .master
= &omap44xx_l4_per_hwmod
,
4845 .slave
= &omap44xx_gpio5_hwmod
,
4847 .addr
= omap44xx_gpio5_addrs
,
4848 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4851 static struct omap_hwmod_addr_space omap44xx_gpio6_addrs
[] = {
4853 .pa_start
= 0x4805d000,
4854 .pa_end
= 0x4805d1ff,
4855 .flags
= ADDR_TYPE_RT
4860 /* l4_per -> gpio6 */
4861 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6
= {
4862 .master
= &omap44xx_l4_per_hwmod
,
4863 .slave
= &omap44xx_gpio6_hwmod
,
4865 .addr
= omap44xx_gpio6_addrs
,
4866 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4869 static struct omap_hwmod_addr_space omap44xx_gpmc_addrs
[] = {
4871 .pa_start
= 0x50000000,
4872 .pa_end
= 0x500003ff,
4873 .flags
= ADDR_TYPE_RT
4878 /* l3_main_2 -> gpmc */
4879 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpmc
= {
4880 .master
= &omap44xx_l3_main_2_hwmod
,
4881 .slave
= &omap44xx_gpmc_hwmod
,
4883 .addr
= omap44xx_gpmc_addrs
,
4884 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4887 static struct omap_hwmod_addr_space omap44xx_gpu_addrs
[] = {
4889 .pa_start
= 0x56000000,
4890 .pa_end
= 0x5600ffff,
4891 .flags
= ADDR_TYPE_RT
4896 /* l3_main_2 -> gpu */
4897 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpu
= {
4898 .master
= &omap44xx_l3_main_2_hwmod
,
4899 .slave
= &omap44xx_gpu_hwmod
,
4901 .addr
= omap44xx_gpu_addrs
,
4902 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4905 static struct omap_hwmod_addr_space omap44xx_hdq1w_addrs
[] = {
4907 .pa_start
= 0x480b2000,
4908 .pa_end
= 0x480b201f,
4909 .flags
= ADDR_TYPE_RT
4914 /* l4_per -> hdq1w */
4915 static struct omap_hwmod_ocp_if omap44xx_l4_per__hdq1w
= {
4916 .master
= &omap44xx_l4_per_hwmod
,
4917 .slave
= &omap44xx_hdq1w_hwmod
,
4919 .addr
= omap44xx_hdq1w_addrs
,
4920 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4923 static struct omap_hwmod_addr_space omap44xx_hsi_addrs
[] = {
4925 .pa_start
= 0x4a058000,
4926 .pa_end
= 0x4a05bfff,
4927 .flags
= ADDR_TYPE_RT
4933 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi
= {
4934 .master
= &omap44xx_l4_cfg_hwmod
,
4935 .slave
= &omap44xx_hsi_hwmod
,
4937 .addr
= omap44xx_hsi_addrs
,
4938 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4941 static struct omap_hwmod_addr_space omap44xx_i2c1_addrs
[] = {
4943 .pa_start
= 0x48070000,
4944 .pa_end
= 0x480700ff,
4945 .flags
= ADDR_TYPE_RT
4950 /* l4_per -> i2c1 */
4951 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1
= {
4952 .master
= &omap44xx_l4_per_hwmod
,
4953 .slave
= &omap44xx_i2c1_hwmod
,
4955 .addr
= omap44xx_i2c1_addrs
,
4956 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4959 static struct omap_hwmod_addr_space omap44xx_i2c2_addrs
[] = {
4961 .pa_start
= 0x48072000,
4962 .pa_end
= 0x480720ff,
4963 .flags
= ADDR_TYPE_RT
4968 /* l4_per -> i2c2 */
4969 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2
= {
4970 .master
= &omap44xx_l4_per_hwmod
,
4971 .slave
= &omap44xx_i2c2_hwmod
,
4973 .addr
= omap44xx_i2c2_addrs
,
4974 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4977 static struct omap_hwmod_addr_space omap44xx_i2c3_addrs
[] = {
4979 .pa_start
= 0x48060000,
4980 .pa_end
= 0x480600ff,
4981 .flags
= ADDR_TYPE_RT
4986 /* l4_per -> i2c3 */
4987 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3
= {
4988 .master
= &omap44xx_l4_per_hwmod
,
4989 .slave
= &omap44xx_i2c3_hwmod
,
4991 .addr
= omap44xx_i2c3_addrs
,
4992 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4995 static struct omap_hwmod_addr_space omap44xx_i2c4_addrs
[] = {
4997 .pa_start
= 0x48350000,
4998 .pa_end
= 0x483500ff,
4999 .flags
= ADDR_TYPE_RT
5004 /* l4_per -> i2c4 */
5005 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4
= {
5006 .master
= &omap44xx_l4_per_hwmod
,
5007 .slave
= &omap44xx_i2c4_hwmod
,
5009 .addr
= omap44xx_i2c4_addrs
,
5010 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5013 /* l3_main_2 -> ipu */
5014 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu
= {
5015 .master
= &omap44xx_l3_main_2_hwmod
,
5016 .slave
= &omap44xx_ipu_hwmod
,
5018 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5021 static struct omap_hwmod_addr_space omap44xx_iss_addrs
[] = {
5023 .pa_start
= 0x52000000,
5024 .pa_end
= 0x520000ff,
5025 .flags
= ADDR_TYPE_RT
5030 /* l3_main_2 -> iss */
5031 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss
= {
5032 .master
= &omap44xx_l3_main_2_hwmod
,
5033 .slave
= &omap44xx_iss_hwmod
,
5035 .addr
= omap44xx_iss_addrs
,
5036 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5040 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_iva__sl2if
= {
5041 .master
= &omap44xx_iva_hwmod
,
5042 .slave
= &omap44xx_sl2if_hwmod
,
5043 .clk
= "dpll_iva_m5x2_ck",
5044 .user
= OCP_USER_IVA
,
5047 static struct omap_hwmod_addr_space omap44xx_iva_addrs
[] = {
5049 .pa_start
= 0x5a000000,
5050 .pa_end
= 0x5a07ffff,
5051 .flags
= ADDR_TYPE_RT
5056 /* l3_main_2 -> iva */
5057 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva
= {
5058 .master
= &omap44xx_l3_main_2_hwmod
,
5059 .slave
= &omap44xx_iva_hwmod
,
5061 .addr
= omap44xx_iva_addrs
,
5062 .user
= OCP_USER_MPU
,
5065 static struct omap_hwmod_addr_space omap44xx_kbd_addrs
[] = {
5067 .pa_start
= 0x4a31c000,
5068 .pa_end
= 0x4a31c07f,
5069 .flags
= ADDR_TYPE_RT
5074 /* l4_wkup -> kbd */
5075 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd
= {
5076 .master
= &omap44xx_l4_wkup_hwmod
,
5077 .slave
= &omap44xx_kbd_hwmod
,
5078 .clk
= "l4_wkup_clk_mux_ck",
5079 .addr
= omap44xx_kbd_addrs
,
5080 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5083 static struct omap_hwmod_addr_space omap44xx_mailbox_addrs
[] = {
5085 .pa_start
= 0x4a0f4000,
5086 .pa_end
= 0x4a0f41ff,
5087 .flags
= ADDR_TYPE_RT
5092 /* l4_cfg -> mailbox */
5093 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox
= {
5094 .master
= &omap44xx_l4_cfg_hwmod
,
5095 .slave
= &omap44xx_mailbox_hwmod
,
5097 .addr
= omap44xx_mailbox_addrs
,
5098 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5101 static struct omap_hwmod_addr_space omap44xx_mcasp_addrs
[] = {
5103 .pa_start
= 0x40128000,
5104 .pa_end
= 0x401283ff,
5105 .flags
= ADDR_TYPE_RT
5110 /* l4_abe -> mcasp */
5111 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp
= {
5112 .master
= &omap44xx_l4_abe_hwmod
,
5113 .slave
= &omap44xx_mcasp_hwmod
,
5114 .clk
= "ocp_abe_iclk",
5115 .addr
= omap44xx_mcasp_addrs
,
5116 .user
= OCP_USER_MPU
,
5119 static struct omap_hwmod_addr_space omap44xx_mcasp_dma_addrs
[] = {
5121 .pa_start
= 0x49028000,
5122 .pa_end
= 0x490283ff,
5123 .flags
= ADDR_TYPE_RT
5128 /* l4_abe -> mcasp (dma) */
5129 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp_dma
= {
5130 .master
= &omap44xx_l4_abe_hwmod
,
5131 .slave
= &omap44xx_mcasp_hwmod
,
5132 .clk
= "ocp_abe_iclk",
5133 .addr
= omap44xx_mcasp_dma_addrs
,
5134 .user
= OCP_USER_SDMA
,
5137 static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs
[] = {
5140 .pa_start
= 0x40122000,
5141 .pa_end
= 0x401220ff,
5142 .flags
= ADDR_TYPE_RT
5147 /* l4_abe -> mcbsp1 */
5148 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1
= {
5149 .master
= &omap44xx_l4_abe_hwmod
,
5150 .slave
= &omap44xx_mcbsp1_hwmod
,
5151 .clk
= "ocp_abe_iclk",
5152 .addr
= omap44xx_mcbsp1_addrs
,
5153 .user
= OCP_USER_MPU
,
5156 static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs
[] = {
5159 .pa_start
= 0x49022000,
5160 .pa_end
= 0x490220ff,
5161 .flags
= ADDR_TYPE_RT
5166 /* l4_abe -> mcbsp1 (dma) */
5167 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma
= {
5168 .master
= &omap44xx_l4_abe_hwmod
,
5169 .slave
= &omap44xx_mcbsp1_hwmod
,
5170 .clk
= "ocp_abe_iclk",
5171 .addr
= omap44xx_mcbsp1_dma_addrs
,
5172 .user
= OCP_USER_SDMA
,
5175 static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs
[] = {
5178 .pa_start
= 0x40124000,
5179 .pa_end
= 0x401240ff,
5180 .flags
= ADDR_TYPE_RT
5185 /* l4_abe -> mcbsp2 */
5186 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2
= {
5187 .master
= &omap44xx_l4_abe_hwmod
,
5188 .slave
= &omap44xx_mcbsp2_hwmod
,
5189 .clk
= "ocp_abe_iclk",
5190 .addr
= omap44xx_mcbsp2_addrs
,
5191 .user
= OCP_USER_MPU
,
5194 static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs
[] = {
5197 .pa_start
= 0x49024000,
5198 .pa_end
= 0x490240ff,
5199 .flags
= ADDR_TYPE_RT
5204 /* l4_abe -> mcbsp2 (dma) */
5205 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma
= {
5206 .master
= &omap44xx_l4_abe_hwmod
,
5207 .slave
= &omap44xx_mcbsp2_hwmod
,
5208 .clk
= "ocp_abe_iclk",
5209 .addr
= omap44xx_mcbsp2_dma_addrs
,
5210 .user
= OCP_USER_SDMA
,
5213 static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs
[] = {
5216 .pa_start
= 0x40126000,
5217 .pa_end
= 0x401260ff,
5218 .flags
= ADDR_TYPE_RT
5223 /* l4_abe -> mcbsp3 */
5224 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3
= {
5225 .master
= &omap44xx_l4_abe_hwmod
,
5226 .slave
= &omap44xx_mcbsp3_hwmod
,
5227 .clk
= "ocp_abe_iclk",
5228 .addr
= omap44xx_mcbsp3_addrs
,
5229 .user
= OCP_USER_MPU
,
5232 static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs
[] = {
5235 .pa_start
= 0x49026000,
5236 .pa_end
= 0x490260ff,
5237 .flags
= ADDR_TYPE_RT
5242 /* l4_abe -> mcbsp3 (dma) */
5243 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma
= {
5244 .master
= &omap44xx_l4_abe_hwmod
,
5245 .slave
= &omap44xx_mcbsp3_hwmod
,
5246 .clk
= "ocp_abe_iclk",
5247 .addr
= omap44xx_mcbsp3_dma_addrs
,
5248 .user
= OCP_USER_SDMA
,
5251 static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs
[] = {
5253 .pa_start
= 0x48096000,
5254 .pa_end
= 0x480960ff,
5255 .flags
= ADDR_TYPE_RT
5260 /* l4_per -> mcbsp4 */
5261 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4
= {
5262 .master
= &omap44xx_l4_per_hwmod
,
5263 .slave
= &omap44xx_mcbsp4_hwmod
,
5265 .addr
= omap44xx_mcbsp4_addrs
,
5266 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5269 static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs
[] = {
5272 .pa_start
= 0x40132000,
5273 .pa_end
= 0x4013207f,
5274 .flags
= ADDR_TYPE_RT
5279 /* l4_abe -> mcpdm */
5280 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm
= {
5281 .master
= &omap44xx_l4_abe_hwmod
,
5282 .slave
= &omap44xx_mcpdm_hwmod
,
5283 .clk
= "ocp_abe_iclk",
5284 .addr
= omap44xx_mcpdm_addrs
,
5285 .user
= OCP_USER_MPU
,
5288 static struct omap_hwmod_addr_space omap44xx_mcpdm_dma_addrs
[] = {
5291 .pa_start
= 0x49032000,
5292 .pa_end
= 0x4903207f,
5293 .flags
= ADDR_TYPE_RT
5298 /* l4_abe -> mcpdm (dma) */
5299 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma
= {
5300 .master
= &omap44xx_l4_abe_hwmod
,
5301 .slave
= &omap44xx_mcpdm_hwmod
,
5302 .clk
= "ocp_abe_iclk",
5303 .addr
= omap44xx_mcpdm_dma_addrs
,
5304 .user
= OCP_USER_SDMA
,
5307 static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs
[] = {
5309 .pa_start
= 0x48098000,
5310 .pa_end
= 0x480981ff,
5311 .flags
= ADDR_TYPE_RT
5316 /* l4_per -> mcspi1 */
5317 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1
= {
5318 .master
= &omap44xx_l4_per_hwmod
,
5319 .slave
= &omap44xx_mcspi1_hwmod
,
5321 .addr
= omap44xx_mcspi1_addrs
,
5322 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5325 static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs
[] = {
5327 .pa_start
= 0x4809a000,
5328 .pa_end
= 0x4809a1ff,
5329 .flags
= ADDR_TYPE_RT
5334 /* l4_per -> mcspi2 */
5335 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2
= {
5336 .master
= &omap44xx_l4_per_hwmod
,
5337 .slave
= &omap44xx_mcspi2_hwmod
,
5339 .addr
= omap44xx_mcspi2_addrs
,
5340 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5343 static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs
[] = {
5345 .pa_start
= 0x480b8000,
5346 .pa_end
= 0x480b81ff,
5347 .flags
= ADDR_TYPE_RT
5352 /* l4_per -> mcspi3 */
5353 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3
= {
5354 .master
= &omap44xx_l4_per_hwmod
,
5355 .slave
= &omap44xx_mcspi3_hwmod
,
5357 .addr
= omap44xx_mcspi3_addrs
,
5358 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5361 static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs
[] = {
5363 .pa_start
= 0x480ba000,
5364 .pa_end
= 0x480ba1ff,
5365 .flags
= ADDR_TYPE_RT
5370 /* l4_per -> mcspi4 */
5371 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4
= {
5372 .master
= &omap44xx_l4_per_hwmod
,
5373 .slave
= &omap44xx_mcspi4_hwmod
,
5375 .addr
= omap44xx_mcspi4_addrs
,
5376 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5379 static struct omap_hwmod_addr_space omap44xx_mmc1_addrs
[] = {
5381 .pa_start
= 0x4809c000,
5382 .pa_end
= 0x4809c3ff,
5383 .flags
= ADDR_TYPE_RT
5388 /* l4_per -> mmc1 */
5389 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1
= {
5390 .master
= &omap44xx_l4_per_hwmod
,
5391 .slave
= &omap44xx_mmc1_hwmod
,
5393 .addr
= omap44xx_mmc1_addrs
,
5394 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5397 static struct omap_hwmod_addr_space omap44xx_mmc2_addrs
[] = {
5399 .pa_start
= 0x480b4000,
5400 .pa_end
= 0x480b43ff,
5401 .flags
= ADDR_TYPE_RT
5406 /* l4_per -> mmc2 */
5407 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2
= {
5408 .master
= &omap44xx_l4_per_hwmod
,
5409 .slave
= &omap44xx_mmc2_hwmod
,
5411 .addr
= omap44xx_mmc2_addrs
,
5412 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5415 static struct omap_hwmod_addr_space omap44xx_mmc3_addrs
[] = {
5417 .pa_start
= 0x480ad000,
5418 .pa_end
= 0x480ad3ff,
5419 .flags
= ADDR_TYPE_RT
5424 /* l4_per -> mmc3 */
5425 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3
= {
5426 .master
= &omap44xx_l4_per_hwmod
,
5427 .slave
= &omap44xx_mmc3_hwmod
,
5429 .addr
= omap44xx_mmc3_addrs
,
5430 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5433 static struct omap_hwmod_addr_space omap44xx_mmc4_addrs
[] = {
5435 .pa_start
= 0x480d1000,
5436 .pa_end
= 0x480d13ff,
5437 .flags
= ADDR_TYPE_RT
5442 /* l4_per -> mmc4 */
5443 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4
= {
5444 .master
= &omap44xx_l4_per_hwmod
,
5445 .slave
= &omap44xx_mmc4_hwmod
,
5447 .addr
= omap44xx_mmc4_addrs
,
5448 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5451 static struct omap_hwmod_addr_space omap44xx_mmc5_addrs
[] = {
5453 .pa_start
= 0x480d5000,
5454 .pa_end
= 0x480d53ff,
5455 .flags
= ADDR_TYPE_RT
5460 /* l4_per -> mmc5 */
5461 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5
= {
5462 .master
= &omap44xx_l4_per_hwmod
,
5463 .slave
= &omap44xx_mmc5_hwmod
,
5465 .addr
= omap44xx_mmc5_addrs
,
5466 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5469 /* l3_main_2 -> ocmc_ram */
5470 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ocmc_ram
= {
5471 .master
= &omap44xx_l3_main_2_hwmod
,
5472 .slave
= &omap44xx_ocmc_ram_hwmod
,
5474 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5477 static struct omap_hwmod_addr_space omap44xx_ocp2scp_usb_phy_addrs
[] = {
5479 .pa_start
= 0x4a0ad000,
5480 .pa_end
= 0x4a0ad01f,
5481 .flags
= ADDR_TYPE_RT
5486 /* l4_cfg -> ocp2scp_usb_phy */
5487 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp2scp_usb_phy
= {
5488 .master
= &omap44xx_l4_cfg_hwmod
,
5489 .slave
= &omap44xx_ocp2scp_usb_phy_hwmod
,
5491 .addr
= omap44xx_ocp2scp_usb_phy_addrs
,
5492 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5495 static struct omap_hwmod_addr_space omap44xx_prcm_mpu_addrs
[] = {
5497 .pa_start
= 0x48243000,
5498 .pa_end
= 0x48243fff,
5499 .flags
= ADDR_TYPE_RT
5504 /* mpu_private -> prcm_mpu */
5505 static struct omap_hwmod_ocp_if omap44xx_mpu_private__prcm_mpu
= {
5506 .master
= &omap44xx_mpu_private_hwmod
,
5507 .slave
= &omap44xx_prcm_mpu_hwmod
,
5509 .addr
= omap44xx_prcm_mpu_addrs
,
5510 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5513 static struct omap_hwmod_addr_space omap44xx_cm_core_aon_addrs
[] = {
5515 .pa_start
= 0x4a004000,
5516 .pa_end
= 0x4a004fff,
5517 .flags
= ADDR_TYPE_RT
5522 /* l4_wkup -> cm_core_aon */
5523 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__cm_core_aon
= {
5524 .master
= &omap44xx_l4_wkup_hwmod
,
5525 .slave
= &omap44xx_cm_core_aon_hwmod
,
5526 .clk
= "l4_wkup_clk_mux_ck",
5527 .addr
= omap44xx_cm_core_aon_addrs
,
5528 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5531 static struct omap_hwmod_addr_space omap44xx_cm_core_addrs
[] = {
5533 .pa_start
= 0x4a008000,
5534 .pa_end
= 0x4a009fff,
5535 .flags
= ADDR_TYPE_RT
5540 /* l4_cfg -> cm_core */
5541 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__cm_core
= {
5542 .master
= &omap44xx_l4_cfg_hwmod
,
5543 .slave
= &omap44xx_cm_core_hwmod
,
5545 .addr
= omap44xx_cm_core_addrs
,
5546 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5549 static struct omap_hwmod_addr_space omap44xx_prm_addrs
[] = {
5551 .pa_start
= 0x4a306000,
5552 .pa_end
= 0x4a307fff,
5553 .flags
= ADDR_TYPE_RT
5558 /* l4_wkup -> prm */
5559 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__prm
= {
5560 .master
= &omap44xx_l4_wkup_hwmod
,
5561 .slave
= &omap44xx_prm_hwmod
,
5562 .clk
= "l4_wkup_clk_mux_ck",
5563 .addr
= omap44xx_prm_addrs
,
5564 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5567 static struct omap_hwmod_addr_space omap44xx_scrm_addrs
[] = {
5569 .pa_start
= 0x4a30a000,
5570 .pa_end
= 0x4a30a7ff,
5571 .flags
= ADDR_TYPE_RT
5576 /* l4_wkup -> scrm */
5577 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__scrm
= {
5578 .master
= &omap44xx_l4_wkup_hwmod
,
5579 .slave
= &omap44xx_scrm_hwmod
,
5580 .clk
= "l4_wkup_clk_mux_ck",
5581 .addr
= omap44xx_scrm_addrs
,
5582 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5585 /* l3_main_2 -> sl2if */
5586 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l3_main_2__sl2if
= {
5587 .master
= &omap44xx_l3_main_2_hwmod
,
5588 .slave
= &omap44xx_sl2if_hwmod
,
5590 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5593 static struct omap_hwmod_addr_space omap44xx_slimbus1_addrs
[] = {
5595 .pa_start
= 0x4012c000,
5596 .pa_end
= 0x4012c3ff,
5597 .flags
= ADDR_TYPE_RT
5602 /* l4_abe -> slimbus1 */
5603 static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1
= {
5604 .master
= &omap44xx_l4_abe_hwmod
,
5605 .slave
= &omap44xx_slimbus1_hwmod
,
5606 .clk
= "ocp_abe_iclk",
5607 .addr
= omap44xx_slimbus1_addrs
,
5608 .user
= OCP_USER_MPU
,
5611 static struct omap_hwmod_addr_space omap44xx_slimbus1_dma_addrs
[] = {
5613 .pa_start
= 0x4902c000,
5614 .pa_end
= 0x4902c3ff,
5615 .flags
= ADDR_TYPE_RT
5620 /* l4_abe -> slimbus1 (dma) */
5621 static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1_dma
= {
5622 .master
= &omap44xx_l4_abe_hwmod
,
5623 .slave
= &omap44xx_slimbus1_hwmod
,
5624 .clk
= "ocp_abe_iclk",
5625 .addr
= omap44xx_slimbus1_dma_addrs
,
5626 .user
= OCP_USER_SDMA
,
5629 static struct omap_hwmod_addr_space omap44xx_slimbus2_addrs
[] = {
5631 .pa_start
= 0x48076000,
5632 .pa_end
= 0x480763ff,
5633 .flags
= ADDR_TYPE_RT
5638 /* l4_per -> slimbus2 */
5639 static struct omap_hwmod_ocp_if omap44xx_l4_per__slimbus2
= {
5640 .master
= &omap44xx_l4_per_hwmod
,
5641 .slave
= &omap44xx_slimbus2_hwmod
,
5643 .addr
= omap44xx_slimbus2_addrs
,
5644 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5647 static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs
[] = {
5649 .pa_start
= 0x4a0dd000,
5650 .pa_end
= 0x4a0dd03f,
5651 .flags
= ADDR_TYPE_RT
5656 /* l4_cfg -> smartreflex_core */
5657 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core
= {
5658 .master
= &omap44xx_l4_cfg_hwmod
,
5659 .slave
= &omap44xx_smartreflex_core_hwmod
,
5661 .addr
= omap44xx_smartreflex_core_addrs
,
5662 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5665 static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs
[] = {
5667 .pa_start
= 0x4a0db000,
5668 .pa_end
= 0x4a0db03f,
5669 .flags
= ADDR_TYPE_RT
5674 /* l4_cfg -> smartreflex_iva */
5675 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva
= {
5676 .master
= &omap44xx_l4_cfg_hwmod
,
5677 .slave
= &omap44xx_smartreflex_iva_hwmod
,
5679 .addr
= omap44xx_smartreflex_iva_addrs
,
5680 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5683 static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs
[] = {
5685 .pa_start
= 0x4a0d9000,
5686 .pa_end
= 0x4a0d903f,
5687 .flags
= ADDR_TYPE_RT
5692 /* l4_cfg -> smartreflex_mpu */
5693 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu
= {
5694 .master
= &omap44xx_l4_cfg_hwmod
,
5695 .slave
= &omap44xx_smartreflex_mpu_hwmod
,
5697 .addr
= omap44xx_smartreflex_mpu_addrs
,
5698 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5701 static struct omap_hwmod_addr_space omap44xx_spinlock_addrs
[] = {
5703 .pa_start
= 0x4a0f6000,
5704 .pa_end
= 0x4a0f6fff,
5705 .flags
= ADDR_TYPE_RT
5710 /* l4_cfg -> spinlock */
5711 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock
= {
5712 .master
= &omap44xx_l4_cfg_hwmod
,
5713 .slave
= &omap44xx_spinlock_hwmod
,
5715 .addr
= omap44xx_spinlock_addrs
,
5716 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5719 static struct omap_hwmod_addr_space omap44xx_timer1_addrs
[] = {
5721 .pa_start
= 0x4a318000,
5722 .pa_end
= 0x4a31807f,
5723 .flags
= ADDR_TYPE_RT
5728 /* l4_wkup -> timer1 */
5729 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1
= {
5730 .master
= &omap44xx_l4_wkup_hwmod
,
5731 .slave
= &omap44xx_timer1_hwmod
,
5732 .clk
= "l4_wkup_clk_mux_ck",
5733 .addr
= omap44xx_timer1_addrs
,
5734 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5737 static struct omap_hwmod_addr_space omap44xx_timer2_addrs
[] = {
5739 .pa_start
= 0x48032000,
5740 .pa_end
= 0x4803207f,
5741 .flags
= ADDR_TYPE_RT
5746 /* l4_per -> timer2 */
5747 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2
= {
5748 .master
= &omap44xx_l4_per_hwmod
,
5749 .slave
= &omap44xx_timer2_hwmod
,
5751 .addr
= omap44xx_timer2_addrs
,
5752 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5755 static struct omap_hwmod_addr_space omap44xx_timer3_addrs
[] = {
5757 .pa_start
= 0x48034000,
5758 .pa_end
= 0x4803407f,
5759 .flags
= ADDR_TYPE_RT
5764 /* l4_per -> timer3 */
5765 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3
= {
5766 .master
= &omap44xx_l4_per_hwmod
,
5767 .slave
= &omap44xx_timer3_hwmod
,
5769 .addr
= omap44xx_timer3_addrs
,
5770 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5773 static struct omap_hwmod_addr_space omap44xx_timer4_addrs
[] = {
5775 .pa_start
= 0x48036000,
5776 .pa_end
= 0x4803607f,
5777 .flags
= ADDR_TYPE_RT
5782 /* l4_per -> timer4 */
5783 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4
= {
5784 .master
= &omap44xx_l4_per_hwmod
,
5785 .slave
= &omap44xx_timer4_hwmod
,
5787 .addr
= omap44xx_timer4_addrs
,
5788 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5791 static struct omap_hwmod_addr_space omap44xx_timer5_addrs
[] = {
5793 .pa_start
= 0x40138000,
5794 .pa_end
= 0x4013807f,
5795 .flags
= ADDR_TYPE_RT
5800 /* l4_abe -> timer5 */
5801 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5
= {
5802 .master
= &omap44xx_l4_abe_hwmod
,
5803 .slave
= &omap44xx_timer5_hwmod
,
5804 .clk
= "ocp_abe_iclk",
5805 .addr
= omap44xx_timer5_addrs
,
5806 .user
= OCP_USER_MPU
,
5809 static struct omap_hwmod_addr_space omap44xx_timer5_dma_addrs
[] = {
5811 .pa_start
= 0x49038000,
5812 .pa_end
= 0x4903807f,
5813 .flags
= ADDR_TYPE_RT
5818 /* l4_abe -> timer5 (dma) */
5819 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma
= {
5820 .master
= &omap44xx_l4_abe_hwmod
,
5821 .slave
= &omap44xx_timer5_hwmod
,
5822 .clk
= "ocp_abe_iclk",
5823 .addr
= omap44xx_timer5_dma_addrs
,
5824 .user
= OCP_USER_SDMA
,
5827 static struct omap_hwmod_addr_space omap44xx_timer6_addrs
[] = {
5829 .pa_start
= 0x4013a000,
5830 .pa_end
= 0x4013a07f,
5831 .flags
= ADDR_TYPE_RT
5836 /* l4_abe -> timer6 */
5837 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6
= {
5838 .master
= &omap44xx_l4_abe_hwmod
,
5839 .slave
= &omap44xx_timer6_hwmod
,
5840 .clk
= "ocp_abe_iclk",
5841 .addr
= omap44xx_timer6_addrs
,
5842 .user
= OCP_USER_MPU
,
5845 static struct omap_hwmod_addr_space omap44xx_timer6_dma_addrs
[] = {
5847 .pa_start
= 0x4903a000,
5848 .pa_end
= 0x4903a07f,
5849 .flags
= ADDR_TYPE_RT
5854 /* l4_abe -> timer6 (dma) */
5855 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma
= {
5856 .master
= &omap44xx_l4_abe_hwmod
,
5857 .slave
= &omap44xx_timer6_hwmod
,
5858 .clk
= "ocp_abe_iclk",
5859 .addr
= omap44xx_timer6_dma_addrs
,
5860 .user
= OCP_USER_SDMA
,
5863 static struct omap_hwmod_addr_space omap44xx_timer7_addrs
[] = {
5865 .pa_start
= 0x4013c000,
5866 .pa_end
= 0x4013c07f,
5867 .flags
= ADDR_TYPE_RT
5872 /* l4_abe -> timer7 */
5873 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7
= {
5874 .master
= &omap44xx_l4_abe_hwmod
,
5875 .slave
= &omap44xx_timer7_hwmod
,
5876 .clk
= "ocp_abe_iclk",
5877 .addr
= omap44xx_timer7_addrs
,
5878 .user
= OCP_USER_MPU
,
5881 static struct omap_hwmod_addr_space omap44xx_timer7_dma_addrs
[] = {
5883 .pa_start
= 0x4903c000,
5884 .pa_end
= 0x4903c07f,
5885 .flags
= ADDR_TYPE_RT
5890 /* l4_abe -> timer7 (dma) */
5891 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma
= {
5892 .master
= &omap44xx_l4_abe_hwmod
,
5893 .slave
= &omap44xx_timer7_hwmod
,
5894 .clk
= "ocp_abe_iclk",
5895 .addr
= omap44xx_timer7_dma_addrs
,
5896 .user
= OCP_USER_SDMA
,
5899 static struct omap_hwmod_addr_space omap44xx_timer8_addrs
[] = {
5901 .pa_start
= 0x4013e000,
5902 .pa_end
= 0x4013e07f,
5903 .flags
= ADDR_TYPE_RT
5908 /* l4_abe -> timer8 */
5909 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8
= {
5910 .master
= &omap44xx_l4_abe_hwmod
,
5911 .slave
= &omap44xx_timer8_hwmod
,
5912 .clk
= "ocp_abe_iclk",
5913 .addr
= omap44xx_timer8_addrs
,
5914 .user
= OCP_USER_MPU
,
5917 static struct omap_hwmod_addr_space omap44xx_timer8_dma_addrs
[] = {
5919 .pa_start
= 0x4903e000,
5920 .pa_end
= 0x4903e07f,
5921 .flags
= ADDR_TYPE_RT
5926 /* l4_abe -> timer8 (dma) */
5927 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma
= {
5928 .master
= &omap44xx_l4_abe_hwmod
,
5929 .slave
= &omap44xx_timer8_hwmod
,
5930 .clk
= "ocp_abe_iclk",
5931 .addr
= omap44xx_timer8_dma_addrs
,
5932 .user
= OCP_USER_SDMA
,
5935 static struct omap_hwmod_addr_space omap44xx_timer9_addrs
[] = {
5937 .pa_start
= 0x4803e000,
5938 .pa_end
= 0x4803e07f,
5939 .flags
= ADDR_TYPE_RT
5944 /* l4_per -> timer9 */
5945 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9
= {
5946 .master
= &omap44xx_l4_per_hwmod
,
5947 .slave
= &omap44xx_timer9_hwmod
,
5949 .addr
= omap44xx_timer9_addrs
,
5950 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5953 static struct omap_hwmod_addr_space omap44xx_timer10_addrs
[] = {
5955 .pa_start
= 0x48086000,
5956 .pa_end
= 0x4808607f,
5957 .flags
= ADDR_TYPE_RT
5962 /* l4_per -> timer10 */
5963 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10
= {
5964 .master
= &omap44xx_l4_per_hwmod
,
5965 .slave
= &omap44xx_timer10_hwmod
,
5967 .addr
= omap44xx_timer10_addrs
,
5968 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5971 static struct omap_hwmod_addr_space omap44xx_timer11_addrs
[] = {
5973 .pa_start
= 0x48088000,
5974 .pa_end
= 0x4808807f,
5975 .flags
= ADDR_TYPE_RT
5980 /* l4_per -> timer11 */
5981 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11
= {
5982 .master
= &omap44xx_l4_per_hwmod
,
5983 .slave
= &omap44xx_timer11_hwmod
,
5985 .addr
= omap44xx_timer11_addrs
,
5986 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5989 static struct omap_hwmod_addr_space omap44xx_uart1_addrs
[] = {
5991 .pa_start
= 0x4806a000,
5992 .pa_end
= 0x4806a0ff,
5993 .flags
= ADDR_TYPE_RT
5998 /* l4_per -> uart1 */
5999 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1
= {
6000 .master
= &omap44xx_l4_per_hwmod
,
6001 .slave
= &omap44xx_uart1_hwmod
,
6003 .addr
= omap44xx_uart1_addrs
,
6004 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
6007 static struct omap_hwmod_addr_space omap44xx_uart2_addrs
[] = {
6009 .pa_start
= 0x4806c000,
6010 .pa_end
= 0x4806c0ff,
6011 .flags
= ADDR_TYPE_RT
6016 /* l4_per -> uart2 */
6017 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2
= {
6018 .master
= &omap44xx_l4_per_hwmod
,
6019 .slave
= &omap44xx_uart2_hwmod
,
6021 .addr
= omap44xx_uart2_addrs
,
6022 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
6025 static struct omap_hwmod_addr_space omap44xx_uart3_addrs
[] = {
6027 .pa_start
= 0x48020000,
6028 .pa_end
= 0x480200ff,
6029 .flags
= ADDR_TYPE_RT
6034 /* l4_per -> uart3 */
6035 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3
= {
6036 .master
= &omap44xx_l4_per_hwmod
,
6037 .slave
= &omap44xx_uart3_hwmod
,
6039 .addr
= omap44xx_uart3_addrs
,
6040 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
6043 static struct omap_hwmod_addr_space omap44xx_uart4_addrs
[] = {
6045 .pa_start
= 0x4806e000,
6046 .pa_end
= 0x4806e0ff,
6047 .flags
= ADDR_TYPE_RT
6052 /* l4_per -> uart4 */
6053 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4
= {
6054 .master
= &omap44xx_l4_per_hwmod
,
6055 .slave
= &omap44xx_uart4_hwmod
,
6057 .addr
= omap44xx_uart4_addrs
,
6058 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
6061 static struct omap_hwmod_addr_space omap44xx_usb_host_fs_addrs
[] = {
6063 .pa_start
= 0x4a0a9000,
6064 .pa_end
= 0x4a0a93ff,
6065 .flags
= ADDR_TYPE_RT
6070 /* l4_cfg -> usb_host_fs */
6071 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_cfg__usb_host_fs
= {
6072 .master
= &omap44xx_l4_cfg_hwmod
,
6073 .slave
= &omap44xx_usb_host_fs_hwmod
,
6075 .addr
= omap44xx_usb_host_fs_addrs
,
6076 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
6079 static struct omap_hwmod_addr_space omap44xx_usb_host_hs_addrs
[] = {
6082 .pa_start
= 0x4a064000,
6083 .pa_end
= 0x4a0647ff,
6084 .flags
= ADDR_TYPE_RT
6088 .pa_start
= 0x4a064800,
6089 .pa_end
= 0x4a064bff,
6093 .pa_start
= 0x4a064c00,
6094 .pa_end
= 0x4a064fff,
6099 /* l4_cfg -> usb_host_hs */
6100 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs
= {
6101 .master
= &omap44xx_l4_cfg_hwmod
,
6102 .slave
= &omap44xx_usb_host_hs_hwmod
,
6104 .addr
= omap44xx_usb_host_hs_addrs
,
6105 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
6108 static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs
[] = {
6110 .pa_start
= 0x4a0ab000,
6111 .pa_end
= 0x4a0ab7ff,
6112 .flags
= ADDR_TYPE_RT
6115 /* XXX: Remove this once control module driver is in place */
6116 .pa_start
= 0x4a00233c,
6117 .pa_end
= 0x4a00233f,
6118 .flags
= ADDR_TYPE_RT
6123 /* l4_cfg -> usb_otg_hs */
6124 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs
= {
6125 .master
= &omap44xx_l4_cfg_hwmod
,
6126 .slave
= &omap44xx_usb_otg_hs_hwmod
,
6128 .addr
= omap44xx_usb_otg_hs_addrs
,
6129 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
6132 static struct omap_hwmod_addr_space omap44xx_usb_tll_hs_addrs
[] = {
6135 .pa_start
= 0x4a062000,
6136 .pa_end
= 0x4a063fff,
6137 .flags
= ADDR_TYPE_RT
6142 /* l4_cfg -> usb_tll_hs */
6143 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_tll_hs
= {
6144 .master
= &omap44xx_l4_cfg_hwmod
,
6145 .slave
= &omap44xx_usb_tll_hs_hwmod
,
6147 .addr
= omap44xx_usb_tll_hs_addrs
,
6148 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
6151 static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs
[] = {
6153 .pa_start
= 0x4a314000,
6154 .pa_end
= 0x4a31407f,
6155 .flags
= ADDR_TYPE_RT
6160 /* l4_wkup -> wd_timer2 */
6161 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2
= {
6162 .master
= &omap44xx_l4_wkup_hwmod
,
6163 .slave
= &omap44xx_wd_timer2_hwmod
,
6164 .clk
= "l4_wkup_clk_mux_ck",
6165 .addr
= omap44xx_wd_timer2_addrs
,
6166 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
6169 static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs
[] = {
6171 .pa_start
= 0x40130000,
6172 .pa_end
= 0x4013007f,
6173 .flags
= ADDR_TYPE_RT
6178 /* l4_abe -> wd_timer3 */
6179 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3
= {
6180 .master
= &omap44xx_l4_abe_hwmod
,
6181 .slave
= &omap44xx_wd_timer3_hwmod
,
6182 .clk
= "ocp_abe_iclk",
6183 .addr
= omap44xx_wd_timer3_addrs
,
6184 .user
= OCP_USER_MPU
,
6187 static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs
[] = {
6189 .pa_start
= 0x49030000,
6190 .pa_end
= 0x4903007f,
6191 .flags
= ADDR_TYPE_RT
6196 /* l4_abe -> wd_timer3 (dma) */
6197 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma
= {
6198 .master
= &omap44xx_l4_abe_hwmod
,
6199 .slave
= &omap44xx_wd_timer3_hwmod
,
6200 .clk
= "ocp_abe_iclk",
6201 .addr
= omap44xx_wd_timer3_dma_addrs
,
6202 .user
= OCP_USER_SDMA
,
6205 static struct omap_hwmod_ocp_if
*omap44xx_hwmod_ocp_ifs
[] __initdata
= {
6206 &omap44xx_c2c__c2c_target_fw
,
6207 &omap44xx_l4_cfg__c2c_target_fw
,
6208 &omap44xx_l3_main_1__dmm
,
6210 &omap44xx_c2c__emif_fw
,
6211 &omap44xx_dmm__emif_fw
,
6212 &omap44xx_l4_cfg__emif_fw
,
6213 &omap44xx_iva__l3_instr
,
6214 &omap44xx_l3_main_3__l3_instr
,
6215 &omap44xx_ocp_wp_noc__l3_instr
,
6216 &omap44xx_dsp__l3_main_1
,
6217 &omap44xx_dss__l3_main_1
,
6218 &omap44xx_l3_main_2__l3_main_1
,
6219 &omap44xx_l4_cfg__l3_main_1
,
6220 &omap44xx_mmc1__l3_main_1
,
6221 &omap44xx_mmc2__l3_main_1
,
6222 &omap44xx_mpu__l3_main_1
,
6223 &omap44xx_c2c_target_fw__l3_main_2
,
6224 &omap44xx_debugss__l3_main_2
,
6225 &omap44xx_dma_system__l3_main_2
,
6226 &omap44xx_fdif__l3_main_2
,
6227 &omap44xx_gpu__l3_main_2
,
6228 &omap44xx_hsi__l3_main_2
,
6229 &omap44xx_ipu__l3_main_2
,
6230 &omap44xx_iss__l3_main_2
,
6231 &omap44xx_iva__l3_main_2
,
6232 &omap44xx_l3_main_1__l3_main_2
,
6233 &omap44xx_l4_cfg__l3_main_2
,
6234 /* &omap44xx_usb_host_fs__l3_main_2, */
6235 &omap44xx_usb_host_hs__l3_main_2
,
6236 &omap44xx_usb_otg_hs__l3_main_2
,
6237 &omap44xx_l3_main_1__l3_main_3
,
6238 &omap44xx_l3_main_2__l3_main_3
,
6239 &omap44xx_l4_cfg__l3_main_3
,
6240 /* &omap44xx_aess__l4_abe, */
6241 &omap44xx_dsp__l4_abe
,
6242 &omap44xx_l3_main_1__l4_abe
,
6243 &omap44xx_mpu__l4_abe
,
6244 &omap44xx_l3_main_1__l4_cfg
,
6245 &omap44xx_l3_main_2__l4_per
,
6246 &omap44xx_l4_cfg__l4_wkup
,
6247 &omap44xx_mpu__mpu_private
,
6248 &omap44xx_l4_cfg__ocp_wp_noc
,
6249 /* &omap44xx_l4_abe__aess, */
6250 /* &omap44xx_l4_abe__aess_dma, */
6251 &omap44xx_l3_main_2__c2c
,
6252 &omap44xx_l4_wkup__counter_32k
,
6253 &omap44xx_l4_cfg__ctrl_module_core
,
6254 &omap44xx_l4_cfg__ctrl_module_pad_core
,
6255 &omap44xx_l4_wkup__ctrl_module_wkup
,
6256 &omap44xx_l4_wkup__ctrl_module_pad_wkup
,
6257 &omap44xx_l3_instr__debugss
,
6258 &omap44xx_l4_cfg__dma_system
,
6259 &omap44xx_l4_abe__dmic
,
6260 &omap44xx_l4_abe__dmic_dma
,
6262 /* &omap44xx_dsp__sl2if, */
6263 &omap44xx_l4_cfg__dsp
,
6264 &omap44xx_l3_main_2__dss
,
6265 &omap44xx_l4_per__dss
,
6266 &omap44xx_l3_main_2__dss_dispc
,
6267 &omap44xx_l4_per__dss_dispc
,
6268 &omap44xx_l3_main_2__dss_dsi1
,
6269 &omap44xx_l4_per__dss_dsi1
,
6270 &omap44xx_l3_main_2__dss_dsi2
,
6271 &omap44xx_l4_per__dss_dsi2
,
6272 &omap44xx_l3_main_2__dss_hdmi
,
6273 &omap44xx_l4_per__dss_hdmi
,
6274 &omap44xx_l3_main_2__dss_rfbi
,
6275 &omap44xx_l4_per__dss_rfbi
,
6276 &omap44xx_l3_main_2__dss_venc
,
6277 &omap44xx_l4_per__dss_venc
,
6278 &omap44xx_l4_per__elm
,
6279 &omap44xx_emif_fw__emif1
,
6280 &omap44xx_emif_fw__emif2
,
6281 &omap44xx_l4_cfg__fdif
,
6282 &omap44xx_l4_wkup__gpio1
,
6283 &omap44xx_l4_per__gpio2
,
6284 &omap44xx_l4_per__gpio3
,
6285 &omap44xx_l4_per__gpio4
,
6286 &omap44xx_l4_per__gpio5
,
6287 &omap44xx_l4_per__gpio6
,
6288 &omap44xx_l3_main_2__gpmc
,
6289 &omap44xx_l3_main_2__gpu
,
6290 &omap44xx_l4_per__hdq1w
,
6291 &omap44xx_l4_cfg__hsi
,
6292 &omap44xx_l4_per__i2c1
,
6293 &omap44xx_l4_per__i2c2
,
6294 &omap44xx_l4_per__i2c3
,
6295 &omap44xx_l4_per__i2c4
,
6296 &omap44xx_l3_main_2__ipu
,
6297 &omap44xx_l3_main_2__iss
,
6298 /* &omap44xx_iva__sl2if, */
6299 &omap44xx_l3_main_2__iva
,
6300 &omap44xx_l4_wkup__kbd
,
6301 &omap44xx_l4_cfg__mailbox
,
6302 &omap44xx_l4_abe__mcasp
,
6303 &omap44xx_l4_abe__mcasp_dma
,
6304 &omap44xx_l4_abe__mcbsp1
,
6305 &omap44xx_l4_abe__mcbsp1_dma
,
6306 &omap44xx_l4_abe__mcbsp2
,
6307 &omap44xx_l4_abe__mcbsp2_dma
,
6308 &omap44xx_l4_abe__mcbsp3
,
6309 &omap44xx_l4_abe__mcbsp3_dma
,
6310 &omap44xx_l4_per__mcbsp4
,
6311 &omap44xx_l4_abe__mcpdm
,
6312 &omap44xx_l4_abe__mcpdm_dma
,
6313 &omap44xx_l4_per__mcspi1
,
6314 &omap44xx_l4_per__mcspi2
,
6315 &omap44xx_l4_per__mcspi3
,
6316 &omap44xx_l4_per__mcspi4
,
6317 &omap44xx_l4_per__mmc1
,
6318 &omap44xx_l4_per__mmc2
,
6319 &omap44xx_l4_per__mmc3
,
6320 &omap44xx_l4_per__mmc4
,
6321 &omap44xx_l4_per__mmc5
,
6322 &omap44xx_l3_main_2__mmu_ipu
,
6323 &omap44xx_l4_cfg__mmu_dsp
,
6324 &omap44xx_l3_main_2__ocmc_ram
,
6325 &omap44xx_l4_cfg__ocp2scp_usb_phy
,
6326 &omap44xx_mpu_private__prcm_mpu
,
6327 &omap44xx_l4_wkup__cm_core_aon
,
6328 &omap44xx_l4_cfg__cm_core
,
6329 &omap44xx_l4_wkup__prm
,
6330 &omap44xx_l4_wkup__scrm
,
6331 /* &omap44xx_l3_main_2__sl2if, */
6332 &omap44xx_l4_abe__slimbus1
,
6333 &omap44xx_l4_abe__slimbus1_dma
,
6334 &omap44xx_l4_per__slimbus2
,
6335 &omap44xx_l4_cfg__smartreflex_core
,
6336 &omap44xx_l4_cfg__smartreflex_iva
,
6337 &omap44xx_l4_cfg__smartreflex_mpu
,
6338 &omap44xx_l4_cfg__spinlock
,
6339 &omap44xx_l4_wkup__timer1
,
6340 &omap44xx_l4_per__timer2
,
6341 &omap44xx_l4_per__timer3
,
6342 &omap44xx_l4_per__timer4
,
6343 &omap44xx_l4_abe__timer5
,
6344 &omap44xx_l4_abe__timer5_dma
,
6345 &omap44xx_l4_abe__timer6
,
6346 &omap44xx_l4_abe__timer6_dma
,
6347 &omap44xx_l4_abe__timer7
,
6348 &omap44xx_l4_abe__timer7_dma
,
6349 &omap44xx_l4_abe__timer8
,
6350 &omap44xx_l4_abe__timer8_dma
,
6351 &omap44xx_l4_per__timer9
,
6352 &omap44xx_l4_per__timer10
,
6353 &omap44xx_l4_per__timer11
,
6354 &omap44xx_l4_per__uart1
,
6355 &omap44xx_l4_per__uart2
,
6356 &omap44xx_l4_per__uart3
,
6357 &omap44xx_l4_per__uart4
,
6358 /* &omap44xx_l4_cfg__usb_host_fs, */
6359 &omap44xx_l4_cfg__usb_host_hs
,
6360 &omap44xx_l4_cfg__usb_otg_hs
,
6361 &omap44xx_l4_cfg__usb_tll_hs
,
6362 &omap44xx_l4_wkup__wd_timer2
,
6363 &omap44xx_l4_abe__wd_timer3
,
6364 &omap44xx_l4_abe__wd_timer3_dma
,
6368 int __init
omap44xx_hwmod_init(void)
6371 return omap_hwmod_register_links(omap44xx_hwmod_ocp_ifs
);