include/asm-x86/cpufeature.h

   1 /*
   2  * Defines x86 CPU feature bits
   3  */
   4 #ifndef _ASM_X86_CPUFEATURE_H
   5 #define _ASM_X86_CPUFEATURE_H
   6
   7 #ifndef __ASSEMBLY__
   8 #include <linux/bitops.h>
   9 #endif
  10 #include <asm/required-features.h>
  11
  12 #define NCAPINTS        8       /* N 32-bit words worth of info */
  13
  14 /* Intel-defined CPU features, CPUID level 0x00000001 (edx), word 0 */
  15 #define X86_FEATURE_FPU         (0*32+ 0) /* Onboard FPU */
  16 #define X86_FEATURE_VME         (0*32+ 1) /* Virtual Mode Extensions */
  17 #define X86_FEATURE_DE          (0*32+ 2) /* Debugging Extensions */
  18 #define X86_FEATURE_PSE         (0*32+ 3) /* Page Size Extensions */
  19 #define X86_FEATURE_TSC         (0*32+ 4) /* Time Stamp Counter */
  20 #define X86_FEATURE_MSR         (0*32+ 5) /* Model-Specific Registers, RDMSR, WRMSR */
  21 #define X86_FEATURE_PAE         (0*32+ 6) /* Physical Address Extensions */
  22 #define X86_FEATURE_MCE         (0*32+ 7) /* Machine Check Architecture */
  23 #define X86_FEATURE_CX8         (0*32+ 8) /* CMPXCHG8 instruction */
  24 #define X86_FEATURE_APIC        (0*32+ 9) /* Onboard APIC */
  25 #define X86_FEATURE_SEP         (0*32+11) /* SYSENTER/SYSEXIT */
  26 #define X86_FEATURE_MTRR        (0*32+12) /* Memory Type Range Registers */
  27 #define X86_FEATURE_PGE         (0*32+13) /* Page Global Enable */
  28 #define X86_FEATURE_MCA         (0*32+14) /* Machine Check Architecture */
  29 #define X86_FEATURE_CMOV        (0*32+15) /* CMOV instruction (FCMOVCC and FCOMI too if FPU present) */
  30 #define X86_FEATURE_PAT         (0*32+16) /* Page Attribute Table */
  31 #define X86_FEATURE_PSE36       (0*32+17) /* 36-bit PSEs */
  32 #define X86_FEATURE_PN          (0*32+18) /* Processor serial number */
  33 #define X86_FEATURE_CLFLSH      (0*32+19) /* Supports the CLFLUSH instruction */
  34 #define X86_FEATURE_DS          (0*32+21) /* Debug Store */
  35 #define X86_FEATURE_ACPI        (0*32+22) /* ACPI via MSR */
  36 #define X86_FEATURE_MMX         (0*32+23) /* Multimedia Extensions */
  37 #define X86_FEATURE_FXSR        (0*32+24) /* FXSAVE and FXRSTOR instructions (fast save and restore */
  38                                           /* of FPU context), and CR4.OSFXSR available */
  39 #define X86_FEATURE_XMM         (0*32+25) /* Streaming SIMD Extensions */
  40 #define X86_FEATURE_XMM2        (0*32+26) /* Streaming SIMD Extensions-2 */
  41 #define X86_FEATURE_SELFSNOOP   (0*32+27) /* CPU self snoop */
  42 #define X86_FEATURE_HT          (0*32+28) /* Hyper-Threading */
  43 #define X86_FEATURE_ACC         (0*32+29) /* Automatic clock control */
  44 #define X86_FEATURE_IA64        (0*32+30) /* IA-64 processor */
  45
  46 /* AMD-defined CPU features, CPUID level 0x80000001, word 1 */
  47 /* Don't duplicate feature flags which are redundant with Intel! */
  48 #define X86_FEATURE_SYSCALL     (1*32+11) /* SYSCALL/SYSRET */
  49 #define X86_FEATURE_MP          (1*32+19) /* MP Capable. */
  50 #define X86_FEATURE_NX          (1*32+20) /* Execute Disable */
  51 #define X86_FEATURE_MMXEXT      (1*32+22) /* AMD MMX extensions */
  52 #define X86_FEATURE_RDTSCP      (1*32+27) /* RDTSCP */
  53 #define X86_FEATURE_LM          (1*32+29) /* Long Mode (x86-64) */
  54 #define X86_FEATURE_3DNOWEXT    (1*32+30) /* AMD 3DNow! extensions */
  55 #define X86_FEATURE_3DNOW       (1*32+31) /* 3DNow! */
  56
  57 /* Transmeta-defined CPU features, CPUID level 0x80860001, word 2 */
  58 #define X86_FEATURE_RECOVERY    (2*32+ 0) /* CPU in recovery mode */
  59 #define X86_FEATURE_LONGRUN     (2*32+ 1) /* Longrun power control */
  60 #define X86_FEATURE_LRTI        (2*32+ 3) /* LongRun table interface */
  61
  62 /* Other features, Linux-defined mapping, word 3 */
  63 /* This range is used for feature bits which conflict or are synthesized */
  64 #define X86_FEATURE_CXMMX       (3*32+ 0) /* Cyrix MMX extensions */
  65 #define X86_FEATURE_K6_MTRR     (3*32+ 1) /* AMD K6 nonstandard MTRRs */
  66 #define X86_FEATURE_CYRIX_ARR   (3*32+ 2) /* Cyrix ARRs (= MTRRs) */
  67 #define X86_FEATURE_CENTAUR_MCR (3*32+ 3) /* Centaur MCRs (= MTRRs) */
  68 /* cpu types for specific tunings: */
  69 #define X86_FEATURE_K8          (3*32+ 4) /* Opteron, Athlon64 */
  70 #define X86_FEATURE_K7          (3*32+ 5) /* Athlon */
  71 #define X86_FEATURE_P3          (3*32+ 6) /* P3 */
  72 #define X86_FEATURE_P4          (3*32+ 7) /* P4 */
  73 #define X86_FEATURE_CONSTANT_TSC (3*32+ 8) /* TSC ticks at a constant rate */
  74 #define X86_FEATURE_UP          (3*32+ 9) /* smp kernel running on up */
  75 #define X86_FEATURE_FXSAVE_LEAK (3*32+10) /* FXSAVE leaks FOP/FIP/FOP */
  76 #define X86_FEATURE_ARCH_PERFMON (3*32+11) /* Intel Architectural PerfMon */
  77 #define X86_FEATURE_PEBS        (3*32+12)  /* Precise-Event Based Sampling */
  78 #define X86_FEATURE_BTS         (3*32+13)  /* Branch Trace Store */
  79 /* 14 free */
  80 /* 15 free */
  81 #define X86_FEATURE_REP_GOOD    (3*32+16) /* rep microcode works well on this CPU */
  82 #define X86_FEATURE_MFENCE_RDTSC (3*32+17) /* Mfence synchronizes RDTSC */
  83 #define X86_FEATURE_LFENCE_RDTSC (3*32+18) /* Lfence synchronizes RDTSC */
  84
  85 /* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */
  86 #define X86_FEATURE_XMM3        (4*32+ 0) /* Streaming SIMD Extensions-3 */
  87 #define X86_FEATURE_MWAIT       (4*32+ 3) /* Monitor/Mwait support */
  88 #define X86_FEATURE_DSCPL       (4*32+ 4) /* CPL Qualified Debug Store */
  89 #define X86_FEATURE_EST         (4*32+ 7) /* Enhanced SpeedStep */
  90 #define X86_FEATURE_TM2         (4*32+ 8) /* Thermal Monitor 2 */
  91 #define X86_FEATURE_CID         (4*32+10) /* Context ID */
  92 #define X86_FEATURE_CX16        (4*32+13) /* CMPXCHG16B */
  93 #define X86_FEATURE_XTPR        (4*32+14) /* Send Task Priority Messages */
  94 #define X86_FEATURE_DCA         (4*32+18) /* Direct Cache Access */
  95
  96 /* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */
  97 #define X86_FEATURE_XSTORE      (5*32+ 2) /* on-CPU RNG present (xstore insn) */
  98 #define X86_FEATURE_XSTORE_EN   (5*32+ 3) /* on-CPU RNG enabled */
  99 #define X86_FEATURE_XCRYPT      (5*32+ 6) /* on-CPU crypto (xcrypt insn) */
 100 #define X86_FEATURE_XCRYPT_EN   (5*32+ 7) /* on-CPU crypto enabled */
 101 #define X86_FEATURE_ACE2        (5*32+ 8) /* Advanced Cryptography Engine v2 */
 102 #define X86_FEATURE_ACE2_EN     (5*32+ 9) /* ACE v2 enabled */
 103 #define X86_FEATURE_PHE         (5*32+ 10) /* PadLock Hash Engine */
 104 #define X86_FEATURE_PHE_EN      (5*32+ 11) /* PHE enabled */
 105 #define X86_FEATURE_PMM         (5*32+ 12) /* PadLock Montgomery Multiplier */
 106 #define X86_FEATURE_PMM_EN      (5*32+ 13) /* PMM enabled */
 107
 108 /* More extended AMD flags: CPUID level 0x80000001, ecx, word 6 */
 109 #define X86_FEATURE_LAHF_LM     (6*32+ 0) /* LAHF/SAHF in long mode */
 110 #define X86_FEATURE_CMP_LEGACY  (6*32+ 1) /* If yes HyperThreading not valid */
 111
 112 /*
 113  * Auxiliary flags: Linux defined - For features scattered in various
 114  * CPUID levels like 0x6, 0xA etc
 115  */
 116 #define X86_FEATURE_IDA         (7*32+ 0) /* Intel Dynamic Acceleration */
 117
 118 #define cpu_has(c, bit)                                                 \
 119         (__builtin_constant_p(bit) &&                                   \
 120          ( (((bit)>>5)==0 && (1UL<<((bit)&31) & REQUIRED_MASK0)) ||     \
 121            (((bit)>>5)==1 && (1UL<<((bit)&31) & REQUIRED_MASK1)) ||     \
 122            (((bit)>>5)==2 && (1UL<<((bit)&31) & REQUIRED_MASK2)) ||     \
 123            (((bit)>>5)==3 && (1UL<<((bit)&31) & REQUIRED_MASK3)) ||     \
 124            (((bit)>>5)==4 && (1UL<<((bit)&31) & REQUIRED_MASK4)) ||     \
 125            (((bit)>>5)==5 && (1UL<<((bit)&31) & REQUIRED_MASK5)) ||     \
 126            (((bit)>>5)==6 && (1UL<<((bit)&31) & REQUIRED_MASK6)) ||     \
 127            (((bit)>>5)==7 && (1UL<<((bit)&31) & REQUIRED_MASK7)) )      \
 128           ? 1 :                                                         \
 129          test_bit(bit, (unsigned long *)((c)->x86_capability)))
 130 #define boot_cpu_has(bit)       cpu_has(&boot_cpu_data, bit)
 131
 132 #define set_cpu_cap(c, bit)     set_bit(bit, (unsigned long *)((c)->x86_capability))
 133 #define clear_cpu_cap(c, bit)   clear_bit(bit, (unsigned long *)((c)->x86_capability))
 134
 135 #define cpu_has_fpu             boot_cpu_has(X86_FEATURE_FPU)
 136 #define cpu_has_vme             boot_cpu_has(X86_FEATURE_VME)
 137 #define cpu_has_de              boot_cpu_has(X86_FEATURE_DE)
 138 #define cpu_has_pse             boot_cpu_has(X86_FEATURE_PSE)
 139 #define cpu_has_tsc             boot_cpu_has(X86_FEATURE_TSC)
 140 #define cpu_has_pae             boot_cpu_has(X86_FEATURE_PAE)
 141 #define cpu_has_pge             boot_cpu_has(X86_FEATURE_PGE)
 142 #define cpu_has_apic            boot_cpu_has(X86_FEATURE_APIC)
 143 #define cpu_has_sep             boot_cpu_has(X86_FEATURE_SEP)
 144 #define cpu_has_mtrr            boot_cpu_has(X86_FEATURE_MTRR)
 145 #define cpu_has_mmx             boot_cpu_has(X86_FEATURE_MMX)
 146 #define cpu_has_fxsr            boot_cpu_has(X86_FEATURE_FXSR)
 147 #define cpu_has_xmm             boot_cpu_has(X86_FEATURE_XMM)
 148 #define cpu_has_xmm2            boot_cpu_has(X86_FEATURE_XMM2)
 149 #define cpu_has_xmm3            boot_cpu_has(X86_FEATURE_XMM3)
 150 #define cpu_has_ht              boot_cpu_has(X86_FEATURE_HT)
 151 #define cpu_has_mp              boot_cpu_has(X86_FEATURE_MP)
 152 #define cpu_has_nx              boot_cpu_has(X86_FEATURE_NX)
 153 #define cpu_has_k6_mtrr         boot_cpu_has(X86_FEATURE_K6_MTRR)
 154 #define cpu_has_cyrix_arr       boot_cpu_has(X86_FEATURE_CYRIX_ARR)
 155 #define cpu_has_centaur_mcr     boot_cpu_has(X86_FEATURE_CENTAUR_MCR)
 156 #define cpu_has_xstore          boot_cpu_has(X86_FEATURE_XSTORE)
 157 #define cpu_has_xstore_enabled  boot_cpu_has(X86_FEATURE_XSTORE_EN)
 158 #define cpu_has_xcrypt          boot_cpu_has(X86_FEATURE_XCRYPT)
 159 #define cpu_has_xcrypt_enabled  boot_cpu_has(X86_FEATURE_XCRYPT_EN)
 160 #define cpu_has_ace2            boot_cpu_has(X86_FEATURE_ACE2)
 161 #define cpu_has_ace2_enabled    boot_cpu_has(X86_FEATURE_ACE2_EN)
 162 #define cpu_has_phe             boot_cpu_has(X86_FEATURE_PHE)
 163 #define cpu_has_phe_enabled     boot_cpu_has(X86_FEATURE_PHE_EN)
 164 #define cpu_has_pmm             boot_cpu_has(X86_FEATURE_PMM)
 165 #define cpu_has_pmm_enabled     boot_cpu_has(X86_FEATURE_PMM_EN)
 166 #define cpu_has_ds              boot_cpu_has(X86_FEATURE_DS)
 167 #define cpu_has_pebs            boot_cpu_has(X86_FEATURE_PEBS)
 168 #define cpu_has_clflush         boot_cpu_has(X86_FEATURE_CLFLSH)
 169 #define cpu_has_bts             boot_cpu_has(X86_FEATURE_BTS)
 170
 171 #if defined(CONFIG_X86_INVLPG) || defined(CONFIG_X86_64)
 172 # define cpu_has_invlpg         1
 173 #else
 174 # define cpu_has_invlpg         (boot_cpu_data.x86 > 3)
 175 #endif
 176
 177 #ifdef CONFIG_X86_64
 178
 179 #undef  cpu_has_vme
 180 #define cpu_has_vme             0
 181
 182 #undef  cpu_has_pae
 183 #define cpu_has_pae             ___BUG___
 184
 185 #undef  cpu_has_mp
 186 #define cpu_has_mp              1
 187
 188 #undef  cpu_has_k6_mtrr
 189 #define cpu_has_k6_mtrr         0
 190
 191 #undef  cpu_has_cyrix_arr
 192 #define cpu_has_cyrix_arr       0
 193
 194 #undef  cpu_has_centaur_mcr
 195 #define cpu_has_centaur_mcr     0
 196
 197 #undef  cpu_has_pse
 198 #define cpu_has_pse             1
 199
 200 #undef  cpu_has_pge
 201 #define cpu_has_pge             1
 202
 203 #undef  cpu_has_xmm
 204 #define cpu_has_xmm             1
 205
 206 #undef  cpu_has_xmm2
 207 #define cpu_has_xmm2            1
 208
 209 #undef  cpu_has_fxsr
 210 #define cpu_has_fxsr            1
 211
 212 #endif /* CONFIG_X86_64 */
 213
 214 #endif /* _ASM_X86_CPUFEATURE_H */