3 * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
5 * Copyright * 2005 Agere Systems Inc.
9 *------------------------------------------------------------------------------
11 * et1310_phy.c - Routines for configuring and accessing the PHY
13 *------------------------------------------------------------------------------
17 * This software is provided subject to the following terms and conditions,
18 * which you should read carefully before using the software. Using this
19 * software indicates your acceptance of these terms and conditions. If you do
20 * not agree with these terms and conditions, do not use the software.
22 * Copyright * 2005 Agere Systems Inc.
23 * All rights reserved.
25 * Redistribution and use in source or binary forms, with or without
26 * modifications, are permitted provided that the following conditions are met:
28 * . Redistributions of source code must retain the above copyright notice, this
29 * list of conditions and the following Disclaimer as comments in the code as
30 * well as in the documentation and/or other materials provided with the
33 * . Redistributions in binary form must reproduce the above copyright notice,
34 * this list of conditions and the following Disclaimer in the documentation
35 * and/or other materials provided with the distribution.
37 * . Neither the name of Agere Systems Inc. nor the names of the contributors
38 * may be used to endorse or promote products derived from this software
39 * without specific prior written permission.
43 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
44 * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
45 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
46 * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
47 * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
48 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
49 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
50 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
51 * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
52 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
53 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
58 #include "et131x_version.h"
59 #include "et131x_defs.h"
61 #include <linux/pci.h>
62 #include <linux/init.h>
63 #include <linux/module.h>
64 #include <linux/types.h>
65 #include <linux/kernel.h>
67 #include <linux/sched.h>
68 #include <linux/ptrace.h>
69 #include <linux/slab.h>
70 #include <linux/ctype.h>
71 #include <linux/string.h>
72 #include <linux/timer.h>
73 #include <linux/interrupt.h>
75 #include <linux/delay.h>
77 #include <linux/bitops.h>
78 #include <asm/system.h>
80 #include <linux/netdevice.h>
81 #include <linux/etherdevice.h>
82 #include <linux/skbuff.h>
83 #include <linux/if_arp.h>
84 #include <linux/ioport.h>
85 #include <linux/random.h>
87 #include "et1310_phy.h"
88 #include "et1310_pm.h"
89 #include "et1310_jagcore.h"
91 #include "et131x_adapter.h"
92 #include "et131x_netdev.h"
93 #include "et131x_initpci.h"
95 #include "et1310_address_map.h"
96 #include "et1310_tx.h"
97 #include "et1310_rx.h"
98 #include "et1310_mac.h"
100 /* Prototypes for functions with local scope */
101 static void et131x_xcvr_init(struct et131x_adapter
*etdev
);
104 * PhyMiRead - Read from the PHY through the MII Interface on the MAC
105 * @etdev: pointer to our private adapter structure
106 * @xcvrAddr: the address of the transciever
107 * @xcvrReg: the register to read
108 * @value: pointer to a 16-bit value in which the value will be stored
110 * Returns 0 on success, errno on failure (as defined in errno.h)
112 int PhyMiRead(struct et131x_adapter
*etdev
, u8 xcvrAddr
,
113 u8 xcvrReg
, u16
*value
)
115 struct _MAC_t __iomem
*mac
= &etdev
->regs
->mac
;
122 /* Save a local copy of the registers we are dealing with so we can
125 miiAddr
= readl(&mac
->mii_mgmt_addr
);
126 miiCmd
= readl(&mac
->mii_mgmt_cmd
);
128 /* Stop the current operation */
129 writel(0, &mac
->mii_mgmt_cmd
);
131 /* Set up the register we need to read from on the correct PHY */
132 writel(MII_ADDR(xcvrAddr
, xcvrReg
), &mac
->mii_mgmt_addr
);
134 /* Kick the read cycle off */
137 writel(0x1, &mac
->mii_mgmt_cmd
);
142 miiIndicator
= readl(&mac
->mii_mgmt_indicator
);
143 } while ((miiIndicator
& MGMT_WAIT
) && delay
< 50);
145 /* If we hit the max delay, we could not read the register */
147 dev_warn(&etdev
->pdev
->dev
,
148 "xcvrReg 0x%08x could not be read\n", xcvrReg
);
149 dev_warn(&etdev
->pdev
->dev
, "status is 0x%08x\n",
155 /* If we hit here we were able to read the register and we need to
156 * return the value to the caller */
157 *value
= readl(&mac
->mii_mgmt_stat
) & 0xFFFF;
159 /* Stop the read operation */
160 writel(0, &mac
->mii_mgmt_cmd
);
162 /* set the registers we touched back to the state at which we entered
165 writel(miiAddr
, &mac
->mii_mgmt_addr
);
166 writel(miiCmd
, &mac
->mii_mgmt_cmd
);
172 * MiWrite - Write to a PHY register through the MII interface of the MAC
173 * @etdev: pointer to our private adapter structure
174 * @xcvrReg: the register to read
175 * @value: 16-bit value to write
177 * FIXME: one caller in netdev still
179 * Return 0 on success, errno on failure (as defined in errno.h)
181 int MiWrite(struct et131x_adapter
*etdev
, u8 xcvrReg
, u16 value
)
183 struct _MAC_t __iomem
*mac
= &etdev
->regs
->mac
;
185 u8 xcvrAddr
= etdev
->Stats
.xcvr_addr
;
191 /* Save a local copy of the registers we are dealing with so we can
194 miiAddr
= readl(&mac
->mii_mgmt_addr
);
195 miiCmd
= readl(&mac
->mii_mgmt_cmd
);
197 /* Stop the current operation */
198 writel(0, &mac
->mii_mgmt_cmd
);
200 /* Set up the register we need to write to on the correct PHY */
201 writel(MII_ADDR(xcvrAddr
, xcvrReg
), &mac
->mii_mgmt_addr
);
203 /* Add the value to write to the registers to the mac */
204 writel(value
, &mac
->mii_mgmt_ctrl
);
210 miiIndicator
= readl(&mac
->mii_mgmt_indicator
);
211 } while ((miiIndicator
& MGMT_BUSY
) && delay
< 100);
213 /* If we hit the max delay, we could not write the register */
217 dev_warn(&etdev
->pdev
->dev
,
218 "xcvrReg 0x%08x could not be written", xcvrReg
);
219 dev_warn(&etdev
->pdev
->dev
, "status is 0x%08x\n",
221 dev_warn(&etdev
->pdev
->dev
, "command is 0x%08x\n",
222 readl(&mac
->mii_mgmt_cmd
));
224 MiRead(etdev
, xcvrReg
, &TempValue
);
228 /* Stop the write operation */
229 writel(0, &mac
->mii_mgmt_cmd
);
231 /* set the registers we touched back to the state at which we entered
234 writel(miiAddr
, &mac
->mii_mgmt_addr
);
235 writel(miiCmd
, &mac
->mii_mgmt_cmd
);
241 * et131x_xcvr_find - Find the PHY ID
242 * @etdev: pointer to our private adapter structure
244 * Returns 0 on success, errno on failure (as defined in errno.h)
246 int et131x_xcvr_find(struct et131x_adapter
*etdev
)
253 /* We need to get xcvr id and address we just get the first one */
254 for (xcvr_addr
= 0; xcvr_addr
< 32; xcvr_addr
++) {
255 /* Read the ID from the PHY */
256 PhyMiRead(etdev
, xcvr_addr
,
257 (u8
) offsetof(MI_REGS_t
, idr1
),
259 PhyMiRead(etdev
, xcvr_addr
,
260 (u8
) offsetof(MI_REGS_t
, idr2
),
263 xcvr_id
= (u32
) ((idr1
.value
<< 16) | idr2
.value
);
265 if (idr1
.value
!= 0 && idr1
.value
!= 0xffff) {
266 etdev
->Stats
.xcvr_id
= xcvr_id
;
267 etdev
->Stats
.xcvr_addr
= xcvr_addr
;
274 void ET1310_PhyReset(struct et131x_adapter
*etdev
)
276 MiWrite(etdev
, PHY_CONTROL
, 0x8000);
280 * ET1310_PhyPowerDown - PHY power control
281 * @etdev: device to control
282 * @down: true for off/false for back on
284 * one hundred, ten, one thousand megs
285 * How would you like to have your LAN accessed
286 * Can't you see that this code processed
287 * Phy power, phy power..
290 void ET1310_PhyPowerDown(struct et131x_adapter
*etdev
, bool down
)
294 MiRead(etdev
, PHY_CONTROL
, &data
);
295 data
&= ~0x0800; /* Power UP */
296 if (down
) /* Power DOWN */
298 MiWrite(etdev
, PHY_CONTROL
, data
);
302 * ET130_PhyAutoNEg - autonegotiate control
303 * @etdev: device to control
304 * @enabe: autoneg on/off
306 * Set up the autonegotiation state according to whether we will be
307 * negotiating the state or forcing a speed.
310 static void ET1310_PhyAutoNeg(struct et131x_adapter
*etdev
, bool enable
)
314 MiRead(etdev
, PHY_CONTROL
, &data
);
315 data
&= ~0x1000; /* Autonegotiation OFF */
317 data
|= 0x1000; /* Autonegotiation ON */
318 MiWrite(etdev
, PHY_CONTROL
, data
);
322 * ET130_PhyDuplexMode - duplex control
323 * @etdev: device to control
324 * @duplex: duplex on/off
326 * Set up the duplex state on the PHY
329 static void ET1310_PhyDuplexMode(struct et131x_adapter
*etdev
, u16 duplex
)
333 MiRead(etdev
, PHY_CONTROL
, &data
);
334 data
&= ~0x100; /* Set Half Duplex */
335 if (duplex
== TRUEPHY_DUPLEX_FULL
)
336 data
|= 0x100; /* Set Full Duplex */
337 MiWrite(etdev
, PHY_CONTROL
, data
);
341 * ET130_PhySpeedSelect - speed control
342 * @etdev: device to control
343 * @duplex: duplex on/off
345 * Set the speed of our PHY.
348 static void ET1310_PhySpeedSelect(struct et131x_adapter
*etdev
, u16 speed
)
351 static const u16 bits
[3]={0x0000, 0x2000, 0x0040};
353 /* Read the PHY control register */
354 MiRead(etdev
, PHY_CONTROL
, &data
);
355 /* Clear all Speed settings (Bits 6, 13) */
357 /* Write back the new speed */
358 MiWrite(etdev
, PHY_CONTROL
, data
| bits
[speed
]);
362 * ET1310_PhyLinkStatus - read link state
363 * @etdev: device to read
364 * @link_status: reported link state
365 * @autoneg: reported autonegotiation state (complete/incomplete/disabled)
366 * @linkspeed: returnedlink speed in use
367 * @duplex_mode: reported half/full duplex state
368 * @mdi_mdix: not yet working
369 * @masterslave: report whether we are master or slave
370 * @polarity: link polarity
372 * I can read your lan like a magazine
374 * I know your link speed
375 * I see all the setting that you'd rather keep
378 static void ET1310_PhyLinkStatus(struct et131x_adapter
*etdev
,
384 u32
*masterslave
, u32
*polarity
)
388 u16 vmi_phystatus
= 0;
391 MiRead(etdev
, PHY_STATUS
, &mistatus
);
392 MiRead(etdev
, PHY_1000_STATUS
, &is1000BaseT
);
393 MiRead(etdev
, PHY_PHY_STATUS
, &vmi_phystatus
);
394 MiRead(etdev
, PHY_CONTROL
, &control
);
396 *link_status
= (vmi_phystatus
& 0x0040) ? 1 : 0;
397 *autoneg
= (control
& 0x1000) ? ((vmi_phystatus
& 0x0020) ?
398 TRUEPHY_ANEG_COMPLETE
:
399 TRUEPHY_ANEG_NOT_COMPLETE
) :
400 TRUEPHY_ANEG_DISABLED
;
401 *linkspeed
= (vmi_phystatus
& 0x0300) >> 8;
402 *duplex_mode
= (vmi_phystatus
& 0x0080) >> 7;
403 /* NOTE: Need to complete this */
406 *masterslave
= (is1000BaseT
& 0x4000) ?
407 TRUEPHY_CFG_MASTER
: TRUEPHY_CFG_SLAVE
;
408 *polarity
= (vmi_phystatus
& 0x0400) ?
409 TRUEPHY_POLARITY_INVERTED
: TRUEPHY_POLARITY_NORMAL
;
412 static void ET1310_PhyAndOrReg(struct et131x_adapter
*etdev
,
413 u16 regnum
, u16 andMask
, u16 orMask
)
417 MiRead(etdev
, regnum
, ®
);
420 MiWrite(etdev
, regnum
, reg
);
423 /* Still used from _mac for BIT_READ */
424 void ET1310_PhyAccessMiBit(struct et131x_adapter
*etdev
, u16 action
,
425 u16 regnum
, u16 bitnum
, u8
*value
)
428 u16 mask
= 0x0001 << bitnum
;
430 /* Read the requested register */
431 MiRead(etdev
, regnum
, ®
);
434 case TRUEPHY_BIT_READ
:
435 *value
= (reg
& mask
) >> bitnum
;
438 case TRUEPHY_BIT_SET
:
439 MiWrite(etdev
, regnum
, reg
| mask
);
442 case TRUEPHY_BIT_CLEAR
:
443 MiWrite(etdev
, regnum
, reg
& ~mask
);
451 void ET1310_PhyAdvertise1000BaseT(struct et131x_adapter
*etdev
,
456 /* Read the PHY 1000 Base-T Control Register */
457 MiRead(etdev
, PHY_1000_CONTROL
, &data
);
463 case TRUEPHY_ADV_DUPLEX_NONE
:
464 /* Duplex already cleared, do nothing */
467 case TRUEPHY_ADV_DUPLEX_FULL
:
472 case TRUEPHY_ADV_DUPLEX_HALF
:
477 case TRUEPHY_ADV_DUPLEX_BOTH
:
483 /* Write back advertisement */
484 MiWrite(etdev
, PHY_1000_CONTROL
, data
);
487 static void ET1310_PhyAdvertise100BaseT(struct et131x_adapter
*etdev
,
492 /* Read the Autonegotiation Register (10/100) */
493 MiRead(etdev
, PHY_AUTO_ADVERTISEMENT
, &data
);
499 case TRUEPHY_ADV_DUPLEX_NONE
:
500 /* Duplex already cleared, do nothing */
503 case TRUEPHY_ADV_DUPLEX_FULL
:
508 case TRUEPHY_ADV_DUPLEX_HALF
:
513 case TRUEPHY_ADV_DUPLEX_BOTH
:
520 /* Write back advertisement */
521 MiWrite(etdev
, PHY_AUTO_ADVERTISEMENT
, data
);
524 static void ET1310_PhyAdvertise10BaseT(struct et131x_adapter
*etdev
,
529 /* Read the Autonegotiation Register (10/100) */
530 MiRead(etdev
, PHY_AUTO_ADVERTISEMENT
, &data
);
536 case TRUEPHY_ADV_DUPLEX_NONE
:
537 /* Duplex already cleared, do nothing */
540 case TRUEPHY_ADV_DUPLEX_FULL
:
545 case TRUEPHY_ADV_DUPLEX_HALF
:
550 case TRUEPHY_ADV_DUPLEX_BOTH
:
557 /* Write back advertisement */
558 MiWrite(etdev
, PHY_AUTO_ADVERTISEMENT
, data
);
562 * et131x_setphy_normal - Set PHY for normal operation.
563 * @etdev: pointer to our private adapter structure
565 * Used by Power Management to force the PHY into 10 Base T half-duplex mode,
566 * when going to D3 in WOL mode. Also used during initialization to set the
567 * PHY for normal operation.
569 void et131x_setphy_normal(struct et131x_adapter
*etdev
)
571 /* Make sure the PHY is powered up */
572 ET1310_PhyPowerDown(etdev
, 0);
573 et131x_xcvr_init(etdev
);
578 * et131x_xcvr_init - Init the phy if we are setting it into force mode
579 * @etdev: pointer to our private adapter structure
582 static void et131x_xcvr_init(struct et131x_adapter
*etdev
)
588 /* Zero out the adapter structure variable representing BMSR */
589 etdev
->Bmsr
.value
= 0;
591 MiRead(etdev
, (u8
) offsetof(MI_REGS_t
, isr
), &isr
.value
);
592 MiRead(etdev
, (u8
) offsetof(MI_REGS_t
, imr
), &imr
.value
);
594 /* Set the link status interrupt only. Bad behavior when link status
595 * and auto neg are set, we run into a nested interrupt problem
597 imr
.bits
.int_en
= 0x1;
598 imr
.bits
.link_status
= 0x1;
599 imr
.bits
.autoneg_status
= 0x1;
601 MiWrite(etdev
, (u8
) offsetof(MI_REGS_t
, imr
), imr
.value
);
603 /* Set the LED behavior such that LED 1 indicates speed (off =
604 * 10Mbits, blink = 100Mbits, on = 1000Mbits) and LED 2 indicates
605 * link and activity (on for link, blink off for activity).
607 * NOTE: Some customizations have been added here for specific
608 * vendors; The LED behavior is now determined by vendor data in the
609 * EEPROM. However, the above description is the default.
611 if ((etdev
->eepromData
[1] & 0x4) == 0) {
612 MiRead(etdev
, (u8
) offsetof(MI_REGS_t
, lcr2
),
614 if ((etdev
->eepromData
[1] & 0x8) == 0)
615 lcr2
.bits
.led_tx_rx
= 0x3;
617 lcr2
.bits
.led_tx_rx
= 0x4;
618 lcr2
.bits
.led_link
= 0xa;
619 MiWrite(etdev
, (u8
) offsetof(MI_REGS_t
, lcr2
),
623 /* Determine if we need to go into a force mode and set it */
624 if (etdev
->AiForceSpeed
== 0 && etdev
->AiForceDpx
== 0) {
625 if (etdev
->RegistryFlowControl
== TxOnly
||
626 etdev
->RegistryFlowControl
== Both
)
627 ET1310_PhyAccessMiBit(etdev
,
628 TRUEPHY_BIT_SET
, 4, 11, NULL
);
630 ET1310_PhyAccessMiBit(etdev
,
631 TRUEPHY_BIT_CLEAR
, 4, 11, NULL
);
633 if (etdev
->RegistryFlowControl
== Both
)
634 ET1310_PhyAccessMiBit(etdev
,
635 TRUEPHY_BIT_SET
, 4, 10, NULL
);
637 ET1310_PhyAccessMiBit(etdev
,
638 TRUEPHY_BIT_CLEAR
, 4, 10, NULL
);
640 /* Set the phy to autonegotiation */
641 ET1310_PhyAutoNeg(etdev
, true);
643 /* NOTE - Do we need this? */
644 ET1310_PhyAccessMiBit(etdev
, TRUEPHY_BIT_SET
, 0, 9, NULL
);
648 ET1310_PhyAutoNeg(etdev
, false);
650 /* Set to the correct force mode. */
651 if (etdev
->AiForceDpx
!= 1) {
652 if (etdev
->RegistryFlowControl
== TxOnly
||
653 etdev
->RegistryFlowControl
== Both
)
654 ET1310_PhyAccessMiBit(etdev
,
655 TRUEPHY_BIT_SET
, 4, 11, NULL
);
657 ET1310_PhyAccessMiBit(etdev
,
658 TRUEPHY_BIT_CLEAR
, 4, 11, NULL
);
660 if (etdev
->RegistryFlowControl
== Both
)
661 ET1310_PhyAccessMiBit(etdev
,
662 TRUEPHY_BIT_SET
, 4, 10, NULL
);
664 ET1310_PhyAccessMiBit(etdev
,
665 TRUEPHY_BIT_CLEAR
, 4, 10, NULL
);
667 ET1310_PhyAccessMiBit(etdev
, TRUEPHY_BIT_CLEAR
, 4, 10, NULL
);
668 ET1310_PhyAccessMiBit(etdev
, TRUEPHY_BIT_CLEAR
, 4, 11, NULL
);
670 ET1310_PhyPowerDown(etdev
, 1);
671 switch (etdev
->AiForceSpeed
) {
673 /* First we need to turn off all other advertisement */
674 ET1310_PhyAdvertise1000BaseT(etdev
, TRUEPHY_ADV_DUPLEX_NONE
);
675 ET1310_PhyAdvertise100BaseT(etdev
, TRUEPHY_ADV_DUPLEX_NONE
);
676 if (etdev
->AiForceDpx
== 1) {
677 /* Set our advertise values accordingly */
678 ET1310_PhyAdvertise10BaseT(etdev
,
679 TRUEPHY_ADV_DUPLEX_HALF
);
680 } else if (etdev
->AiForceDpx
== 2) {
681 /* Set our advertise values accordingly */
682 ET1310_PhyAdvertise10BaseT(etdev
,
683 TRUEPHY_ADV_DUPLEX_FULL
);
685 /* Disable autoneg */
686 ET1310_PhyAutoNeg(etdev
, false);
687 /* Disable rest of the advertisements */
688 ET1310_PhyAdvertise10BaseT(etdev
,
689 TRUEPHY_ADV_DUPLEX_NONE
);
691 ET1310_PhySpeedSelect(etdev
, TRUEPHY_SPEED_10MBPS
);
692 /* Force Full duplex */
693 ET1310_PhyDuplexMode(etdev
, TRUEPHY_DUPLEX_FULL
);
697 /* first we need to turn off all other advertisement */
698 ET1310_PhyAdvertise1000BaseT(etdev
, TRUEPHY_ADV_DUPLEX_NONE
);
699 ET1310_PhyAdvertise10BaseT(etdev
, TRUEPHY_ADV_DUPLEX_NONE
);
700 if (etdev
->AiForceDpx
== 1) {
701 /* Set our advertise values accordingly */
702 ET1310_PhyAdvertise100BaseT(etdev
,
703 TRUEPHY_ADV_DUPLEX_HALF
);
705 ET1310_PhySpeedSelect(etdev
, TRUEPHY_SPEED_100MBPS
);
706 } else if (etdev
->AiForceDpx
== 2) {
707 /* Set our advertise values accordingly */
708 ET1310_PhyAdvertise100BaseT(etdev
,
709 TRUEPHY_ADV_DUPLEX_FULL
);
711 /* Disable autoneg */
712 ET1310_PhyAutoNeg(etdev
, false);
713 /* Disable other advertisement */
714 ET1310_PhyAdvertise100BaseT(etdev
,
715 TRUEPHY_ADV_DUPLEX_NONE
);
717 ET1310_PhySpeedSelect(etdev
, TRUEPHY_SPEED_100MBPS
);
718 /* Force Full duplex */
719 ET1310_PhyDuplexMode(etdev
, TRUEPHY_DUPLEX_FULL
);
723 /* first we need to turn off all other advertisement */
724 ET1310_PhyAdvertise100BaseT(etdev
, TRUEPHY_ADV_DUPLEX_NONE
);
725 ET1310_PhyAdvertise10BaseT(etdev
, TRUEPHY_ADV_DUPLEX_NONE
);
726 /* set our advertise values accordingly */
727 ET1310_PhyAdvertise1000BaseT(etdev
, TRUEPHY_ADV_DUPLEX_FULL
);
730 ET1310_PhyPowerDown(etdev
, 0);
733 void et131x_Mii_check(struct et131x_adapter
*etdev
,
734 MI_BMSR_t bmsr
, MI_BMSR_t bmsr_ints
)
745 if (bmsr_ints
.bits
.link_status
) {
746 if (bmsr
.bits
.link_status
) {
747 etdev
->PoMgmt
.TransPhyComaModeOnBoot
= 20;
749 /* Update our state variables and indicate the
752 spin_lock_irqsave(&etdev
->Lock
, flags
);
754 etdev
->MediaState
= NETIF_STATUS_MEDIA_CONNECT
;
755 etdev
->Flags
&= ~fMP_ADAPTER_LINK_DETECTION
;
757 spin_unlock_irqrestore(&etdev
->Lock
, flags
);
759 netif_carrier_on(etdev
->netdev
);
761 dev_warn(&etdev
->pdev
->dev
,
762 "Link down - cable problem ?\n");
764 if (etdev
->linkspeed
== TRUEPHY_SPEED_10MBPS
) {
765 /* NOTE - Is there a way to query this without
767 * && TRU_QueryCoreType(etdev->hTruePhy, 0) == EMI_TRUEPHY_A13O) {
771 MiRead(etdev
, 0x12, &Register18
);
772 MiWrite(etdev
, 0x12, Register18
| 0x4);
773 MiWrite(etdev
, 0x10, Register18
| 0x8402);
774 MiWrite(etdev
, 0x11, Register18
| 511);
775 MiWrite(etdev
, 0x12, Register18
);
778 /* For the first N seconds of life, we are in "link
779 * detection" When we are in this state, we should
780 * only report "connected". When the LinkDetection
781 * Timer expires, we can report disconnected (handled
782 * in the LinkDetectionDPC).
784 if (!(etdev
->Flags
& fMP_ADAPTER_LINK_DETECTION
) ||
785 (etdev
->MediaState
== NETIF_STATUS_MEDIA_DISCONNECT
)) {
786 spin_lock_irqsave(&etdev
->Lock
, flags
);
788 NETIF_STATUS_MEDIA_DISCONNECT
;
789 spin_unlock_irqrestore(&etdev
->Lock
,
792 netif_carrier_off(etdev
->netdev
);
795 etdev
->linkspeed
= 0;
796 etdev
->duplex_mode
= 0;
798 /* Free the packets being actively sent & stopped */
799 et131x_free_busy_send_packets(etdev
);
801 /* Re-initialize the send structures */
802 et131x_init_send(etdev
);
804 /* Reset the RFD list and re-start RU */
805 et131x_reset_recv(etdev
);
808 * Bring the device back to the state it was during
809 * init prior to autonegotiation being complete. This
810 * way, when we get the auto-neg complete interrupt,
811 * we can complete init by calling ConfigMacREGS2.
813 et131x_soft_reset(etdev
);
815 /* Setup ET1310 as per the documentation */
816 et131x_adapter_setup(etdev
);
818 /* Setup the PHY into coma mode until the cable is
821 if (etdev
->RegistryPhyComa
== 1)
822 EnablePhyComa(etdev
);
826 if (bmsr_ints
.bits
.auto_neg_complete
||
827 (etdev
->AiForceDpx
== 3 && bmsr_ints
.bits
.link_status
)) {
828 if (bmsr
.bits
.auto_neg_complete
|| etdev
->AiForceDpx
== 3) {
829 ET1310_PhyLinkStatus(etdev
,
830 &link_status
, &autoneg_status
,
831 &speed
, &duplex
, &mdi_mdix
,
832 &masterslave
, &polarity
);
834 etdev
->linkspeed
= speed
;
835 etdev
->duplex_mode
= duplex
;
837 etdev
->PoMgmt
.TransPhyComaModeOnBoot
= 20;
839 if (etdev
->linkspeed
== TRUEPHY_SPEED_10MBPS
) {
841 * NOTE - Is there a way to query this without
843 * && TRU_QueryCoreType(etdev->hTruePhy, 0)== EMI_TRUEPHY_A13O) {
847 MiRead(etdev
, 0x12, &Register18
);
848 MiWrite(etdev
, 0x12, Register18
| 0x4);
849 MiWrite(etdev
, 0x10, Register18
| 0x8402);
850 MiWrite(etdev
, 0x11, Register18
| 511);
851 MiWrite(etdev
, 0x12, Register18
);
854 ConfigFlowControl(etdev
);
856 if (etdev
->linkspeed
== TRUEPHY_SPEED_1000MBPS
&&
857 etdev
->RegistryJumboPacket
> 2048)
858 ET1310_PhyAndOrReg(etdev
, 0x16, 0xcfff,
861 SetRxDmaTimer(etdev
);
862 ConfigMACRegs2(etdev
);
868 * The routines which follow provide low-level access to the PHY, and are used
869 * primarily by the routines above (although there are a few places elsewhere
870 * in the driver where this level of access is required).
873 static const u16 ConfigPhy
[25][2] = {
874 /* Reg Value Register */
876 {0x880B, 0x0926}, /* AfeIfCreg4B1000Msbs */
877 {0x880C, 0x0926}, /* AfeIfCreg4B100Msbs */
878 {0x880D, 0x0926}, /* AfeIfCreg4B10Msbs */
880 {0x880E, 0xB4D3}, /* AfeIfCreg4B1000Lsbs */
881 {0x880F, 0xB4D3}, /* AfeIfCreg4B100Lsbs */
882 {0x8810, 0xB4D3}, /* AfeIfCreg4B10Lsbs */
884 {0x8805, 0xB03E}, /* AfeIfCreg3B1000Msbs */
885 {0x8806, 0xB03E}, /* AfeIfCreg3B100Msbs */
886 {0x8807, 0xFF00}, /* AfeIfCreg3B10Msbs */
888 {0x8808, 0xE090}, /* AfeIfCreg3B1000Lsbs */
889 {0x8809, 0xE110}, /* AfeIfCreg3B100Lsbs */
890 {0x880A, 0x0000}, /* AfeIfCreg3B10Lsbs */
892 {0x300D, 1}, /* DisableNorm */
894 {0x280C, 0x0180}, /* LinkHoldEnd */
896 {0x1C21, 0x0002}, /* AlphaM */
898 {0x3821, 6}, /* FfeLkgTx0 */
899 {0x381D, 1}, /* FfeLkg1g4 */
900 {0x381E, 1}, /* FfeLkg1g5 */
901 {0x381F, 1}, /* FfeLkg1g6 */
902 {0x3820, 1}, /* FfeLkg1g7 */
904 {0x8402, 0x01F0}, /* Btinact */
905 {0x800E, 20}, /* LftrainTime */
906 {0x800F, 24}, /* DvguardTime */
907 {0x8010, 46}, /* IdlguardTime */
913 /* condensed version of the phy initialization routine */
914 void ET1310_PhyInit(struct et131x_adapter
*etdev
)
921 /* get the identity (again ?) */
922 MiRead(etdev
, PHY_ID_1
, &data
);
923 MiRead(etdev
, PHY_ID_2
, &data
);
925 /* what does this do/achieve ? */
926 MiRead(etdev
, PHY_MPHY_CONTROL_REG
, &data
); /* should read 0002 */
927 MiWrite(etdev
, PHY_MPHY_CONTROL_REG
, 0x0006);
929 /* read modem register 0402, should I do something with the return
931 MiWrite(etdev
, PHY_INDEX_REG
, 0x0402);
932 MiRead(etdev
, PHY_DATA_REG
, &data
);
934 /* what does this do/achieve ? */
935 MiWrite(etdev
, PHY_MPHY_CONTROL_REG
, 0x0002);
937 /* get the identity (again ?) */
938 MiRead(etdev
, PHY_ID_1
, &data
);
939 MiRead(etdev
, PHY_ID_2
, &data
);
941 /* what does this achieve ? */
942 MiRead(etdev
, PHY_MPHY_CONTROL_REG
, &data
); /* should read 0002 */
943 MiWrite(etdev
, PHY_MPHY_CONTROL_REG
, 0x0006);
945 /* read modem register 0402, should I do something with
947 MiWrite(etdev
, PHY_INDEX_REG
, 0x0402);
948 MiRead(etdev
, PHY_DATA_REG
, &data
);
950 MiWrite(etdev
, PHY_MPHY_CONTROL_REG
, 0x0002);
952 /* what does this achieve (should return 0x1040) */
953 MiRead(etdev
, PHY_CONTROL
, &data
);
954 MiRead(etdev
, PHY_MPHY_CONTROL_REG
, &data
); /* should read 0002 */
955 MiWrite(etdev
, PHY_CONTROL
, 0x1840);
957 MiWrite(etdev
, PHY_MPHY_CONTROL_REG
, 0x0007);
959 /* here the writing of the array starts.... */
961 while (ConfigPhy
[index
][0] != 0x0000) {
963 MiWrite(etdev
, PHY_INDEX_REG
, ConfigPhy
[index
][0]);
964 MiWrite(etdev
, PHY_DATA_REG
, ConfigPhy
[index
][1]);
967 MiWrite(etdev
, PHY_INDEX_REG
, ConfigPhy
[index
][0]);
968 MiRead(etdev
, PHY_DATA_REG
, &data
);
970 /* do a check on the value read back ? */
973 /* here the writing of the array ends... */
975 MiRead(etdev
, PHY_CONTROL
, &data
); /* 0x1840 */
976 MiRead(etdev
, PHY_MPHY_CONTROL_REG
, &data
);/* should read 0007 */
977 MiWrite(etdev
, PHY_CONTROL
, 0x1040);
978 MiWrite(etdev
, PHY_MPHY_CONTROL_REG
, 0x0002);