include/linux/amba/pl08x.h

   1 /*
   2  * linux/amba/pl08x.h - ARM PrimeCell DMA Controller driver
   3  *
   4  * Copyright (C) 2005 ARM Ltd
   5  * Copyright (C) 2010 ST-Ericsson SA
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  *
  11  * pl08x information required by platform code
  12  *
  13  * Please credit ARM.com
  14  * Documentation: ARM DDI 0196D
  15  *
  16  */
  17
  18 #ifndef AMBA_PL08X_H
  19 #define AMBA_PL08X_H
  20
  21 /* We need sizes of structs from this header */
  22 #include <linux/dmaengine.h>
  23 #include <linux/interrupt.h>
  24
  25 struct pl08x_lli;
  26 struct pl08x_driver_data;
  27
  28 /* Bitmasks for selecting AHB ports for DMA transfers */
  29 enum {
  30         PL08X_AHB1 = (1 << 0),
  31         PL08X_AHB2 = (1 << 1)
  32 };
  33
  34 /**
  35  * struct pl08x_channel_data - data structure to pass info between
  36  * platform and PL08x driver regarding channel configuration
  37  * @bus_id: name of this device channel, not just a device name since
  38  * devices may have more than one channel e.g. "foo_tx"
  39  * @min_signal: the minimum DMA signal number to be muxed in for this
  40  * channel (for platforms supporting muxed signals). If you have
  41  * static assignments, make sure this is set to the assigned signal
  42  * number, PL08x have 16 possible signals in number 0 thru 15 so
  43  * when these are not enough they often get muxed (in hardware)
  44  * disabling simultaneous use of the same channel for two devices.
  45  * @max_signal: the maximum DMA signal number to be muxed in for
  46  * the channel. Set to the same as min_signal for
  47  * devices with static assignments
  48  * @muxval: a number usually used to poke into some mux regiser to
  49  * mux in the signal to this channel
  50  * @cctl_opt: default options for the channel control register
  51  * @addr: source/target address in physical memory for this DMA channel,
  52  * can be the address of a FIFO register for burst requests for example.
  53  * This can be left undefined if the PrimeCell API is used for configuring
  54  * this.
  55  * @circular_buffer: whether the buffer passed in is circular and
  56  * shall simply be looped round round (like a record baby round
  57  * round round round)
  58  * @single: the device connected to this channel will request single
  59  * DMA transfers, not bursts. (Bursts are default.)
  60  * @periph_buses: the device connected to this channel is accessible via
  61  * these buses (use PL08X_AHB1 | PL08X_AHB2).
  62  */
  63 struct pl08x_channel_data {
  64         char *bus_id;
  65         int min_signal;
  66         int max_signal;
  67         u32 muxval;
  68         u32 cctl;
  69         dma_addr_t addr;
  70         bool circular_buffer;
  71         bool single;
  72         u8 periph_buses;
  73 };
  74
  75 /**
  76  * Struct pl08x_bus_data - information of source or destination
  77  * busses for a transfer
  78  * @addr: current address
  79  * @maxwidth: the maximum width of a transfer on this bus
  80  * @buswidth: the width of this bus in bytes: 1, 2 or 4
  81  * @fill_bytes: bytes required to fill to the next bus memory
  82  * boundary
  83  */
  84 struct pl08x_bus_data {
  85         dma_addr_t addr;
  86         u8 maxwidth;
  87         u8 buswidth;
  88         size_t fill_bytes;
  89 };
  90
  91 /**
  92  * struct pl08x_phy_chan - holder for the physical channels
  93  * @id: physical index to this channel
  94  * @lock: a lock to use when altering an instance of this struct
  95  * @signal: the physical signal (aka channel) serving this
  96  * physical channel right now
  97  * @serving: the virtual channel currently being served by this
  98  * physical channel
  99  */
 100 struct pl08x_phy_chan {
 101         unsigned int id;
 102         void __iomem *base;
 103         spinlock_t lock;
 104         int signal;
 105         struct pl08x_dma_chan *serving;
 106 };
 107
 108 /**
 109  * struct pl08x_txd - wrapper for struct dma_async_tx_descriptor
 110  * @llis_bus: DMA memory address (physical) start for the LLIs
 111  * @llis_va: virtual memory address start for the LLIs
 112  */
 113 struct pl08x_txd {
 114         struct dma_async_tx_descriptor tx;
 115         struct list_head node;
 116         enum dma_data_direction direction;
 117         dma_addr_t src_addr;
 118         dma_addr_t dst_addr;
 119         size_t len;
 120         dma_addr_t llis_bus;
 121         struct pl08x_lli *llis_va;
 122         bool active;
 123         /* Default cctl value for LLIs */
 124         u32 cctl;
 125         /*
 126          * Settings to be put into the physical channel when we
 127          * trigger this txd.  Other registers are in llis_va[0].
 128          */
 129         u32 ccfg;
 130 };
 131
 132 /**
 133  * struct pl08x_dma_chan_state - holds the PL08x specific virtual
 134  * channel states
 135  * @PL08X_CHAN_IDLE: the channel is idle
 136  * @PL08X_CHAN_RUNNING: the channel has allocated a physical transport
 137  * channel and is running a transfer on it
 138  * @PL08X_CHAN_PAUSED: the channel has allocated a physical transport
 139  * channel, but the transfer is currently paused
 140  * @PL08X_CHAN_WAITING: the channel is waiting for a physical transport
 141  * channel to become available (only pertains to memcpy channels)
 142  */
 143 enum pl08x_dma_chan_state {
 144         PL08X_CHAN_IDLE,
 145         PL08X_CHAN_RUNNING,
 146         PL08X_CHAN_PAUSED,
 147         PL08X_CHAN_WAITING,
 148 };
 149
 150 /**
 151  * struct pl08x_dma_chan - this structure wraps a DMA ENGINE channel
 152  * @chan: wrappped abstract channel
 153  * @phychan: the physical channel utilized by this channel, if there is one
 154  * @phychan_hold: if non-zero, hold on to the physical channel even if we
 155  *  have no pending entries
 156  * @tasklet: tasklet scheduled by the IRQ to handle actual work etc
 157  * @name: name of channel
 158  * @cd: channel platform data
 159  * @runtime_addr: address for RX/TX according to the runtime config
 160  * @runtime_direction: current direction of this channel according to
 161  * runtime config
 162  * @lc: last completed transaction on this channel
 163  * @pend_list: queued transactions pending on this channel
 164  * @at: active transaction on this channel
 165  * @lock: a lock for this channel data
 166  * @host: a pointer to the host (internal use)
 167  * @state: whether the channel is idle, paused, running etc
 168  * @slave: whether this channel is a device (slave) or for memcpy
 169  * @waiting: a TX descriptor on this channel which is waiting for
 170  * a physical channel to become available
 171  */
 172 struct pl08x_dma_chan {
 173         struct dma_chan chan;
 174         struct pl08x_phy_chan *phychan;
 175         int phychan_hold;
 176         struct tasklet_struct tasklet;
 177         char *name;
 178         struct pl08x_channel_data *cd;
 179         dma_addr_t runtime_addr;
 180         enum dma_data_direction runtime_direction;
 181         dma_cookie_t lc;
 182         struct list_head pend_list;
 183         struct pl08x_txd *at;
 184         spinlock_t lock;
 185         struct pl08x_driver_data *host;
 186         enum pl08x_dma_chan_state state;
 187         bool slave;
 188         struct pl08x_txd *waiting;
 189 };
 190
 191 /**
 192  * struct pl08x_platform_data - the platform configuration for the
 193  * PL08x PrimeCells.
 194  * @slave_channels: the channels defined for the different devices on the
 195  * platform, all inclusive, including multiplexed channels. The available
 196  * physical channels will be multiplexed around these signals as they
 197  * are requested, just enumerate all possible channels.
 198  * @get_signal: request a physical signal to be used for a DMA
 199  * transfer immediately: if there is some multiplexing or similar blocking
 200  * the use of the channel the transfer can be denied by returning
 201  * less than zero, else it returns the allocated signal number
 202  * @put_signal: indicate to the platform that this physical signal is not
 203  * running any DMA transfer and multiplexing can be recycled
 204  * @lli_buses: buses which LLIs can be fetched from: PL08X_AHB1 | PL08X_AHB2
 205  * @mem_buses: buses which memory can be accessed from: PL08X_AHB1 | PL08X_AHB2
 206  */
 207 struct pl08x_platform_data {
 208         struct pl08x_channel_data *slave_channels;
 209         unsigned int num_slave_channels;
 210         struct pl08x_channel_data memcpy_channel;
 211         int (*get_signal)(struct pl08x_dma_chan *);
 212         void (*put_signal)(struct pl08x_dma_chan *);
 213         u8 lli_buses;
 214         u8 mem_buses;
 215 };
 216
 217 #ifdef CONFIG_AMBA_PL08X
 218 bool pl08x_filter_id(struct dma_chan *chan, void *chan_id);
 219 #else
 220 static inline bool pl08x_filter_id(struct dma_chan *chan, void *chan_id)
 221 {
 222         return false;
 223 }
 224 #endif
 225
 226 #endif  /* AMBA_PL08X_H */