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staging: rtl8192e: Fix sparse (non-endian) messages - Part I
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / staging / rtl8192e / r8192E_phy.c
blob96ccbd5b25d1a4ddcd5270abc9cea9c7be97d860
1 /******************************************************************************
2 * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved.
3 *
4 * This program is distributed in the hope that it will be useful, but WITHOUT
5 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
6 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
7 * more details.
8 *
9 * You should have received a copy of the GNU General Public License along with
10 * this program; if not, write to the Free Software Foundation, Inc.,
11 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
12 *
13 * The full GNU General Public License is included in this distribution in the
14 * file called LICENSE.
15 *
16 * Contact Information:
17 * wlanfae <wlanfae@realtek.com>
18 ******************************************************************************/
19
20 #include "rtl_core.h"
21 #include "r8192E_hw.h"
22 #include "r8192E_phyreg.h"
23 #include "r8190P_rtl8256.h"
24 #include "r8192E_phy.h"
25 #include "rtl_dm.h"
26 #include "dot11d.h"
27
28 #include "r8192E_hwimg.h"
29
30 static u32 RF_CHANNEL_TABLE_ZEBRA[] = {
31 0,
32 0x085c,
33 0x08dc,
34 0x095c,
35 0x09dc,
36 0x0a5c,
37 0x0adc,
38 0x0b5c,
39 0x0bdc,
40 0x0c5c,
41 0x0cdc,
42 0x0d5c,
43 0x0ddc,
44 0x0e5c,
45 0x0f72,
46 };
47
48 /*************************Define local function prototype**********************/
49
50 static u32 phy_FwRFSerialRead(struct net_device *dev,
51 enum rf90_radio_path eRFPath,
52 u32 Offset);
53 static void phy_FwRFSerialWrite(struct net_device *dev,
54 enum rf90_radio_path eRFPath,
55 u32 Offset, u32 Data);
56 u32 rtl8192_CalculateBitShift(u32 dwBitMask)
57 {
58 u32 i;
59 for (i = 0; i <= 31; i++) {
60 if (((dwBitMask >> i) & 0x1) == 1)
61 break;
62 }
63 return i;
64 }
65
66 u8 rtl8192_phy_CheckIsLegalRFPath(struct net_device *dev, u32 eRFPath)
67 {
68 u8 ret = 1;
69 struct r8192_priv *priv = rtllib_priv(dev);
70 if (priv->rf_type == RF_2T4R)
71 ret = 0;
72 else if (priv->rf_type == RF_1T2R) {
73 if (eRFPath == RF90_PATH_A || eRFPath == RF90_PATH_B)
74 ret = 1;
75 else if (eRFPath == RF90_PATH_C || eRFPath == RF90_PATH_D)
76 ret = 0;
77 }
78 return ret;
79 }
80
81 void rtl8192_setBBreg(struct net_device *dev, u32 dwRegAddr, u32 dwBitMask,
82 u32 dwData)
83 {
84
85 u32 OriginalValue, BitShift, NewValue;
86
87 if (dwBitMask != bMaskDWord) {
88 OriginalValue = read_nic_dword(dev, dwRegAddr);
89 BitShift = rtl8192_CalculateBitShift(dwBitMask);
90 NewValue = (((OriginalValue) & (~dwBitMask)) |
91 (dwData << BitShift));
92 write_nic_dword(dev, dwRegAddr, NewValue);
93 } else
94 write_nic_dword(dev, dwRegAddr, dwData);
95 return;
96 }
97
98 u32 rtl8192_QueryBBReg(struct net_device *dev, u32 dwRegAddr, u32 dwBitMask)
99 {
100 u32 Ret = 0, OriginalValue, BitShift;
101
102 OriginalValue = read_nic_dword(dev, dwRegAddr);
103 BitShift = rtl8192_CalculateBitShift(dwBitMask);
104 Ret = (OriginalValue & dwBitMask) >> BitShift;
105
106 return Ret;
107 }
108 u32 rtl8192_phy_RFSerialRead(struct net_device *dev,
109 enum rf90_radio_path eRFPath, u32 Offset)
110 {
111 struct r8192_priv *priv = rtllib_priv(dev);
112 u32 ret = 0;
113 u32 NewOffset = 0;
114 struct bb_reg_definition *pPhyReg = &priv->PHYRegDef[eRFPath];
115 Offset &= 0x3f;
116
117 if (priv->rf_chip == RF_8256) {
118 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0);
119 if (Offset >= 31) {
120 priv->RfReg0Value[eRFPath] |= 0x140;
121 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset,
122 bMaskDWord,
123 (priv->RfReg0Value[eRFPath]<<16));
124 NewOffset = Offset - 30;
125 } else if (Offset >= 16) {
126 priv->RfReg0Value[eRFPath] |= 0x100;
127 priv->RfReg0Value[eRFPath] &= (~0x40);
128 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset,
129 bMaskDWord,
130 (priv->RfReg0Value[eRFPath]<<16));
131
132 NewOffset = Offset - 15;
133 } else
134 NewOffset = Offset;
135 } else {
136 RT_TRACE((COMP_PHY|COMP_ERR), "check RF type here, need"
137 " to be 8256\n");
138 NewOffset = Offset;
139 }
140 rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadAddress,
141 NewOffset);
142 rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x0);
143 rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x1);
144
145 mdelay(1);
146
147 ret = rtl8192_QueryBBReg(dev, pPhyReg->rfLSSIReadBack,
148 bLSSIReadBackData);
149
150 if (priv->rf_chip == RF_8256) {
151 priv->RfReg0Value[eRFPath] &= 0xebf;
152
153 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord,
154 (priv->RfReg0Value[eRFPath] << 16));
155
156 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300, 0x3);
157 }
158
159
160 return ret;
161
162 }
163
164 void rtl8192_phy_RFSerialWrite(struct net_device *dev,
165 enum rf90_radio_path eRFPath, u32 Offset,
166 u32 Data)
167 {
168 struct r8192_priv *priv = rtllib_priv(dev);
169 u32 DataAndAddr = 0, NewOffset = 0;
170 struct bb_reg_definition *pPhyReg = &priv->PHYRegDef[eRFPath];
171
172 Offset &= 0x3f;
173 if (priv->rf_chip == RF_8256) {
174 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0);
175
176 if (Offset >= 31) {
177 priv->RfReg0Value[eRFPath] |= 0x140;
178 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset,
179 bMaskDWord,
180 (priv->RfReg0Value[eRFPath] << 16));
181 NewOffset = Offset - 30;
182 } else if (Offset >= 16) {
183 priv->RfReg0Value[eRFPath] |= 0x100;
184 priv->RfReg0Value[eRFPath] &= (~0x40);
185 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset,
186 bMaskDWord,
187 (priv->RfReg0Value[eRFPath] << 16));
188 NewOffset = Offset - 15;
189 } else
190 NewOffset = Offset;
191 } else {
192 RT_TRACE((COMP_PHY|COMP_ERR), "check RF type here, need to be"
193 " 8256\n");
194 NewOffset = Offset;
195 }
196
197 DataAndAddr = (Data<<16) | (NewOffset&0x3f);
198
199 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr);
200
201 if (Offset == 0x0)
202 priv->RfReg0Value[eRFPath] = Data;
203
204 if (priv->rf_chip == RF_8256) {
205 if (Offset != 0) {
206 priv->RfReg0Value[eRFPath] &= 0xebf;
207 rtl8192_setBBreg(
208 dev,
209 pPhyReg->rf3wireOffset,
210 bMaskDWord,
211 (priv->RfReg0Value[eRFPath] << 16));
212 }
213 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300, 0x3);
214 }
215 return;
216 }
217
218 void rtl8192_phy_SetRFReg(struct net_device *dev, enum rf90_radio_path eRFPath,
219 u32 RegAddr, u32 BitMask, u32 Data)
220 {
221 struct r8192_priv *priv = rtllib_priv(dev);
222 u32 Original_Value, BitShift, New_Value;
223
224 if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
225 return;
226 if (priv->rtllib->eRFPowerState != eRfOn && !priv->being_init_adapter)
227 return;
228
229 RT_TRACE(COMP_PHY, "FW RF CTRL is not ready now\n");
230 if (priv->Rf_Mode == RF_OP_By_FW) {
231 if (BitMask != bMask12Bits) {
232 Original_Value = phy_FwRFSerialRead(dev, eRFPath,
233 RegAddr);
234 BitShift = rtl8192_CalculateBitShift(BitMask);
235 New_Value = (((Original_Value) & (~BitMask)) |
236 (Data << BitShift));
237
238 phy_FwRFSerialWrite(dev, eRFPath, RegAddr, New_Value);
239 } else
240 phy_FwRFSerialWrite(dev, eRFPath, RegAddr, Data);
241 udelay(200);
242
243 } else {
244 if (BitMask != bMask12Bits) {
245 Original_Value = rtl8192_phy_RFSerialRead(dev, eRFPath,
246 RegAddr);
247 BitShift = rtl8192_CalculateBitShift(BitMask);
248 New_Value = (((Original_Value) & (~BitMask)) |
249 (Data << BitShift));
250
251 rtl8192_phy_RFSerialWrite(dev, eRFPath, RegAddr,
252 New_Value);
253 } else
254 rtl8192_phy_RFSerialWrite(dev, eRFPath, RegAddr, Data);
255 }
256 return;
257 }
258
259 u32 rtl8192_phy_QueryRFReg(struct net_device *dev, enum rf90_radio_path eRFPath,
260 u32 RegAddr, u32 BitMask)
261 {
262 u32 Original_Value, Readback_Value, BitShift;
263 struct r8192_priv *priv = rtllib_priv(dev);
264 if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
265 return 0;
266 if (priv->rtllib->eRFPowerState != eRfOn && !priv->being_init_adapter)
267 return 0;
268 down(&priv->rf_sem);
269 if (priv->Rf_Mode == RF_OP_By_FW) {
270 Original_Value = phy_FwRFSerialRead(dev, eRFPath, RegAddr);
271 udelay(200);
272 } else {
273 Original_Value = rtl8192_phy_RFSerialRead(dev, eRFPath,
274 RegAddr);
275 }
276 BitShift = rtl8192_CalculateBitShift(BitMask);
277 Readback_Value = (Original_Value & BitMask) >> BitShift;
278 up(&priv->rf_sem);
279 return Readback_Value;
280 }
281
282 static u32 phy_FwRFSerialRead(struct net_device *dev,
283 enum rf90_radio_path eRFPath, u32 Offset)
284 {
285 u32 retValue = 0;
286 u32 Data = 0;
287 u8 time = 0;
288 Data |= ((Offset & 0xFF) << 12);
289 Data |= ((eRFPath & 0x3) << 20);
290 Data |= 0x80000000;
291 while (read_nic_dword(dev, QPNR)&0x80000000) {
292 if (time++ < 100)
293 udelay(10);
294 else
295 break;
296 }
297 write_nic_dword(dev, QPNR, Data);
298 while (read_nic_dword(dev, QPNR) & 0x80000000) {
299 if (time++ < 100)
300 udelay(10);
301 else
302 return 0;
303 }
304 retValue = read_nic_dword(dev, RF_DATA);
305
306 return retValue;
307
308 } /* phy_FwRFSerialRead */
309
310 static void phy_FwRFSerialWrite(struct net_device *dev,
311 enum rf90_radio_path eRFPath,
312 u32 Offset, u32 Data)
313 {
314 u8 time = 0;
315
316 Data |= ((Offset & 0xFF) << 12);
317 Data |= ((eRFPath & 0x3) << 20);
318 Data |= 0x400000;
319 Data |= 0x80000000;
320
321 while (read_nic_dword(dev, QPNR) & 0x80000000) {
322 if (time++ < 100)
323 udelay(10);
324 else
325 break;
326 }
327 write_nic_dword(dev, QPNR, Data);
328
329 } /* phy_FwRFSerialWrite */
330
331
332 void rtl8192_phy_configmac(struct net_device *dev)
333 {
334 u32 dwArrayLen = 0, i = 0;
335 u32 *pdwArray = NULL;
336 struct r8192_priv *priv = rtllib_priv(dev);
337
338 if (priv->bTXPowerDataReadFromEEPORM) {
339 RT_TRACE(COMP_PHY, "Rtl819XMACPHY_Array_PG\n");
340 dwArrayLen = MACPHY_Array_PGLength;
341 pdwArray = Rtl819XMACPHY_Array_PG;
342
343 } else {
344 RT_TRACE(COMP_PHY, "Read rtl819XMACPHY_Array\n");
345 dwArrayLen = MACPHY_ArrayLength;
346 pdwArray = Rtl819XMACPHY_Array;
347 }
348 for (i = 0; i < dwArrayLen; i += 3) {
349 RT_TRACE(COMP_DBG, "The Rtl8190MACPHY_Array[0] is %x Rtl8190MAC"
350 "PHY_Array[1] is %x Rtl8190MACPHY_Array[2] is %x\n",
351 pdwArray[i], pdwArray[i+1], pdwArray[i+2]);
352 if (pdwArray[i] == 0x318)
353 pdwArray[i+2] = 0x00000800;
354 rtl8192_setBBreg(dev, pdwArray[i], pdwArray[i+1],
355 pdwArray[i+2]);
356 }
357 return;
358
359 }
360
361 void rtl8192_phyConfigBB(struct net_device *dev, u8 ConfigType)
362 {
363 int i;
364 u32 *Rtl819XPHY_REGArray_Table = NULL;
365 u32 *Rtl819XAGCTAB_Array_Table = NULL;
366 u16 AGCTAB_ArrayLen, PHY_REGArrayLen = 0;
367 struct r8192_priv *priv = rtllib_priv(dev);
368
369 AGCTAB_ArrayLen = AGCTAB_ArrayLength;
370 Rtl819XAGCTAB_Array_Table = Rtl819XAGCTAB_Array;
371 if (priv->rf_type == RF_2T4R) {
372 PHY_REGArrayLen = PHY_REGArrayLength;
373 Rtl819XPHY_REGArray_Table = Rtl819XPHY_REGArray;
374 } else if (priv->rf_type == RF_1T2R) {
375 PHY_REGArrayLen = PHY_REG_1T2RArrayLength;
376 Rtl819XPHY_REGArray_Table = Rtl819XPHY_REG_1T2RArray;
377 }
378
379 if (ConfigType == BaseBand_Config_PHY_REG) {
380 for (i = 0; i < PHY_REGArrayLen; i += 2) {
381 rtl8192_setBBreg(dev, Rtl819XPHY_REGArray_Table[i],
382 bMaskDWord,
383 Rtl819XPHY_REGArray_Table[i+1]);
384 RT_TRACE(COMP_DBG, "i: %x, The Rtl819xUsbPHY_REGArray"
385 "[0] is %x Rtl819xUsbPHY_REGArray[1] is %x\n",
386 i, Rtl819XPHY_REGArray_Table[i],
387 Rtl819XPHY_REGArray_Table[i+1]);
388 }
389 } else if (ConfigType == BaseBand_Config_AGC_TAB) {
390 for (i = 0; i < AGCTAB_ArrayLen; i += 2) {
391 rtl8192_setBBreg(dev, Rtl819XAGCTAB_Array_Table[i],
392 bMaskDWord,
393 Rtl819XAGCTAB_Array_Table[i+1]);
394 RT_TRACE(COMP_DBG, "i:%x, The rtl819XAGCTAB_Array[0] "
395 "is %x rtl819XAGCTAB_Array[1] is %x\n", i,
396 Rtl819XAGCTAB_Array_Table[i],
397 Rtl819XAGCTAB_Array_Table[i+1]);
398 }
399 }
400 return;
401 }
402
403 void rtl8192_InitBBRFRegDef(struct net_device *dev)
404 {
405 struct r8192_priv *priv = rtllib_priv(dev);
406
407 priv->PHYRegDef[RF90_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW;
408 priv->PHYRegDef[RF90_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW;
409 priv->PHYRegDef[RF90_PATH_C].rfintfs = rFPGA0_XCD_RFInterfaceSW;
410 priv->PHYRegDef[RF90_PATH_D].rfintfs = rFPGA0_XCD_RFInterfaceSW;
411
412 priv->PHYRegDef[RF90_PATH_A].rfintfi = rFPGA0_XAB_RFInterfaceRB;
413 priv->PHYRegDef[RF90_PATH_B].rfintfi = rFPGA0_XAB_RFInterfaceRB;
414 priv->PHYRegDef[RF90_PATH_C].rfintfi = rFPGA0_XCD_RFInterfaceRB;
415 priv->PHYRegDef[RF90_PATH_D].rfintfi = rFPGA0_XCD_RFInterfaceRB;
416
417 priv->PHYRegDef[RF90_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE;
418 priv->PHYRegDef[RF90_PATH_B].rfintfo = rFPGA0_XB_RFInterfaceOE;
419 priv->PHYRegDef[RF90_PATH_C].rfintfo = rFPGA0_XC_RFInterfaceOE;
420 priv->PHYRegDef[RF90_PATH_D].rfintfo = rFPGA0_XD_RFInterfaceOE;
421
422 priv->PHYRegDef[RF90_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE;
423 priv->PHYRegDef[RF90_PATH_B].rfintfe = rFPGA0_XB_RFInterfaceOE;
424 priv->PHYRegDef[RF90_PATH_C].rfintfe = rFPGA0_XC_RFInterfaceOE;
425 priv->PHYRegDef[RF90_PATH_D].rfintfe = rFPGA0_XD_RFInterfaceOE;
426
427 priv->PHYRegDef[RF90_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter;
428 priv->PHYRegDef[RF90_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter;
429 priv->PHYRegDef[RF90_PATH_C].rf3wireOffset = rFPGA0_XC_LSSIParameter;
430 priv->PHYRegDef[RF90_PATH_D].rf3wireOffset = rFPGA0_XD_LSSIParameter;
431
432 priv->PHYRegDef[RF90_PATH_A].rfLSSI_Select = rFPGA0_XAB_RFParameter;
433 priv->PHYRegDef[RF90_PATH_B].rfLSSI_Select = rFPGA0_XAB_RFParameter;
434 priv->PHYRegDef[RF90_PATH_C].rfLSSI_Select = rFPGA0_XCD_RFParameter;
435 priv->PHYRegDef[RF90_PATH_D].rfLSSI_Select = rFPGA0_XCD_RFParameter;
436
437 priv->PHYRegDef[RF90_PATH_A].rfTxGainStage = rFPGA0_TxGainStage;
438 priv->PHYRegDef[RF90_PATH_B].rfTxGainStage = rFPGA0_TxGainStage;
439 priv->PHYRegDef[RF90_PATH_C].rfTxGainStage = rFPGA0_TxGainStage;
440 priv->PHYRegDef[RF90_PATH_D].rfTxGainStage = rFPGA0_TxGainStage;
441
442 priv->PHYRegDef[RF90_PATH_A].rfHSSIPara1 = rFPGA0_XA_HSSIParameter1;
443 priv->PHYRegDef[RF90_PATH_B].rfHSSIPara1 = rFPGA0_XB_HSSIParameter1;
444 priv->PHYRegDef[RF90_PATH_C].rfHSSIPara1 = rFPGA0_XC_HSSIParameter1;
445 priv->PHYRegDef[RF90_PATH_D].rfHSSIPara1 = rFPGA0_XD_HSSIParameter1;
446
447 priv->PHYRegDef[RF90_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2;
448 priv->PHYRegDef[RF90_PATH_B].rfHSSIPara2 = rFPGA0_XB_HSSIParameter2;
449 priv->PHYRegDef[RF90_PATH_C].rfHSSIPara2 = rFPGA0_XC_HSSIParameter2;
450 priv->PHYRegDef[RF90_PATH_D].rfHSSIPara2 = rFPGA0_XD_HSSIParameter2;
451
452 priv->PHYRegDef[RF90_PATH_A].rfSwitchControl = rFPGA0_XAB_SwitchControl;
453 priv->PHYRegDef[RF90_PATH_B].rfSwitchControl = rFPGA0_XAB_SwitchControl;
454 priv->PHYRegDef[RF90_PATH_C].rfSwitchControl = rFPGA0_XCD_SwitchControl;
455 priv->PHYRegDef[RF90_PATH_D].rfSwitchControl = rFPGA0_XCD_SwitchControl;
456
457 priv->PHYRegDef[RF90_PATH_A].rfAGCControl1 = rOFDM0_XAAGCCore1;
458 priv->PHYRegDef[RF90_PATH_B].rfAGCControl1 = rOFDM0_XBAGCCore1;
459 priv->PHYRegDef[RF90_PATH_C].rfAGCControl1 = rOFDM0_XCAGCCore1;
460 priv->PHYRegDef[RF90_PATH_D].rfAGCControl1 = rOFDM0_XDAGCCore1;
461
462 priv->PHYRegDef[RF90_PATH_A].rfAGCControl2 = rOFDM0_XAAGCCore2;
463 priv->PHYRegDef[RF90_PATH_B].rfAGCControl2 = rOFDM0_XBAGCCore2;
464 priv->PHYRegDef[RF90_PATH_C].rfAGCControl2 = rOFDM0_XCAGCCore2;
465 priv->PHYRegDef[RF90_PATH_D].rfAGCControl2 = rOFDM0_XDAGCCore2;
466
467 priv->PHYRegDef[RF90_PATH_A].rfRxIQImbalance = rOFDM0_XARxIQImbalance;
468 priv->PHYRegDef[RF90_PATH_B].rfRxIQImbalance = rOFDM0_XBRxIQImbalance;
469 priv->PHYRegDef[RF90_PATH_C].rfRxIQImbalance = rOFDM0_XCRxIQImbalance;
470 priv->PHYRegDef[RF90_PATH_D].rfRxIQImbalance = rOFDM0_XDRxIQImbalance;
471
472 priv->PHYRegDef[RF90_PATH_A].rfRxAFE = rOFDM0_XARxAFE;
473 priv->PHYRegDef[RF90_PATH_B].rfRxAFE = rOFDM0_XBRxAFE;
474 priv->PHYRegDef[RF90_PATH_C].rfRxAFE = rOFDM0_XCRxAFE;
475 priv->PHYRegDef[RF90_PATH_D].rfRxAFE = rOFDM0_XDRxAFE;
476
477 priv->PHYRegDef[RF90_PATH_A].rfTxIQImbalance = rOFDM0_XATxIQImbalance;
478 priv->PHYRegDef[RF90_PATH_B].rfTxIQImbalance = rOFDM0_XBTxIQImbalance;
479 priv->PHYRegDef[RF90_PATH_C].rfTxIQImbalance = rOFDM0_XCTxIQImbalance;
480 priv->PHYRegDef[RF90_PATH_D].rfTxIQImbalance = rOFDM0_XDTxIQImbalance;
481
482 priv->PHYRegDef[RF90_PATH_A].rfTxAFE = rOFDM0_XATxAFE;
483 priv->PHYRegDef[RF90_PATH_B].rfTxAFE = rOFDM0_XBTxAFE;
484 priv->PHYRegDef[RF90_PATH_C].rfTxAFE = rOFDM0_XCTxAFE;
485 priv->PHYRegDef[RF90_PATH_D].rfTxAFE = rOFDM0_XDTxAFE;
486
487 priv->PHYRegDef[RF90_PATH_A].rfLSSIReadBack = rFPGA0_XA_LSSIReadBack;
488 priv->PHYRegDef[RF90_PATH_B].rfLSSIReadBack = rFPGA0_XB_LSSIReadBack;
489 priv->PHYRegDef[RF90_PATH_C].rfLSSIReadBack = rFPGA0_XC_LSSIReadBack;
490 priv->PHYRegDef[RF90_PATH_D].rfLSSIReadBack = rFPGA0_XD_LSSIReadBack;
491
492 }
493
494 bool rtl8192_phy_checkBBAndRF(struct net_device *dev,
495 enum hw90_block CheckBlock,
496 enum rf90_radio_path eRFPath)
497 {
498 bool ret = true;
499 u32 i, CheckTimes = 4, dwRegRead = 0;
500 u32 WriteAddr[4];
501 u32 WriteData[] = {0xfffff027, 0xaa55a02f, 0x00000027, 0x55aa502f};
502
503 WriteAddr[HW90_BLOCK_MAC] = 0x100;
504 WriteAddr[HW90_BLOCK_PHY0] = 0x900;
505 WriteAddr[HW90_BLOCK_PHY1] = 0x800;
506 WriteAddr[HW90_BLOCK_RF] = 0x3;
507 RT_TRACE(COMP_PHY, "=======>%s(), CheckBlock:%d\n", __func__,
508 CheckBlock);
509 for (i = 0; i < CheckTimes; i++) {
510 switch (CheckBlock) {
511 case HW90_BLOCK_MAC:
512 RT_TRACE(COMP_ERR, "PHY_CheckBBRFOK(): Never Write "
513 "0x100 here!");
514 break;
515
516 case HW90_BLOCK_PHY0:
517 case HW90_BLOCK_PHY1:
518 write_nic_dword(dev, WriteAddr[CheckBlock],
519 WriteData[i]);
520 dwRegRead = read_nic_dword(dev, WriteAddr[CheckBlock]);
521 break;
522
523 case HW90_BLOCK_RF:
524 WriteData[i] &= 0xfff;
525 rtl8192_phy_SetRFReg(dev, eRFPath,
526 WriteAddr[HW90_BLOCK_RF],
527 bMask12Bits, WriteData[i]);
528 mdelay(10);
529 dwRegRead = rtl8192_phy_QueryRFReg(dev, eRFPath,
530 WriteAddr[HW90_BLOCK_RF],
531 bMaskDWord);
532 mdelay(10);
533 break;
534
535 default:
536 ret = false;
537 break;
538 }
539
540
541 if (dwRegRead != WriteData[i]) {
542 RT_TRACE(COMP_ERR, "====>error=====dwRegRead: %x, "
543 "WriteData: %x\n", dwRegRead, WriteData[i]);
544 ret = false;
545 break;
546 }
547 }
548
549 return ret;
550 }
551
552 bool rtl8192_BB_Config_ParaFile(struct net_device *dev)
553 {
554 struct r8192_priv *priv = rtllib_priv(dev);
555 bool rtStatus = true;
556 u8 bRegValue = 0, eCheckItem = 0;
557 u32 dwRegValue = 0;
558
559 bRegValue = read_nic_byte(dev, BB_GLOBAL_RESET);
560 write_nic_byte(dev, BB_GLOBAL_RESET, (bRegValue|BB_GLOBAL_RESET_BIT));
561
562 dwRegValue = read_nic_dword(dev, CPU_GEN);
563 write_nic_dword(dev, CPU_GEN, (dwRegValue&(~CPU_GEN_BB_RST)));
564
565 for (eCheckItem = (enum hw90_block)HW90_BLOCK_PHY0;
566 eCheckItem <= HW90_BLOCK_PHY1; eCheckItem++) {
567 rtStatus = rtl8192_phy_checkBBAndRF(dev,
568 (enum hw90_block)eCheckItem,
569 (enum rf90_radio_path)0);
570 if (rtStatus != true) {
571 RT_TRACE((COMP_ERR | COMP_PHY), "PHY_RF8256_Config():"
572 "Check PHY%d Fail!!\n", eCheckItem-1);
573 return rtStatus;
574 }
575 }
576 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0x0);
577 rtl8192_phyConfigBB(dev, BaseBand_Config_PHY_REG);
578
579 dwRegValue = read_nic_dword(dev, CPU_GEN);
580 write_nic_dword(dev, CPU_GEN, (dwRegValue|CPU_GEN_BB_RST));
581
582 rtl8192_phyConfigBB(dev, BaseBand_Config_AGC_TAB);
583
584 if (priv->IC_Cut > VERSION_8190_BD) {
585 if (priv->rf_type == RF_2T4R)
586 dwRegValue = (priv->AntennaTxPwDiff[2]<<8 |
587 priv->AntennaTxPwDiff[1]<<4 |
588 priv->AntennaTxPwDiff[0]);
589 else
590 dwRegValue = 0x0;
591 rtl8192_setBBreg(dev, rFPGA0_TxGainStage,
592 (bXBTxAGC|bXCTxAGC|bXDTxAGC), dwRegValue);
593
594
595 dwRegValue = priv->CrystalCap;
596 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, bXtalCap92x,
597 dwRegValue);
598 }
599
600 return rtStatus;
601 }
602 bool rtl8192_BBConfig(struct net_device *dev)
603 {
604 bool rtStatus = true;
605
606 rtl8192_InitBBRFRegDef(dev);
607 rtStatus = rtl8192_BB_Config_ParaFile(dev);
608 return rtStatus;
609 }
610
611 void rtl8192_phy_getTxPower(struct net_device *dev)
612 {
613 struct r8192_priv *priv = rtllib_priv(dev);
614
615 priv->MCSTxPowerLevelOriginalOffset[0] =
616 read_nic_dword(dev, rTxAGC_Rate18_06);
617 priv->MCSTxPowerLevelOriginalOffset[1] =
618 read_nic_dword(dev, rTxAGC_Rate54_24);
619 priv->MCSTxPowerLevelOriginalOffset[2] =
620 read_nic_dword(dev, rTxAGC_Mcs03_Mcs00);
621 priv->MCSTxPowerLevelOriginalOffset[3] =
622 read_nic_dword(dev, rTxAGC_Mcs07_Mcs04);
623 priv->MCSTxPowerLevelOriginalOffset[4] =
624 read_nic_dword(dev, rTxAGC_Mcs11_Mcs08);
625 priv->MCSTxPowerLevelOriginalOffset[5] =
626 read_nic_dword(dev, rTxAGC_Mcs15_Mcs12);
627
628 priv->DefaultInitialGain[0] = read_nic_byte(dev, rOFDM0_XAAGCCore1);
629 priv->DefaultInitialGain[1] = read_nic_byte(dev, rOFDM0_XBAGCCore1);
630 priv->DefaultInitialGain[2] = read_nic_byte(dev, rOFDM0_XCAGCCore1);
631 priv->DefaultInitialGain[3] = read_nic_byte(dev, rOFDM0_XDAGCCore1);
632 RT_TRACE(COMP_INIT, "Default initial gain (c50=0x%x, c58=0x%x, "
633 "c60=0x%x, c68=0x%x)\n",
634 priv->DefaultInitialGain[0], priv->DefaultInitialGain[1],
635 priv->DefaultInitialGain[2], priv->DefaultInitialGain[3]);
636
637 priv->framesync = read_nic_byte(dev, rOFDM0_RxDetector3);
638 priv->framesyncC34 = read_nic_dword(dev, rOFDM0_RxDetector2);
639 RT_TRACE(COMP_INIT, "Default framesync (0x%x) = 0x%x\n",
640 rOFDM0_RxDetector3, priv->framesync);
641 priv->SifsTime = read_nic_word(dev, SIFS);
642 return;
643 }
644
645 void rtl8192_phy_setTxPower(struct net_device *dev, u8 channel)
646 {
647 struct r8192_priv *priv = rtllib_priv(dev);
648 u8 powerlevel = 0, powerlevelOFDM24G = 0;
649 char ant_pwr_diff;
650 u32 u4RegValue;
651
652 if (priv->epromtype == EEPROM_93C46) {
653 powerlevel = priv->TxPowerLevelCCK[channel-1];
654 powerlevelOFDM24G = priv->TxPowerLevelOFDM24G[channel-1];
655 } else if (priv->epromtype == EEPROM_93C56) {
656 if (priv->rf_type == RF_1T2R) {
657 powerlevel = priv->TxPowerLevelCCK_C[channel-1];
658 powerlevelOFDM24G = priv->TxPowerLevelOFDM24G_C[channel-1];
659 } else if (priv->rf_type == RF_2T4R) {
660 powerlevel = priv->TxPowerLevelCCK_A[channel-1];
661 powerlevelOFDM24G = priv->TxPowerLevelOFDM24G_A[channel-1];
662
663 ant_pwr_diff = priv->TxPowerLevelOFDM24G_C[channel-1]
664 - priv->TxPowerLevelOFDM24G_A[channel-1];
665
666 priv->RF_C_TxPwDiff = ant_pwr_diff;
667
668 ant_pwr_diff &= 0xf;
669
670 priv->AntennaTxPwDiff[2] = 0;
671 priv->AntennaTxPwDiff[1] = (u8)(ant_pwr_diff);
672 priv->AntennaTxPwDiff[0] = 0;
673
674 u4RegValue = (priv->AntennaTxPwDiff[2]<<8 |
675 priv->AntennaTxPwDiff[1]<<4 |
676 priv->AntennaTxPwDiff[0]);
677
678 rtl8192_setBBreg(dev, rFPGA0_TxGainStage,
679 (bXBTxAGC|bXCTxAGC|bXDTxAGC), u4RegValue);
680 }
681 }
682 switch (priv->rf_chip) {
683 case RF_8225:
684 break;
685 case RF_8256:
686 PHY_SetRF8256CCKTxPower(dev, powerlevel);
687 PHY_SetRF8256OFDMTxPower(dev, powerlevelOFDM24G);
688 break;
689 case RF_8258:
690 break;
691 default:
692 RT_TRACE(COMP_ERR, "unknown rf chip in funtion %s()\n",
693 __func__);
694 break;
695 }
696 return;
697 }
698
699 bool rtl8192_phy_RFConfig(struct net_device *dev)
700 {
701 struct r8192_priv *priv = rtllib_priv(dev);
702 bool rtStatus = true;
703 switch (priv->rf_chip) {
704 case RF_8225:
705 break;
706 case RF_8256:
707 rtStatus = PHY_RF8256_Config(dev);
708 break;
709
710 case RF_8258:
711 break;
712 case RF_PSEUDO_11N:
713 break;
714
715 default:
716 RT_TRACE(COMP_ERR, "error chip id\n");
717 break;
718 }
719 return rtStatus;
720 }
721
722 void rtl8192_phy_updateInitGain(struct net_device *dev)
723 {
724 return;
725 }
726
727 u8 rtl8192_phy_ConfigRFWithHeaderFile(struct net_device *dev,
728 enum rf90_radio_path eRFPath)
729 {
730
731 int i;
732 u8 ret = 0;
733
734 switch (eRFPath) {
735 case RF90_PATH_A:
736 for (i = 0; i < RadioA_ArrayLength; i += 2) {
737 if (Rtl819XRadioA_Array[i] == 0xfe) {
738 msleep(100);
739 continue;
740 }
741 rtl8192_phy_SetRFReg(dev, eRFPath,
742 Rtl819XRadioA_Array[i],
743 bMask12Bits,
744 Rtl819XRadioA_Array[i+1]);
745
746 }
747 break;
748 case RF90_PATH_B:
749 for (i = 0; i < RadioB_ArrayLength; i += 2) {
750 if (Rtl819XRadioB_Array[i] == 0xfe) {
751 msleep(100);
752 continue;
753 }
754 rtl8192_phy_SetRFReg(dev, eRFPath,
755 Rtl819XRadioB_Array[i],
756 bMask12Bits,
757 Rtl819XRadioB_Array[i+1]);
758
759 }
760 break;
761 case RF90_PATH_C:
762 for (i = 0; i < RadioC_ArrayLength; i += 2) {
763 if (Rtl819XRadioC_Array[i] == 0xfe) {
764 msleep(100);
765 continue;
766 }
767 rtl8192_phy_SetRFReg(dev, eRFPath,
768 Rtl819XRadioC_Array[i],
769 bMask12Bits,
770 Rtl819XRadioC_Array[i+1]);
771
772 }
773 break;
774 case RF90_PATH_D:
775 for (i = 0; i < RadioD_ArrayLength; i += 2) {
776 if (Rtl819XRadioD_Array[i] == 0xfe) {
777 msleep(100);
778 continue;
779 }
780 rtl8192_phy_SetRFReg(dev, eRFPath,
781 Rtl819XRadioD_Array[i], bMask12Bits,
782 Rtl819XRadioD_Array[i+1]);
783
784 }
785 break;
786 default:
787 break;
788 }
789
790 return ret;
791
792 }
793 void rtl8192_SetTxPowerLevel(struct net_device *dev, u8 channel)
794 {
795 struct r8192_priv *priv = rtllib_priv(dev);
796 u8 powerlevel = priv->TxPowerLevelCCK[channel-1];
797 u8 powerlevelOFDM24G = priv->TxPowerLevelOFDM24G[channel-1];
798
799 switch (priv->rf_chip) {
800 case RF_8225:
801 break;
802
803 case RF_8256:
804 PHY_SetRF8256CCKTxPower(dev, powerlevel);
805 PHY_SetRF8256OFDMTxPower(dev, powerlevelOFDM24G);
806 break;
807
808 case RF_8258:
809 break;
810 default:
811 RT_TRACE(COMP_ERR, "unknown rf chip ID in rtl8192_SetTxPower"
812 "Level()\n");
813 break;
814 }
815 return;
816 }
817
818 u8 rtl8192_phy_SetSwChnlCmdArray(struct sw_chnl_cmd *CmdTable, u32 CmdTableIdx,
819 u32 CmdTableSz, enum sw_chnl_cmd_id CmdID,
820 u32 Para1, u32 Para2, u32 msDelay)
821 {
822 struct sw_chnl_cmd *pCmd;
823
824 if (CmdTable == NULL) {
825 RT_TRACE(COMP_ERR, "phy_SetSwChnlCmdArray(): CmdTable cannot "
826 "be NULL.\n");
827 return false;
828 }
829 if (CmdTableIdx >= CmdTableSz) {
830 RT_TRACE(COMP_ERR, "phy_SetSwChnlCmdArray(): Access invalid"
831 " index, please check size of the table, CmdTableIdx:"
832 "%d, CmdTableSz:%d\n",
833 CmdTableIdx, CmdTableSz);
834 return false;
835 }
836
837 pCmd = CmdTable + CmdTableIdx;
838 pCmd->CmdID = CmdID;
839 pCmd->Para1 = Para1;
840 pCmd->Para2 = Para2;
841 pCmd->msDelay = msDelay;
842
843 return true;
844 }
845
846 u8 rtl8192_phy_SwChnlStepByStep(struct net_device *dev, u8 channel, u8 *stage,
847 u8 *step, u32 *delay)
848 {
849 struct r8192_priv *priv = rtllib_priv(dev);
850 struct sw_chnl_cmd PreCommonCmd[MAX_PRECMD_CNT];
851 u32 PreCommonCmdCnt;
852 struct sw_chnl_cmd PostCommonCmd[MAX_POSTCMD_CNT];
853 u32 PostCommonCmdCnt;
854 struct sw_chnl_cmd RfDependCmd[MAX_RFDEPENDCMD_CNT];
855 u32 RfDependCmdCnt;
856 struct sw_chnl_cmd *CurrentCmd = NULL;
857 u8 eRFPath;
858
859 RT_TRACE(COMP_TRACE, "====>%s()====stage:%d, step:%d, channel:%d\n",
860 __func__, *stage, *step, channel);
861
862 if (!IsLegalChannel(priv->rtllib, channel)) {
863 RT_TRACE(COMP_ERR, "=============>set to illegal channel:%d\n",
864 channel);
865 return true;
866 }
867
868 {
869 PreCommonCmdCnt = 0;
870 rtl8192_phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++,
871 MAX_PRECMD_CNT, CmdID_SetTxPowerLevel,
872 0, 0, 0);
873 rtl8192_phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++,
874 MAX_PRECMD_CNT, CmdID_End, 0, 0, 0);
875
876 PostCommonCmdCnt = 0;
877
878 rtl8192_phy_SetSwChnlCmdArray(PostCommonCmd, PostCommonCmdCnt++,
879 MAX_POSTCMD_CNT, CmdID_End, 0, 0, 0);
880
881 RfDependCmdCnt = 0;
882 switch (priv->rf_chip) {
883 case RF_8225:
884 if (!(channel >= 1 && channel <= 14)) {
885 RT_TRACE(COMP_ERR, "illegal channel for Zebra "
886 "8225: %d\n", channel);
887 return false;
888 }
889 rtl8192_phy_SetSwChnlCmdArray(RfDependCmd,
890 RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
891 CmdID_RF_WriteReg, rZebra1_Channel,
892 RF_CHANNEL_TABLE_ZEBRA[channel], 10);
893 rtl8192_phy_SetSwChnlCmdArray(RfDependCmd,
894 RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
895 CmdID_End, 0, 0, 0);
896 break;
897
898 case RF_8256:
899 if (!(channel >= 1 && channel <= 14)) {
900 RT_TRACE(COMP_ERR, "illegal channel for Zebra"
901 " 8256: %d\n", channel);
902 return false;
903 }
904 rtl8192_phy_SetSwChnlCmdArray(RfDependCmd,
905 RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
906 CmdID_RF_WriteReg, rZebra1_Channel, channel,
907 10);
908 rtl8192_phy_SetSwChnlCmdArray(RfDependCmd,
909 RfDependCmdCnt++,
910 MAX_RFDEPENDCMD_CNT,
911 CmdID_End, 0, 0, 0);
912 break;
913
914 case RF_8258:
915 break;
916
917 default:
918 RT_TRACE(COMP_ERR, "Unknown RFChipID: %d\n",
919 priv->rf_chip);
920 return false;
921 break;
922 }
923
924
925 do {
926 switch (*stage) {
927 case 0:
928 CurrentCmd = &PreCommonCmd[*step];
929 break;
930 case 1:
931 CurrentCmd = &RfDependCmd[*step];
932 break;
933 case 2:
934 CurrentCmd = &PostCommonCmd[*step];
935 break;
936 }
937
938 if (CurrentCmd->CmdID == CmdID_End) {
939 if ((*stage) == 2) {
940 return true;
941 } else {
942 (*stage)++;
943 (*step) = 0;
944 continue;
945 }
946 }
947
948 switch (CurrentCmd->CmdID) {
949 case CmdID_SetTxPowerLevel:
950 if (priv->IC_Cut > (u8)VERSION_8190_BD)
951 rtl8192_SetTxPowerLevel(dev, channel);
952 break;
953 case CmdID_WritePortUlong:
954 write_nic_dword(dev, CurrentCmd->Para1,
955 CurrentCmd->Para2);
956 break;
957 case CmdID_WritePortUshort:
958 write_nic_word(dev, CurrentCmd->Para1,
959 (u16)CurrentCmd->Para2);
960 break;
961 case CmdID_WritePortUchar:
962 write_nic_byte(dev, CurrentCmd->Para1,
963 (u8)CurrentCmd->Para2);
964 break;
965 case CmdID_RF_WriteReg:
966 for (eRFPath = 0; eRFPath <
967 priv->NumTotalRFPath; eRFPath++)
968 rtl8192_phy_SetRFReg(dev,
969 (enum rf90_radio_path)eRFPath,
970 CurrentCmd->Para1, bMask12Bits,
971 CurrentCmd->Para2<<7);
972 break;
973 default:
974 break;
975 }
976
977 break;
978 } while (true);
979 } /*for (Number of RF paths)*/
980
981 (*delay) = CurrentCmd->msDelay;
982 (*step)++;
983 return false;
984 }
985
986 void rtl8192_phy_FinishSwChnlNow(struct net_device *dev, u8 channel)
987 {
988 struct r8192_priv *priv = rtllib_priv(dev);
989 u32 delay = 0;
990
991 while (!rtl8192_phy_SwChnlStepByStep(dev, channel, &priv->SwChnlStage,
992 &priv->SwChnlStep, &delay)) {
993 if (delay > 0)
994 msleep(delay);
995 if (IS_NIC_DOWN(priv))
996 break;
997 }
998 }
999 void rtl8192_SwChnl_WorkItem(struct net_device *dev)
1000 {
1001
1002 struct r8192_priv *priv = rtllib_priv(dev);
1003
1004 RT_TRACE(COMP_TRACE, "==> SwChnlCallback819xUsbWorkItem()\n");
1005
1006 RT_TRACE(COMP_TRACE, "=====>--%s(), set chan:%d, priv:%p\n", __func__,
1007 priv->chan, priv);
1008
1009 rtl8192_phy_FinishSwChnlNow(dev , priv->chan);
1010
1011 RT_TRACE(COMP_TRACE, "<== SwChnlCallback819xUsbWorkItem()\n");
1012 }
1013
1014 u8 rtl8192_phy_SwChnl(struct net_device *dev, u8 channel)
1015 {
1016 struct r8192_priv *priv = rtllib_priv(dev);
1017 RT_TRACE(COMP_PHY, "=====>%s()\n", __func__);
1018 if (IS_NIC_DOWN(priv)) {
1019 RT_TRACE(COMP_ERR, "%s(): ERR !! driver is not up\n", __func__);
1020 return false;
1021 }
1022 if (priv->SwChnlInProgress)
1023 return false;
1024
1025
1026 switch (priv->rtllib->mode) {
1027 case WIRELESS_MODE_A:
1028 case WIRELESS_MODE_N_5G:
1029 if (channel <= 14) {
1030 RT_TRACE(COMP_ERR, "WIRELESS_MODE_A but channel<=14");
1031 return false;
1032 }
1033 break;
1034 case WIRELESS_MODE_B:
1035 if (channel > 14) {
1036 RT_TRACE(COMP_ERR, "WIRELESS_MODE_B but channel>14");
1037 return false;
1038 }
1039 break;
1040 case WIRELESS_MODE_G:
1041 case WIRELESS_MODE_N_24G:
1042 if (channel > 14) {
1043 RT_TRACE(COMP_ERR, "WIRELESS_MODE_G but channel>14");
1044 return false;
1045 }
1046 break;
1047 }
1048
1049 priv->SwChnlInProgress = true;
1050 if (channel == 0)
1051 channel = 1;
1052
1053 priv->chan = channel;
1054
1055 priv->SwChnlStage = 0;
1056 priv->SwChnlStep = 0;
1057
1058 if (!IS_NIC_DOWN(priv))
1059 rtl8192_SwChnl_WorkItem(dev);
1060 priv->SwChnlInProgress = false;
1061 return true;
1062 }
1063
1064 static void CCK_Tx_Power_Track_BW_Switch_TSSI(struct net_device *dev)
1065 {
1066 struct r8192_priv *priv = rtllib_priv(dev);
1067
1068 switch (priv->CurrentChannelBW) {
1069 case HT_CHANNEL_WIDTH_20:
1070 priv->CCKPresentAttentuation =
1071 priv->CCKPresentAttentuation_20Mdefault +
1072 priv->CCKPresentAttentuation_difference;
1073
1074 if (priv->CCKPresentAttentuation >
1075 (CCKTxBBGainTableLength-1))
1076 priv->CCKPresentAttentuation =
1077 CCKTxBBGainTableLength-1;
1078 if (priv->CCKPresentAttentuation < 0)
1079 priv->CCKPresentAttentuation = 0;
1080
1081 RT_TRACE(COMP_POWER_TRACKING, "20M, priv->CCKPresent"
1082 "Attentuation = %d\n",
1083 priv->CCKPresentAttentuation);
1084
1085 if (priv->rtllib->current_network.channel == 14 &&
1086 !priv->bcck_in_ch14) {
1087 priv->bcck_in_ch14 = true;
1088 dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1089 } else if (priv->rtllib->current_network.channel !=
1090 14 && priv->bcck_in_ch14) {
1091 priv->bcck_in_ch14 = false;
1092 dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1093 } else {
1094 dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1095 }
1096 break;
1097
1098 case HT_CHANNEL_WIDTH_20_40:
1099 priv->CCKPresentAttentuation =
1100 priv->CCKPresentAttentuation_40Mdefault +
1101 priv->CCKPresentAttentuation_difference;
1102
1103 RT_TRACE(COMP_POWER_TRACKING, "40M, priv->CCKPresent"
1104 "Attentuation = %d\n",
1105 priv->CCKPresentAttentuation);
1106 if (priv->CCKPresentAttentuation >
1107 (CCKTxBBGainTableLength - 1))
1108 priv->CCKPresentAttentuation =
1109 CCKTxBBGainTableLength-1;
1110 if (priv->CCKPresentAttentuation < 0)
1111 priv->CCKPresentAttentuation = 0;
1112
1113 if (priv->rtllib->current_network.channel == 14 &&
1114 !priv->bcck_in_ch14) {
1115 priv->bcck_in_ch14 = true;
1116 dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1117 } else if (priv->rtllib->current_network.channel != 14
1118 && priv->bcck_in_ch14) {
1119 priv->bcck_in_ch14 = false;
1120 dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1121 } else {
1122 dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1123 }
1124 break;
1125 }
1126 }
1127
1128 static void CCK_Tx_Power_Track_BW_Switch_ThermalMeter(struct net_device *dev)
1129 {
1130 struct r8192_priv *priv = rtllib_priv(dev);
1131
1132 if (priv->rtllib->current_network.channel == 14 &&
1133 !priv->bcck_in_ch14)
1134 priv->bcck_in_ch14 = true;
1135 else if (priv->rtllib->current_network.channel != 14 &&
1136 priv->bcck_in_ch14)
1137 priv->bcck_in_ch14 = false;
1138
1139 switch (priv->CurrentChannelBW) {
1140 case HT_CHANNEL_WIDTH_20:
1141 if (priv->Record_CCK_20Mindex == 0)
1142 priv->Record_CCK_20Mindex = 6;
1143 priv->CCK_index = priv->Record_CCK_20Mindex;
1144 RT_TRACE(COMP_POWER_TRACKING, "20MHz, CCK_Tx_Power_Track_BW_"
1145 "Switch_ThermalMeter(),CCK_index = %d\n",
1146 priv->CCK_index);
1147 break;
1148
1149 case HT_CHANNEL_WIDTH_20_40:
1150 priv->CCK_index = priv->Record_CCK_40Mindex;
1151 RT_TRACE(COMP_POWER_TRACKING, "40MHz, CCK_Tx_Power_Track_BW_"
1152 "Switch_ThermalMeter(), CCK_index = %d\n",
1153 priv->CCK_index);
1154 break;
1155 }
1156 dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1157 }
1158
1159 static void CCK_Tx_Power_Track_BW_Switch(struct net_device *dev)
1160 {
1161 struct r8192_priv *priv = rtllib_priv(dev);
1162
1163 if (priv->IC_Cut >= IC_VersionCut_D)
1164 CCK_Tx_Power_Track_BW_Switch_TSSI(dev);
1165 else
1166 CCK_Tx_Power_Track_BW_Switch_ThermalMeter(dev);
1167 }
1168
1169 void rtl8192_SetBWModeWorkItem(struct net_device *dev)
1170 {
1171
1172 struct r8192_priv *priv = rtllib_priv(dev);
1173 u8 regBwOpMode;
1174
1175 RT_TRACE(COMP_SWBW, "==>rtl8192_SetBWModeWorkItem() Switch to %s "
1176 "bandwidth\n", priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20 ?
1177 "20MHz" : "40MHz")
1178
1179
1180 if (priv->rf_chip == RF_PSEUDO_11N) {
1181 priv->SetBWModeInProgress = false;
1182 return;
1183 }
1184 if (IS_NIC_DOWN(priv)) {
1185 RT_TRACE(COMP_ERR, "%s(): ERR!! driver is not up\n", __func__);
1186 return;
1187 }
1188 regBwOpMode = read_nic_byte(dev, BW_OPMODE);
1189
1190 switch (priv->CurrentChannelBW) {
1191 case HT_CHANNEL_WIDTH_20:
1192 regBwOpMode |= BW_OPMODE_20MHZ;
1193 write_nic_byte(dev, BW_OPMODE, regBwOpMode);
1194 break;
1195
1196 case HT_CHANNEL_WIDTH_20_40:
1197 regBwOpMode &= ~BW_OPMODE_20MHZ;
1198 write_nic_byte(dev, BW_OPMODE, regBwOpMode);
1199 break;
1200
1201 default:
1202 RT_TRACE(COMP_ERR, "SetChannelBandwidth819xUsb(): unknown "
1203 "Bandwidth: %#X\n", priv->CurrentChannelBW);
1204 break;
1205 }
1206
1207 switch (priv->CurrentChannelBW) {
1208 case HT_CHANNEL_WIDTH_20:
1209 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x0);
1210 rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x0);
1211
1212 if (!priv->btxpower_tracking) {
1213 write_nic_dword(dev, rCCK0_TxFilter1, 0x1a1b0000);
1214 write_nic_dword(dev, rCCK0_TxFilter2, 0x090e1317);
1215 write_nic_dword(dev, rCCK0_DebugPort, 0x00000204);
1216 } else {
1217 CCK_Tx_Power_Track_BW_Switch(dev);
1218 }
1219
1220 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 1);
1221
1222 break;
1223 case HT_CHANNEL_WIDTH_20_40:
1224 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x1);
1225 rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x1);
1226
1227 if (!priv->btxpower_tracking) {
1228 write_nic_dword(dev, rCCK0_TxFilter1, 0x35360000);
1229 write_nic_dword(dev, rCCK0_TxFilter2, 0x121c252e);
1230 write_nic_dword(dev, rCCK0_DebugPort, 0x00000409);
1231 } else {
1232 CCK_Tx_Power_Track_BW_Switch(dev);
1233 }
1234
1235 rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand,
1236 (priv->nCur40MhzPrimeSC>>1));
1237 rtl8192_setBBreg(dev, rOFDM1_LSTF, 0xC00,
1238 priv->nCur40MhzPrimeSC);
1239
1240 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 0);
1241 break;
1242 default:
1243 RT_TRACE(COMP_ERR, "SetChannelBandwidth819xUsb(): unknown "
1244 "Bandwidth: %#X\n", priv->CurrentChannelBW);
1245 break;
1246
1247 }
1248
1249 switch (priv->rf_chip) {
1250 case RF_8225:
1251 break;
1252
1253 case RF_8256:
1254 PHY_SetRF8256Bandwidth(dev, priv->CurrentChannelBW);
1255 break;
1256
1257 case RF_8258:
1258 break;
1259
1260 case RF_PSEUDO_11N:
1261 break;
1262
1263 default:
1264 RT_TRACE(COMP_ERR, "Unknown RFChipID: %d\n", priv->rf_chip);
1265 break;
1266 }
1267
1268 atomic_dec(&(priv->rtllib->atm_swbw));
1269 priv->SetBWModeInProgress = false;
1270
1271 RT_TRACE(COMP_SWBW, "<==SetBWMode819xUsb()");
1272 }
1273
1274 void rtl8192_SetBWMode(struct net_device *dev, enum ht_channel_width Bandwidth,
1275 enum ht_extchnl_offset Offset)
1276 {
1277 struct r8192_priv *priv = rtllib_priv(dev);
1278
1279
1280 if (priv->SetBWModeInProgress)
1281 return;
1282
1283 atomic_inc(&(priv->rtllib->atm_swbw));
1284 priv->SetBWModeInProgress = true;
1285
1286 priv->CurrentChannelBW = Bandwidth;
1287
1288 if (Offset == HT_EXTCHNL_OFFSET_LOWER)
1289 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_UPPER;
1290 else if (Offset == HT_EXTCHNL_OFFSET_UPPER)
1291 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_LOWER;
1292 else
1293 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
1294
1295 rtl8192_SetBWModeWorkItem(dev);
1296
1297 }
1298
1299 void InitialGain819xPci(struct net_device *dev, u8 Operation)
1300 {
1301 #define SCAN_RX_INITIAL_GAIN 0x17
1302 #define POWER_DETECTION_TH 0x08
1303 struct r8192_priv *priv = rtllib_priv(dev);
1304 u32 BitMask;
1305 u8 initial_gain;
1306
1307 if (!IS_NIC_DOWN(priv)) {
1308 switch (Operation) {
1309 case IG_Backup:
1310 RT_TRACE(COMP_SCAN, "IG_Backup, backup the initial"
1311 " gain.\n");
1312 initial_gain = SCAN_RX_INITIAL_GAIN;
1313 BitMask = bMaskByte0;
1314 if (dm_digtable.dig_algorithm ==
1315 DIG_ALGO_BY_FALSE_ALARM)
1316 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8);
1317 priv->initgain_backup.xaagccore1 =
1318 (u8)rtl8192_QueryBBReg(dev, rOFDM0_XAAGCCore1,
1319 BitMask);
1320 priv->initgain_backup.xbagccore1 =
1321 (u8)rtl8192_QueryBBReg(dev, rOFDM0_XBAGCCore1,
1322 BitMask);
1323 priv->initgain_backup.xcagccore1 =
1324 (u8)rtl8192_QueryBBReg(dev, rOFDM0_XCAGCCore1,
1325 BitMask);
1326 priv->initgain_backup.xdagccore1 =
1327 (u8)rtl8192_QueryBBReg(dev, rOFDM0_XDAGCCore1,
1328 BitMask);
1329 BitMask = bMaskByte2;
1330 priv->initgain_backup.cca = (u8)rtl8192_QueryBBReg(dev,
1331 rCCK0_CCA, BitMask);
1332
1333 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc50 is"
1334 " %x\n", priv->initgain_backup.xaagccore1);
1335 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc58 is"
1336 " %x\n", priv->initgain_backup.xbagccore1);
1337 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc60 is"
1338 " %x\n", priv->initgain_backup.xcagccore1);
1339 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc68 is"
1340 " %x\n", priv->initgain_backup.xdagccore1);
1341 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xa0a is"
1342 " %x\n", priv->initgain_backup.cca);
1343
1344 RT_TRACE(COMP_SCAN, "Write scan initial gain = 0x%x\n",
1345 initial_gain);
1346 write_nic_byte(dev, rOFDM0_XAAGCCore1, initial_gain);
1347 write_nic_byte(dev, rOFDM0_XBAGCCore1, initial_gain);
1348 write_nic_byte(dev, rOFDM0_XCAGCCore1, initial_gain);
1349 write_nic_byte(dev, rOFDM0_XDAGCCore1, initial_gain);
1350 RT_TRACE(COMP_SCAN, "Write scan 0xa0a = 0x%x\n",
1351 POWER_DETECTION_TH);
1352 write_nic_byte(dev, 0xa0a, POWER_DETECTION_TH);
1353 break;
1354 case IG_Restore:
1355 RT_TRACE(COMP_SCAN, "IG_Restore, restore the initial "
1356 "gain.\n");
1357 BitMask = 0x7f;
1358 if (dm_digtable.dig_algorithm ==
1359 DIG_ALGO_BY_FALSE_ALARM)
1360 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8);
1361
1362 rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, BitMask,
1363 (u32)priv->initgain_backup.xaagccore1);
1364 rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, BitMask,
1365 (u32)priv->initgain_backup.xbagccore1);
1366 rtl8192_setBBreg(dev, rOFDM0_XCAGCCore1, BitMask,
1367 (u32)priv->initgain_backup.xcagccore1);
1368 rtl8192_setBBreg(dev, rOFDM0_XDAGCCore1, BitMask,
1369 (u32)priv->initgain_backup.xdagccore1);
1370 BitMask = bMaskByte2;
1371 rtl8192_setBBreg(dev, rCCK0_CCA, BitMask,
1372 (u32)priv->initgain_backup.cca);
1373
1374 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc50"
1375 " is %x\n", priv->initgain_backup.xaagccore1);
1376 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc58"
1377 " is %x\n", priv->initgain_backup.xbagccore1);
1378 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc60"
1379 " is %x\n", priv->initgain_backup.xcagccore1);
1380 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc68"
1381 " is %x\n", priv->initgain_backup.xdagccore1);
1382 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xa0a"
1383 " is %x\n", priv->initgain_backup.cca);
1384
1385 rtl8192_phy_setTxPower(dev,
1386 priv->rtllib->current_network.channel);
1387
1388 if (dm_digtable.dig_algorithm ==
1389 DIG_ALGO_BY_FALSE_ALARM)
1390 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1);
1391 break;
1392 default:
1393 RT_TRACE(COMP_SCAN, "Unknown IG Operation.\n");
1394 break;
1395 }
1396 }
1397 }
1398
1399 void PHY_SetRtl8192eRfOff(struct net_device *dev)
1400 {
1401
1402 rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT4, 0x0);
1403 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300, 0x0);
1404 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x18, 0x0);
1405 rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0xf, 0x0);
1406 rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0xf, 0x0);
1407 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x60, 0x0);
1408 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x4, 0x0);
1409 write_nic_byte(dev, ANAPAR_FOR_8192PciE, 0x07);
1410
1411 }
1412
1413 bool SetRFPowerState8190(struct net_device *dev,
1414 enum rt_rf_power_state eRFPowerState)
1415 {
1416 struct r8192_priv *priv = rtllib_priv(dev);
1417 struct rt_pwr_save_ctrl *pPSC = (struct rt_pwr_save_ctrl *)
1418 (&(priv->rtllib->PowerSaveControl));
1419 bool bResult = true;
1420 u8 i = 0, QueueID = 0;
1421 struct rtl8192_tx_ring *ring = NULL;
1422
1423 if (priv->SetRFPowerStateInProgress == true)
1424 return false;
1425 RT_TRACE(COMP_PS, "===========> SetRFPowerState8190()!\n");
1426 priv->SetRFPowerStateInProgress = true;
1427
1428 switch (priv->rf_chip) {
1429 case RF_8256:
1430 switch (eRFPowerState) {
1431 case eRfOn:
1432 RT_TRACE(COMP_PS, "SetRFPowerState8190() eRfOn!\n");
1433 if ((priv->rtllib->eRFPowerState == eRfOff) &&
1434 RT_IN_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC)) {
1435 bool rtstatus = true;
1436 u32 InitilizeCount = 3;
1437 do {
1438 InitilizeCount--;
1439 priv->RegRfOff = false;
1440 rtstatus = NicIFEnableNIC(dev);
1441 } while ((rtstatus != true) &&
1442 (InitilizeCount > 0));
1443
1444 if (rtstatus != true) {
1445 RT_TRACE(COMP_ERR, "%s():Initialize Ada"
1446 "pter fail,return\n",
1447 __func__);
1448 priv->SetRFPowerStateInProgress = false;
1449 return false;
1450 }
1451
1452 RT_CLEAR_PS_LEVEL(pPSC,
1453 RT_RF_OFF_LEVL_HALT_NIC);
1454 } else {
1455 write_nic_byte(dev, ANAPAR, 0x37);
1456 mdelay(1);
1457 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1,
1458 0x4, 0x1);
1459 priv->bHwRfOffAction = 0;
1460
1461 rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE,
1462 BIT4, 0x1);
1463 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4,
1464 0x300, 0x3);
1465 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1,
1466 0x18, 0x3);
1467 rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0x3,
1468 0x3);
1469 rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0x3,
1470 0x3);
1471 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1,
1472 0x60, 0x3);
1473
1474 }
1475
1476 break;
1477
1478 case eRfSleep:
1479 if (priv->rtllib->eRFPowerState == eRfOff)
1480 break;
1481
1482
1483 for (QueueID = 0, i = 0; QueueID < MAX_TX_QUEUE; ) {
1484 ring = &priv->tx_ring[QueueID];
1485
1486 if (skb_queue_len(&ring->queue) == 0) {
1487 QueueID++;
1488 continue;
1489 } else {
1490 RT_TRACE((COMP_POWER|COMP_RF), "eRf Off"
1491 "/Sleep: %d times TcbBusyQueue"
1492 "[%d] !=0 before doze!\n",
1493 (i+1), QueueID);
1494 udelay(10);
1495 i++;
1496 }
1497
1498 if (i >= MAX_DOZE_WAITING_TIMES_9x) {
1499 RT_TRACE(COMP_POWER, "\n\n\n TimeOut!! "
1500 "SetRFPowerState8190(): eRfOff"
1501 ": %d times TcbBusyQueue[%d] "
1502 "!= 0 !!!\n",
1503 MAX_DOZE_WAITING_TIMES_9x,
1504 QueueID);
1505 break;
1506 }
1507 }
1508 PHY_SetRtl8192eRfOff(dev);
1509 break;
1510
1511 case eRfOff:
1512 RT_TRACE(COMP_PS, "SetRFPowerState8190() eRfOff/"
1513 "Sleep !\n");
1514
1515 for (QueueID = 0, i = 0; QueueID < MAX_TX_QUEUE; ) {
1516 ring = &priv->tx_ring[QueueID];
1517
1518 if (skb_queue_len(&ring->queue) == 0) {
1519 QueueID++;
1520 continue;
1521 } else {
1522 RT_TRACE(COMP_POWER, "eRf Off/Sleep: %d"
1523 " times TcbBusyQueue[%d] !=0 b"
1524 "efore doze!\n", (i+1),
1525 QueueID);
1526 udelay(10);
1527 i++;
1528 }
1529
1530 if (i >= MAX_DOZE_WAITING_TIMES_9x) {
1531 RT_TRACE(COMP_POWER, "\n\n\n SetZebra: "
1532 "RFPowerState8185B(): eRfOff:"
1533 " %d times TcbBusyQueue[%d] "
1534 "!= 0 !!!\n",
1535 MAX_DOZE_WAITING_TIMES_9x,
1536 QueueID);
1537 break;
1538 }
1539 }
1540
1541 if (pPSC->RegRfPsLevel & RT_RF_OFF_LEVL_HALT_NIC &&
1542 !RT_IN_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC)) {
1543 NicIFDisableNIC(dev);
1544 RT_SET_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC);
1545 } else if (!(pPSC->RegRfPsLevel &
1546 RT_RF_OFF_LEVL_HALT_NIC)) {
1547 PHY_SetRtl8192eRfOff(dev);
1548 }
1549
1550 break;
1551
1552 default:
1553 bResult = false;
1554 RT_TRACE(COMP_ERR, "SetRFPowerState8190(): unknow state"
1555 " to set: 0x%X!!!\n", eRFPowerState);
1556 break;
1557 }
1558
1559 break;
1560
1561 default:
1562 RT_TRACE(COMP_ERR, "SetRFPowerState8190(): Unknown RF type\n");
1563 break;
1564 }
1565
1566 if (bResult) {
1567 priv->rtllib->eRFPowerState = eRFPowerState;
1568
1569 switch (priv->rf_chip) {
1570 case RF_8256:
1571 break;
1572
1573 default:
1574 RT_TRACE(COMP_ERR, "SetRFPowerState8190(): Unknown "
1575 "RF type\n");
1576 break;
1577 }
1578 }
1579
1580 priv->SetRFPowerStateInProgress = false;
1581 RT_TRACE(COMP_PS, "<=========== SetRFPowerState8190() bResult = %d!\n",
1582 bResult);
1583 return bResult;
1584 }
1585
1586 bool SetRFPowerState(struct net_device *dev,
1587 enum rt_rf_power_state eRFPowerState)
1588 {
1589 struct r8192_priv *priv = rtllib_priv(dev);
1590
1591 bool bResult = false;
1592
1593 RT_TRACE(COMP_PS, "---------> SetRFPowerState(): eRFPowerState(%d)\n",
1594 eRFPowerState);
1595 if (eRFPowerState == priv->rtllib->eRFPowerState &&
1596 priv->bHwRfOffAction == 0) {
1597 RT_TRACE(COMP_PS, "<--------- SetRFPowerState(): discard the "
1598 "request for eRFPowerState(%d) is the same.\n",
1599 eRFPowerState);
1600 return bResult;
1601 }
1602
1603 bResult = SetRFPowerState8190(dev, eRFPowerState);
1604
1605 RT_TRACE(COMP_PS, "<--------- SetRFPowerState(): bResult(%d)\n",
1606 bResult);
1607
1608 return bResult;
1609 }
1610
1611 extern void PHY_ScanOperationBackup8192(struct net_device *dev, u8 Operation)
1612 {
1613 struct r8192_priv *priv = rtllib_priv(dev);
1614
1615 if (priv->up) {
1616 switch (Operation) {
1617 case SCAN_OPT_BACKUP:
1618 priv->rtllib->InitialGainHandler(dev, IG_Backup);
1619 break;
1620
1621 case SCAN_OPT_RESTORE:
1622 priv->rtllib->InitialGainHandler(dev, IG_Restore);
1623 break;
1624
1625 default:
1626 RT_TRACE(COMP_SCAN, "Unknown Scan Backup Operation.\n");
1627 break;
1628 }
1629 }
1630
1631 }
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree