| blob | 3bb3a13c4047566d70057db9342c93da06fefd8e |
1 /*
2 * arch/ia64/kernel/ivt.S
3 *
4 * Copyright (C) 1998-2001, 2003, 2005 Hewlett-Packard Co
5 * Stephane Eranian <eranian@hpl.hp.com>
6 * David Mosberger <davidm@hpl.hp.com>
7 * Copyright (C) 2000, 2002-2003 Intel Co
8 * Asit Mallick <asit.k.mallick@intel.com>
9 * Suresh Siddha <suresh.b.siddha@intel.com>
10 * Kenneth Chen <kenneth.w.chen@intel.com>
11 * Fenghua Yu <fenghua.yu@intel.com>
12 *
13 * 00/08/23 Asit Mallick <asit.k.mallick@intel.com> TLB handling for SMP
14 * 00/12/20 David Mosberger-Tang <davidm@hpl.hp.com> DTLB/ITLB handler now uses virtual PT.
15 */
16 /*
17 * This file defines the interruption vector table used by the CPU.
18 * It does not include one entry per possible cause of interruption.
19 *
20 * The first 20 entries of the table contain 64 bundles each while the
21 * remaining 48 entries contain only 16 bundles each.
22 *
23 * The 64 bundles are used to allow inlining the whole handler for critical
24 * interruptions like TLB misses.
25 *
26 * For each entry, the comment is as follows:
27 *
28 * // 0x1c00 Entry 7 (size 64 bundles) Data Key Miss (12,51)
29 * entry offset ----/ / / / /
30 * entry number ---------/ / / /
31 * size of the entry -------------/ / /
32 * vector name -------------------------------------/ /
33 * interruptions triggering this vector ----------------------/
34 *
35 * The table is 32KB in size and must be aligned on 32KB boundary.
36 * (The CPU ignores the 15 lower bits of the address)
37 *
38 * Table is based upon EAS2.6 (Oct 1999)
39 */
41 #include <linux/config.h>
43 #include <asm/asmmacro.h>
44 #include <asm/break.h>
45 #include <asm/ia32.h>
46 #include <asm/kregs.h>
47 #include <asm/offsets.h>
48 #include <asm/pgtable.h>
49 #include <asm/processor.h>
50 #include <asm/ptrace.h>
51 #include <asm/system.h>
52 #include <asm/thread_info.h>
53 #include <asm/unistd.h>
54 #include <asm/errno.h>
56 #if 1
57 # define PSR_DEFAULT_BITS psr.ac
58 #else
59 # define PSR_DEFAULT_BITS 0
60 #endif
62 #if 0
63 /*
64 * This lets you track the last eight faults that occurred on the CPU. Make sure ar.k2 isn't
65 * needed for something else before enabling this...
66 */
67 # define DBG_FAULT(i) mov r16=ar.k2;; shl r16=r16,8;; add r16=(i),r16;;mov ar.k2=r16
68 #else
69 # define DBG_FAULT(i)
70 #endif
72 #define MINSTATE_VIRT /* needed by minstate.h */
73 #include "minstate.h"
75 #define FAULT(n) \
76 mov r31=pr; \
77 mov r19=n;; /* prepare to save predicates */ \
78 br.sptk.many dispatch_to_fault_handler
80 .section .text.ivt,"ax"
82 .align 32768 // align on 32KB boundary
83 .global ia64_ivt
84 ia64_ivt:
85 /////////////////////////////////////////////////////////////////////////////////////////
86 // 0x0000 Entry 0 (size 64 bundles) VHPT Translation (8,20,47)
87 ENTRY(vhpt_miss)
88 DBG_FAULT(0)
89 /*
90 * The VHPT vector is invoked when the TLB entry for the virtual page table
91 * is missing. This happens only as a result of a previous
92 * (the "original") TLB miss, which may either be caused by an instruction
93 * fetch or a data access (or non-access).
94 *
95 * What we do here is normal TLB miss handing for the _original_ miss, followed
96 * by inserting the TLB entry for the virtual page table page that the VHPT
97 * walker was attempting to access. The latter gets inserted as long
98 * as both L1 and L2 have valid mappings for the faulting address.
99 * The TLB entry for the original miss gets inserted only if
100 * the L3 entry indicates that the page is present.
101 *
102 * do_page_fault gets invoked in the following cases:
103 * - the faulting virtual address uses unimplemented address bits
104 * - the faulting virtual address has no L1, L2, or L3 mapping
105 */
106 mov r16=cr.ifa // get address that caused the TLB miss
107 #ifdef CONFIG_HUGETLB_PAGE
108 movl r18=PAGE_SHIFT
109 mov r25=cr.itir
110 #endif
111 ;;
112 rsm psr.dt // use physical addressing for data
113 mov r31=pr // save the predicate registers
114 mov r19=IA64_KR(PT_BASE) // get page table base address
115 shl r21=r16,3 // shift bit 60 into sign bit
116 shr.u r17=r16,61 // get the region number into r17
117 ;;
118 shr r22=r21,3
119 #ifdef CONFIG_HUGETLB_PAGE
120 extr.u r26=r25,2,6
121 ;;
122 cmp.ne p8,p0=r18,r26
123 sub r27=r26,r18
124 ;;
125 (p8) dep r25=r18,r25,2,6
126 (p8) shr r22=r22,r27
127 #endif
128 ;;
129 cmp.eq p6,p7=5,r17 // is IFA pointing into to region 5?
130 shr.u r18=r22,PGDIR_SHIFT // get bits 33-63 of the faulting address
131 ;;
132 (p7) dep r17=r17,r19,(PAGE_SHIFT-3),3 // put region number bits in place
134 srlz.d
135 LOAD_PHYSICAL(p6, r19, swapper_pg_dir) // region 5 is rooted at swapper_pg_dir
137 .pred.rel "mutex", p6, p7
138 (p6) shr.u r21=r21,PGDIR_SHIFT+PAGE_SHIFT
139 (p7) shr.u r21=r21,PGDIR_SHIFT+PAGE_SHIFT-3
140 ;;
141 (p6) dep r17=r18,r19,3,(PAGE_SHIFT-3) // r17=PTA + IFA(33,42)*8
142 (p7) dep r17=r18,r17,3,(PAGE_SHIFT-6) // r17=PTA + (((IFA(61,63) << 7) | IFA(33,39))*8)
143 cmp.eq p7,p6=0,r21 // unused address bits all zeroes?
144 shr.u r18=r22,PMD_SHIFT // shift L2 index into position
145 ;;
146 ld8 r17=[r17] // fetch the L1 entry (may be 0)
147 ;;
148 (p7) cmp.eq p6,p7=r17,r0 // was L1 entry NULL?
149 dep r17=r18,r17,3,(PAGE_SHIFT-3) // compute address of L2 page table entry
150 ;;
151 (p7) ld8 r20=[r17] // fetch the L2 entry (may be 0)
152 shr.u r19=r22,PAGE_SHIFT // shift L3 index into position
153 ;;
154 (p7) cmp.eq.or.andcm p6,p7=r20,r0 // was L2 entry NULL?
155 dep r21=r19,r20,3,(PAGE_SHIFT-3) // compute address of L3 page table entry
156 ;;
157 (p7) ld8 r18=[r21] // read the L3 PTE
158 mov r19=cr.isr // cr.isr bit 0 tells us if this is an insn miss
159 ;;
160 (p7) tbit.z p6,p7=r18,_PAGE_P_BIT // page present bit cleared?
161 mov r22=cr.iha // get the VHPT address that caused the TLB miss
162 ;; // avoid RAW on p7
163 (p7) tbit.nz.unc p10,p11=r19,32 // is it an instruction TLB miss?
164 dep r23=0,r20,0,PAGE_SHIFT // clear low bits to get page address
165 ;;
166 (p10) itc.i r18 // insert the instruction TLB entry
167 (p11) itc.d r18 // insert the data TLB entry
168 (p6) br.cond.spnt.many page_fault // handle bad address/page not present (page fault)
169 mov cr.ifa=r22
171 #ifdef CONFIG_HUGETLB_PAGE
172 (p8) mov cr.itir=r25 // change to default page-size for VHPT
173 #endif
175 /*
176 * Now compute and insert the TLB entry for the virtual page table. We never
177 * execute in a page table page so there is no need to set the exception deferral
178 * bit.
179 */
180 adds r24=__DIRTY_BITS_NO_ED|_PAGE_PL_0|_PAGE_AR_RW,r23
181 ;;
182 (p7) itc.d r24
183 ;;
184 #ifdef CONFIG_SMP
185 /*
186 * Tell the assemblers dependency-violation checker that the above "itc" instructions
187 * cannot possibly affect the following loads:
188 */
189 dv_serialize_data
191 /*
192 * Re-check L2 and L3 pagetable. If they changed, we may have received a ptc.g
193 * between reading the pagetable and the "itc". If so, flush the entry we
194 * inserted and retry.
195 */
196 ld8 r25=[r21] // read L3 PTE again
197 ld8 r26=[r17] // read L2 entry again
198 ;;
199 cmp.ne p6,p7=r26,r20 // did L2 entry change
200 mov r27=PAGE_SHIFT<<2
201 ;;
202 (p6) ptc.l r22,r27 // purge PTE page translation
203 (p7) cmp.ne.or.andcm p6,p7=r25,r18 // did L3 PTE change
204 ;;
205 (p6) ptc.l r16,r27 // purge translation
206 #endif
208 mov pr=r31,-1 // restore predicate registers
209 rfi
210 END(vhpt_miss)
212 .org ia64_ivt+0x400
213 /////////////////////////////////////////////////////////////////////////////////////////
214 // 0x0400 Entry 1 (size 64 bundles) ITLB (21)
215 ENTRY(itlb_miss)
216 DBG_FAULT(1)
217 /*
218 * The ITLB handler accesses the L3 PTE via the virtually mapped linear
219 * page table. If a nested TLB miss occurs, we switch into physical
220 * mode, walk the page table, and then re-execute the L3 PTE read
221 * and go on normally after that.
222 */
223 mov r16=cr.ifa // get virtual address
224 mov r29=b0 // save b0
225 mov r31=pr // save predicates
226 .itlb_fault:
227 mov r17=cr.iha // get virtual address of L3 PTE
228 movl r30=1f // load nested fault continuation point
229 ;;
230 1: ld8 r18=[r17] // read L3 PTE
231 ;;
232 mov b0=r29
233 tbit.z p6,p0=r18,_PAGE_P_BIT // page present bit cleared?
234 (p6) br.cond.spnt page_fault
235 ;;
236 itc.i r18
237 ;;
238 #ifdef CONFIG_SMP
239 /*
240 * Tell the assemblers dependency-violation checker that the above "itc" instructions
241 * cannot possibly affect the following loads:
242 */
243 dv_serialize_data
245 ld8 r19=[r17] // read L3 PTE again and see if same
246 mov r20=PAGE_SHIFT<<2 // setup page size for purge
247 ;;
248 cmp.ne p7,p0=r18,r19
249 ;;
250 (p7) ptc.l r16,r20
251 #endif
252 mov pr=r31,-1
253 rfi
254 END(itlb_miss)
256 .org ia64_ivt+0x0800
257 /////////////////////////////////////////////////////////////////////////////////////////
258 // 0x0800 Entry 2 (size 64 bundles) DTLB (9,48)
259 ENTRY(dtlb_miss)
260 DBG_FAULT(2)
261 /*
262 * The DTLB handler accesses the L3 PTE via the virtually mapped linear
263 * page table. If a nested TLB miss occurs, we switch into physical
264 * mode, walk the page table, and then re-execute the L3 PTE read
265 * and go on normally after that.
266 */
267 mov r16=cr.ifa // get virtual address
268 mov r29=b0 // save b0
269 mov r31=pr // save predicates
270 dtlb_fault:
271 mov r17=cr.iha // get virtual address of L3 PTE
272 movl r30=1f // load nested fault continuation point
273 ;;
274 1: ld8 r18=[r17] // read L3 PTE
275 ;;
276 mov b0=r29
277 tbit.z p6,p0=r18,_PAGE_P_BIT // page present bit cleared?
278 (p6) br.cond.spnt page_fault
279 ;;
280 itc.d r18
281 ;;
282 #ifdef CONFIG_SMP
283 /*
284 * Tell the assemblers dependency-violation checker that the above "itc" instructions
285 * cannot possibly affect the following loads:
286 */
287 dv_serialize_data
289 ld8 r19=[r17] // read L3 PTE again and see if same
290 mov r20=PAGE_SHIFT<<2 // setup page size for purge
291 ;;
292 cmp.ne p7,p0=r18,r19
293 ;;
294 (p7) ptc.l r16,r20
295 #endif
296 mov pr=r31,-1
297 rfi
298 END(dtlb_miss)
300 .org ia64_ivt+0x0c00
301 /////////////////////////////////////////////////////////////////////////////////////////
302 // 0x0c00 Entry 3 (size 64 bundles) Alt ITLB (19)
303 ENTRY(alt_itlb_miss)
304 DBG_FAULT(3)
305 mov r16=cr.ifa // get address that caused the TLB miss
306 movl r17=PAGE_KERNEL
307 mov r21=cr.ipsr
308 movl r19=(((1 << IA64_MAX_PHYS_BITS) - 1) & ~0xfff)
309 mov r31=pr
310 ;;
311 #ifdef CONFIG_DISABLE_VHPT
312 shr.u r22=r16,61 // get the region number into r21
313 ;;
314 cmp.gt p8,p0=6,r22 // user mode
315 ;;
316 (p8) thash r17=r16
317 ;;
318 (p8) mov cr.iha=r17
319 (p8) mov r29=b0 // save b0
320 (p8) br.cond.dptk .itlb_fault
321 #endif
322 extr.u r23=r21,IA64_PSR_CPL0_BIT,2 // extract psr.cpl
323 and r19=r19,r16 // clear ed, reserved bits, and PTE control bits
324 shr.u r18=r16,57 // move address bit 61 to bit 4
325 ;;
326 andcm r18=0x10,r18 // bit 4=~address-bit(61)
327 cmp.ne p8,p0=r0,r23 // psr.cpl != 0?
328 or r19=r17,r19 // insert PTE control bits into r19
329 ;;
330 or r19=r19,r18 // set bit 4 (uncached) if the access was to region 6
331 (p8) br.cond.spnt page_fault
332 ;;
333 itc.i r19 // insert the TLB entry
334 mov pr=r31,-1
335 rfi
336 END(alt_itlb_miss)
338 .org ia64_ivt+0x1000
339 /////////////////////////////////////////////////////////////////////////////////////////
340 // 0x1000 Entry 4 (size 64 bundles) Alt DTLB (7,46)
341 ENTRY(alt_dtlb_miss)
342 DBG_FAULT(4)
343 mov r16=cr.ifa // get address that caused the TLB miss
344 movl r17=PAGE_KERNEL
345 mov r20=cr.isr
346 movl r19=(((1 << IA64_MAX_PHYS_BITS) - 1) & ~0xfff)
347 mov r21=cr.ipsr
348 mov r31=pr
349 ;;
350 #ifdef CONFIG_DISABLE_VHPT
351 shr.u r22=r16,61 // get the region number into r21
352 ;;
353 cmp.gt p8,p0=6,r22 // access to region 0-5
354 ;;
355 (p8) thash r17=r16
356 ;;
357 (p8) mov cr.iha=r17
358 (p8) mov r29=b0 // save b0
359 (p8) br.cond.dptk dtlb_fault
360 #endif
361 extr.u r23=r21,IA64_PSR_CPL0_BIT,2 // extract psr.cpl
362 and r22=IA64_ISR_CODE_MASK,r20 // get the isr.code field
363 tbit.nz p6,p7=r20,IA64_ISR_SP_BIT // is speculation bit on?
364 shr.u r18=r16,57 // move address bit 61 to bit 4
365 and r19=r19,r16 // clear ed, reserved bits, and PTE control bits
366 tbit.nz p9,p0=r20,IA64_ISR_NA_BIT // is non-access bit on?
367 ;;
368 andcm r18=0x10,r18 // bit 4=~address-bit(61)
369 cmp.ne p8,p0=r0,r23
370 (p9) cmp.eq.or.andcm p6,p7=IA64_ISR_CODE_LFETCH,r22 // check isr.code field
371 (p8) br.cond.spnt page_fault
373 dep r21=-1,r21,IA64_PSR_ED_BIT,1
374 or r19=r19,r17 // insert PTE control bits into r19
375 ;;
376 or r19=r19,r18 // set bit 4 (uncached) if the access was to region 6
377 (p6) mov cr.ipsr=r21
378 ;;
379 (p7) itc.d r19 // insert the TLB entry
380 mov pr=r31,-1
381 rfi
382 END(alt_dtlb_miss)
384 .org ia64_ivt+0x1400
385 /////////////////////////////////////////////////////////////////////////////////////////
386 // 0x1400 Entry 5 (size 64 bundles) Data nested TLB (6,45)
387 ENTRY(nested_dtlb_miss)
388 /*
389 * In the absence of kernel bugs, we get here when the virtually mapped linear
390 * page table is accessed non-speculatively (e.g., in the Dirty-bit, Instruction
391 * Access-bit, or Data Access-bit faults). If the DTLB entry for the virtual page
392 * table is missing, a nested TLB miss fault is triggered and control is
393 * transferred to this point. When this happens, we lookup the pte for the
394 * faulting address by walking the page table in physical mode and return to the
395 * continuation point passed in register r30 (or call page_fault if the address is
396 * not mapped).
397 *
398 * Input: r16: faulting address
399 * r29: saved b0
400 * r30: continuation address
401 * r31: saved pr
402 *
403 * Output: r17: physical address of L3 PTE of faulting address
404 * r29: saved b0
405 * r30: continuation address
406 * r31: saved pr
407 *
408 * Clobbered: b0, r18, r19, r21, r22, psr.dt (cleared)
409 */
410 rsm psr.dt // switch to using physical data addressing
411 mov r19=IA64_KR(PT_BASE) // get the page table base address
412 shl r21=r16,3 // shift bit 60 into sign bit
413 mov r18=cr.itir
414 ;;
415 shr.u r17=r16,61 // get the region number into r17
416 extr.u r18=r18,2,6 // get the faulting page size
417 ;;
418 cmp.eq p6,p7=5,r17 // is faulting address in region 5?
419 add r22=-PAGE_SHIFT,r18 // adjustment for hugetlb address
420 add r18=PGDIR_SHIFT-PAGE_SHIFT,r18
421 ;;
422 shr.u r22=r16,r22
423 shr.u r18=r16,r18
424 (p7) dep r17=r17,r19,(PAGE_SHIFT-3),3 // put region number bits in place
426 srlz.d
427 LOAD_PHYSICAL(p6, r19, swapper_pg_dir) // region 5 is rooted at swapper_pg_dir
429 .pred.rel "mutex", p6, p7
430 (p6) shr.u r21=r21,PGDIR_SHIFT+PAGE_SHIFT
431 (p7) shr.u r21=r21,PGDIR_SHIFT+PAGE_SHIFT-3
432 ;;
433 (p6) dep r17=r18,r19,3,(PAGE_SHIFT-3) // r17=PTA + IFA(33,42)*8
434 (p7) dep r17=r18,r17,3,(PAGE_SHIFT-6) // r17=PTA + (((IFA(61,63) << 7) | IFA(33,39))*8)
435 cmp.eq p7,p6=0,r21 // unused address bits all zeroes?
436 shr.u r18=r22,PMD_SHIFT // shift L2 index into position
437 ;;
438 ld8 r17=[r17] // fetch the L1 entry (may be 0)
439 ;;
440 (p7) cmp.eq p6,p7=r17,r0 // was L1 entry NULL?
441 dep r17=r18,r17,3,(PAGE_SHIFT-3) // compute address of L2 page table entry
442 ;;
443 (p7) ld8 r17=[r17] // fetch the L2 entry (may be 0)
444 shr.u r19=r22,PAGE_SHIFT // shift L3 index into position
445 ;;
446 (p7) cmp.eq.or.andcm p6,p7=r17,r0 // was L2 entry NULL?
447 dep r17=r19,r17,3,(PAGE_SHIFT-3) // compute address of L3 page table entry
448 (p6) br.cond.spnt page_fault
449 mov b0=r30
450 br.sptk.many b0 // return to continuation point
451 END(nested_dtlb_miss)
453 .org ia64_ivt+0x1800
454 /////////////////////////////////////////////////////////////////////////////////////////
455 // 0x1800 Entry 6 (size 64 bundles) Instruction Key Miss (24)
456 ENTRY(ikey_miss)
457 DBG_FAULT(6)
458 FAULT(6)
459 END(ikey_miss)
461 //-----------------------------------------------------------------------------------
462 // call do_page_fault (predicates are in r31, psr.dt may be off, r16 is faulting address)
463 ENTRY(page_fault)
464 ssm psr.dt
465 ;;
466 srlz.i
467 ;;
468 SAVE_MIN_WITH_COVER
469 alloc r15=ar.pfs,0,0,3,0
470 mov out0=cr.ifa
471 mov out1=cr.isr
472 adds r3=8,r2 // set up second base pointer
473 ;;
474 ssm psr.ic | PSR_DEFAULT_BITS
475 ;;
476 srlz.i // guarantee that interruption collectin is on
477 ;;
478 (p15) ssm psr.i // restore psr.i
479 movl r14=ia64_leave_kernel
480 ;;
481 SAVE_REST
482 mov rp=r14
483 ;;
484 adds out2=16,r12 // out2 = pointer to pt_regs
485 br.call.sptk.many b6=ia64_do_page_fault // ignore return address
486 END(page_fault)
488 .org ia64_ivt+0x1c00
489 /////////////////////////////////////////////////////////////////////////////////////////
490 // 0x1c00 Entry 7 (size 64 bundles) Data Key Miss (12,51)
491 ENTRY(dkey_miss)
492 DBG_FAULT(7)
493 FAULT(7)
494 END(dkey_miss)
496 .org ia64_ivt+0x2000
497 /////////////////////////////////////////////////////////////////////////////////////////
498 // 0x2000 Entry 8 (size 64 bundles) Dirty-bit (54)
499 ENTRY(dirty_bit)
500 DBG_FAULT(8)
501 /*
502 * What we do here is to simply turn on the dirty bit in the PTE. We need to
503 * update both the page-table and the TLB entry. To efficiently access the PTE,
504 * we address it through the virtual page table. Most likely, the TLB entry for
505 * the relevant virtual page table page is still present in the TLB so we can
506 * normally do this without additional TLB misses. In case the necessary virtual
507 * page table TLB entry isn't present, we take a nested TLB miss hit where we look
508 * up the physical address of the L3 PTE and then continue at label 1 below.
509 */
510 mov r16=cr.ifa // get the address that caused the fault
511 movl r30=1f // load continuation point in case of nested fault
512 ;;
513 thash r17=r16 // compute virtual address of L3 PTE
514 mov r29=b0 // save b0 in case of nested fault
515 mov r31=pr // save pr
516 #ifdef CONFIG_SMP
517 mov r28=ar.ccv // save ar.ccv
518 ;;
519 1: ld8 r18=[r17]
520 ;; // avoid RAW on r18
521 mov ar.ccv=r18 // set compare value for cmpxchg
522 or r25=_PAGE_D|_PAGE_A,r18 // set the dirty and accessed bits
523 ;;
524 cmpxchg8.acq r26=[r17],r25,ar.ccv
525 mov r24=PAGE_SHIFT<<2
526 ;;
527 cmp.eq p6,p7=r26,r18
528 ;;
529 (p6) itc.d r25 // install updated PTE
530 ;;
531 /*
532 * Tell the assemblers dependency-violation checker that the above "itc" instructions
533 * cannot possibly affect the following loads:
534 */
535 dv_serialize_data
537 ld8 r18=[r17] // read PTE again
538 ;;
539 cmp.eq p6,p7=r18,r25 // is it same as the newly installed
540 ;;
541 (p7) ptc.l r16,r24
542 mov b0=r29 // restore b0
543 mov ar.ccv=r28
544 #else
545 ;;
546 1: ld8 r18=[r17]
547 ;; // avoid RAW on r18
548 or r18=_PAGE_D|_PAGE_A,r18 // set the dirty and accessed bits
549 mov b0=r29 // restore b0
550 ;;
551 st8 [r17]=r18 // store back updated PTE
552 itc.d r18 // install updated PTE
553 #endif
554 mov pr=r31,-1 // restore pr
555 rfi
556 END(dirty_bit)
558 .org ia64_ivt+0x2400
559 /////////////////////////////////////////////////////////////////////////////////////////
560 // 0x2400 Entry 9 (size 64 bundles) Instruction Access-bit (27)
561 ENTRY(iaccess_bit)
562 DBG_FAULT(9)
563 // Like Entry 8, except for instruction access
564 mov r16=cr.ifa // get the address that caused the fault
565 movl r30=1f // load continuation point in case of nested fault
566 mov r31=pr // save predicates
567 #ifdef CONFIG_ITANIUM
568 /*
569 * Erratum 10 (IFA may contain incorrect address) has "NoFix" status.
570 */
571 mov r17=cr.ipsr
572 ;;
573 mov r18=cr.iip
574 tbit.z p6,p0=r17,IA64_PSR_IS_BIT // IA64 instruction set?
575 ;;
576 (p6) mov r16=r18 // if so, use cr.iip instead of cr.ifa
577 #endif /* CONFIG_ITANIUM */
578 ;;
579 thash r17=r16 // compute virtual address of L3 PTE
580 mov r29=b0 // save b0 in case of nested fault)
581 #ifdef CONFIG_SMP
582 mov r28=ar.ccv // save ar.ccv
583 ;;
584 1: ld8 r18=[r17]
585 ;;
586 mov ar.ccv=r18 // set compare value for cmpxchg
587 or r25=_PAGE_A,r18 // set the accessed bit
588 ;;
589 cmpxchg8.acq r26=[r17],r25,ar.ccv
590 mov r24=PAGE_SHIFT<<2
591 ;;
592 cmp.eq p6,p7=r26,r18
593 ;;
594 (p6) itc.i r25 // install updated PTE
595 ;;
596 /*
597 * Tell the assemblers dependency-violation checker that the above "itc" instructions
598 * cannot possibly affect the following loads:
599 */
600 dv_serialize_data
602 ld8 r18=[r17] // read PTE again
603 ;;
604 cmp.eq p6,p7=r18,r25 // is it same as the newly installed
605 ;;
606 (p7) ptc.l r16,r24
607 mov b0=r29 // restore b0
608 mov ar.ccv=r28
609 #else /* !CONFIG_SMP */
610 ;;
611 1: ld8 r18=[r17]
612 ;;
613 or r18=_PAGE_A,r18 // set the accessed bit
614 mov b0=r29 // restore b0
615 ;;
616 st8 [r17]=r18 // store back updated PTE
617 itc.i r18 // install updated PTE
618 #endif /* !CONFIG_SMP */
619 mov pr=r31,-1
620 rfi
621 END(iaccess_bit)
623 .org ia64_ivt+0x2800
624 /////////////////////////////////////////////////////////////////////////////////////////
625 // 0x2800 Entry 10 (size 64 bundles) Data Access-bit (15,55)
626 ENTRY(daccess_bit)
627 DBG_FAULT(10)
628 // Like Entry 8, except for data access
629 mov r16=cr.ifa // get the address that caused the fault
630 movl r30=1f // load continuation point in case of nested fault
631 ;;
632 thash r17=r16 // compute virtual address of L3 PTE
633 mov r31=pr
634 mov r29=b0 // save b0 in case of nested fault)
635 #ifdef CONFIG_SMP
636 mov r28=ar.ccv // save ar.ccv
637 ;;
638 1: ld8 r18=[r17]
639 ;; // avoid RAW on r18
640 mov ar.ccv=r18 // set compare value for cmpxchg
641 or r25=_PAGE_A,r18 // set the dirty bit
642 ;;
643 cmpxchg8.acq r26=[r17],r25,ar.ccv
644 mov r24=PAGE_SHIFT<<2
645 ;;
646 cmp.eq p6,p7=r26,r18
647 ;;
648 (p6) itc.d r25 // install updated PTE
649 /*
650 * Tell the assemblers dependency-violation checker that the above "itc" instructions
651 * cannot possibly affect the following loads:
652 */
653 dv_serialize_data
654 ;;
655 ld8 r18=[r17] // read PTE again
656 ;;
657 cmp.eq p6,p7=r18,r25 // is it same as the newly installed
658 ;;
659 (p7) ptc.l r16,r24
660 mov ar.ccv=r28
661 #else
662 ;;
663 1: ld8 r18=[r17]
664 ;; // avoid RAW on r18
665 or r18=_PAGE_A,r18 // set the accessed bit
666 ;;
667 st8 [r17]=r18 // store back updated PTE
668 itc.d r18 // install updated PTE
669 #endif
670 mov b0=r29 // restore b0
671 mov pr=r31,-1
672 rfi
673 END(daccess_bit)
675 .org ia64_ivt+0x2c00
676 /////////////////////////////////////////////////////////////////////////////////////////
677 // 0x2c00 Entry 11 (size 64 bundles) Break instruction (33)
678 ENTRY(break_fault)
679 /*
680 * The streamlined system call entry/exit paths only save/restore the initial part
681 * of pt_regs. This implies that the callers of system-calls must adhere to the
682 * normal procedure calling conventions.
683 *
684 * Registers to be saved & restored:
685 * CR registers: cr.ipsr, cr.iip, cr.ifs
686 * AR registers: ar.unat, ar.pfs, ar.rsc, ar.rnat, ar.bspstore, ar.fpsr
687 * others: pr, b0, b6, loadrs, r1, r11, r12, r13, r15
688 * Registers to be restored only:
689 * r8-r11: output value from the system call.
690 *
691 * During system call exit, scratch registers (including r15) are modified/cleared
692 * to prevent leaking bits from kernel to user level.
693 */
694 DBG_FAULT(11)
695 mov.m r16=IA64_KR(CURRENT) // M2 r16 <- current task (12 cyc)
696 mov r29=cr.ipsr // M2 (12 cyc)
697 mov r31=pr // I0 (2 cyc)
699 mov r17=cr.iim // M2 (2 cyc)
700 mov.m r27=ar.rsc // M2 (12 cyc)
701 mov r18=__IA64_BREAK_SYSCALL // A
703 mov.m ar.rsc=0 // M2
704 mov.m r21=ar.fpsr // M2 (12 cyc)
705 mov r19=b6 // I0 (2 cyc)
706 ;;
707 mov.m r23=ar.bspstore // M2 (12 cyc)
708 mov.m r24=ar.rnat // M2 (5 cyc)
709 mov.i r26=ar.pfs // I0 (2 cyc)
711 invala // M0|1
712 nop.m 0 // M
713 mov r20=r1 // A save r1
715 nop.m 0
716 movl r30=sys_call_table // X
718 mov r28=cr.iip // M2 (2 cyc)
719 cmp.eq p0,p7=r18,r17 // I0 is this a system call?
720 (p7) br.cond.spnt non_syscall // B no ->
721 //
722 // From this point on, we are definitely on the syscall-path
723 // and we can use (non-banked) scratch registers.
724 //
725 ///////////////////////////////////////////////////////////////////////
726 mov r1=r16 // A move task-pointer to "addl"-addressable reg
727 mov r2=r16 // A setup r2 for ia64_syscall_setup
728 add r9=TI_FLAGS+IA64_TASK_SIZE,r16 // A r9 = ¤t_thread_info()->flags
730 adds r16=IA64_TASK_THREAD_ON_USTACK_OFFSET,r16
731 adds r15=-1024,r15 // A subtract 1024 from syscall number
732 mov r3=NR_syscalls - 1
733 ;;
734 ld1.bias r17=[r16] // M0|1 r17 = current->thread.on_ustack flag
735 ld4 r9=[r9] // M0|1 r9 = current_thread_info()->flags
736 extr.u r8=r29,41,2 // I0 extract ei field from cr.ipsr
738 shladd r30=r15,3,r30 // A r30 = sys_call_table + 8*(syscall-1024)
739 addl r22=IA64_RBS_OFFSET,r1 // A compute base of RBS
740 cmp.leu p6,p7=r15,r3 // A syscall number in range?
741 ;;
743 lfetch.fault.excl.nt1 [r22] // M0|1 prefetch RBS
744 (p6) ld8 r30=[r30] // M0|1 load address of syscall entry point
745 tnat.nz.or p7,p0=r15 // I0 is syscall nr a NaT?
747 mov.m ar.bspstore=r22 // M2 switch to kernel RBS
748 cmp.eq p8,p9=2,r8 // A isr.ei==2?
749 ;;
751 (p8) mov r8=0 // A clear ei to 0
752 (p7) movl r30=sys_ni_syscall // X
754 (p8) adds r28=16,r28 // A switch cr.iip to next bundle
755 (p9) adds r8=1,r8 // A increment ei to next slot
756 nop.i 0
757 ;;
759 mov.m r25=ar.unat // M2 (5 cyc)
760 dep r29=r8,r29,41,2 // I0 insert new ei into cr.ipsr
761 adds r15=1024,r15 // A restore original syscall number
762 //
763 // If any of the above loads miss in L1D, we'll stall here until
764 // the data arrives.
765 //
766 ///////////////////////////////////////////////////////////////////////
767 st1 [r16]=r0 // M2|3 clear current->thread.on_ustack flag
768 mov b6=r30 // I0 setup syscall handler branch reg early
769 cmp.eq pKStk,pUStk=r0,r17 // A were we on kernel stacks already?
771 and r9=_TIF_SYSCALL_TRACEAUDIT,r9 // A mask trace or audit
772 mov r18=ar.bsp // M2 (12 cyc)
773 (pKStk) br.cond.spnt .break_fixup // B we're already in kernel-mode -- fix up RBS
774 ;;
775 .back_from_break_fixup:
776 (pUStk) addl r1=IA64_STK_OFFSET-IA64_PT_REGS_SIZE,r1 // A compute base of memory stack
777 cmp.eq p14,p0=r9,r0 // A are syscalls being traced/audited?
778 br.call.sptk.many b7=ia64_syscall_setup // B
779 1:
780 mov ar.rsc=0x3 // M2 set eager mode, pl 0, LE, loadrs=0
781 nop 0
782 bsw.1 // B (6 cyc) regs are saved, switch to bank 1
783 ;;
785 ssm psr.ic | PSR_DEFAULT_BITS // M2 now it's safe to re-enable intr.-collection
786 movl r3=ia64_ret_from_syscall // X
787 ;;
789 srlz.i // M0 ensure interruption collection is on
790 mov rp=r3 // I0 set the real return addr
791 (p10) br.cond.spnt.many ia64_ret_from_syscall // B return if bad call-frame or r15 is a NaT
793 (p15) ssm psr.i // M2 restore psr.i
794 (p14) br.call.sptk.many b6=b6 // B invoke syscall-handker (ignore return addr)
795 br.cond.spnt.many ia64_trace_syscall // B do syscall-tracing thingamagic
796 // NOT REACHED
797 ///////////////////////////////////////////////////////////////////////
798 // On entry, we optimistically assumed that we're coming from user-space.
799 // For the rare cases where a system-call is done from within the kernel,
800 // we fix things up at this point:
801 .break_fixup:
802 add r1=-IA64_PT_REGS_SIZE,sp // A allocate space for pt_regs structure
803 mov ar.rnat=r24 // M2 restore kernel's AR.RNAT
804 ;;
805 mov ar.bspstore=r23 // M2 restore kernel's AR.BSPSTORE
806 br.cond.sptk .back_from_break_fixup
807 END(break_fault)
809 .org ia64_ivt+0x3000
810 /////////////////////////////////////////////////////////////////////////////////////////
811 // 0x3000 Entry 12 (size 64 bundles) External Interrupt (4)
812 ENTRY(interrupt)
813 DBG_FAULT(12)
814 mov r31=pr // prepare to save predicates
815 ;;
816 SAVE_MIN_WITH_COVER // uses r31; defines r2 and r3
817 ssm psr.ic | PSR_DEFAULT_BITS
818 ;;
819 adds r3=8,r2 // set up second base pointer for SAVE_REST
820 srlz.i // ensure everybody knows psr.ic is back on
821 ;;
822 SAVE_REST
823 ;;
824 alloc r14=ar.pfs,0,0,2,0 // must be first in an insn group
825 mov out0=cr.ivr // pass cr.ivr as first arg
826 add out1=16,sp // pass pointer to pt_regs as second arg
827 ;;
828 srlz.d // make sure we see the effect of cr.ivr
829 movl r14=ia64_leave_kernel
830 ;;
831 mov rp=r14
832 br.call.sptk.many b6=ia64_handle_irq
833 END(interrupt)
835 .org ia64_ivt+0x3400
836 /////////////////////////////////////////////////////////////////////////////////////////
837 // 0x3400 Entry 13 (size 64 bundles) Reserved
838 DBG_FAULT(13)
839 FAULT(13)
841 .org ia64_ivt+0x3800
842 /////////////////////////////////////////////////////////////////////////////////////////
843 // 0x3800 Entry 14 (size 64 bundles) Reserved
844 DBG_FAULT(14)
845 FAULT(14)
847 /*
848 * There is no particular reason for this code to be here, other than that
849 * there happens to be space here that would go unused otherwise. If this
850 * fault ever gets "unreserved", simply moved the following code to a more
851 * suitable spot...
852 *
853 * ia64_syscall_setup() is a separate subroutine so that it can
854 * allocate stacked registers so it can safely demine any
855 * potential NaT values from the input registers.
856 *
857 * On entry:
858 * - executing on bank 0 or bank 1 register set (doesn't matter)
859 * - r1: stack pointer
860 * - r2: current task pointer
861 * - r3: preserved
862 * - r11: original contents (saved ar.pfs to be saved)
863 * - r12: original contents (sp to be saved)
864 * - r13: original contents (tp to be saved)
865 * - r15: original contents (syscall # to be saved)
866 * - r18: saved bsp (after switching to kernel stack)
867 * - r19: saved b6
868 * - r20: saved r1 (gp)
869 * - r21: saved ar.fpsr
870 * - r22: kernel's register backing store base (krbs_base)
871 * - r23: saved ar.bspstore
872 * - r24: saved ar.rnat
873 * - r25: saved ar.unat
874 * - r26: saved ar.pfs
875 * - r27: saved ar.rsc
876 * - r28: saved cr.iip
877 * - r29: saved cr.ipsr
878 * - r31: saved pr
879 * - b0: original contents (to be saved)
880 * On exit:
881 * - p10: TRUE if syscall is invoked with more than 8 out
882 * registers or r15's Nat is true
883 * - r1: kernel's gp
884 * - r3: preserved (same as on entry)
885 * - r8: -EINVAL if p10 is true
886 * - r12: points to kernel stack
887 * - r13: points to current task
888 * - r14: preserved (same as on entry)
889 * - p13: preserved
890 * - p15: TRUE if interrupts need to be re-enabled
891 * - ar.fpsr: set to kernel settings
892 * - b6: preserved (same as on entry)
893 */
894 GLOBAL_ENTRY(ia64_syscall_setup)
895 #if PT(B6) != 0
896 # error This code assumes that b6 is the first field in pt_regs.
897 #endif
898 st8 [r1]=r19 // save b6
899 add r16=PT(CR_IPSR),r1 // initialize first base pointer
900 add r17=PT(R11),r1 // initialize second base pointer
901 ;;
902 alloc r19=ar.pfs,8,0,0,0 // ensure in0-in7 are writable
903 st8 [r16]=r29,PT(AR_PFS)-PT(CR_IPSR) // save cr.ipsr
904 tnat.nz p8,p0=in0
906 st8.spill [r17]=r11,PT(CR_IIP)-PT(R11) // save r11
907 tnat.nz p9,p0=in1
908 (pKStk) mov r18=r0 // make sure r18 isn't NaT
909 ;;
911 st8 [r16]=r26,PT(CR_IFS)-PT(AR_PFS) // save ar.pfs
912 st8 [r17]=r28,PT(AR_UNAT)-PT(CR_IIP) // save cr.iip
913 mov r28=b0 // save b0 (2 cyc)
914 ;;
916 st8 [r17]=r25,PT(AR_RSC)-PT(AR_UNAT) // save ar.unat
917 dep r19=0,r19,38,26 // clear all bits but 0..37 [I0]
918 (p8) mov in0=-1
919 ;;
921 st8 [r16]=r19,PT(AR_RNAT)-PT(CR_IFS) // store ar.pfs.pfm in cr.ifs
922 extr.u r11=r19,7,7 // I0 // get sol of ar.pfs
923 and r8=0x7f,r19 // A // get sof of ar.pfs
925 st8 [r17]=r27,PT(AR_BSPSTORE)-PT(AR_RSC)// save ar.rsc
926 tbit.nz p15,p0=r29,IA64_PSR_I_BIT // I0
927 (p9) mov in1=-1
928 ;;
930 (pUStk) sub r18=r18,r22 // r18=RSE.ndirty*8
931 tnat.nz p10,p0=in2
932 add r11=8,r11
933 ;;
934 (pKStk) adds r16=PT(PR)-PT(AR_RNAT),r16 // skip over ar_rnat field
935 (pKStk) adds r17=PT(B0)-PT(AR_BSPSTORE),r17 // skip over ar_bspstore field
936 tnat.nz p11,p0=in3
937 ;;
938 (p10) mov in2=-1
939 tnat.nz p12,p0=in4 // [I0]
940 (p11) mov in3=-1
941 ;;
942 (pUStk) st8 [r16]=r24,PT(PR)-PT(AR_RNAT) // save ar.rnat
943 (pUStk) st8 [r17]=r23,PT(B0)-PT(AR_BSPSTORE) // save ar.bspstore
944 shl r18=r18,16 // compute ar.rsc to be used for "loadrs"
945 ;;
946 st8 [r16]=r31,PT(LOADRS)-PT(PR) // save predicates
947 st8 [r17]=r28,PT(R1)-PT(B0) // save b0
948 tnat.nz p13,p0=in5 // [I0]
949 ;;
950 st8 [r16]=r18,PT(R12)-PT(LOADRS) // save ar.rsc value for "loadrs"
951 st8.spill [r17]=r20,PT(R13)-PT(R1) // save original r1
952 (p12) mov in4=-1
953 ;;
955 .mem.offset 0,0; st8.spill [r16]=r12,PT(AR_FPSR)-PT(R12) // save r12
956 .mem.offset 8,0; st8.spill [r17]=r13,PT(R15)-PT(R13) // save r13
957 (p13) mov in5=-1
958 ;;
959 st8 [r16]=r21,PT(R8)-PT(AR_FPSR) // save ar.fpsr
960 tnat.nz p13,p0=in6
961 cmp.lt p10,p9=r11,r8 // frame size can't be more than local+8
962 ;;
963 mov r8=1
964 (p9) tnat.nz p10,p0=r15
965 adds r12=-16,r1 // switch to kernel memory stack (with 16 bytes of scratch)
967 st8.spill [r17]=r15 // save r15
968 tnat.nz p8,p0=in7
969 nop.i 0
971 mov r13=r2 // establish `current'
972 movl r1=__gp // establish kernel global pointer
973 ;;
974 st8 [r16]=r8 // ensure pt_regs.r8 != 0 (see handle_syscall_error)
975 (p13) mov in6=-1
976 (p8) mov in7=-1
978 cmp.eq pSys,pNonSys=r0,r0 // set pSys=1, pNonSys=0
979 movl r17=FPSR_DEFAULT
980 ;;
981 mov.m ar.fpsr=r17 // set ar.fpsr to kernel default value
982 (p10) mov r8=-EINVAL
983 br.ret.sptk.many b7
984 END(ia64_syscall_setup)
986 .org ia64_ivt+0x3c00
987 /////////////////////////////////////////////////////////////////////////////////////////
988 // 0x3c00 Entry 15 (size 64 bundles) Reserved
989 DBG_FAULT(15)
990 FAULT(15)
992 /*
993 * Squatting in this space ...
994 *
995 * This special case dispatcher for illegal operation faults allows preserved
996 * registers to be modified through a callback function (asm only) that is handed
997 * back from the fault handler in r8. Up to three arguments can be passed to the
998 * callback function by returning an aggregate with the callback as its first
999 * element, followed by the arguments.
1000 */
1001 ENTRY(dispatch_illegal_op_fault)
1002 .prologue
1003 .body
1004 SAVE_MIN_WITH_COVER
1005 ssm psr.ic | PSR_DEFAULT_BITS
1006 ;;
1007 srlz.i // guarantee that interruption collection is on
1008 ;;
1009 (p15) ssm psr.i // restore psr.i
1010 adds r3=8,r2 // set up second base pointer for SAVE_REST
1011 ;;
1012 alloc r14=ar.pfs,0,0,1,0 // must be first in insn group
1013 mov out0=ar.ec
1014 ;;
1015 SAVE_REST
1016 PT_REGS_UNWIND_INFO(0)
1017 ;;
1018 br.call.sptk.many rp=ia64_illegal_op_fault
1019 .ret0: ;;
1020 alloc r14=ar.pfs,0,0,3,0 // must be first in insn group
1021 mov out0=r9
1022 mov out1=r10
1023 mov out2=r11
1024 movl r15=ia64_leave_kernel
1025 ;;
1026 mov rp=r15
1027 mov b6=r8
1028 ;;
1029 cmp.ne p6,p0=0,r8
1030 (p6) br.call.dpnt.many b6=b6 // call returns to ia64_leave_kernel
1031 br.sptk.many ia64_leave_kernel
1032 END(dispatch_illegal_op_fault)
1034 .org ia64_ivt+0x4000
1035 /////////////////////////////////////////////////////////////////////////////////////////
1036 // 0x4000 Entry 16 (size 64 bundles) Reserved
1037 DBG_FAULT(16)
1038 FAULT(16)
1040 .org ia64_ivt+0x4400
1041 /////////////////////////////////////////////////////////////////////////////////////////
1042 // 0x4400 Entry 17 (size 64 bundles) Reserved
1043 DBG_FAULT(17)
1044 FAULT(17)
1046 ENTRY(non_syscall)
1047 mov ar.rsc=r27 // restore ar.rsc before SAVE_MIN_WITH_COVER
1048 ;;
1049 SAVE_MIN_WITH_COVER
1051 // There is no particular reason for this code to be here, other than that
1052 // there happens to be space here that would go unused otherwise. If this
1053 // fault ever gets "unreserved", simply moved the following code to a more
1054 // suitable spot...
1056 alloc r14=ar.pfs,0,0,2,0
1057 mov out0=cr.iim
1058 add out1=16,sp
1059 adds r3=8,r2 // set up second base pointer for SAVE_REST
1061 ssm psr.ic | PSR_DEFAULT_BITS
1062 ;;
1063 srlz.i // guarantee that interruption collection is on
1064 ;;
1065 (p15) ssm psr.i // restore psr.i
1066 movl r15=ia64_leave_kernel
1067 ;;
1068 SAVE_REST
1069 mov rp=r15
1070 ;;
1071 br.call.sptk.many b6=ia64_bad_break // avoid WAW on CFM and ignore return addr
1072 END(non_syscall)
1074 .org ia64_ivt+0x4800
1075 /////////////////////////////////////////////////////////////////////////////////////////
1076 // 0x4800 Entry 18 (size 64 bundles) Reserved
1077 DBG_FAULT(18)
1078 FAULT(18)
1080 /*
1081 * There is no particular reason for this code to be here, other than that
1082 * there happens to be space here that would go unused otherwise. If this
1083 * fault ever gets "unreserved", simply moved the following code to a more
1084 * suitable spot...
1085 */
1087 ENTRY(dispatch_unaligned_handler)
1088 SAVE_MIN_WITH_COVER
1089 ;;
1090 alloc r14=ar.pfs,0,0,2,0 // now it's safe (must be first in insn group!)
1091 mov out0=cr.ifa
1092 adds out1=16,sp
1094 ssm psr.ic | PSR_DEFAULT_BITS
1095 ;;
1096 srlz.i // guarantee that interruption collection is on
1097 ;;
1098 (p15) ssm psr.i // restore psr.i
1099 adds r3=8,r2 // set up second base pointer
1100 ;;
1101 SAVE_REST
1102 movl r14=ia64_leave_kernel
1103 ;;
1104 mov rp=r14
1105 br.sptk.many ia64_prepare_handle_unaligned
1106 END(dispatch_unaligned_handler)
1108 .org ia64_ivt+0x4c00
1109 /////////////////////////////////////////////////////////////////////////////////////////
1110 // 0x4c00 Entry 19 (size 64 bundles) Reserved
1111 DBG_FAULT(19)
1112 FAULT(19)
1114 /*
1115 * There is no particular reason for this code to be here, other than that
1116 * there happens to be space here that would go unused otherwise. If this
1117 * fault ever gets "unreserved", simply moved the following code to a more
1118 * suitable spot...
1119 */
1121 ENTRY(dispatch_to_fault_handler)
1122 /*
1123 * Input:
1124 * psr.ic: off
1125 * r19: fault vector number (e.g., 24 for General Exception)
1126 * r31: contains saved predicates (pr)
1127 */
1128 SAVE_MIN_WITH_COVER_R19
1129 alloc r14=ar.pfs,0,0,5,0
1130 mov out0=r15
1131 mov out1=cr.isr
1132 mov out2=cr.ifa
1133 mov out3=cr.iim
1134 mov out4=cr.itir
1135 ;;
1136 ssm psr.ic | PSR_DEFAULT_BITS
1137 ;;
1138 srlz.i // guarantee that interruption collection is on
1139 ;;
1140 (p15) ssm psr.i // restore psr.i
1141 adds r3=8,r2 // set up second base pointer for SAVE_REST
1142 ;;
1143 SAVE_REST
1144 movl r14=ia64_leave_kernel
1145 ;;
1146 mov rp=r14
1147 br.call.sptk.many b6=ia64_fault
1148 END(dispatch_to_fault_handler)
1150 //
1151 // --- End of long entries, Beginning of short entries
1152 //
1154 .org ia64_ivt+0x5000
1155 /////////////////////////////////////////////////////////////////////////////////////////
1156 // 0x5000 Entry 20 (size 16 bundles) Page Not Present (10,22,49)
1157 ENTRY(page_not_present)
1158 DBG_FAULT(20)
1159 mov r16=cr.ifa
1160 rsm psr.dt
1161 /*
1162 * The Linux page fault handler doesn't expect non-present pages to be in
1163 * the TLB. Flush the existing entry now, so we meet that expectation.
1164 */
1165 mov r17=PAGE_SHIFT<<2
1166 ;;
1167 ptc.l r16,r17
1168 ;;
1169 mov r31=pr
1170 srlz.d
1171 br.sptk.many page_fault
1172 END(page_not_present)
1174 .org ia64_ivt+0x5100
1175 /////////////////////////////////////////////////////////////////////////////////////////
1176 // 0x5100 Entry 21 (size 16 bundles) Key Permission (13,25,52)
1177 ENTRY(key_permission)
1178 DBG_FAULT(21)
1179 mov r16=cr.ifa
1180 rsm psr.dt
1181 mov r31=pr
1182 ;;
1183 srlz.d
1184 br.sptk.many page_fault
1185 END(key_permission)
1187 .org ia64_ivt+0x5200
1188 /////////////////////////////////////////////////////////////////////////////////////////
1189 // 0x5200 Entry 22 (size 16 bundles) Instruction Access Rights (26)
1190 ENTRY(iaccess_rights)
1191 DBG_FAULT(22)
1192 mov r16=cr.ifa
1193 rsm psr.dt
1194 mov r31=pr
1195 ;;
1196 srlz.d
1197 br.sptk.many page_fault
1198 END(iaccess_rights)
1200 .org ia64_ivt+0x5300
1201 /////////////////////////////////////////////////////////////////////////////////////////
1202 // 0x5300 Entry 23 (size 16 bundles) Data Access Rights (14,53)
1203 ENTRY(daccess_rights)
1204 DBG_FAULT(23)
1205 mov r16=cr.ifa
1206 rsm psr.dt
1207 mov r31=pr
1208 ;;
1209 srlz.d
1210 br.sptk.many page_fault
1211 END(daccess_rights)
1213 .org ia64_ivt+0x5400
1214 /////////////////////////////////////////////////////////////////////////////////////////
1215 // 0x5400 Entry 24 (size 16 bundles) General Exception (5,32,34,36,38,39)
1216 ENTRY(general_exception)
1217 DBG_FAULT(24)
1218 mov r16=cr.isr
1219 mov r31=pr
1220 ;;
1221 cmp4.eq p6,p0=0,r16
1222 (p6) br.sptk.many dispatch_illegal_op_fault
1223 ;;
1224 mov r19=24 // fault number
1225 br.sptk.many dispatch_to_fault_handler
1226 END(general_exception)
1228 .org ia64_ivt+0x5500
1229 /////////////////////////////////////////////////////////////////////////////////////////
1230 // 0x5500 Entry 25 (size 16 bundles) Disabled FP-Register (35)
1231 ENTRY(disabled_fp_reg)
1232 DBG_FAULT(25)
1233 rsm psr.dfh // ensure we can access fph
1234 ;;
1235 srlz.d
1236 mov r31=pr
1237 mov r19=25
1238 br.sptk.many dispatch_to_fault_handler
1239 END(disabled_fp_reg)
1241 .org ia64_ivt+0x5600
1242 /////////////////////////////////////////////////////////////////////////////////////////
1243 // 0x5600 Entry 26 (size 16 bundles) Nat Consumption (11,23,37,50)
1244 ENTRY(nat_consumption)
1245 DBG_FAULT(26)
1247 mov r16=cr.ipsr
1248 mov r17=cr.isr
1249 mov r31=pr // save PR
1250 ;;
1251 and r18=0xf,r17 // r18 = cr.ipsr.code{3:0}
1252 tbit.z p6,p0=r17,IA64_ISR_NA_BIT
1253 ;;
1254 cmp.ne.or p6,p0=IA64_ISR_CODE_LFETCH,r18
1255 dep r16=-1,r16,IA64_PSR_ED_BIT,1
1256 (p6) br.cond.spnt 1f // branch if (cr.ispr.na == 0 || cr.ipsr.code{3:0} != LFETCH)
1257 ;;
1258 mov cr.ipsr=r16 // set cr.ipsr.na
1259 mov pr=r31,-1
1260 ;;
1261 rfi
1263 1: mov pr=r31,-1
1264 ;;
1265 FAULT(26)
1266 END(nat_consumption)
1268 .org ia64_ivt+0x5700
1269 /////////////////////////////////////////////////////////////////////////////////////////
1270 // 0x5700 Entry 27 (size 16 bundles) Speculation (40)
1271 ENTRY(speculation_vector)
1272 DBG_FAULT(27)
1273 /*
1274 * A [f]chk.[as] instruction needs to take the branch to the recovery code but
1275 * this part of the architecture is not implemented in hardware on some CPUs, such
1276 * as Itanium. Thus, in general we need to emulate the behavior. IIM contains
1277 * the relative target (not yet sign extended). So after sign extending it we
1278 * simply add it to IIP. We also need to reset the EI field of the IPSR to zero,
1279 * i.e., the slot to restart into.
1280 *
1281 * cr.imm contains zero_ext(imm21)
1282 */
1283 mov r18=cr.iim
1284 ;;
1285 mov r17=cr.iip
1286 shl r18=r18,43 // put sign bit in position (43=64-21)
1287 ;;
1289 mov r16=cr.ipsr
1290 shr r18=r18,39 // sign extend (39=43-4)
1291 ;;
1293 add r17=r17,r18 // now add the offset
1294 ;;
1295 mov cr.iip=r17
1296 dep r16=0,r16,41,2 // clear EI
1297 ;;
1299 mov cr.ipsr=r16
1300 ;;
1302 rfi // and go back
1303 END(speculation_vector)
1305 .org ia64_ivt+0x5800
1306 /////////////////////////////////////////////////////////////////////////////////////////
1307 // 0x5800 Entry 28 (size 16 bundles) Reserved
1308 DBG_FAULT(28)
1309 FAULT(28)
1311 .org ia64_ivt+0x5900
1312 /////////////////////////////////////////////////////////////////////////////////////////
1313 // 0x5900 Entry 29 (size 16 bundles) Debug (16,28,56)
1314 ENTRY(debug_vector)
1315 DBG_FAULT(29)
1316 FAULT(29)
1317 END(debug_vector)
1319 .org ia64_ivt+0x5a00
1320 /////////////////////////////////////////////////////////////////////////////////////////
1321 // 0x5a00 Entry 30 (size 16 bundles) Unaligned Reference (57)
1322 ENTRY(unaligned_access)
1323 DBG_FAULT(30)
1324 mov r16=cr.ipsr
1325 mov r31=pr // prepare to save predicates
1326 ;;
1327 br.sptk.many dispatch_unaligned_handler
1328 END(unaligned_access)
1330 .org ia64_ivt+0x5b00
1331 /////////////////////////////////////////////////////////////////////////////////////////
1332 // 0x5b00 Entry 31 (size 16 bundles) Unsupported Data Reference (57)
1333 ENTRY(unsupported_data_reference)
1334 DBG_FAULT(31)
1335 FAULT(31)
1336 END(unsupported_data_reference)
1338 .org ia64_ivt+0x5c00
1339 /////////////////////////////////////////////////////////////////////////////////////////
1340 // 0x5c00 Entry 32 (size 16 bundles) Floating-Point Fault (64)
1341 ENTRY(floating_point_fault)
1342 DBG_FAULT(32)
1343 FAULT(32)
1344 END(floating_point_fault)
1346 .org ia64_ivt+0x5d00
1347 /////////////////////////////////////////////////////////////////////////////////////////
1348 // 0x5d00 Entry 33 (size 16 bundles) Floating Point Trap (66)
1349 ENTRY(floating_point_trap)
1350 DBG_FAULT(33)
1351 FAULT(33)
1352 END(floating_point_trap)
1354 .org ia64_ivt+0x5e00
1355 /////////////////////////////////////////////////////////////////////////////////////////
1356 // 0x5e00 Entry 34 (size 16 bundles) Lower Privilege Transfer Trap (66)
1357 ENTRY(lower_privilege_trap)
1358 DBG_FAULT(34)
1359 FAULT(34)
1360 END(lower_privilege_trap)
1362 .org ia64_ivt+0x5f00
1363 /////////////////////////////////////////////////////////////////////////////////////////
1364 // 0x5f00 Entry 35 (size 16 bundles) Taken Branch Trap (68)
1365 ENTRY(taken_branch_trap)
1366 DBG_FAULT(35)
1367 FAULT(35)
1368 END(taken_branch_trap)
1370 .org ia64_ivt+0x6000
1371 /////////////////////////////////////////////////////////////////////////////////////////
1372 // 0x6000 Entry 36 (size 16 bundles) Single Step Trap (69)
1373 ENTRY(single_step_trap)
1374 DBG_FAULT(36)
1375 FAULT(36)
1376 END(single_step_trap)
1378 .org ia64_ivt+0x6100
1379 /////////////////////////////////////////////////////////////////////////////////////////
1380 // 0x6100 Entry 37 (size 16 bundles) Reserved
1381 DBG_FAULT(37)
1382 FAULT(37)
1384 .org ia64_ivt+0x6200
1385 /////////////////////////////////////////////////////////////////////////////////////////
1386 // 0x6200 Entry 38 (size 16 bundles) Reserved
1387 DBG_FAULT(38)
1388 FAULT(38)
1390 .org ia64_ivt+0x6300
1391 /////////////////////////////////////////////////////////////////////////////////////////
1392 // 0x6300 Entry 39 (size 16 bundles) Reserved
1393 DBG_FAULT(39)
1394 FAULT(39)
1396 .org ia64_ivt+0x6400
1397 /////////////////////////////////////////////////////////////////////////////////////////
1398 // 0x6400 Entry 40 (size 16 bundles) Reserved
1399 DBG_FAULT(40)
1400 FAULT(40)
1402 .org ia64_ivt+0x6500
1403 /////////////////////////////////////////////////////////////////////////////////////////
1404 // 0x6500 Entry 41 (size 16 bundles) Reserved
1405 DBG_FAULT(41)
1406 FAULT(41)
1408 .org ia64_ivt+0x6600
1409 /////////////////////////////////////////////////////////////////////////////////////////
1410 // 0x6600 Entry 42 (size 16 bundles) Reserved
1411 DBG_FAULT(42)
1412 FAULT(42)
1414 .org ia64_ivt+0x6700
1415 /////////////////////////////////////////////////////////////////////////////////////////
1416 // 0x6700 Entry 43 (size 16 bundles) Reserved
1417 DBG_FAULT(43)
1418 FAULT(43)
1420 .org ia64_ivt+0x6800
1421 /////////////////////////////////////////////////////////////////////////////////////////
1422 // 0x6800 Entry 44 (size 16 bundles) Reserved
1423 DBG_FAULT(44)
1424 FAULT(44)
1426 .org ia64_ivt+0x6900
1427 /////////////////////////////////////////////////////////////////////////////////////////
1428 // 0x6900 Entry 45 (size 16 bundles) IA-32 Exeception (17,18,29,41,42,43,44,58,60,61,62,72,73,75,76,77)
1429 ENTRY(ia32_exception)
1430 DBG_FAULT(45)
1431 FAULT(45)
1432 END(ia32_exception)
1434 .org ia64_ivt+0x6a00
1435 /////////////////////////////////////////////////////////////////////////////////////////
1436 // 0x6a00 Entry 46 (size 16 bundles) IA-32 Intercept (30,31,59,70,71)
1437 ENTRY(ia32_intercept)
1438 DBG_FAULT(46)
1439 #ifdef CONFIG_IA32_SUPPORT
1440 mov r31=pr
1441 mov r16=cr.isr
1442 ;;
1443 extr.u r17=r16,16,8 // get ISR.code
1444 mov r18=ar.eflag
1445 mov r19=cr.iim // old eflag value
1446 ;;
1447 cmp.ne p6,p0=2,r17
1448 (p6) br.cond.spnt 1f // not a system flag fault
1449 xor r16=r18,r19
1450 ;;
1451 extr.u r17=r16,18,1 // get the eflags.ac bit
1452 ;;
1453 cmp.eq p6,p0=0,r17
1454 (p6) br.cond.spnt 1f // eflags.ac bit didn't change
1455 ;;
1456 mov pr=r31,-1 // restore predicate registers
1457 rfi
1459 1:
1460 #endif // CONFIG_IA32_SUPPORT
1461 FAULT(46)
1462 END(ia32_intercept)
1464 .org ia64_ivt+0x6b00
1465 /////////////////////////////////////////////////////////////////////////////////////////
1466 // 0x6b00 Entry 47 (size 16 bundles) IA-32 Interrupt (74)
1467 ENTRY(ia32_interrupt)
1468 DBG_FAULT(47)
1469 #ifdef CONFIG_IA32_SUPPORT
1470 mov r31=pr
1471 br.sptk.many dispatch_to_ia32_handler
1472 #else
1473 FAULT(47)
1474 #endif
1475 END(ia32_interrupt)
1477 .org ia64_ivt+0x6c00
1478 /////////////////////////////////////////////////////////////////////////////////////////
1479 // 0x6c00 Entry 48 (size 16 bundles) Reserved
1480 DBG_FAULT(48)
1481 FAULT(48)
1483 .org ia64_ivt+0x6d00
1484 /////////////////////////////////////////////////////////////////////////////////////////
1485 // 0x6d00 Entry 49 (size 16 bundles) Reserved
1486 DBG_FAULT(49)
1487 FAULT(49)
1489 .org ia64_ivt+0x6e00
1490 /////////////////////////////////////////////////////////////////////////////////////////
1491 // 0x6e00 Entry 50 (size 16 bundles) Reserved
1492 DBG_FAULT(50)
1493 FAULT(50)
1495 .org ia64_ivt+0x6f00
1496 /////////////////////////////////////////////////////////////////////////////////////////
1497 // 0x6f00 Entry 51 (size 16 bundles) Reserved
1498 DBG_FAULT(51)
1499 FAULT(51)
1501 .org ia64_ivt+0x7000
1502 /////////////////////////////////////////////////////////////////////////////////////////
1503 // 0x7000 Entry 52 (size 16 bundles) Reserved
1504 DBG_FAULT(52)
1505 FAULT(52)
1507 .org ia64_ivt+0x7100
1508 /////////////////////////////////////////////////////////////////////////////////////////
1509 // 0x7100 Entry 53 (size 16 bundles) Reserved
1510 DBG_FAULT(53)
1511 FAULT(53)
1513 .org ia64_ivt+0x7200
1514 /////////////////////////////////////////////////////////////////////////////////////////
1515 // 0x7200 Entry 54 (size 16 bundles) Reserved
1516 DBG_FAULT(54)
1517 FAULT(54)
1519 .org ia64_ivt+0x7300
1520 /////////////////////////////////////////////////////////////////////////////////////////
1521 // 0x7300 Entry 55 (size 16 bundles) Reserved
1522 DBG_FAULT(55)
1523 FAULT(55)
1525 .org ia64_ivt+0x7400
1526 /////////////////////////////////////////////////////////////////////////////////////////
1527 // 0x7400 Entry 56 (size 16 bundles) Reserved
1528 DBG_FAULT(56)
1529 FAULT(56)
1531 .org ia64_ivt+0x7500
1532 /////////////////////////////////////////////////////////////////////////////////////////
1533 // 0x7500 Entry 57 (size 16 bundles) Reserved
1534 DBG_FAULT(57)
1535 FAULT(57)
1537 .org ia64_ivt+0x7600
1538 /////////////////////////////////////////////////////////////////////////////////////////
1539 // 0x7600 Entry 58 (size 16 bundles) Reserved
1540 DBG_FAULT(58)
1541 FAULT(58)
1543 .org ia64_ivt+0x7700
1544 /////////////////////////////////////////////////////////////////////////////////////////
1545 // 0x7700 Entry 59 (size 16 bundles) Reserved
1546 DBG_FAULT(59)
1547 FAULT(59)
1549 .org ia64_ivt+0x7800
1550 /////////////////////////////////////////////////////////////////////////////////////////
1551 // 0x7800 Entry 60 (size 16 bundles) Reserved
1552 DBG_FAULT(60)
1553 FAULT(60)
1555 .org ia64_ivt+0x7900
1556 /////////////////////////////////////////////////////////////////////////////////////////
1557 // 0x7900 Entry 61 (size 16 bundles) Reserved
1558 DBG_FAULT(61)
1559 FAULT(61)
1561 .org ia64_ivt+0x7a00
1562 /////////////////////////////////////////////////////////////////////////////////////////
1563 // 0x7a00 Entry 62 (size 16 bundles) Reserved
1564 DBG_FAULT(62)
1565 FAULT(62)
1567 .org ia64_ivt+0x7b00
1568 /////////////////////////////////////////////////////////////////////////////////////////
1569 // 0x7b00 Entry 63 (size 16 bundles) Reserved
1570 DBG_FAULT(63)
1571 FAULT(63)
1573 .org ia64_ivt+0x7c00
1574 /////////////////////////////////////////////////////////////////////////////////////////
1575 // 0x7c00 Entry 64 (size 16 bundles) Reserved
1576 DBG_FAULT(64)
1577 FAULT(64)
1579 .org ia64_ivt+0x7d00
1580 /////////////////////////////////////////////////////////////////////////////////////////
1581 // 0x7d00 Entry 65 (size 16 bundles) Reserved
1582 DBG_FAULT(65)
1583 FAULT(65)
1585 .org ia64_ivt+0x7e00
1586 /////////////////////////////////////////////////////////////////////////////////////////
1587 // 0x7e00 Entry 66 (size 16 bundles) Reserved
1588 DBG_FAULT(66)
1589 FAULT(66)
1591 .org ia64_ivt+0x7f00
1592 /////////////////////////////////////////////////////////////////////////////////////////
1593 // 0x7f00 Entry 67 (size 16 bundles) Reserved
1594 DBG_FAULT(67)
1595 FAULT(67)
1597 #ifdef CONFIG_IA32_SUPPORT
1599 /*
1600 * There is no particular reason for this code to be here, other than that
1601 * there happens to be space here that would go unused otherwise. If this
1602 * fault ever gets "unreserved", simply moved the following code to a more
1603 * suitable spot...
1604 */
1606 // IA32 interrupt entry point
1608 ENTRY(dispatch_to_ia32_handler)
1609 SAVE_MIN
1610 ;;
1611 mov r14=cr.isr
1612 ssm psr.ic | PSR_DEFAULT_BITS
1613 ;;
1614 srlz.i // guarantee that interruption collection is on
1615 ;;
1616 (p15) ssm psr.i
1617 adds r3=8,r2 // Base pointer for SAVE_REST
1618 ;;
1619 SAVE_REST
1620 ;;
1621 mov r15=0x80
1622 shr r14=r14,16 // Get interrupt number
1623 ;;
1624 cmp.ne p6,p0=r14,r15
1625 (p6) br.call.dpnt.many b6=non_ia32_syscall
1627 adds r14=IA64_PT_REGS_R8_OFFSET + 16,sp // 16 byte hole per SW conventions
1628 adds r15=IA64_PT_REGS_R1_OFFSET + 16,sp
1629 ;;
1630 cmp.eq pSys,pNonSys=r0,r0 // set pSys=1, pNonSys=0
1631 ld8 r8=[r14] // get r8
1632 ;;
1633 st8 [r15]=r8 // save original EAX in r1 (IA32 procs don't use the GP)
1634 ;;
1635 alloc r15=ar.pfs,0,0,6,0 // must first in an insn group
1636 ;;
1637 ld4 r8=[r14],8 // r8 == eax (syscall number)
1638 mov r15=IA32_NR_syscalls
1639 ;;
1640 cmp.ltu.unc p6,p7=r8,r15
1641 ld4 out1=[r14],8 // r9 == ecx
1642 ;;
1643 ld4 out2=[r14],8 // r10 == edx
1644 ;;
1645 ld4 out0=[r14] // r11 == ebx
1646 adds r14=(IA64_PT_REGS_R13_OFFSET) + 16,sp
1647 ;;
1648 ld4 out5=[r14],PT(R14)-PT(R13) // r13 == ebp
1649 ;;
1650 ld4 out3=[r14],PT(R15)-PT(R14) // r14 == esi
1651 adds r2=TI_FLAGS+IA64_TASK_SIZE,r13
1652 ;;
1653 ld4 out4=[r14] // r15 == edi
1654 movl r16=ia32_syscall_table
1655 ;;
1656 (p6) shladd r16=r8,3,r16 // force ni_syscall if not valid syscall number
1657 ld4 r2=[r2] // r2 = current_thread_info()->flags
1658 ;;
1659 ld8 r16=[r16]
1660 and r2=_TIF_SYSCALL_TRACEAUDIT,r2 // mask trace or audit
1661 ;;
1662 mov b6=r16
1663 movl r15=ia32_ret_from_syscall
1664 cmp.eq p8,p0=r2,r0
1665 ;;
1666 mov rp=r15
1667 (p8) br.call.sptk.many b6=b6
1668 br.cond.sptk ia32_trace_syscall
1670 non_ia32_syscall:
1671 alloc r15=ar.pfs,0,0,2,0
1672 mov out0=r14 // interrupt #
1673 add out1=16,sp // pointer to pt_regs
1674 ;; // avoid WAW on CFM
1675 br.call.sptk.many rp=ia32_bad_interrupt
1676 .ret1: movl r15=ia64_leave_kernel
1677 ;;
1678 mov rp=r15
1679 br.ret.sptk.many rp
1680 END(dispatch_to_ia32_handler)
1682 #endif /* CONFIG_IA32_SUPPORT */