USB: ftdi_sio: Add more identifiers
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / gpio / gpio-mpc8xxx.c
blob5cd04b65c55610f1e015f25738f7c9f3b2649df7
1 /*
2 * GPIOs on MPC512x/8349/8572/8610 and compatible
4 * Copyright (C) 2008 Peter Korsgaard <jacmet@sunsite.dk>
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
11 #include <linux/kernel.h>
12 #include <linux/init.h>
13 #include <linux/spinlock.h>
14 #include <linux/io.h>
15 #include <linux/of.h>
16 #include <linux/of_gpio.h>
17 #include <linux/gpio.h>
18 #include <linux/slab.h>
19 #include <linux/irq.h>
21 #define MPC8XXX_GPIO_PINS 32
23 #define GPIO_DIR 0x00
24 #define GPIO_ODR 0x04
25 #define GPIO_DAT 0x08
26 #define GPIO_IER 0x0c
27 #define GPIO_IMR 0x10
28 #define GPIO_ICR 0x14
29 #define GPIO_ICR2 0x18
31 struct mpc8xxx_gpio_chip {
32 struct of_mm_gpio_chip mm_gc;
33 spinlock_t lock;
36 * shadowed data register to be able to clear/set output pins in
37 * open drain mode safely
39 u32 data;
40 struct irq_host *irq;
41 void *of_dev_id_data;
44 static inline u32 mpc8xxx_gpio2mask(unsigned int gpio)
46 return 1u << (MPC8XXX_GPIO_PINS - 1 - gpio);
49 static inline struct mpc8xxx_gpio_chip *
50 to_mpc8xxx_gpio_chip(struct of_mm_gpio_chip *mm)
52 return container_of(mm, struct mpc8xxx_gpio_chip, mm_gc);
55 static void mpc8xxx_gpio_save_regs(struct of_mm_gpio_chip *mm)
57 struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
59 mpc8xxx_gc->data = in_be32(mm->regs + GPIO_DAT);
62 /* Workaround GPIO 1 errata on MPC8572/MPC8536. The status of GPIOs
63 * defined as output cannot be determined by reading GPDAT register,
64 * so we use shadow data register instead. The status of input pins
65 * is determined by reading GPDAT register.
67 static int mpc8572_gpio_get(struct gpio_chip *gc, unsigned int gpio)
69 u32 val;
70 struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
71 struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
73 val = in_be32(mm->regs + GPIO_DAT) & ~in_be32(mm->regs + GPIO_DIR);
75 return (val | mpc8xxx_gc->data) & mpc8xxx_gpio2mask(gpio);
78 static int mpc8xxx_gpio_get(struct gpio_chip *gc, unsigned int gpio)
80 struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
82 return in_be32(mm->regs + GPIO_DAT) & mpc8xxx_gpio2mask(gpio);
85 static void mpc8xxx_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
87 struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
88 struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
89 unsigned long flags;
91 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
93 if (val)
94 mpc8xxx_gc->data |= mpc8xxx_gpio2mask(gpio);
95 else
96 mpc8xxx_gc->data &= ~mpc8xxx_gpio2mask(gpio);
98 out_be32(mm->regs + GPIO_DAT, mpc8xxx_gc->data);
100 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
103 static int mpc8xxx_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
105 struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
106 struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
107 unsigned long flags;
109 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
111 clrbits32(mm->regs + GPIO_DIR, mpc8xxx_gpio2mask(gpio));
113 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
115 return 0;
118 static int mpc8xxx_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
120 struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
121 struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
122 unsigned long flags;
124 mpc8xxx_gpio_set(gc, gpio, val);
126 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
128 setbits32(mm->regs + GPIO_DIR, mpc8xxx_gpio2mask(gpio));
130 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
132 return 0;
135 static int mpc5121_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
137 /* GPIO 28..31 are input only on MPC5121 */
138 if (gpio >= 28)
139 return -EINVAL;
141 return mpc8xxx_gpio_dir_out(gc, gpio, val);
144 static int mpc8xxx_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
146 struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
147 struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
149 if (mpc8xxx_gc->irq && offset < MPC8XXX_GPIO_PINS)
150 return irq_create_mapping(mpc8xxx_gc->irq, offset);
151 else
152 return -ENXIO;
155 static void mpc8xxx_gpio_irq_cascade(unsigned int irq, struct irq_desc *desc)
157 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_desc_get_handler_data(desc);
158 struct irq_chip *chip = irq_desc_get_chip(desc);
159 struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
160 unsigned int mask;
162 mask = in_be32(mm->regs + GPIO_IER) & in_be32(mm->regs + GPIO_IMR);
163 if (mask)
164 generic_handle_irq(irq_linear_revmap(mpc8xxx_gc->irq,
165 32 - ffs(mask)));
166 chip->irq_eoi(&desc->irq_data);
169 static void mpc8xxx_irq_unmask(struct irq_data *d)
171 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
172 struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
173 unsigned long flags;
175 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
177 setbits32(mm->regs + GPIO_IMR, mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
179 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
182 static void mpc8xxx_irq_mask(struct irq_data *d)
184 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
185 struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
186 unsigned long flags;
188 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
190 clrbits32(mm->regs + GPIO_IMR, mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
192 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
195 static void mpc8xxx_irq_ack(struct irq_data *d)
197 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
198 struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
200 out_be32(mm->regs + GPIO_IER, mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
203 static int mpc8xxx_irq_set_type(struct irq_data *d, unsigned int flow_type)
205 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
206 struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
207 unsigned long flags;
209 switch (flow_type) {
210 case IRQ_TYPE_EDGE_FALLING:
211 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
212 setbits32(mm->regs + GPIO_ICR,
213 mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
214 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
215 break;
217 case IRQ_TYPE_EDGE_BOTH:
218 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
219 clrbits32(mm->regs + GPIO_ICR,
220 mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
221 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
222 break;
224 default:
225 return -EINVAL;
228 return 0;
231 static int mpc512x_irq_set_type(struct irq_data *d, unsigned int flow_type)
233 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
234 struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
235 unsigned long gpio = irqd_to_hwirq(d);
236 void __iomem *reg;
237 unsigned int shift;
238 unsigned long flags;
240 if (gpio < 16) {
241 reg = mm->regs + GPIO_ICR;
242 shift = (15 - gpio) * 2;
243 } else {
244 reg = mm->regs + GPIO_ICR2;
245 shift = (15 - (gpio % 16)) * 2;
248 switch (flow_type) {
249 case IRQ_TYPE_EDGE_FALLING:
250 case IRQ_TYPE_LEVEL_LOW:
251 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
252 clrsetbits_be32(reg, 3 << shift, 2 << shift);
253 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
254 break;
256 case IRQ_TYPE_EDGE_RISING:
257 case IRQ_TYPE_LEVEL_HIGH:
258 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
259 clrsetbits_be32(reg, 3 << shift, 1 << shift);
260 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
261 break;
263 case IRQ_TYPE_EDGE_BOTH:
264 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
265 clrbits32(reg, 3 << shift);
266 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
267 break;
269 default:
270 return -EINVAL;
273 return 0;
276 static struct irq_chip mpc8xxx_irq_chip = {
277 .name = "mpc8xxx-gpio",
278 .irq_unmask = mpc8xxx_irq_unmask,
279 .irq_mask = mpc8xxx_irq_mask,
280 .irq_ack = mpc8xxx_irq_ack,
281 .irq_set_type = mpc8xxx_irq_set_type,
284 static int mpc8xxx_gpio_irq_map(struct irq_host *h, unsigned int virq,
285 irq_hw_number_t hw)
287 struct mpc8xxx_gpio_chip *mpc8xxx_gc = h->host_data;
289 if (mpc8xxx_gc->of_dev_id_data)
290 mpc8xxx_irq_chip.irq_set_type = mpc8xxx_gc->of_dev_id_data;
292 irq_set_chip_data(virq, h->host_data);
293 irq_set_chip_and_handler(virq, &mpc8xxx_irq_chip, handle_level_irq);
294 irq_set_irq_type(virq, IRQ_TYPE_NONE);
296 return 0;
299 static int mpc8xxx_gpio_irq_xlate(struct irq_host *h, struct device_node *ct,
300 const u32 *intspec, unsigned int intsize,
301 irq_hw_number_t *out_hwirq,
302 unsigned int *out_flags)
305 /* interrupt sense values coming from the device tree equal either
306 * EDGE_FALLING or EDGE_BOTH
308 *out_hwirq = intspec[0];
309 *out_flags = intspec[1];
311 return 0;
314 static struct irq_host_ops mpc8xxx_gpio_irq_ops = {
315 .map = mpc8xxx_gpio_irq_map,
316 .xlate = mpc8xxx_gpio_irq_xlate,
319 static struct of_device_id mpc8xxx_gpio_ids[] __initdata = {
320 { .compatible = "fsl,mpc8349-gpio", },
321 { .compatible = "fsl,mpc8572-gpio", },
322 { .compatible = "fsl,mpc8610-gpio", },
323 { .compatible = "fsl,mpc5121-gpio", .data = mpc512x_irq_set_type, },
324 { .compatible = "fsl,pq3-gpio", },
325 { .compatible = "fsl,qoriq-gpio", },
329 static void __init mpc8xxx_add_controller(struct device_node *np)
331 struct mpc8xxx_gpio_chip *mpc8xxx_gc;
332 struct of_mm_gpio_chip *mm_gc;
333 struct gpio_chip *gc;
334 const struct of_device_id *id;
335 unsigned hwirq;
336 int ret;
338 mpc8xxx_gc = kzalloc(sizeof(*mpc8xxx_gc), GFP_KERNEL);
339 if (!mpc8xxx_gc) {
340 ret = -ENOMEM;
341 goto err;
344 spin_lock_init(&mpc8xxx_gc->lock);
346 mm_gc = &mpc8xxx_gc->mm_gc;
347 gc = &mm_gc->gc;
349 mm_gc->save_regs = mpc8xxx_gpio_save_regs;
350 gc->ngpio = MPC8XXX_GPIO_PINS;
351 gc->direction_input = mpc8xxx_gpio_dir_in;
352 gc->direction_output = of_device_is_compatible(np, "fsl,mpc5121-gpio") ?
353 mpc5121_gpio_dir_out : mpc8xxx_gpio_dir_out;
354 gc->get = of_device_is_compatible(np, "fsl,mpc8572-gpio") ?
355 mpc8572_gpio_get : mpc8xxx_gpio_get;
356 gc->set = mpc8xxx_gpio_set;
357 gc->to_irq = mpc8xxx_gpio_to_irq;
359 ret = of_mm_gpiochip_add(np, mm_gc);
360 if (ret)
361 goto err;
363 hwirq = irq_of_parse_and_map(np, 0);
364 if (hwirq == NO_IRQ)
365 goto skip_irq;
367 mpc8xxx_gc->irq =
368 irq_alloc_host(np, IRQ_HOST_MAP_LINEAR, MPC8XXX_GPIO_PINS,
369 &mpc8xxx_gpio_irq_ops, MPC8XXX_GPIO_PINS);
370 if (!mpc8xxx_gc->irq)
371 goto skip_irq;
373 id = of_match_node(mpc8xxx_gpio_ids, np);
374 if (id)
375 mpc8xxx_gc->of_dev_id_data = id->data;
377 mpc8xxx_gc->irq->host_data = mpc8xxx_gc;
379 /* ack and mask all irqs */
380 out_be32(mm_gc->regs + GPIO_IER, 0xffffffff);
381 out_be32(mm_gc->regs + GPIO_IMR, 0);
383 irq_set_handler_data(hwirq, mpc8xxx_gc);
384 irq_set_chained_handler(hwirq, mpc8xxx_gpio_irq_cascade);
386 skip_irq:
387 return;
389 err:
390 pr_err("%s: registration failed with status %d\n",
391 np->full_name, ret);
392 kfree(mpc8xxx_gc);
394 return;
397 static int __init mpc8xxx_add_gpiochips(void)
399 struct device_node *np;
401 for_each_matching_node(np, mpc8xxx_gpio_ids)
402 mpc8xxx_add_controller(np);
404 return 0;
406 arch_initcall(mpc8xxx_add_gpiochips);