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sky2: convert to SKB paged frag API.
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / ethernet / marvell / sky2.c
blobef2dc021d09c8a6a6f2023a8157b17a5a956e6ec
1 /*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
25 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
26
27 #include <linux/crc32.h>
28 #include <linux/kernel.h>
29 #include <linux/module.h>
30 #include <linux/netdevice.h>
31 #include <linux/dma-mapping.h>
32 #include <linux/etherdevice.h>
33 #include <linux/ethtool.h>
34 #include <linux/pci.h>
35 #include <linux/interrupt.h>
36 #include <linux/ip.h>
37 #include <linux/slab.h>
38 #include <net/ip.h>
39 #include <linux/tcp.h>
40 #include <linux/in.h>
41 #include <linux/delay.h>
42 #include <linux/workqueue.h>
43 #include <linux/if_vlan.h>
44 #include <linux/prefetch.h>
45 #include <linux/debugfs.h>
46 #include <linux/mii.h>
47
48 #include <asm/irq.h>
49
50 #include "sky2.h"
51
52 #define DRV_NAME "sky2"
53 #define DRV_VERSION "1.29"
54
55 /*
56 * The Yukon II chipset takes 64 bit command blocks (called list elements)
57 * that are organized into three (receive, transmit, status) different rings
58 * similar to Tigon3.
59 */
60
61 #define RX_LE_SIZE 1024
62 #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
63 #define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
64 #define RX_DEF_PENDING RX_MAX_PENDING
65
66 /* This is the worst case number of transmit list elements for a single skb:
67 VLAN:GSO + CKSUM + Data + skb_frags * DMA */
68 #define MAX_SKB_TX_LE (2 + (sizeof(dma_addr_t)/sizeof(u32))*(MAX_SKB_FRAGS+1))
69 #define TX_MIN_PENDING (MAX_SKB_TX_LE+1)
70 #define TX_MAX_PENDING 1024
71 #define TX_DEF_PENDING 127
72
73 #define TX_WATCHDOG (5 * HZ)
74 #define NAPI_WEIGHT 64
75 #define PHY_RETRIES 1000
76
77 #define SKY2_EEPROM_MAGIC 0x9955aabb
78
79 #define RING_NEXT(x, s) (((x)+1) & ((s)-1))
80
81 static const u32 default_msg =
82 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
83 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
84 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
85
86 static int debug = -1; /* defaults above */
87 module_param(debug, int, 0);
88 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
89
90 static int copybreak __read_mostly = 128;
91 module_param(copybreak, int, 0);
92 MODULE_PARM_DESC(copybreak, "Receive copy threshold");
93
94 static int disable_msi = 0;
95 module_param(disable_msi, int, 0);
96 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
97
98 static DEFINE_PCI_DEVICE_TABLE(sky2_id_table) = {
99 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
100 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
101 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E01) }, /* SK-9E21M */
102 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
103 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
104 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
105 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
106 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
107 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
108 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4354) }, /* 88E8040 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4355) }, /* 88E8040T */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4357) }, /* 88E8042 */
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x435A) }, /* 88E8048 */
123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) }, /* 88E8070 */
129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
135 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436C) }, /* 88E8072 */
136 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436D) }, /* 88E8055 */
137 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4370) }, /* 88E8075 */
138 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4380) }, /* 88E8057 */
139 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4381) }, /* 88E8059 */
140 { 0 }
141 };
142
143 MODULE_DEVICE_TABLE(pci, sky2_id_table);
144
145 /* Avoid conditionals by using array */
146 static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
147 static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
148 static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
149
150 static void sky2_set_multicast(struct net_device *dev);
151
152 /* Access to PHY via serial interconnect */
153 static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
154 {
155 int i;
156
157 gma_write16(hw, port, GM_SMI_DATA, val);
158 gma_write16(hw, port, GM_SMI_CTRL,
159 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
160
161 for (i = 0; i < PHY_RETRIES; i++) {
162 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
163 if (ctrl == 0xffff)
164 goto io_error;
165
166 if (!(ctrl & GM_SMI_CT_BUSY))
167 return 0;
168
169 udelay(10);
170 }
171
172 dev_warn(&hw->pdev->dev, "%s: phy write timeout\n", hw->dev[port]->name);
173 return -ETIMEDOUT;
174
175 io_error:
176 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
177 return -EIO;
178 }
179
180 static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
181 {
182 int i;
183
184 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
185 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
186
187 for (i = 0; i < PHY_RETRIES; i++) {
188 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
189 if (ctrl == 0xffff)
190 goto io_error;
191
192 if (ctrl & GM_SMI_CT_RD_VAL) {
193 *val = gma_read16(hw, port, GM_SMI_DATA);
194 return 0;
195 }
196
197 udelay(10);
198 }
199
200 dev_warn(&hw->pdev->dev, "%s: phy read timeout\n", hw->dev[port]->name);
201 return -ETIMEDOUT;
202 io_error:
203 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
204 return -EIO;
205 }
206
207 static inline u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
208 {
209 u16 v;
210 __gm_phy_read(hw, port, reg, &v);
211 return v;
212 }
213
214
215 static void sky2_power_on(struct sky2_hw *hw)
216 {
217 /* switch power to VCC (WA for VAUX problem) */
218 sky2_write8(hw, B0_POWER_CTRL,
219 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
220
221 /* disable Core Clock Division, */
222 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
223
224 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > CHIP_REV_YU_XL_A1)
225 /* enable bits are inverted */
226 sky2_write8(hw, B2_Y2_CLK_GATE,
227 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
228 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
229 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
230 else
231 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
232
233 if (hw->flags & SKY2_HW_ADV_POWER_CTL) {
234 u32 reg;
235
236 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
237
238 reg = sky2_pci_read32(hw, PCI_DEV_REG4);
239 /* set all bits to 0 except bits 15..12 and 8 */
240 reg &= P_ASPM_CONTROL_MSK;
241 sky2_pci_write32(hw, PCI_DEV_REG4, reg);
242
243 reg = sky2_pci_read32(hw, PCI_DEV_REG5);
244 /* set all bits to 0 except bits 28 & 27 */
245 reg &= P_CTL_TIM_VMAIN_AV_MSK;
246 sky2_pci_write32(hw, PCI_DEV_REG5, reg);
247
248 sky2_pci_write32(hw, PCI_CFG_REG_1, 0);
249
250 sky2_write16(hw, B0_CTST, Y2_HW_WOL_ON);
251
252 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
253 reg = sky2_read32(hw, B2_GP_IO);
254 reg |= GLB_GPIO_STAT_RACE_DIS;
255 sky2_write32(hw, B2_GP_IO, reg);
256
257 sky2_read32(hw, B2_GP_IO);
258 }
259
260 /* Turn on "driver loaded" LED */
261 sky2_write16(hw, B0_CTST, Y2_LED_STAT_ON);
262 }
263
264 static void sky2_power_aux(struct sky2_hw *hw)
265 {
266 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > CHIP_REV_YU_XL_A1)
267 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
268 else
269 /* enable bits are inverted */
270 sky2_write8(hw, B2_Y2_CLK_GATE,
271 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
272 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
273 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
274
275 /* switch power to VAUX if supported and PME from D3cold */
276 if ( (sky2_read32(hw, B0_CTST) & Y2_VAUX_AVAIL) &&
277 pci_pme_capable(hw->pdev, PCI_D3cold))
278 sky2_write8(hw, B0_POWER_CTRL,
279 (PC_VAUX_ENA | PC_VCC_ENA |
280 PC_VAUX_ON | PC_VCC_OFF));
281
282 /* turn off "driver loaded LED" */
283 sky2_write16(hw, B0_CTST, Y2_LED_STAT_OFF);
284 }
285
286 static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
287 {
288 u16 reg;
289
290 /* disable all GMAC IRQ's */
291 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
292
293 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
294 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
295 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
296 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
297
298 reg = gma_read16(hw, port, GM_RX_CTRL);
299 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
300 gma_write16(hw, port, GM_RX_CTRL, reg);
301 }
302
303 /* flow control to advertise bits */
304 static const u16 copper_fc_adv[] = {
305 [FC_NONE] = 0,
306 [FC_TX] = PHY_M_AN_ASP,
307 [FC_RX] = PHY_M_AN_PC,
308 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
309 };
310
311 /* flow control to advertise bits when using 1000BaseX */
312 static const u16 fiber_fc_adv[] = {
313 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
314 [FC_TX] = PHY_M_P_ASYM_MD_X,
315 [FC_RX] = PHY_M_P_SYM_MD_X,
316 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
317 };
318
319 /* flow control to GMA disable bits */
320 static const u16 gm_fc_disable[] = {
321 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
322 [FC_TX] = GM_GPCR_FC_RX_DIS,
323 [FC_RX] = GM_GPCR_FC_TX_DIS,
324 [FC_BOTH] = 0,
325 };
326
327
328 static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
329 {
330 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
331 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
332
333 if ( (sky2->flags & SKY2_FLAG_AUTO_SPEED) &&
334 !(hw->flags & SKY2_HW_NEWER_PHY)) {
335 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
336
337 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
338 PHY_M_EC_MAC_S_MSK);
339 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
340
341 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
342 if (hw->chip_id == CHIP_ID_YUKON_EC)
343 /* set downshift counter to 3x and enable downshift */
344 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
345 else
346 /* set master & slave downshift counter to 1x */
347 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
348
349 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
350 }
351
352 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
353 if (sky2_is_copper(hw)) {
354 if (!(hw->flags & SKY2_HW_GIGABIT)) {
355 /* enable automatic crossover */
356 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
357
358 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
359 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
360 u16 spec;
361
362 /* Enable Class A driver for FE+ A0 */
363 spec = gm_phy_read(hw, port, PHY_MARV_FE_SPEC_2);
364 spec |= PHY_M_FESC_SEL_CL_A;
365 gm_phy_write(hw, port, PHY_MARV_FE_SPEC_2, spec);
366 }
367 } else {
368 if (hw->chip_id >= CHIP_ID_YUKON_OPT) {
369 u16 ctrl2 = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL_2);
370
371 /* enable PHY Reverse Auto-Negotiation */
372 ctrl2 |= 1u << 13;
373
374 /* Write PHY changes (SW-reset must follow) */
375 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL_2, ctrl2);
376 }
377
378
379 /* disable energy detect */
380 ctrl &= ~PHY_M_PC_EN_DET_MSK;
381
382 /* enable automatic crossover */
383 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
384
385 /* downshift on PHY 88E1112 and 88E1149 is changed */
386 if ( (sky2->flags & SKY2_FLAG_AUTO_SPEED) &&
387 (hw->flags & SKY2_HW_NEWER_PHY)) {
388 /* set downshift counter to 3x and enable downshift */
389 ctrl &= ~PHY_M_PC_DSC_MSK;
390 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
391 }
392 }
393 } else {
394 /* workaround for deviation #4.88 (CRC errors) */
395 /* disable Automatic Crossover */
396
397 ctrl &= ~PHY_M_PC_MDIX_MSK;
398 }
399
400 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
401
402 /* special setup for PHY 88E1112 Fiber */
403 if (hw->chip_id == CHIP_ID_YUKON_XL && (hw->flags & SKY2_HW_FIBRE_PHY)) {
404 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
405
406 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
407 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
408 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
409 ctrl &= ~PHY_M_MAC_MD_MSK;
410 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
411 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
412
413 if (hw->pmd_type == 'P') {
414 /* select page 1 to access Fiber registers */
415 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
416
417 /* for SFP-module set SIGDET polarity to low */
418 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
419 ctrl |= PHY_M_FIB_SIGD_POL;
420 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
421 }
422
423 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
424 }
425
426 ctrl = PHY_CT_RESET;
427 ct1000 = 0;
428 adv = PHY_AN_CSMA;
429 reg = 0;
430
431 if (sky2->flags & SKY2_FLAG_AUTO_SPEED) {
432 if (sky2_is_copper(hw)) {
433 if (sky2->advertising & ADVERTISED_1000baseT_Full)
434 ct1000 |= PHY_M_1000C_AFD;
435 if (sky2->advertising & ADVERTISED_1000baseT_Half)
436 ct1000 |= PHY_M_1000C_AHD;
437 if (sky2->advertising & ADVERTISED_100baseT_Full)
438 adv |= PHY_M_AN_100_FD;
439 if (sky2->advertising & ADVERTISED_100baseT_Half)
440 adv |= PHY_M_AN_100_HD;
441 if (sky2->advertising & ADVERTISED_10baseT_Full)
442 adv |= PHY_M_AN_10_FD;
443 if (sky2->advertising & ADVERTISED_10baseT_Half)
444 adv |= PHY_M_AN_10_HD;
445
446 } else { /* special defines for FIBER (88E1040S only) */
447 if (sky2->advertising & ADVERTISED_1000baseT_Full)
448 adv |= PHY_M_AN_1000X_AFD;
449 if (sky2->advertising & ADVERTISED_1000baseT_Half)
450 adv |= PHY_M_AN_1000X_AHD;
451 }
452
453 /* Restart Auto-negotiation */
454 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
455 } else {
456 /* forced speed/duplex settings */
457 ct1000 = PHY_M_1000C_MSE;
458
459 /* Disable auto update for duplex flow control and duplex */
460 reg |= GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_SPD_DIS;
461
462 switch (sky2->speed) {
463 case SPEED_1000:
464 ctrl |= PHY_CT_SP1000;
465 reg |= GM_GPCR_SPEED_1000;
466 break;
467 case SPEED_100:
468 ctrl |= PHY_CT_SP100;
469 reg |= GM_GPCR_SPEED_100;
470 break;
471 }
472
473 if (sky2->duplex == DUPLEX_FULL) {
474 reg |= GM_GPCR_DUP_FULL;
475 ctrl |= PHY_CT_DUP_MD;
476 } else if (sky2->speed < SPEED_1000)
477 sky2->flow_mode = FC_NONE;
478 }
479
480 if (sky2->flags & SKY2_FLAG_AUTO_PAUSE) {
481 if (sky2_is_copper(hw))
482 adv |= copper_fc_adv[sky2->flow_mode];
483 else
484 adv |= fiber_fc_adv[sky2->flow_mode];
485 } else {
486 reg |= GM_GPCR_AU_FCT_DIS;
487 reg |= gm_fc_disable[sky2->flow_mode];
488
489 /* Forward pause packets to GMAC? */
490 if (sky2->flow_mode & FC_RX)
491 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
492 else
493 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
494 }
495
496 gma_write16(hw, port, GM_GP_CTRL, reg);
497
498 if (hw->flags & SKY2_HW_GIGABIT)
499 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
500
501 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
502 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
503
504 /* Setup Phy LED's */
505 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
506 ledover = 0;
507
508 switch (hw->chip_id) {
509 case CHIP_ID_YUKON_FE:
510 /* on 88E3082 these bits are at 11..9 (shifted left) */
511 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
512
513 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
514
515 /* delete ACT LED control bits */
516 ctrl &= ~PHY_M_FELP_LED1_MSK;
517 /* change ACT LED control to blink mode */
518 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
519 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
520 break;
521
522 case CHIP_ID_YUKON_FE_P:
523 /* Enable Link Partner Next Page */
524 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
525 ctrl |= PHY_M_PC_ENA_LIP_NP;
526
527 /* disable Energy Detect and enable scrambler */
528 ctrl &= ~(PHY_M_PC_ENA_ENE_DT | PHY_M_PC_DIS_SCRAMB);
529 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
530
531 /* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */
532 ctrl = PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL) |
533 PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_LINK) |
534 PHY_M_FELP_LED0_CTRL(LED_PAR_CTRL_SPEED);
535
536 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
537 break;
538
539 case CHIP_ID_YUKON_XL:
540 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
541
542 /* select page 3 to access LED control register */
543 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
544
545 /* set LED Function Control register */
546 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
547 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
548 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
549 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
550 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
551
552 /* set Polarity Control register */
553 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
554 (PHY_M_POLC_LS1_P_MIX(4) |
555 PHY_M_POLC_IS0_P_MIX(4) |
556 PHY_M_POLC_LOS_CTRL(2) |
557 PHY_M_POLC_INIT_CTRL(2) |
558 PHY_M_POLC_STA1_CTRL(2) |
559 PHY_M_POLC_STA0_CTRL(2)));
560
561 /* restore page register */
562 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
563 break;
564
565 case CHIP_ID_YUKON_EC_U:
566 case CHIP_ID_YUKON_EX:
567 case CHIP_ID_YUKON_SUPR:
568 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
569
570 /* select page 3 to access LED control register */
571 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
572
573 /* set LED Function Control register */
574 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
575 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
576 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
577 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
578 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
579
580 /* set Blink Rate in LED Timer Control Register */
581 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
582 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
583 /* restore page register */
584 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
585 break;
586
587 default:
588 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
589 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
590
591 /* turn off the Rx LED (LED_RX) */
592 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
593 }
594
595 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_UL_2) {
596 /* apply fixes in PHY AFE */
597 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
598
599 /* increase differential signal amplitude in 10BASE-T */
600 gm_phy_write(hw, port, 0x18, 0xaa99);
601 gm_phy_write(hw, port, 0x17, 0x2011);
602
603 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
604 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
605 gm_phy_write(hw, port, 0x18, 0xa204);
606 gm_phy_write(hw, port, 0x17, 0x2002);
607 }
608
609 /* set page register to 0 */
610 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
611 } else if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
612 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
613 /* apply workaround for integrated resistors calibration */
614 gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17);
615 gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60);
616 } else if (hw->chip_id == CHIP_ID_YUKON_OPT && hw->chip_rev == 0) {
617 /* apply fixes in PHY AFE */
618 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00ff);
619
620 /* apply RDAC termination workaround */
621 gm_phy_write(hw, port, 24, 0x2800);
622 gm_phy_write(hw, port, 23, 0x2001);
623
624 /* set page register back to 0 */
625 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
626 } else if (hw->chip_id != CHIP_ID_YUKON_EX &&
627 hw->chip_id < CHIP_ID_YUKON_SUPR) {
628 /* no effect on Yukon-XL */
629 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
630
631 if (!(sky2->flags & SKY2_FLAG_AUTO_SPEED) ||
632 sky2->speed == SPEED_100) {
633 /* turn on 100 Mbps LED (LED_LINK100) */
634 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
635 }
636
637 if (ledover)
638 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
639
640 } else if (hw->chip_id == CHIP_ID_YUKON_PRM &&
641 (sky2_read8(hw, B2_MAC_CFG) & 0xf) == 0x7) {
642 int i;
643 /* This a phy register setup workaround copied from vendor driver. */
644 static const struct {
645 u16 reg, val;
646 } eee_afe[] = {
647 { 0x156, 0x58ce },
648 { 0x153, 0x99eb },
649 { 0x141, 0x8064 },
650 /* { 0x155, 0x130b },*/
651 { 0x000, 0x0000 },
652 { 0x151, 0x8433 },
653 { 0x14b, 0x8c44 },
654 { 0x14c, 0x0f90 },
655 { 0x14f, 0x39aa },
656 /* { 0x154, 0x2f39 },*/
657 { 0x14d, 0xba33 },
658 { 0x144, 0x0048 },
659 { 0x152, 0x2010 },
660 /* { 0x158, 0x1223 },*/
661 { 0x140, 0x4444 },
662 { 0x154, 0x2f3b },
663 { 0x158, 0xb203 },
664 { 0x157, 0x2029 },
665 };
666
667 /* Start Workaround for OptimaEEE Rev.Z0 */
668 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00fb);
669
670 gm_phy_write(hw, port, 1, 0x4099);
671 gm_phy_write(hw, port, 3, 0x1120);
672 gm_phy_write(hw, port, 11, 0x113c);
673 gm_phy_write(hw, port, 14, 0x8100);
674 gm_phy_write(hw, port, 15, 0x112a);
675 gm_phy_write(hw, port, 17, 0x1008);
676
677 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00fc);
678 gm_phy_write(hw, port, 1, 0x20b0);
679
680 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00ff);
681
682 for (i = 0; i < ARRAY_SIZE(eee_afe); i++) {
683 /* apply AFE settings */
684 gm_phy_write(hw, port, 17, eee_afe[i].val);
685 gm_phy_write(hw, port, 16, eee_afe[i].reg | 1u<<13);
686 }
687
688 /* End Workaround for OptimaEEE */
689 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
690
691 /* Enable 10Base-Te (EEE) */
692 if (hw->chip_id >= CHIP_ID_YUKON_PRM) {
693 reg = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
694 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL,
695 reg | PHY_M_10B_TE_ENABLE);
696 }
697 }
698
699 /* Enable phy interrupt on auto-negotiation complete (or link up) */
700 if (sky2->flags & SKY2_FLAG_AUTO_SPEED)
701 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
702 else
703 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
704 }
705
706 static const u32 phy_power[] = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
707 static const u32 coma_mode[] = { PCI_Y2_PHY1_COMA, PCI_Y2_PHY2_COMA };
708
709 static void sky2_phy_power_up(struct sky2_hw *hw, unsigned port)
710 {
711 u32 reg1;
712
713 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
714 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
715 reg1 &= ~phy_power[port];
716
717 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > CHIP_REV_YU_XL_A1)
718 reg1 |= coma_mode[port];
719
720 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
721 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
722 sky2_pci_read32(hw, PCI_DEV_REG1);
723
724 if (hw->chip_id == CHIP_ID_YUKON_FE)
725 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_ANE);
726 else if (hw->flags & SKY2_HW_ADV_POWER_CTL)
727 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
728 }
729
730 static void sky2_phy_power_down(struct sky2_hw *hw, unsigned port)
731 {
732 u32 reg1;
733 u16 ctrl;
734
735 /* release GPHY Control reset */
736 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
737
738 /* release GMAC reset */
739 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
740
741 if (hw->flags & SKY2_HW_NEWER_PHY) {
742 /* select page 2 to access MAC control register */
743 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
744
745 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
746 /* allow GMII Power Down */
747 ctrl &= ~PHY_M_MAC_GMIF_PUP;
748 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
749
750 /* set page register back to 0 */
751 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
752 }
753
754 /* setup General Purpose Control Register */
755 gma_write16(hw, port, GM_GP_CTRL,
756 GM_GPCR_FL_PASS | GM_GPCR_SPEED_100 |
757 GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS |
758 GM_GPCR_AU_SPD_DIS);
759
760 if (hw->chip_id != CHIP_ID_YUKON_EC) {
761 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
762 /* select page 2 to access MAC control register */
763 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
764
765 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
766 /* enable Power Down */
767 ctrl |= PHY_M_PC_POW_D_ENA;
768 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
769
770 /* set page register back to 0 */
771 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
772 }
773
774 /* set IEEE compatible Power Down Mode (dev. #4.99) */
775 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_PDOWN);
776 }
777
778 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
779 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
780 reg1 |= phy_power[port]; /* set PHY to PowerDown/COMA Mode */
781 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
782 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
783 }
784
785 /* configure IPG according to used link speed */
786 static void sky2_set_ipg(struct sky2_port *sky2)
787 {
788 u16 reg;
789
790 reg = gma_read16(sky2->hw, sky2->port, GM_SERIAL_MODE);
791 reg &= ~GM_SMOD_IPG_MSK;
792 if (sky2->speed > SPEED_100)
793 reg |= IPG_DATA_VAL(IPG_DATA_DEF_1000);
794 else
795 reg |= IPG_DATA_VAL(IPG_DATA_DEF_10_100);
796 gma_write16(sky2->hw, sky2->port, GM_SERIAL_MODE, reg);
797 }
798
799 /* Enable Rx/Tx */
800 static void sky2_enable_rx_tx(struct sky2_port *sky2)
801 {
802 struct sky2_hw *hw = sky2->hw;
803 unsigned port = sky2->port;
804 u16 reg;
805
806 reg = gma_read16(hw, port, GM_GP_CTRL);
807 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
808 gma_write16(hw, port, GM_GP_CTRL, reg);
809 }
810
811 /* Force a renegotiation */
812 static void sky2_phy_reinit(struct sky2_port *sky2)
813 {
814 spin_lock_bh(&sky2->phy_lock);
815 sky2_phy_init(sky2->hw, sky2->port);
816 sky2_enable_rx_tx(sky2);
817 spin_unlock_bh(&sky2->phy_lock);
818 }
819
820 /* Put device in state to listen for Wake On Lan */
821 static void sky2_wol_init(struct sky2_port *sky2)
822 {
823 struct sky2_hw *hw = sky2->hw;
824 unsigned port = sky2->port;
825 enum flow_control save_mode;
826 u16 ctrl;
827
828 /* Bring hardware out of reset */
829 sky2_write16(hw, B0_CTST, CS_RST_CLR);
830 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
831
832 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
833 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
834
835 /* Force to 10/100
836 * sky2_reset will re-enable on resume
837 */
838 save_mode = sky2->flow_mode;
839 ctrl = sky2->advertising;
840
841 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
842 sky2->flow_mode = FC_NONE;
843
844 spin_lock_bh(&sky2->phy_lock);
845 sky2_phy_power_up(hw, port);
846 sky2_phy_init(hw, port);
847 spin_unlock_bh(&sky2->phy_lock);
848
849 sky2->flow_mode = save_mode;
850 sky2->advertising = ctrl;
851
852 /* Set GMAC to no flow control and auto update for speed/duplex */
853 gma_write16(hw, port, GM_GP_CTRL,
854 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
855 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
856
857 /* Set WOL address */
858 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
859 sky2->netdev->dev_addr, ETH_ALEN);
860
861 /* Turn on appropriate WOL control bits */
862 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
863 ctrl = 0;
864 if (sky2->wol & WAKE_PHY)
865 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
866 else
867 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
868
869 if (sky2->wol & WAKE_MAGIC)
870 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
871 else
872 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;
873
874 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
875 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
876
877 /* Disable PiG firmware */
878 sky2_write16(hw, B0_CTST, Y2_HW_WOL_OFF);
879
880 /* block receiver */
881 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
882 }
883
884 static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port)
885 {
886 struct net_device *dev = hw->dev[port];
887
888 if ( (hw->chip_id == CHIP_ID_YUKON_EX &&
889 hw->chip_rev != CHIP_REV_YU_EX_A0) ||
890 hw->chip_id >= CHIP_ID_YUKON_FE_P) {
891 /* Yukon-Extreme B0 and further Extreme devices */
892 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA);
893 } else if (dev->mtu > ETH_DATA_LEN) {
894 /* set Tx GMAC FIFO Almost Empty Threshold */
895 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
896 (ECU_JUMBO_WM << 16) | ECU_AE_THR);
897
898 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
899 } else
900 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA);
901 }
902
903 static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
904 {
905 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
906 u16 reg;
907 u32 rx_reg;
908 int i;
909 const u8 *addr = hw->dev[port]->dev_addr;
910
911 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
912 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
913
914 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
915
916 if (hw->chip_id == CHIP_ID_YUKON_XL &&
917 hw->chip_rev == CHIP_REV_YU_XL_A0 &&
918 port == 1) {
919 /* WA DEV_472 -- looks like crossed wires on port 2 */
920 /* clear GMAC 1 Control reset */
921 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
922 do {
923 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
924 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
925 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
926 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
927 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
928 }
929
930 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
931
932 /* Enable Transmit FIFO Underrun */
933 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
934
935 spin_lock_bh(&sky2->phy_lock);
936 sky2_phy_power_up(hw, port);
937 sky2_phy_init(hw, port);
938 spin_unlock_bh(&sky2->phy_lock);
939
940 /* MIB clear */
941 reg = gma_read16(hw, port, GM_PHY_ADDR);
942 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
943
944 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
945 gma_read16(hw, port, i);
946 gma_write16(hw, port, GM_PHY_ADDR, reg);
947
948 /* transmit control */
949 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
950
951 /* receive control reg: unicast + multicast + no FCS */
952 gma_write16(hw, port, GM_RX_CTRL,
953 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
954
955 /* transmit flow control */
956 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
957
958 /* transmit parameter */
959 gma_write16(hw, port, GM_TX_PARAM,
960 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
961 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
962 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
963 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
964
965 /* serial mode register */
966 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
967 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF_1000);
968
969 if (hw->dev[port]->mtu > ETH_DATA_LEN)
970 reg |= GM_SMOD_JUMBO_ENA;
971
972 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
973 hw->chip_rev == CHIP_REV_YU_EC_U_B1)
974 reg |= GM_NEW_FLOW_CTRL;
975
976 gma_write16(hw, port, GM_SERIAL_MODE, reg);
977
978 /* virtual address for data */
979 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
980
981 /* physical address: used for pause frames */
982 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
983
984 /* ignore counter overflows */
985 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
986 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
987 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
988
989 /* Configure Rx MAC FIFO */
990 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
991 rx_reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
992 if (hw->chip_id == CHIP_ID_YUKON_EX ||
993 hw->chip_id == CHIP_ID_YUKON_FE_P)
994 rx_reg |= GMF_RX_OVER_ON;
995
996 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg);
997
998 if (hw->chip_id == CHIP_ID_YUKON_XL) {
999 /* Hardware errata - clear flush mask */
1000 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), 0);
1001 } else {
1002 /* Flush Rx MAC FIFO on any flow control or error */
1003 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
1004 }
1005
1006 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
1007 reg = RX_GMF_FL_THR_DEF + 1;
1008 /* Another magic mystery workaround from sk98lin */
1009 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
1010 hw->chip_rev == CHIP_REV_YU_FE2_A0)
1011 reg = 0x178;
1012 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), reg);
1013
1014 /* Configure Tx MAC FIFO */
1015 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
1016 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
1017
1018 /* On chips without ram buffer, pause is controlled by MAC level */
1019 if (!(hw->flags & SKY2_HW_RAM_BUFFER)) {
1020 /* Pause threshold is scaled by 8 in bytes */
1021 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
1022 hw->chip_rev == CHIP_REV_YU_FE2_A0)
1023 reg = 1568 / 8;
1024 else
1025 reg = 1024 / 8;
1026 sky2_write16(hw, SK_REG(port, RX_GMF_UP_THR), reg);
1027 sky2_write16(hw, SK_REG(port, RX_GMF_LP_THR), 768 / 8);
1028
1029 sky2_set_tx_stfwd(hw, port);
1030 }
1031
1032 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
1033 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
1034 /* disable dynamic watermark */
1035 reg = sky2_read16(hw, SK_REG(port, TX_GMF_EA));
1036 reg &= ~TX_DYN_WM_ENA;
1037 sky2_write16(hw, SK_REG(port, TX_GMF_EA), reg);
1038 }
1039 }
1040
1041 /* Assign Ram Buffer allocation to queue */
1042 static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
1043 {
1044 u32 end;
1045
1046 /* convert from K bytes to qwords used for hw register */
1047 start *= 1024/8;
1048 space *= 1024/8;
1049 end = start + space - 1;
1050
1051 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
1052 sky2_write32(hw, RB_ADDR(q, RB_START), start);
1053 sky2_write32(hw, RB_ADDR(q, RB_END), end);
1054 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
1055 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
1056
1057 if (q == Q_R1 || q == Q_R2) {
1058 u32 tp = space - space/4;
1059
1060 /* On receive queue's set the thresholds
1061 * give receiver priority when > 3/4 full
1062 * send pause when down to 2K
1063 */
1064 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
1065 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
1066
1067 tp = space - 2048/8;
1068 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
1069 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
1070 } else {
1071 /* Enable store & forward on Tx queue's because
1072 * Tx FIFO is only 1K on Yukon
1073 */
1074 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
1075 }
1076
1077 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
1078 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
1079 }
1080
1081 /* Setup Bus Memory Interface */
1082 static void sky2_qset(struct sky2_hw *hw, u16 q)
1083 {
1084 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
1085 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
1086 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
1087 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
1088 }
1089
1090 /* Setup prefetch unit registers. This is the interface between
1091 * hardware and driver list elements
1092 */
1093 static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
1094 dma_addr_t addr, u32 last)
1095 {
1096 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1097 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
1098 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), upper_32_bits(addr));
1099 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), lower_32_bits(addr));
1100 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
1101 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
1102
1103 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
1104 }
1105
1106 static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2, u16 *slot)
1107 {
1108 struct sky2_tx_le *le = sky2->tx_le + *slot;
1109
1110 *slot = RING_NEXT(*slot, sky2->tx_ring_size);
1111 le->ctrl = 0;
1112 return le;
1113 }
1114
1115 static void tx_init(struct sky2_port *sky2)
1116 {
1117 struct sky2_tx_le *le;
1118
1119 sky2->tx_prod = sky2->tx_cons = 0;
1120 sky2->tx_tcpsum = 0;
1121 sky2->tx_last_mss = 0;
1122
1123 le = get_tx_le(sky2, &sky2->tx_prod);
1124 le->addr = 0;
1125 le->opcode = OP_ADDR64 | HW_OWNER;
1126 sky2->tx_last_upper = 0;
1127 }
1128
1129 /* Update chip's next pointer */
1130 static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
1131 {
1132 /* Make sure write' to descriptors are complete before we tell hardware */
1133 wmb();
1134 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
1135
1136 /* Synchronize I/O on since next processor may write to tail */
1137 mmiowb();
1138 }
1139
1140
1141 static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
1142 {
1143 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
1144 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
1145 le->ctrl = 0;
1146 return le;
1147 }
1148
1149 static unsigned sky2_get_rx_threshold(struct sky2_port *sky2)
1150 {
1151 unsigned size;
1152
1153 /* Space needed for frame data + headers rounded up */
1154 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
1155
1156 /* Stopping point for hardware truncation */
1157 return (size - 8) / sizeof(u32);
1158 }
1159
1160 static unsigned sky2_get_rx_data_size(struct sky2_port *sky2)
1161 {
1162 struct rx_ring_info *re;
1163 unsigned size;
1164
1165 /* Space needed for frame data + headers rounded up */
1166 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
1167
1168 sky2->rx_nfrags = size >> PAGE_SHIFT;
1169 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1170
1171 /* Compute residue after pages */
1172 size -= sky2->rx_nfrags << PAGE_SHIFT;
1173
1174 /* Optimize to handle small packets and headers */
1175 if (size < copybreak)
1176 size = copybreak;
1177 if (size < ETH_HLEN)
1178 size = ETH_HLEN;
1179
1180 return size;
1181 }
1182
1183 /* Build description to hardware for one receive segment */
1184 static void sky2_rx_add(struct sky2_port *sky2, u8 op,
1185 dma_addr_t map, unsigned len)
1186 {
1187 struct sky2_rx_le *le;
1188
1189 if (sizeof(dma_addr_t) > sizeof(u32)) {
1190 le = sky2_next_rx(sky2);
1191 le->addr = cpu_to_le32(upper_32_bits(map));
1192 le->opcode = OP_ADDR64 | HW_OWNER;
1193 }
1194
1195 le = sky2_next_rx(sky2);
1196 le->addr = cpu_to_le32(lower_32_bits(map));
1197 le->length = cpu_to_le16(len);
1198 le->opcode = op | HW_OWNER;
1199 }
1200
1201 /* Build description to hardware for one possibly fragmented skb */
1202 static void sky2_rx_submit(struct sky2_port *sky2,
1203 const struct rx_ring_info *re)
1204 {
1205 int i;
1206
1207 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
1208
1209 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
1210 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
1211 }
1212
1213
1214 static int sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
1215 unsigned size)
1216 {
1217 struct sk_buff *skb = re->skb;
1218 int i;
1219
1220 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
1221 if (pci_dma_mapping_error(pdev, re->data_addr))
1222 goto mapping_error;
1223
1224 dma_unmap_len_set(re, data_size, size);
1225
1226 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1227 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1228
1229 re->frag_addr[i] = skb_frag_dma_map(&pdev->dev, frag, 0,
1230 frag->size,
1231 PCI_DMA_FROMDEVICE);
1232
1233 if (pci_dma_mapping_error(pdev, re->frag_addr[i]))
1234 goto map_page_error;
1235 }
1236 return 0;
1237
1238 map_page_error:
1239 while (--i >= 0) {
1240 pci_unmap_page(pdev, re->frag_addr[i],
1241 skb_shinfo(skb)->frags[i].size,
1242 PCI_DMA_FROMDEVICE);
1243 }
1244
1245 pci_unmap_single(pdev, re->data_addr, dma_unmap_len(re, data_size),
1246 PCI_DMA_FROMDEVICE);
1247
1248 mapping_error:
1249 if (net_ratelimit())
1250 dev_warn(&pdev->dev, "%s: rx mapping error\n",
1251 skb->dev->name);
1252 return -EIO;
1253 }
1254
1255 static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
1256 {
1257 struct sk_buff *skb = re->skb;
1258 int i;
1259
1260 pci_unmap_single(pdev, re->data_addr, dma_unmap_len(re, data_size),
1261 PCI_DMA_FROMDEVICE);
1262
1263 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1264 pci_unmap_page(pdev, re->frag_addr[i],
1265 skb_shinfo(skb)->frags[i].size,
1266 PCI_DMA_FROMDEVICE);
1267 }
1268
1269 /* Tell chip where to start receive checksum.
1270 * Actually has two checksums, but set both same to avoid possible byte
1271 * order problems.
1272 */
1273 static void rx_set_checksum(struct sky2_port *sky2)
1274 {
1275 struct sky2_rx_le *le = sky2_next_rx(sky2);
1276
1277 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
1278 le->ctrl = 0;
1279 le->opcode = OP_TCPSTART | HW_OWNER;
1280
1281 sky2_write32(sky2->hw,
1282 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1283 (sky2->netdev->features & NETIF_F_RXCSUM)
1284 ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
1285 }
1286
1287 /* Enable/disable receive hash calculation (RSS) */
1288 static void rx_set_rss(struct net_device *dev, u32 features)
1289 {
1290 struct sky2_port *sky2 = netdev_priv(dev);
1291 struct sky2_hw *hw = sky2->hw;
1292 int i, nkeys = 4;
1293
1294 /* Supports IPv6 and other modes */
1295 if (hw->flags & SKY2_HW_NEW_LE) {
1296 nkeys = 10;
1297 sky2_write32(hw, SK_REG(sky2->port, RSS_CFG), HASH_ALL);
1298 }
1299
1300 /* Program RSS initial values */
1301 if (features & NETIF_F_RXHASH) {
1302 u32 key[nkeys];
1303
1304 get_random_bytes(key, nkeys * sizeof(u32));
1305 for (i = 0; i < nkeys; i++)
1306 sky2_write32(hw, SK_REG(sky2->port, RSS_KEY + i * 4),
1307 key[i]);
1308
1309 /* Need to turn on (undocumented) flag to make hashing work */
1310 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T),
1311 RX_STFW_ENA);
1312
1313 sky2_write32(hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1314 BMU_ENA_RX_RSS_HASH);
1315 } else
1316 sky2_write32(hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1317 BMU_DIS_RX_RSS_HASH);
1318 }
1319
1320 /*
1321 * The RX Stop command will not work for Yukon-2 if the BMU does not
1322 * reach the end of packet and since we can't make sure that we have
1323 * incoming data, we must reset the BMU while it is not doing a DMA
1324 * transfer. Since it is possible that the RX path is still active,
1325 * the RX RAM buffer will be stopped first, so any possible incoming
1326 * data will not trigger a DMA. After the RAM buffer is stopped, the
1327 * BMU is polled until any DMA in progress is ended and only then it
1328 * will be reset.
1329 */
1330 static void sky2_rx_stop(struct sky2_port *sky2)
1331 {
1332 struct sky2_hw *hw = sky2->hw;
1333 unsigned rxq = rxqaddr[sky2->port];
1334 int i;
1335
1336 /* disable the RAM Buffer receive queue */
1337 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
1338
1339 for (i = 0; i < 0xffff; i++)
1340 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
1341 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
1342 goto stopped;
1343
1344 netdev_warn(sky2->netdev, "receiver stop failed\n");
1345 stopped:
1346 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
1347
1348 /* reset the Rx prefetch unit */
1349 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1350 mmiowb();
1351 }
1352
1353 /* Clean out receive buffer area, assumes receiver hardware stopped */
1354 static void sky2_rx_clean(struct sky2_port *sky2)
1355 {
1356 unsigned i;
1357
1358 memset(sky2->rx_le, 0, RX_LE_BYTES);
1359 for (i = 0; i < sky2->rx_pending; i++) {
1360 struct rx_ring_info *re = sky2->rx_ring + i;
1361
1362 if (re->skb) {
1363 sky2_rx_unmap_skb(sky2->hw->pdev, re);
1364 kfree_skb(re->skb);
1365 re->skb = NULL;
1366 }
1367 }
1368 }
1369
1370 /* Basic MII support */
1371 static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1372 {
1373 struct mii_ioctl_data *data = if_mii(ifr);
1374 struct sky2_port *sky2 = netdev_priv(dev);
1375 struct sky2_hw *hw = sky2->hw;
1376 int err = -EOPNOTSUPP;
1377
1378 if (!netif_running(dev))
1379 return -ENODEV; /* Phy still in reset */
1380
1381 switch (cmd) {
1382 case SIOCGMIIPHY:
1383 data->phy_id = PHY_ADDR_MARV;
1384
1385 /* fallthru */
1386 case SIOCGMIIREG: {
1387 u16 val = 0;
1388
1389 spin_lock_bh(&sky2->phy_lock);
1390 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
1391 spin_unlock_bh(&sky2->phy_lock);
1392
1393 data->val_out = val;
1394 break;
1395 }
1396
1397 case SIOCSMIIREG:
1398 spin_lock_bh(&sky2->phy_lock);
1399 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1400 data->val_in);
1401 spin_unlock_bh(&sky2->phy_lock);
1402 break;
1403 }
1404 return err;
1405 }
1406
1407 #define SKY2_VLAN_OFFLOADS (NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_TSO)
1408
1409 static void sky2_vlan_mode(struct net_device *dev, u32 features)
1410 {
1411 struct sky2_port *sky2 = netdev_priv(dev);
1412 struct sky2_hw *hw = sky2->hw;
1413 u16 port = sky2->port;
1414
1415 if (features & NETIF_F_HW_VLAN_RX)
1416 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1417 RX_VLAN_STRIP_ON);
1418 else
1419 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1420 RX_VLAN_STRIP_OFF);
1421
1422 if (features & NETIF_F_HW_VLAN_TX) {
1423 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1424 TX_VLAN_TAG_ON);
1425
1426 dev->vlan_features |= SKY2_VLAN_OFFLOADS;
1427 } else {
1428 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1429 TX_VLAN_TAG_OFF);
1430
1431 /* Can't do transmit offload of vlan without hw vlan */
1432 dev->vlan_features &= ~SKY2_VLAN_OFFLOADS;
1433 }
1434 }
1435
1436 /* Amount of required worst case padding in rx buffer */
1437 static inline unsigned sky2_rx_pad(const struct sky2_hw *hw)
1438 {
1439 return (hw->flags & SKY2_HW_RAM_BUFFER) ? 8 : 2;
1440 }
1441
1442 /*
1443 * Allocate an skb for receiving. If the MTU is large enough
1444 * make the skb non-linear with a fragment list of pages.
1445 */
1446 static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2, gfp_t gfp)
1447 {
1448 struct sk_buff *skb;
1449 int i;
1450
1451 skb = __netdev_alloc_skb(sky2->netdev,
1452 sky2->rx_data_size + sky2_rx_pad(sky2->hw),
1453 gfp);
1454 if (!skb)
1455 goto nomem;
1456
1457 if (sky2->hw->flags & SKY2_HW_RAM_BUFFER) {
1458 unsigned char *start;
1459 /*
1460 * Workaround for a bug in FIFO that cause hang
1461 * if the FIFO if the receive buffer is not 64 byte aligned.
1462 * The buffer returned from netdev_alloc_skb is
1463 * aligned except if slab debugging is enabled.
1464 */
1465 start = PTR_ALIGN(skb->data, 8);
1466 skb_reserve(skb, start - skb->data);
1467 } else
1468 skb_reserve(skb, NET_IP_ALIGN);
1469
1470 for (i = 0; i < sky2->rx_nfrags; i++) {
1471 struct page *page = alloc_page(gfp);
1472
1473 if (!page)
1474 goto free_partial;
1475 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
1476 }
1477
1478 return skb;
1479 free_partial:
1480 kfree_skb(skb);
1481 nomem:
1482 return NULL;
1483 }
1484
1485 static inline void sky2_rx_update(struct sky2_port *sky2, unsigned rxq)
1486 {
1487 sky2_put_idx(sky2->hw, rxq, sky2->rx_put);
1488 }
1489
1490 static int sky2_alloc_rx_skbs(struct sky2_port *sky2)
1491 {
1492 struct sky2_hw *hw = sky2->hw;
1493 unsigned i;
1494
1495 sky2->rx_data_size = sky2_get_rx_data_size(sky2);
1496
1497 /* Fill Rx ring */
1498 for (i = 0; i < sky2->rx_pending; i++) {
1499 struct rx_ring_info *re = sky2->rx_ring + i;
1500
1501 re->skb = sky2_rx_alloc(sky2, GFP_KERNEL);
1502 if (!re->skb)
1503 return -ENOMEM;
1504
1505 if (sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size)) {
1506 dev_kfree_skb(re->skb);
1507 re->skb = NULL;
1508 return -ENOMEM;
1509 }
1510 }
1511 return 0;
1512 }
1513
1514 /*
1515 * Setup receiver buffer pool.
1516 * Normal case this ends up creating one list element for skb
1517 * in the receive ring. Worst case if using large MTU and each
1518 * allocation falls on a different 64 bit region, that results
1519 * in 6 list elements per ring entry.
1520 * One element is used for checksum enable/disable, and one
1521 * extra to avoid wrap.
1522 */
1523 static void sky2_rx_start(struct sky2_port *sky2)
1524 {
1525 struct sky2_hw *hw = sky2->hw;
1526 struct rx_ring_info *re;
1527 unsigned rxq = rxqaddr[sky2->port];
1528 unsigned i, thresh;
1529
1530 sky2->rx_put = sky2->rx_next = 0;
1531 sky2_qset(hw, rxq);
1532
1533 /* On PCI express lowering the watermark gives better performance */
1534 if (pci_is_pcie(hw->pdev))
1535 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1536
1537 /* These chips have no ram buffer?
1538 * MAC Rx RAM Read is controlled by hardware */
1539 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
1540 hw->chip_rev > CHIP_REV_YU_EC_U_A0)
1541 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS);
1542
1543 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1544
1545 if (!(hw->flags & SKY2_HW_NEW_LE))
1546 rx_set_checksum(sky2);
1547
1548 if (!(hw->flags & SKY2_HW_RSS_BROKEN))
1549 rx_set_rss(sky2->netdev, sky2->netdev->features);
1550
1551 /* submit Rx ring */
1552 for (i = 0; i < sky2->rx_pending; i++) {
1553 re = sky2->rx_ring + i;
1554 sky2_rx_submit(sky2, re);
1555 }
1556
1557 /*
1558 * The receiver hangs if it receives frames larger than the
1559 * packet buffer. As a workaround, truncate oversize frames, but
1560 * the register is limited to 9 bits, so if you do frames > 2052
1561 * you better get the MTU right!
1562 */
1563 thresh = sky2_get_rx_threshold(sky2);
1564 if (thresh > 0x1ff)
1565 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1566 else {
1567 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1568 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1569 }
1570
1571 /* Tell chip about available buffers */
1572 sky2_rx_update(sky2, rxq);
1573
1574 if (hw->chip_id == CHIP_ID_YUKON_EX ||
1575 hw->chip_id == CHIP_ID_YUKON_SUPR) {
1576 /*
1577 * Disable flushing of non ASF packets;
1578 * must be done after initializing the BMUs;
1579 * drivers without ASF support should do this too, otherwise
1580 * it may happen that they cannot run on ASF devices;
1581 * remember that the MAC FIFO isn't reset during initialization.
1582 */
1583 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_MACSEC_FLUSH_OFF);
1584 }
1585
1586 if (hw->chip_id >= CHIP_ID_YUKON_SUPR) {
1587 /* Enable RX Home Address & Routing Header checksum fix */
1588 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_FL_CTRL),
1589 RX_IPV6_SA_MOB_ENA | RX_IPV6_DA_MOB_ENA);
1590
1591 /* Enable TX Home Address & Routing Header checksum fix */
1592 sky2_write32(hw, Q_ADDR(txqaddr[sky2->port], Q_TEST),
1593 TBMU_TEST_HOME_ADD_FIX_EN | TBMU_TEST_ROUTING_ADD_FIX_EN);
1594 }
1595 }
1596
1597 static int sky2_alloc_buffers(struct sky2_port *sky2)
1598 {
1599 struct sky2_hw *hw = sky2->hw;
1600
1601 /* must be power of 2 */
1602 sky2->tx_le = pci_alloc_consistent(hw->pdev,
1603 sky2->tx_ring_size *
1604 sizeof(struct sky2_tx_le),
1605 &sky2->tx_le_map);
1606 if (!sky2->tx_le)
1607 goto nomem;
1608
1609 sky2->tx_ring = kcalloc(sky2->tx_ring_size, sizeof(struct tx_ring_info),
1610 GFP_KERNEL);
1611 if (!sky2->tx_ring)
1612 goto nomem;
1613
1614 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1615 &sky2->rx_le_map);
1616 if (!sky2->rx_le)
1617 goto nomem;
1618 memset(sky2->rx_le, 0, RX_LE_BYTES);
1619
1620 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
1621 GFP_KERNEL);
1622 if (!sky2->rx_ring)
1623 goto nomem;
1624
1625 return sky2_alloc_rx_skbs(sky2);
1626 nomem:
1627 return -ENOMEM;
1628 }
1629
1630 static void sky2_free_buffers(struct sky2_port *sky2)
1631 {
1632 struct sky2_hw *hw = sky2->hw;
1633
1634 sky2_rx_clean(sky2);
1635
1636 if (sky2->rx_le) {
1637 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1638 sky2->rx_le, sky2->rx_le_map);
1639 sky2->rx_le = NULL;
1640 }
1641 if (sky2->tx_le) {
1642 pci_free_consistent(hw->pdev,
1643 sky2->tx_ring_size * sizeof(struct sky2_tx_le),
1644 sky2->tx_le, sky2->tx_le_map);
1645 sky2->tx_le = NULL;
1646 }
1647 kfree(sky2->tx_ring);
1648 kfree(sky2->rx_ring);
1649
1650 sky2->tx_ring = NULL;
1651 sky2->rx_ring = NULL;
1652 }
1653
1654 static void sky2_hw_up(struct sky2_port *sky2)
1655 {
1656 struct sky2_hw *hw = sky2->hw;
1657 unsigned port = sky2->port;
1658 u32 ramsize;
1659 int cap;
1660 struct net_device *otherdev = hw->dev[sky2->port^1];
1661
1662 tx_init(sky2);
1663
1664 /*
1665 * On dual port PCI-X card, there is an problem where status
1666 * can be received out of order due to split transactions
1667 */
1668 if (otherdev && netif_running(otherdev) &&
1669 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
1670 u16 cmd;
1671
1672 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
1673 cmd &= ~PCI_X_CMD_MAX_SPLIT;
1674 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1675 }
1676
1677 sky2_mac_init(hw, port);
1678
1679 /* Register is number of 4K blocks on internal RAM buffer. */
1680 ramsize = sky2_read8(hw, B2_E_0) * 4;
1681 if (ramsize > 0) {
1682 u32 rxspace;
1683
1684 netdev_dbg(sky2->netdev, "ram buffer %dK\n", ramsize);
1685 if (ramsize < 16)
1686 rxspace = ramsize / 2;
1687 else
1688 rxspace = 8 + (2*(ramsize - 16))/3;
1689
1690 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1691 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1692
1693 /* Make sure SyncQ is disabled */
1694 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1695 RB_RST_SET);
1696 }
1697
1698 sky2_qset(hw, txqaddr[port]);
1699
1700 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */
1701 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0)
1702 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF);
1703
1704 /* Set almost empty threshold */
1705 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
1706 hw->chip_rev == CHIP_REV_YU_EC_U_A0)
1707 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
1708
1709 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1710 sky2->tx_ring_size - 1);
1711
1712 sky2_vlan_mode(sky2->netdev, sky2->netdev->features);
1713 netdev_update_features(sky2->netdev);
1714
1715 sky2_rx_start(sky2);
1716 }
1717
1718 /* Bring up network interface. */
1719 static int sky2_up(struct net_device *dev)
1720 {
1721 struct sky2_port *sky2 = netdev_priv(dev);
1722 struct sky2_hw *hw = sky2->hw;
1723 unsigned port = sky2->port;
1724 u32 imask;
1725 int err;
1726
1727 netif_carrier_off(dev);
1728
1729 err = sky2_alloc_buffers(sky2);
1730 if (err)
1731 goto err_out;
1732
1733 sky2_hw_up(sky2);
1734
1735 /* Enable interrupts from phy/mac for port */
1736 imask = sky2_read32(hw, B0_IMSK);
1737 imask |= portirq_msk[port];
1738 sky2_write32(hw, B0_IMSK, imask);
1739 sky2_read32(hw, B0_IMSK);
1740
1741 netif_info(sky2, ifup, dev, "enabling interface\n");
1742
1743 return 0;
1744
1745 err_out:
1746 sky2_free_buffers(sky2);
1747 return err;
1748 }
1749
1750 /* Modular subtraction in ring */
1751 static inline int tx_inuse(const struct sky2_port *sky2)
1752 {
1753 return (sky2->tx_prod - sky2->tx_cons) & (sky2->tx_ring_size - 1);
1754 }
1755
1756 /* Number of list elements available for next tx */
1757 static inline int tx_avail(const struct sky2_port *sky2)
1758 {
1759 return sky2->tx_pending - tx_inuse(sky2);
1760 }
1761
1762 /* Estimate of number of transmit list elements required */
1763 static unsigned tx_le_req(const struct sk_buff *skb)
1764 {
1765 unsigned count;
1766
1767 count = (skb_shinfo(skb)->nr_frags + 1)
1768 * (sizeof(dma_addr_t) / sizeof(u32));
1769
1770 if (skb_is_gso(skb))
1771 ++count;
1772 else if (sizeof(dma_addr_t) == sizeof(u32))
1773 ++count; /* possible vlan */
1774
1775 if (skb->ip_summed == CHECKSUM_PARTIAL)
1776 ++count;
1777
1778 return count;
1779 }
1780
1781 static void sky2_tx_unmap(struct pci_dev *pdev, struct tx_ring_info *re)
1782 {
1783 if (re->flags & TX_MAP_SINGLE)
1784 pci_unmap_single(pdev, dma_unmap_addr(re, mapaddr),
1785 dma_unmap_len(re, maplen),
1786 PCI_DMA_TODEVICE);
1787 else if (re->flags & TX_MAP_PAGE)
1788 pci_unmap_page(pdev, dma_unmap_addr(re, mapaddr),
1789 dma_unmap_len(re, maplen),
1790 PCI_DMA_TODEVICE);
1791 re->flags = 0;
1792 }
1793
1794 /*
1795 * Put one packet in ring for transmit.
1796 * A single packet can generate multiple list elements, and
1797 * the number of ring elements will probably be less than the number
1798 * of list elements used.
1799 */
1800 static netdev_tx_t sky2_xmit_frame(struct sk_buff *skb,
1801 struct net_device *dev)
1802 {
1803 struct sky2_port *sky2 = netdev_priv(dev);
1804 struct sky2_hw *hw = sky2->hw;
1805 struct sky2_tx_le *le = NULL;
1806 struct tx_ring_info *re;
1807 unsigned i, len;
1808 dma_addr_t mapping;
1809 u32 upper;
1810 u16 slot;
1811 u16 mss;
1812 u8 ctrl;
1813
1814 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1815 return NETDEV_TX_BUSY;
1816
1817 len = skb_headlen(skb);
1818 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
1819
1820 if (pci_dma_mapping_error(hw->pdev, mapping))
1821 goto mapping_error;
1822
1823 slot = sky2->tx_prod;
1824 netif_printk(sky2, tx_queued, KERN_DEBUG, dev,
1825 "tx queued, slot %u, len %d\n", slot, skb->len);
1826
1827 /* Send high bits if needed */
1828 upper = upper_32_bits(mapping);
1829 if (upper != sky2->tx_last_upper) {
1830 le = get_tx_le(sky2, &slot);
1831 le->addr = cpu_to_le32(upper);
1832 sky2->tx_last_upper = upper;
1833 le->opcode = OP_ADDR64 | HW_OWNER;
1834 }
1835
1836 /* Check for TCP Segmentation Offload */
1837 mss = skb_shinfo(skb)->gso_size;
1838 if (mss != 0) {
1839
1840 if (!(hw->flags & SKY2_HW_NEW_LE))
1841 mss += ETH_HLEN + ip_hdrlen(skb) + tcp_hdrlen(skb);
1842
1843 if (mss != sky2->tx_last_mss) {
1844 le = get_tx_le(sky2, &slot);
1845 le->addr = cpu_to_le32(mss);
1846
1847 if (hw->flags & SKY2_HW_NEW_LE)
1848 le->opcode = OP_MSS | HW_OWNER;
1849 else
1850 le->opcode = OP_LRGLEN | HW_OWNER;
1851 sky2->tx_last_mss = mss;
1852 }
1853 }
1854
1855 ctrl = 0;
1856
1857 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1858 if (vlan_tx_tag_present(skb)) {
1859 if (!le) {
1860 le = get_tx_le(sky2, &slot);
1861 le->addr = 0;
1862 le->opcode = OP_VLAN|HW_OWNER;
1863 } else
1864 le->opcode |= OP_VLAN;
1865 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1866 ctrl |= INS_VLAN;
1867 }
1868
1869 /* Handle TCP checksum offload */
1870 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1871 /* On Yukon EX (some versions) encoding change. */
1872 if (hw->flags & SKY2_HW_AUTO_TX_SUM)
1873 ctrl |= CALSUM; /* auto checksum */
1874 else {
1875 const unsigned offset = skb_transport_offset(skb);
1876 u32 tcpsum;
1877
1878 tcpsum = offset << 16; /* sum start */
1879 tcpsum |= offset + skb->csum_offset; /* sum write */
1880
1881 ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1882 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1883 ctrl |= UDPTCP;
1884
1885 if (tcpsum != sky2->tx_tcpsum) {
1886 sky2->tx_tcpsum = tcpsum;
1887
1888 le = get_tx_le(sky2, &slot);
1889 le->addr = cpu_to_le32(tcpsum);
1890 le->length = 0; /* initial checksum value */
1891 le->ctrl = 1; /* one packet */
1892 le->opcode = OP_TCPLISW | HW_OWNER;
1893 }
1894 }
1895 }
1896
1897 re = sky2->tx_ring + slot;
1898 re->flags = TX_MAP_SINGLE;
1899 dma_unmap_addr_set(re, mapaddr, mapping);
1900 dma_unmap_len_set(re, maplen, len);
1901
1902 le = get_tx_le(sky2, &slot);
1903 le->addr = cpu_to_le32(lower_32_bits(mapping));
1904 le->length = cpu_to_le16(len);
1905 le->ctrl = ctrl;
1906 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
1907
1908
1909 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1910 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1911
1912 mapping = skb_frag_dma_map(&hw->pdev->dev, frag, 0,
1913 frag->size, PCI_DMA_TODEVICE);
1914
1915 if (pci_dma_mapping_error(hw->pdev, mapping))
1916 goto mapping_unwind;
1917
1918 upper = upper_32_bits(mapping);
1919 if (upper != sky2->tx_last_upper) {
1920 le = get_tx_le(sky2, &slot);
1921 le->addr = cpu_to_le32(upper);
1922 sky2->tx_last_upper = upper;
1923 le->opcode = OP_ADDR64 | HW_OWNER;
1924 }
1925
1926 re = sky2->tx_ring + slot;
1927 re->flags = TX_MAP_PAGE;
1928 dma_unmap_addr_set(re, mapaddr, mapping);
1929 dma_unmap_len_set(re, maplen, frag->size);
1930
1931 le = get_tx_le(sky2, &slot);
1932 le->addr = cpu_to_le32(lower_32_bits(mapping));
1933 le->length = cpu_to_le16(frag->size);
1934 le->ctrl = ctrl;
1935 le->opcode = OP_BUFFER | HW_OWNER;
1936 }
1937
1938 re->skb = skb;
1939 le->ctrl |= EOP;
1940
1941 sky2->tx_prod = slot;
1942
1943 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1944 netif_stop_queue(dev);
1945
1946 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
1947
1948 return NETDEV_TX_OK;
1949
1950 mapping_unwind:
1951 for (i = sky2->tx_prod; i != slot; i = RING_NEXT(i, sky2->tx_ring_size)) {
1952 re = sky2->tx_ring + i;
1953
1954 sky2_tx_unmap(hw->pdev, re);
1955 }
1956
1957 mapping_error:
1958 if (net_ratelimit())
1959 dev_warn(&hw->pdev->dev, "%s: tx mapping error\n", dev->name);
1960 dev_kfree_skb(skb);
1961 return NETDEV_TX_OK;
1962 }
1963
1964 /*
1965 * Free ring elements from starting at tx_cons until "done"
1966 *
1967 * NB:
1968 * 1. The hardware will tell us about partial completion of multi-part
1969 * buffers so make sure not to free skb to early.
1970 * 2. This may run in parallel start_xmit because the it only
1971 * looks at the tail of the queue of FIFO (tx_cons), not
1972 * the head (tx_prod)
1973 */
1974 static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
1975 {
1976 struct net_device *dev = sky2->netdev;
1977 unsigned idx;
1978
1979 BUG_ON(done >= sky2->tx_ring_size);
1980
1981 for (idx = sky2->tx_cons; idx != done;
1982 idx = RING_NEXT(idx, sky2->tx_ring_size)) {
1983 struct tx_ring_info *re = sky2->tx_ring + idx;
1984 struct sk_buff *skb = re->skb;
1985
1986 sky2_tx_unmap(sky2->hw->pdev, re);
1987
1988 if (skb) {
1989 netif_printk(sky2, tx_done, KERN_DEBUG, dev,
1990 "tx done %u\n", idx);
1991
1992 u64_stats_update_begin(&sky2->tx_stats.syncp);
1993 ++sky2->tx_stats.packets;
1994 sky2->tx_stats.bytes += skb->len;
1995 u64_stats_update_end(&sky2->tx_stats.syncp);
1996
1997 re->skb = NULL;
1998 dev_kfree_skb_any(skb);
1999
2000 sky2->tx_next = RING_NEXT(idx, sky2->tx_ring_size);
2001 }
2002 }
2003
2004 sky2->tx_cons = idx;
2005 smp_mb();
2006 }
2007
2008 static void sky2_tx_reset(struct sky2_hw *hw, unsigned port)
2009 {
2010 /* Disable Force Sync bit and Enable Alloc bit */
2011 sky2_write8(hw, SK_REG(port, TXA_CTRL),
2012 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
2013
2014 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
2015 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
2016 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
2017
2018 /* Reset the PCI FIFO of the async Tx queue */
2019 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
2020 BMU_RST_SET | BMU_FIFO_RST);
2021
2022 /* Reset the Tx prefetch units */
2023 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
2024 PREF_UNIT_RST_SET);
2025
2026 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
2027 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
2028 }
2029
2030 static void sky2_hw_down(struct sky2_port *sky2)
2031 {
2032 struct sky2_hw *hw = sky2->hw;
2033 unsigned port = sky2->port;
2034 u16 ctrl;
2035
2036 /* Force flow control off */
2037 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2038
2039 /* Stop transmitter */
2040 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
2041 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
2042
2043 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
2044 RB_RST_SET | RB_DIS_OP_MD);
2045
2046 ctrl = gma_read16(hw, port, GM_GP_CTRL);
2047 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
2048 gma_write16(hw, port, GM_GP_CTRL, ctrl);
2049
2050 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
2051
2052 /* Workaround shared GMAC reset */
2053 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 &&
2054 port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
2055 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
2056
2057 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
2058
2059 /* Force any delayed status interrrupt and NAPI */
2060 sky2_write32(hw, STAT_LEV_TIMER_CNT, 0);
2061 sky2_write32(hw, STAT_TX_TIMER_CNT, 0);
2062 sky2_write32(hw, STAT_ISR_TIMER_CNT, 0);
2063 sky2_read8(hw, STAT_ISR_TIMER_CTRL);
2064
2065 sky2_rx_stop(sky2);
2066
2067 spin_lock_bh(&sky2->phy_lock);
2068 sky2_phy_power_down(hw, port);
2069 spin_unlock_bh(&sky2->phy_lock);
2070
2071 sky2_tx_reset(hw, port);
2072
2073 /* Free any pending frames stuck in HW queue */
2074 sky2_tx_complete(sky2, sky2->tx_prod);
2075 }
2076
2077 /* Network shutdown */
2078 static int sky2_down(struct net_device *dev)
2079 {
2080 struct sky2_port *sky2 = netdev_priv(dev);
2081 struct sky2_hw *hw = sky2->hw;
2082
2083 /* Never really got started! */
2084 if (!sky2->tx_le)
2085 return 0;
2086
2087 netif_info(sky2, ifdown, dev, "disabling interface\n");
2088
2089 /* Disable port IRQ */
2090 sky2_write32(hw, B0_IMSK,
2091 sky2_read32(hw, B0_IMSK) & ~portirq_msk[sky2->port]);
2092 sky2_read32(hw, B0_IMSK);
2093
2094 synchronize_irq(hw->pdev->irq);
2095 napi_synchronize(&hw->napi);
2096
2097 sky2_hw_down(sky2);
2098
2099 sky2_free_buffers(sky2);
2100
2101 return 0;
2102 }
2103
2104 static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
2105 {
2106 if (hw->flags & SKY2_HW_FIBRE_PHY)
2107 return SPEED_1000;
2108
2109 if (!(hw->flags & SKY2_HW_GIGABIT)) {
2110 if (aux & PHY_M_PS_SPEED_100)
2111 return SPEED_100;
2112 else
2113 return SPEED_10;
2114 }
2115
2116 switch (aux & PHY_M_PS_SPEED_MSK) {
2117 case PHY_M_PS_SPEED_1000:
2118 return SPEED_1000;
2119 case PHY_M_PS_SPEED_100:
2120 return SPEED_100;
2121 default:
2122 return SPEED_10;
2123 }
2124 }
2125
2126 static void sky2_link_up(struct sky2_port *sky2)
2127 {
2128 struct sky2_hw *hw = sky2->hw;
2129 unsigned port = sky2->port;
2130 static const char *fc_name[] = {
2131 [FC_NONE] = "none",
2132 [FC_TX] = "tx",
2133 [FC_RX] = "rx",
2134 [FC_BOTH] = "both",
2135 };
2136
2137 sky2_set_ipg(sky2);
2138
2139 sky2_enable_rx_tx(sky2);
2140
2141 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
2142
2143 netif_carrier_on(sky2->netdev);
2144
2145 mod_timer(&hw->watchdog_timer, jiffies + 1);
2146
2147 /* Turn on link LED */
2148 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
2149 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
2150
2151 netif_info(sky2, link, sky2->netdev,
2152 "Link is up at %d Mbps, %s duplex, flow control %s\n",
2153 sky2->speed,
2154 sky2->duplex == DUPLEX_FULL ? "full" : "half",
2155 fc_name[sky2->flow_status]);
2156 }
2157
2158 static void sky2_link_down(struct sky2_port *sky2)
2159 {
2160 struct sky2_hw *hw = sky2->hw;
2161 unsigned port = sky2->port;
2162 u16 reg;
2163
2164 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
2165
2166 reg = gma_read16(hw, port, GM_GP_CTRL);
2167 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
2168 gma_write16(hw, port, GM_GP_CTRL, reg);
2169
2170 netif_carrier_off(sky2->netdev);
2171
2172 /* Turn off link LED */
2173 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
2174
2175 netif_info(sky2, link, sky2->netdev, "Link is down\n");
2176
2177 sky2_phy_init(hw, port);
2178 }
2179
2180 static enum flow_control sky2_flow(int rx, int tx)
2181 {
2182 if (rx)
2183 return tx ? FC_BOTH : FC_RX;
2184 else
2185 return tx ? FC_TX : FC_NONE;
2186 }
2187
2188 static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
2189 {
2190 struct sky2_hw *hw = sky2->hw;
2191 unsigned port = sky2->port;
2192 u16 advert, lpa;
2193
2194 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
2195 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
2196 if (lpa & PHY_M_AN_RF) {
2197 netdev_err(sky2->netdev, "remote fault\n");
2198 return -1;
2199 }
2200
2201 if (!(aux & PHY_M_PS_SPDUP_RES)) {
2202 netdev_err(sky2->netdev, "speed/duplex mismatch\n");
2203 return -1;
2204 }
2205
2206 sky2->speed = sky2_phy_speed(hw, aux);
2207 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2208
2209 /* Since the pause result bits seem to in different positions on
2210 * different chips. look at registers.
2211 */
2212 if (hw->flags & SKY2_HW_FIBRE_PHY) {
2213 /* Shift for bits in fiber PHY */
2214 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
2215 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
2216
2217 if (advert & ADVERTISE_1000XPAUSE)
2218 advert |= ADVERTISE_PAUSE_CAP;
2219 if (advert & ADVERTISE_1000XPSE_ASYM)
2220 advert |= ADVERTISE_PAUSE_ASYM;
2221 if (lpa & LPA_1000XPAUSE)
2222 lpa |= LPA_PAUSE_CAP;
2223 if (lpa & LPA_1000XPAUSE_ASYM)
2224 lpa |= LPA_PAUSE_ASYM;
2225 }
2226
2227 sky2->flow_status = FC_NONE;
2228 if (advert & ADVERTISE_PAUSE_CAP) {
2229 if (lpa & LPA_PAUSE_CAP)
2230 sky2->flow_status = FC_BOTH;
2231 else if (advert & ADVERTISE_PAUSE_ASYM)
2232 sky2->flow_status = FC_RX;
2233 } else if (advert & ADVERTISE_PAUSE_ASYM) {
2234 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
2235 sky2->flow_status = FC_TX;
2236 }
2237
2238 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000 &&
2239 !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
2240 sky2->flow_status = FC_NONE;
2241
2242 if (sky2->flow_status & FC_TX)
2243 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
2244 else
2245 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2246
2247 return 0;
2248 }
2249
2250 /* Interrupt from PHY */
2251 static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
2252 {
2253 struct net_device *dev = hw->dev[port];
2254 struct sky2_port *sky2 = netdev_priv(dev);
2255 u16 istatus, phystat;
2256
2257 if (!netif_running(dev))
2258 return;
2259
2260 spin_lock(&sky2->phy_lock);
2261 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
2262 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
2263
2264 netif_info(sky2, intr, sky2->netdev, "phy interrupt status 0x%x 0x%x\n",
2265 istatus, phystat);
2266
2267 if (istatus & PHY_M_IS_AN_COMPL) {
2268 if (sky2_autoneg_done(sky2, phystat) == 0 &&
2269 !netif_carrier_ok(dev))
2270 sky2_link_up(sky2);
2271 goto out;
2272 }
2273
2274 if (istatus & PHY_M_IS_LSP_CHANGE)
2275 sky2->speed = sky2_phy_speed(hw, phystat);
2276
2277 if (istatus & PHY_M_IS_DUP_CHANGE)
2278 sky2->duplex =
2279 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2280
2281 if (istatus & PHY_M_IS_LST_CHANGE) {
2282 if (phystat & PHY_M_PS_LINK_UP)
2283 sky2_link_up(sky2);
2284 else
2285 sky2_link_down(sky2);
2286 }
2287 out:
2288 spin_unlock(&sky2->phy_lock);
2289 }
2290
2291 /* Special quick link interrupt (Yukon-2 Optima only) */
2292 static void sky2_qlink_intr(struct sky2_hw *hw)
2293 {
2294 struct sky2_port *sky2 = netdev_priv(hw->dev[0]);
2295 u32 imask;
2296 u16 phy;
2297
2298 /* disable irq */
2299 imask = sky2_read32(hw, B0_IMSK);
2300 imask &= ~Y2_IS_PHY_QLNK;
2301 sky2_write32(hw, B0_IMSK, imask);
2302
2303 /* reset PHY Link Detect */
2304 phy = sky2_pci_read16(hw, PSM_CONFIG_REG4);
2305 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2306 sky2_pci_write16(hw, PSM_CONFIG_REG4, phy | 1);
2307 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2308
2309 sky2_link_up(sky2);
2310 }
2311
2312 /* Transmit timeout is only called if we are running, carrier is up
2313 * and tx queue is full (stopped).
2314 */
2315 static void sky2_tx_timeout(struct net_device *dev)
2316 {
2317 struct sky2_port *sky2 = netdev_priv(dev);
2318 struct sky2_hw *hw = sky2->hw;
2319
2320 netif_err(sky2, timer, dev, "tx timeout\n");
2321
2322 netdev_printk(KERN_DEBUG, dev, "transmit ring %u .. %u report=%u done=%u\n",
2323 sky2->tx_cons, sky2->tx_prod,
2324 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
2325 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
2326
2327 /* can't restart safely under softirq */
2328 schedule_work(&hw->restart_work);
2329 }
2330
2331 static int sky2_change_mtu(struct net_device *dev, int new_mtu)
2332 {
2333 struct sky2_port *sky2 = netdev_priv(dev);
2334 struct sky2_hw *hw = sky2->hw;
2335 unsigned port = sky2->port;
2336 int err;
2337 u16 ctl, mode;
2338 u32 imask;
2339
2340 /* MTU size outside the spec */
2341 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
2342 return -EINVAL;
2343
2344 /* MTU > 1500 on yukon FE and FE+ not allowed */
2345 if (new_mtu > ETH_DATA_LEN &&
2346 (hw->chip_id == CHIP_ID_YUKON_FE ||
2347 hw->chip_id == CHIP_ID_YUKON_FE_P))
2348 return -EINVAL;
2349
2350 if (!netif_running(dev)) {
2351 dev->mtu = new_mtu;
2352 netdev_update_features(dev);
2353 return 0;
2354 }
2355
2356 imask = sky2_read32(hw, B0_IMSK);
2357 sky2_write32(hw, B0_IMSK, 0);
2358
2359 dev->trans_start = jiffies; /* prevent tx timeout */
2360 napi_disable(&hw->napi);
2361 netif_tx_disable(dev);
2362
2363 synchronize_irq(hw->pdev->irq);
2364
2365 if (!(hw->flags & SKY2_HW_RAM_BUFFER))
2366 sky2_set_tx_stfwd(hw, port);
2367
2368 ctl = gma_read16(hw, port, GM_GP_CTRL);
2369 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
2370 sky2_rx_stop(sky2);
2371 sky2_rx_clean(sky2);
2372
2373 dev->mtu = new_mtu;
2374 netdev_update_features(dev);
2375
2376 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) | GM_SMOD_VLAN_ENA;
2377 if (sky2->speed > SPEED_100)
2378 mode |= IPG_DATA_VAL(IPG_DATA_DEF_1000);
2379 else
2380 mode |= IPG_DATA_VAL(IPG_DATA_DEF_10_100);
2381
2382 if (dev->mtu > ETH_DATA_LEN)
2383 mode |= GM_SMOD_JUMBO_ENA;
2384
2385 gma_write16(hw, port, GM_SERIAL_MODE, mode);
2386
2387 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
2388
2389 err = sky2_alloc_rx_skbs(sky2);
2390 if (!err)
2391 sky2_rx_start(sky2);
2392 else
2393 sky2_rx_clean(sky2);
2394 sky2_write32(hw, B0_IMSK, imask);
2395
2396 sky2_read32(hw, B0_Y2_SP_LISR);
2397 napi_enable(&hw->napi);
2398
2399 if (err)
2400 dev_close(dev);
2401 else {
2402 gma_write16(hw, port, GM_GP_CTRL, ctl);
2403
2404 netif_wake_queue(dev);
2405 }
2406
2407 return err;
2408 }
2409
2410 /* For small just reuse existing skb for next receive */
2411 static struct sk_buff *receive_copy(struct sky2_port *sky2,
2412 const struct rx_ring_info *re,
2413 unsigned length)
2414 {
2415 struct sk_buff *skb;
2416
2417 skb = netdev_alloc_skb_ip_align(sky2->netdev, length);
2418 if (likely(skb)) {
2419 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
2420 length, PCI_DMA_FROMDEVICE);
2421 skb_copy_from_linear_data(re->skb, skb->data, length);
2422 skb->ip_summed = re->skb->ip_summed;
2423 skb->csum = re->skb->csum;
2424 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
2425 length, PCI_DMA_FROMDEVICE);
2426 re->skb->ip_summed = CHECKSUM_NONE;
2427 skb_put(skb, length);
2428 }
2429 return skb;
2430 }
2431
2432 /* Adjust length of skb with fragments to match received data */
2433 static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
2434 unsigned int length)
2435 {
2436 int i, num_frags;
2437 unsigned int size;
2438
2439 /* put header into skb */
2440 size = min(length, hdr_space);
2441 skb->tail += size;
2442 skb->len += size;
2443 length -= size;
2444
2445 num_frags = skb_shinfo(skb)->nr_frags;
2446 for (i = 0; i < num_frags; i++) {
2447 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2448
2449 if (length == 0) {
2450 /* don't need this page */
2451 __skb_frag_unref(frag);
2452 --skb_shinfo(skb)->nr_frags;
2453 } else {
2454 size = min(length, (unsigned) PAGE_SIZE);
2455
2456 frag->size = size;
2457 skb->data_len += size;
2458 skb->truesize += size;
2459 skb->len += size;
2460 length -= size;
2461 }
2462 }
2463 }
2464
2465 /* Normal packet - take skb from ring element and put in a new one */
2466 static struct sk_buff *receive_new(struct sky2_port *sky2,
2467 struct rx_ring_info *re,
2468 unsigned int length)
2469 {
2470 struct sk_buff *skb;
2471 struct rx_ring_info nre;
2472 unsigned hdr_space = sky2->rx_data_size;
2473
2474 nre.skb = sky2_rx_alloc(sky2, GFP_ATOMIC);
2475 if (unlikely(!nre.skb))
2476 goto nobuf;
2477
2478 if (sky2_rx_map_skb(sky2->hw->pdev, &nre, hdr_space))
2479 goto nomap;
2480
2481 skb = re->skb;
2482 sky2_rx_unmap_skb(sky2->hw->pdev, re);
2483 prefetch(skb->data);
2484 *re = nre;
2485
2486 if (skb_shinfo(skb)->nr_frags)
2487 skb_put_frags(skb, hdr_space, length);
2488 else
2489 skb_put(skb, length);
2490 return skb;
2491
2492 nomap:
2493 dev_kfree_skb(nre.skb);
2494 nobuf:
2495 return NULL;
2496 }
2497
2498 /*
2499 * Receive one packet.
2500 * For larger packets, get new buffer.
2501 */
2502 static struct sk_buff *sky2_receive(struct net_device *dev,
2503 u16 length, u32 status)
2504 {
2505 struct sky2_port *sky2 = netdev_priv(dev);
2506 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
2507 struct sk_buff *skb = NULL;
2508 u16 count = (status & GMR_FS_LEN) >> 16;
2509
2510 if (status & GMR_FS_VLAN)
2511 count -= VLAN_HLEN; /* Account for vlan tag */
2512
2513 netif_printk(sky2, rx_status, KERN_DEBUG, dev,
2514 "rx slot %u status 0x%x len %d\n",
2515 sky2->rx_next, status, length);
2516
2517 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
2518 prefetch(sky2->rx_ring + sky2->rx_next);
2519
2520 /* This chip has hardware problems that generates bogus status.
2521 * So do only marginal checking and expect higher level protocols
2522 * to handle crap frames.
2523 */
2524 if (sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
2525 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0 &&
2526 length != count)
2527 goto okay;
2528
2529 if (status & GMR_FS_ANY_ERR)
2530 goto error;
2531
2532 if (!(status & GMR_FS_RX_OK))
2533 goto resubmit;
2534
2535 /* if length reported by DMA does not match PHY, packet was truncated */
2536 if (length != count)
2537 goto error;
2538
2539 okay:
2540 if (length < copybreak)
2541 skb = receive_copy(sky2, re, length);
2542 else
2543 skb = receive_new(sky2, re, length);
2544
2545 dev->stats.rx_dropped += (skb == NULL);
2546
2547 resubmit:
2548 sky2_rx_submit(sky2, re);
2549
2550 return skb;
2551
2552 error:
2553 ++dev->stats.rx_errors;
2554
2555 if (net_ratelimit())
2556 netif_info(sky2, rx_err, dev,
2557 "rx error, status 0x%x length %d\n", status, length);
2558
2559 goto resubmit;
2560 }
2561
2562 /* Transmit complete */
2563 static inline void sky2_tx_done(struct net_device *dev, u16 last)
2564 {
2565 struct sky2_port *sky2 = netdev_priv(dev);
2566
2567 if (netif_running(dev)) {
2568 sky2_tx_complete(sky2, last);
2569
2570 /* Wake unless it's detached, and called e.g. from sky2_down() */
2571 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
2572 netif_wake_queue(dev);
2573 }
2574 }
2575
2576 static inline void sky2_skb_rx(const struct sky2_port *sky2,
2577 u32 status, struct sk_buff *skb)
2578 {
2579 if (status & GMR_FS_VLAN)
2580 __vlan_hwaccel_put_tag(skb, be16_to_cpu(sky2->rx_tag));
2581
2582 if (skb->ip_summed == CHECKSUM_NONE)
2583 netif_receive_skb(skb);
2584 else
2585 napi_gro_receive(&sky2->hw->napi, skb);
2586 }
2587
2588 static inline void sky2_rx_done(struct sky2_hw *hw, unsigned port,
2589 unsigned packets, unsigned bytes)
2590 {
2591 struct net_device *dev = hw->dev[port];
2592 struct sky2_port *sky2 = netdev_priv(dev);
2593
2594 if (packets == 0)
2595 return;
2596
2597 u64_stats_update_begin(&sky2->rx_stats.syncp);
2598 sky2->rx_stats.packets += packets;
2599 sky2->rx_stats.bytes += bytes;
2600 u64_stats_update_end(&sky2->rx_stats.syncp);
2601
2602 dev->last_rx = jiffies;
2603 sky2_rx_update(netdev_priv(dev), rxqaddr[port]);
2604 }
2605
2606 static void sky2_rx_checksum(struct sky2_port *sky2, u32 status)
2607 {
2608 /* If this happens then driver assuming wrong format for chip type */
2609 BUG_ON(sky2->hw->flags & SKY2_HW_NEW_LE);
2610
2611 /* Both checksum counters are programmed to start at
2612 * the same offset, so unless there is a problem they
2613 * should match. This failure is an early indication that
2614 * hardware receive checksumming won't work.
2615 */
2616 if (likely((u16)(status >> 16) == (u16)status)) {
2617 struct sk_buff *skb = sky2->rx_ring[sky2->rx_next].skb;
2618 skb->ip_summed = CHECKSUM_COMPLETE;
2619 skb->csum = le16_to_cpu(status);
2620 } else {
2621 dev_notice(&sky2->hw->pdev->dev,
2622 "%s: receive checksum problem (status = %#x)\n",
2623 sky2->netdev->name, status);
2624
2625 /* Disable checksum offload
2626 * It will be reenabled on next ndo_set_features, but if it's
2627 * really broken, will get disabled again
2628 */
2629 sky2->netdev->features &= ~NETIF_F_RXCSUM;
2630 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2631 BMU_DIS_RX_CHKSUM);
2632 }
2633 }
2634
2635 static void sky2_rx_hash(struct sky2_port *sky2, u32 status)
2636 {
2637 struct sk_buff *skb;
2638
2639 skb = sky2->rx_ring[sky2->rx_next].skb;
2640 skb->rxhash = le32_to_cpu(status);
2641 }
2642
2643 /* Process status response ring */
2644 static int sky2_status_intr(struct sky2_hw *hw, int to_do, u16 idx)
2645 {
2646 int work_done = 0;
2647 unsigned int total_bytes[2] = { 0 };
2648 unsigned int total_packets[2] = { 0 };
2649
2650 rmb();
2651 do {
2652 struct sky2_port *sky2;
2653 struct sky2_status_le *le = hw->st_le + hw->st_idx;
2654 unsigned port;
2655 struct net_device *dev;
2656 struct sk_buff *skb;
2657 u32 status;
2658 u16 length;
2659 u8 opcode = le->opcode;
2660
2661 if (!(opcode & HW_OWNER))
2662 break;
2663
2664 hw->st_idx = RING_NEXT(hw->st_idx, hw->st_size);
2665
2666 port = le->css & CSS_LINK_BIT;
2667 dev = hw->dev[port];
2668 sky2 = netdev_priv(dev);
2669 length = le16_to_cpu(le->length);
2670 status = le32_to_cpu(le->status);
2671
2672 le->opcode = 0;
2673 switch (opcode & ~HW_OWNER) {
2674 case OP_RXSTAT:
2675 total_packets[port]++;
2676 total_bytes[port] += length;
2677
2678 skb = sky2_receive(dev, length, status);
2679 if (!skb)
2680 break;
2681
2682 /* This chip reports checksum status differently */
2683 if (hw->flags & SKY2_HW_NEW_LE) {
2684 if ((dev->features & NETIF_F_RXCSUM) &&
2685 (le->css & (CSS_ISIPV4 | CSS_ISIPV6)) &&
2686 (le->css & CSS_TCPUDPCSOK))
2687 skb->ip_summed = CHECKSUM_UNNECESSARY;
2688 else
2689 skb->ip_summed = CHECKSUM_NONE;
2690 }
2691
2692 skb->protocol = eth_type_trans(skb, dev);
2693
2694 sky2_skb_rx(sky2, status, skb);
2695
2696 /* Stop after net poll weight */
2697 if (++work_done >= to_do)
2698 goto exit_loop;
2699 break;
2700
2701 case OP_RXVLAN:
2702 sky2->rx_tag = length;
2703 break;
2704
2705 case OP_RXCHKSVLAN:
2706 sky2->rx_tag = length;
2707 /* fall through */
2708 case OP_RXCHKS:
2709 if (likely(dev->features & NETIF_F_RXCSUM))
2710 sky2_rx_checksum(sky2, status);
2711 break;
2712
2713 case OP_RSS_HASH:
2714 sky2_rx_hash(sky2, status);
2715 break;
2716
2717 case OP_TXINDEXLE:
2718 /* TX index reports status for both ports */
2719 sky2_tx_done(hw->dev[0], status & 0xfff);
2720 if (hw->dev[1])
2721 sky2_tx_done(hw->dev[1],
2722 ((status >> 24) & 0xff)
2723 | (u16)(length & 0xf) << 8);
2724 break;
2725
2726 default:
2727 if (net_ratelimit())
2728 pr_warning("unknown status opcode 0x%x\n", opcode);
2729 }
2730 } while (hw->st_idx != idx);
2731
2732 /* Fully processed status ring so clear irq */
2733 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2734
2735 exit_loop:
2736 sky2_rx_done(hw, 0, total_packets[0], total_bytes[0]);
2737 sky2_rx_done(hw, 1, total_packets[1], total_bytes[1]);
2738
2739 return work_done;
2740 }
2741
2742 static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2743 {
2744 struct net_device *dev = hw->dev[port];
2745
2746 if (net_ratelimit())
2747 netdev_info(dev, "hw error interrupt status 0x%x\n", status);
2748
2749 if (status & Y2_IS_PAR_RD1) {
2750 if (net_ratelimit())
2751 netdev_err(dev, "ram data read parity error\n");
2752 /* Clear IRQ */
2753 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2754 }
2755
2756 if (status & Y2_IS_PAR_WR1) {
2757 if (net_ratelimit())
2758 netdev_err(dev, "ram data write parity error\n");
2759
2760 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2761 }
2762
2763 if (status & Y2_IS_PAR_MAC1) {
2764 if (net_ratelimit())
2765 netdev_err(dev, "MAC parity error\n");
2766 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2767 }
2768
2769 if (status & Y2_IS_PAR_RX1) {
2770 if (net_ratelimit())
2771 netdev_err(dev, "RX parity error\n");
2772 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2773 }
2774
2775 if (status & Y2_IS_TCP_TXA1) {
2776 if (net_ratelimit())
2777 netdev_err(dev, "TCP segmentation error\n");
2778 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2779 }
2780 }
2781
2782 static void sky2_hw_intr(struct sky2_hw *hw)
2783 {
2784 struct pci_dev *pdev = hw->pdev;
2785 u32 status = sky2_read32(hw, B0_HWE_ISRC);
2786 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2787
2788 status &= hwmsk;
2789
2790 if (status & Y2_IS_TIST_OV)
2791 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2792
2793 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
2794 u16 pci_err;
2795
2796 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2797 pci_err = sky2_pci_read16(hw, PCI_STATUS);
2798 if (net_ratelimit())
2799 dev_err(&pdev->dev, "PCI hardware error (0x%x)\n",
2800 pci_err);
2801
2802 sky2_pci_write16(hw, PCI_STATUS,
2803 pci_err | PCI_STATUS_ERROR_BITS);
2804 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2805 }
2806
2807 if (status & Y2_IS_PCI_EXP) {
2808 /* PCI-Express uncorrectable Error occurred */
2809 u32 err;
2810
2811 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2812 err = sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2813 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2814 0xfffffffful);
2815 if (net_ratelimit())
2816 dev_err(&pdev->dev, "PCI Express error (0x%x)\n", err);
2817
2818 sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2819 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2820 }
2821
2822 if (status & Y2_HWE_L1_MASK)
2823 sky2_hw_error(hw, 0, status);
2824 status >>= 8;
2825 if (status & Y2_HWE_L1_MASK)
2826 sky2_hw_error(hw, 1, status);
2827 }
2828
2829 static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2830 {
2831 struct net_device *dev = hw->dev[port];
2832 struct sky2_port *sky2 = netdev_priv(dev);
2833 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2834
2835 netif_info(sky2, intr, dev, "mac interrupt status 0x%x\n", status);
2836
2837 if (status & GM_IS_RX_CO_OV)
2838 gma_read16(hw, port, GM_RX_IRQ_SRC);
2839
2840 if (status & GM_IS_TX_CO_OV)
2841 gma_read16(hw, port, GM_TX_IRQ_SRC);
2842
2843 if (status & GM_IS_RX_FF_OR) {
2844 ++dev->stats.rx_fifo_errors;
2845 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2846 }
2847
2848 if (status & GM_IS_TX_FF_UR) {
2849 ++dev->stats.tx_fifo_errors;
2850 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2851 }
2852 }
2853
2854 /* This should never happen it is a bug. */
2855 static void sky2_le_error(struct sky2_hw *hw, unsigned port, u16 q)
2856 {
2857 struct net_device *dev = hw->dev[port];
2858 u16 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
2859
2860 dev_err(&hw->pdev->dev, "%s: descriptor error q=%#x get=%u put=%u\n",
2861 dev->name, (unsigned) q, (unsigned) idx,
2862 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
2863
2864 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
2865 }
2866
2867 static int sky2_rx_hung(struct net_device *dev)
2868 {
2869 struct sky2_port *sky2 = netdev_priv(dev);
2870 struct sky2_hw *hw = sky2->hw;
2871 unsigned port = sky2->port;
2872 unsigned rxq = rxqaddr[port];
2873 u32 mac_rp = sky2_read32(hw, SK_REG(port, RX_GMF_RP));
2874 u8 mac_lev = sky2_read8(hw, SK_REG(port, RX_GMF_RLEV));
2875 u8 fifo_rp = sky2_read8(hw, Q_ADDR(rxq, Q_RP));
2876 u8 fifo_lev = sky2_read8(hw, Q_ADDR(rxq, Q_RL));
2877
2878 /* If idle and MAC or PCI is stuck */
2879 if (sky2->check.last == dev->last_rx &&
2880 ((mac_rp == sky2->check.mac_rp &&
2881 mac_lev != 0 && mac_lev >= sky2->check.mac_lev) ||
2882 /* Check if the PCI RX hang */
2883 (fifo_rp == sky2->check.fifo_rp &&
2884 fifo_lev != 0 && fifo_lev >= sky2->check.fifo_lev))) {
2885 netdev_printk(KERN_DEBUG, dev,
2886 "hung mac %d:%d fifo %d (%d:%d)\n",
2887 mac_lev, mac_rp, fifo_lev,
2888 fifo_rp, sky2_read8(hw, Q_ADDR(rxq, Q_WP)));
2889 return 1;
2890 } else {
2891 sky2->check.last = dev->last_rx;
2892 sky2->check.mac_rp = mac_rp;
2893 sky2->check.mac_lev = mac_lev;
2894 sky2->check.fifo_rp = fifo_rp;
2895 sky2->check.fifo_lev = fifo_lev;
2896 return 0;
2897 }
2898 }
2899
2900 static void sky2_watchdog(unsigned long arg)
2901 {
2902 struct sky2_hw *hw = (struct sky2_hw *) arg;
2903
2904 /* Check for lost IRQ once a second */
2905 if (sky2_read32(hw, B0_ISRC)) {
2906 napi_schedule(&hw->napi);
2907 } else {
2908 int i, active = 0;
2909
2910 for (i = 0; i < hw->ports; i++) {
2911 struct net_device *dev = hw->dev[i];
2912 if (!netif_running(dev))
2913 continue;
2914 ++active;
2915
2916 /* For chips with Rx FIFO, check if stuck */
2917 if ((hw->flags & SKY2_HW_RAM_BUFFER) &&
2918 sky2_rx_hung(dev)) {
2919 netdev_info(dev, "receiver hang detected\n");
2920 schedule_work(&hw->restart_work);
2921 return;
2922 }
2923 }
2924
2925 if (active == 0)
2926 return;
2927 }
2928
2929 mod_timer(&hw->watchdog_timer, round_jiffies(jiffies + HZ));
2930 }
2931
2932 /* Hardware/software error handling */
2933 static void sky2_err_intr(struct sky2_hw *hw, u32 status)
2934 {
2935 if (net_ratelimit())
2936 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status);
2937
2938 if (status & Y2_IS_HW_ERR)
2939 sky2_hw_intr(hw);
2940
2941 if (status & Y2_IS_IRQ_MAC1)
2942 sky2_mac_intr(hw, 0);
2943
2944 if (status & Y2_IS_IRQ_MAC2)
2945 sky2_mac_intr(hw, 1);
2946
2947 if (status & Y2_IS_CHK_RX1)
2948 sky2_le_error(hw, 0, Q_R1);
2949
2950 if (status & Y2_IS_CHK_RX2)
2951 sky2_le_error(hw, 1, Q_R2);
2952
2953 if (status & Y2_IS_CHK_TXA1)
2954 sky2_le_error(hw, 0, Q_XA1);
2955
2956 if (status & Y2_IS_CHK_TXA2)
2957 sky2_le_error(hw, 1, Q_XA2);
2958 }
2959
2960 static int sky2_poll(struct napi_struct *napi, int work_limit)
2961 {
2962 struct sky2_hw *hw = container_of(napi, struct sky2_hw, napi);
2963 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
2964 int work_done = 0;
2965 u16 idx;
2966
2967 if (unlikely(status & Y2_IS_ERROR))
2968 sky2_err_intr(hw, status);
2969
2970 if (status & Y2_IS_IRQ_PHY1)
2971 sky2_phy_intr(hw, 0);
2972
2973 if (status & Y2_IS_IRQ_PHY2)
2974 sky2_phy_intr(hw, 1);
2975
2976 if (status & Y2_IS_PHY_QLNK)
2977 sky2_qlink_intr(hw);
2978
2979 while ((idx = sky2_read16(hw, STAT_PUT_IDX)) != hw->st_idx) {
2980 work_done += sky2_status_intr(hw, work_limit - work_done, idx);
2981
2982 if (work_done >= work_limit)
2983 goto done;
2984 }
2985
2986 napi_complete(napi);
2987 sky2_read32(hw, B0_Y2_SP_LISR);
2988 done:
2989
2990 return work_done;
2991 }
2992
2993 static irqreturn_t sky2_intr(int irq, void *dev_id)
2994 {
2995 struct sky2_hw *hw = dev_id;
2996 u32 status;
2997
2998 /* Reading this mask interrupts as side effect */
2999 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
3000 if (status == 0 || status == ~0)
3001 return IRQ_NONE;
3002
3003 prefetch(&hw->st_le[hw->st_idx]);
3004
3005 napi_schedule(&hw->napi);
3006
3007 return IRQ_HANDLED;
3008 }
3009
3010 #ifdef CONFIG_NET_POLL_CONTROLLER
3011 static void sky2_netpoll(struct net_device *dev)
3012 {
3013 struct sky2_port *sky2 = netdev_priv(dev);
3014
3015 napi_schedule(&sky2->hw->napi);
3016 }
3017 #endif
3018
3019 /* Chip internal frequency for clock calculations */
3020 static u32 sky2_mhz(const struct sky2_hw *hw)
3021 {
3022 switch (hw->chip_id) {
3023 case CHIP_ID_YUKON_EC:
3024 case CHIP_ID_YUKON_EC_U:
3025 case CHIP_ID_YUKON_EX:
3026 case CHIP_ID_YUKON_SUPR:
3027 case CHIP_ID_YUKON_UL_2:
3028 case CHIP_ID_YUKON_OPT:
3029 case CHIP_ID_YUKON_PRM:
3030 case CHIP_ID_YUKON_OP_2:
3031 return 125;
3032
3033 case CHIP_ID_YUKON_FE:
3034 return 100;
3035
3036 case CHIP_ID_YUKON_FE_P:
3037 return 50;
3038
3039 case CHIP_ID_YUKON_XL:
3040 return 156;
3041
3042 default:
3043 BUG();
3044 }
3045 }
3046
3047 static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
3048 {
3049 return sky2_mhz(hw) * us;
3050 }
3051
3052 static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
3053 {
3054 return clk / sky2_mhz(hw);
3055 }
3056
3057
3058 static int __devinit sky2_init(struct sky2_hw *hw)
3059 {
3060 u8 t8;
3061
3062 /* Enable all clocks and check for bad PCI access */
3063 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
3064
3065 sky2_write8(hw, B0_CTST, CS_RST_CLR);
3066
3067 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
3068 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
3069
3070 switch (hw->chip_id) {
3071 case CHIP_ID_YUKON_XL:
3072 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_NEWER_PHY;
3073 if (hw->chip_rev < CHIP_REV_YU_XL_A2)
3074 hw->flags |= SKY2_HW_RSS_BROKEN;
3075 break;
3076
3077 case CHIP_ID_YUKON_EC_U:
3078 hw->flags = SKY2_HW_GIGABIT
3079 | SKY2_HW_NEWER_PHY
3080 | SKY2_HW_ADV_POWER_CTL;
3081 break;
3082
3083 case CHIP_ID_YUKON_EX:
3084 hw->flags = SKY2_HW_GIGABIT
3085 | SKY2_HW_NEWER_PHY
3086 | SKY2_HW_NEW_LE
3087 | SKY2_HW_ADV_POWER_CTL
3088 | SKY2_HW_RSS_CHKSUM;
3089
3090 /* New transmit checksum */
3091 if (hw->chip_rev != CHIP_REV_YU_EX_B0)
3092 hw->flags |= SKY2_HW_AUTO_TX_SUM;
3093 break;
3094
3095 case CHIP_ID_YUKON_EC:
3096 /* This rev is really old, and requires untested workarounds */
3097 if (hw->chip_rev == CHIP_REV_YU_EC_A1) {
3098 dev_err(&hw->pdev->dev, "unsupported revision Yukon-EC rev A1\n");
3099 return -EOPNOTSUPP;
3100 }
3101 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_RSS_BROKEN;
3102 break;
3103
3104 case CHIP_ID_YUKON_FE:
3105 hw->flags = SKY2_HW_RSS_BROKEN;
3106 break;
3107
3108 case CHIP_ID_YUKON_FE_P:
3109 hw->flags = SKY2_HW_NEWER_PHY
3110 | SKY2_HW_NEW_LE
3111 | SKY2_HW_AUTO_TX_SUM
3112 | SKY2_HW_ADV_POWER_CTL;
3113
3114 /* The workaround for status conflicts VLAN tag detection. */
3115 if (hw->chip_rev == CHIP_REV_YU_FE2_A0)
3116 hw->flags |= SKY2_HW_VLAN_BROKEN | SKY2_HW_RSS_CHKSUM;
3117 break;
3118
3119 case CHIP_ID_YUKON_SUPR:
3120 hw->flags = SKY2_HW_GIGABIT
3121 | SKY2_HW_NEWER_PHY
3122 | SKY2_HW_NEW_LE
3123 | SKY2_HW_AUTO_TX_SUM
3124 | SKY2_HW_ADV_POWER_CTL;
3125
3126 if (hw->chip_rev == CHIP_REV_YU_SU_A0)
3127 hw->flags |= SKY2_HW_RSS_CHKSUM;
3128 break;
3129
3130 case CHIP_ID_YUKON_UL_2:
3131 hw->flags = SKY2_HW_GIGABIT
3132 | SKY2_HW_ADV_POWER_CTL;
3133 break;
3134
3135 case CHIP_ID_YUKON_OPT:
3136 case CHIP_ID_YUKON_PRM:
3137 case CHIP_ID_YUKON_OP_2:
3138 hw->flags = SKY2_HW_GIGABIT
3139 | SKY2_HW_NEW_LE
3140 | SKY2_HW_ADV_POWER_CTL;
3141 break;
3142
3143 default:
3144 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
3145 hw->chip_id);
3146 return -EOPNOTSUPP;
3147 }
3148
3149 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
3150 if (hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P')
3151 hw->flags |= SKY2_HW_FIBRE_PHY;
3152
3153 hw->ports = 1;
3154 t8 = sky2_read8(hw, B2_Y2_HW_RES);
3155 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
3156 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
3157 ++hw->ports;
3158 }
3159
3160 if (sky2_read8(hw, B2_E_0))
3161 hw->flags |= SKY2_HW_RAM_BUFFER;
3162
3163 return 0;
3164 }
3165
3166 static void sky2_reset(struct sky2_hw *hw)
3167 {
3168 struct pci_dev *pdev = hw->pdev;
3169 u16 status;
3170 int i;
3171 u32 hwe_mask = Y2_HWE_ALL_MASK;
3172
3173 /* disable ASF */
3174 if (hw->chip_id == CHIP_ID_YUKON_EX
3175 || hw->chip_id == CHIP_ID_YUKON_SUPR) {
3176 sky2_write32(hw, CPU_WDOG, 0);
3177 status = sky2_read16(hw, HCU_CCSR);
3178 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
3179 HCU_CCSR_UC_STATE_MSK);
3180 /*
3181 * CPU clock divider shouldn't be used because
3182 * - ASF firmware may malfunction
3183 * - Yukon-Supreme: Parallel FLASH doesn't support divided clocks
3184 */
3185 status &= ~HCU_CCSR_CPU_CLK_DIVIDE_MSK;
3186 sky2_write16(hw, HCU_CCSR, status);
3187 sky2_write32(hw, CPU_WDOG, 0);
3188 } else
3189 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
3190 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
3191
3192 /* do a SW reset */
3193 sky2_write8(hw, B0_CTST, CS_RST_SET);
3194 sky2_write8(hw, B0_CTST, CS_RST_CLR);
3195
3196 /* allow writes to PCI config */
3197 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3198
3199 /* clear PCI errors, if any */
3200 status = sky2_pci_read16(hw, PCI_STATUS);
3201 status |= PCI_STATUS_ERROR_BITS;
3202 sky2_pci_write16(hw, PCI_STATUS, status);
3203
3204 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
3205
3206 if (pci_is_pcie(pdev)) {
3207 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
3208 0xfffffffful);
3209
3210 /* If error bit is stuck on ignore it */
3211 if (sky2_read32(hw, B0_HWE_ISRC) & Y2_IS_PCI_EXP)
3212 dev_info(&pdev->dev, "ignoring stuck error report bit\n");
3213 else
3214 hwe_mask |= Y2_IS_PCI_EXP;
3215 }
3216
3217 sky2_power_on(hw);
3218 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3219
3220 for (i = 0; i < hw->ports; i++) {
3221 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
3222 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
3223
3224 if (hw->chip_id == CHIP_ID_YUKON_EX ||
3225 hw->chip_id == CHIP_ID_YUKON_SUPR)
3226 sky2_write16(hw, SK_REG(i, GMAC_CTRL),
3227 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON
3228 | GMC_BYP_RETR_ON);
3229
3230 }
3231
3232 if (hw->chip_id == CHIP_ID_YUKON_SUPR && hw->chip_rev > CHIP_REV_YU_SU_B0) {
3233 /* enable MACSec clock gating */
3234 sky2_pci_write32(hw, PCI_DEV_REG3, P_CLK_MACSEC_DIS);
3235 }
3236
3237 if (hw->chip_id == CHIP_ID_YUKON_OPT ||
3238 hw->chip_id == CHIP_ID_YUKON_PRM ||
3239 hw->chip_id == CHIP_ID_YUKON_OP_2) {
3240 u16 reg;
3241 u32 msk;
3242
3243 if (hw->chip_id == CHIP_ID_YUKON_OPT && hw->chip_rev == 0) {
3244 /* disable PCI-E PHY power down (set PHY reg 0x80, bit 7 */
3245 sky2_write32(hw, Y2_PEX_PHY_DATA, (0x80UL << 16) | (1 << 7));
3246
3247 /* set PHY Link Detect Timer to 1.1 second (11x 100ms) */
3248 reg = 10;
3249
3250 /* re-enable PEX PM in PEX PHY debug reg. 8 (clear bit 12) */
3251 sky2_write32(hw, Y2_PEX_PHY_DATA, PEX_DB_ACCESS | (0x08UL << 16));
3252 } else {
3253 /* set PHY Link Detect Timer to 0.4 second (4x 100ms) */
3254 reg = 3;
3255 }
3256
3257 reg <<= PSM_CONFIG_REG4_TIMER_PHY_LINK_DETECT_BASE;
3258 reg |= PSM_CONFIG_REG4_RST_PHY_LINK_DETECT;
3259
3260 /* reset PHY Link Detect */
3261 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3262 sky2_pci_write16(hw, PSM_CONFIG_REG4, reg);
3263
3264 /* enable PHY Quick Link */
3265 msk = sky2_read32(hw, B0_IMSK);
3266 msk |= Y2_IS_PHY_QLNK;
3267 sky2_write32(hw, B0_IMSK, msk);
3268
3269 /* check if PSMv2 was running before */
3270 reg = sky2_pci_read16(hw, PSM_CONFIG_REG3);
3271 if (reg & PCI_EXP_LNKCTL_ASPMC)
3272 /* restore the PCIe Link Control register */
3273 sky2_pci_write16(hw, pdev->pcie_cap + PCI_EXP_LNKCTL,
3274 reg);
3275
3276 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3277
3278 /* re-enable PEX PM in PEX PHY debug reg. 8 (clear bit 12) */
3279 sky2_write32(hw, Y2_PEX_PHY_DATA, PEX_DB_ACCESS | (0x08UL << 16));
3280 }
3281
3282 /* Clear I2C IRQ noise */
3283 sky2_write32(hw, B2_I2C_IRQ, 1);
3284
3285 /* turn off hardware timer (unused) */
3286 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
3287 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
3288
3289 /* Turn off descriptor polling */
3290 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
3291
3292 /* Turn off receive timestamp */
3293 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
3294 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
3295
3296 /* enable the Tx Arbiters */
3297 for (i = 0; i < hw->ports; i++)
3298 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
3299
3300 /* Initialize ram interface */
3301 for (i = 0; i < hw->ports; i++) {
3302 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
3303
3304 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
3305 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
3306 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
3307 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
3308 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
3309 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
3310 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
3311 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
3312 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
3313 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
3314 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
3315 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
3316 }
3317
3318 sky2_write32(hw, B0_HWE_IMSK, hwe_mask);
3319
3320 for (i = 0; i < hw->ports; i++)
3321 sky2_gmac_reset(hw, i);
3322
3323 memset(hw->st_le, 0, hw->st_size * sizeof(struct sky2_status_le));
3324 hw->st_idx = 0;
3325
3326 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
3327 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
3328
3329 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
3330 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
3331
3332 /* Set the list last index */
3333 sky2_write16(hw, STAT_LAST_IDX, hw->st_size - 1);
3334
3335 sky2_write16(hw, STAT_TX_IDX_TH, 10);
3336 sky2_write8(hw, STAT_FIFO_WM, 16);
3337
3338 /* set Status-FIFO ISR watermark */
3339 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
3340 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
3341 else
3342 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
3343
3344 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
3345 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
3346 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
3347
3348 /* enable status unit */
3349 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
3350
3351 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3352 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3353 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3354 }
3355
3356 /* Take device down (offline).
3357 * Equivalent to doing dev_stop() but this does not
3358 * inform upper layers of the transition.
3359 */
3360 static void sky2_detach(struct net_device *dev)
3361 {
3362 if (netif_running(dev)) {
3363 netif_tx_lock(dev);
3364 netif_device_detach(dev); /* stop txq */
3365 netif_tx_unlock(dev);
3366 sky2_down(dev);
3367 }
3368 }
3369
3370 /* Bring device back after doing sky2_detach */
3371 static int sky2_reattach(struct net_device *dev)
3372 {
3373 int err = 0;
3374
3375 if (netif_running(dev)) {
3376 err = sky2_up(dev);
3377 if (err) {
3378 netdev_info(dev, "could not restart %d\n", err);
3379 dev_close(dev);
3380 } else {
3381 netif_device_attach(dev);
3382 sky2_set_multicast(dev);
3383 }
3384 }
3385
3386 return err;
3387 }
3388
3389 static void sky2_all_down(struct sky2_hw *hw)
3390 {
3391 int i;
3392
3393 sky2_read32(hw, B0_IMSK);
3394 sky2_write32(hw, B0_IMSK, 0);
3395 synchronize_irq(hw->pdev->irq);
3396 napi_disable(&hw->napi);
3397
3398 for (i = 0; i < hw->ports; i++) {
3399 struct net_device *dev = hw->dev[i];
3400 struct sky2_port *sky2 = netdev_priv(dev);
3401
3402 if (!netif_running(dev))
3403 continue;
3404
3405 netif_carrier_off(dev);
3406 netif_tx_disable(dev);
3407 sky2_hw_down(sky2);
3408 }
3409 }
3410
3411 static void sky2_all_up(struct sky2_hw *hw)
3412 {
3413 u32 imask = Y2_IS_BASE;
3414 int i;
3415
3416 for (i = 0; i < hw->ports; i++) {
3417 struct net_device *dev = hw->dev[i];
3418 struct sky2_port *sky2 = netdev_priv(dev);
3419
3420 if (!netif_running(dev))
3421 continue;
3422
3423 sky2_hw_up(sky2);
3424 sky2_set_multicast(dev);
3425 imask |= portirq_msk[i];
3426 netif_wake_queue(dev);
3427 }
3428
3429 sky2_write32(hw, B0_IMSK, imask);
3430 sky2_read32(hw, B0_IMSK);
3431
3432 sky2_read32(hw, B0_Y2_SP_LISR);
3433 napi_enable(&hw->napi);
3434 }
3435
3436 static void sky2_restart(struct work_struct *work)
3437 {
3438 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
3439
3440 rtnl_lock();
3441
3442 sky2_all_down(hw);
3443 sky2_reset(hw);
3444 sky2_all_up(hw);
3445
3446 rtnl_unlock();
3447 }
3448
3449 static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
3450 {
3451 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
3452 }
3453
3454 static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3455 {
3456 const struct sky2_port *sky2 = netdev_priv(dev);
3457
3458 wol->supported = sky2_wol_supported(sky2->hw);
3459 wol->wolopts = sky2->wol;
3460 }
3461
3462 static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3463 {
3464 struct sky2_port *sky2 = netdev_priv(dev);
3465 struct sky2_hw *hw = sky2->hw;
3466 bool enable_wakeup = false;
3467 int i;
3468
3469 if ((wol->wolopts & ~sky2_wol_supported(sky2->hw)) ||
3470 !device_can_wakeup(&hw->pdev->dev))
3471 return -EOPNOTSUPP;
3472
3473 sky2->wol = wol->wolopts;
3474
3475 for (i = 0; i < hw->ports; i++) {
3476 struct net_device *dev = hw->dev[i];
3477 struct sky2_port *sky2 = netdev_priv(dev);
3478
3479 if (sky2->wol)
3480 enable_wakeup = true;
3481 }
3482 device_set_wakeup_enable(&hw->pdev->dev, enable_wakeup);
3483
3484 return 0;
3485 }
3486
3487 static u32 sky2_supported_modes(const struct sky2_hw *hw)
3488 {
3489 if (sky2_is_copper(hw)) {
3490 u32 modes = SUPPORTED_10baseT_Half
3491 | SUPPORTED_10baseT_Full
3492 | SUPPORTED_100baseT_Half
3493 | SUPPORTED_100baseT_Full;
3494
3495 if (hw->flags & SKY2_HW_GIGABIT)
3496 modes |= SUPPORTED_1000baseT_Half
3497 | SUPPORTED_1000baseT_Full;
3498 return modes;
3499 } else
3500 return SUPPORTED_1000baseT_Half
3501 | SUPPORTED_1000baseT_Full;
3502 }
3503
3504 static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3505 {
3506 struct sky2_port *sky2 = netdev_priv(dev);
3507 struct sky2_hw *hw = sky2->hw;
3508
3509 ecmd->transceiver = XCVR_INTERNAL;
3510 ecmd->supported = sky2_supported_modes(hw);
3511 ecmd->phy_address = PHY_ADDR_MARV;
3512 if (sky2_is_copper(hw)) {
3513 ecmd->port = PORT_TP;
3514 ethtool_cmd_speed_set(ecmd, sky2->speed);
3515 ecmd->supported |= SUPPORTED_Autoneg | SUPPORTED_TP;
3516 } else {
3517 ethtool_cmd_speed_set(ecmd, SPEED_1000);
3518 ecmd->port = PORT_FIBRE;
3519 ecmd->supported |= SUPPORTED_Autoneg | SUPPORTED_FIBRE;
3520 }
3521
3522 ecmd->advertising = sky2->advertising;
3523 ecmd->autoneg = (sky2->flags & SKY2_FLAG_AUTO_SPEED)
3524 ? AUTONEG_ENABLE : AUTONEG_DISABLE;
3525 ecmd->duplex = sky2->duplex;
3526 return 0;
3527 }
3528
3529 static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3530 {
3531 struct sky2_port *sky2 = netdev_priv(dev);
3532 const struct sky2_hw *hw = sky2->hw;
3533 u32 supported = sky2_supported_modes(hw);
3534
3535 if (ecmd->autoneg == AUTONEG_ENABLE) {
3536 if (ecmd->advertising & ~supported)
3537 return -EINVAL;
3538
3539 if (sky2_is_copper(hw))
3540 sky2->advertising = ecmd->advertising |
3541 ADVERTISED_TP |
3542 ADVERTISED_Autoneg;
3543 else
3544 sky2->advertising = ecmd->advertising |
3545 ADVERTISED_FIBRE |
3546 ADVERTISED_Autoneg;
3547
3548 sky2->flags |= SKY2_FLAG_AUTO_SPEED;
3549 sky2->duplex = -1;
3550 sky2->speed = -1;
3551 } else {
3552 u32 setting;
3553 u32 speed = ethtool_cmd_speed(ecmd);
3554
3555 switch (speed) {
3556 case SPEED_1000:
3557 if (ecmd->duplex == DUPLEX_FULL)
3558 setting = SUPPORTED_1000baseT_Full;
3559 else if (ecmd->duplex == DUPLEX_HALF)
3560 setting = SUPPORTED_1000baseT_Half;
3561 else
3562 return -EINVAL;
3563 break;
3564 case SPEED_100:
3565 if (ecmd->duplex == DUPLEX_FULL)
3566 setting = SUPPORTED_100baseT_Full;
3567 else if (ecmd->duplex == DUPLEX_HALF)
3568 setting = SUPPORTED_100baseT_Half;
3569 else
3570 return -EINVAL;
3571 break;
3572
3573 case SPEED_10:
3574 if (ecmd->duplex == DUPLEX_FULL)
3575 setting = SUPPORTED_10baseT_Full;
3576 else if (ecmd->duplex == DUPLEX_HALF)
3577 setting = SUPPORTED_10baseT_Half;
3578 else
3579 return -EINVAL;
3580 break;
3581 default:
3582 return -EINVAL;
3583 }
3584
3585 if ((setting & supported) == 0)
3586 return -EINVAL;
3587
3588 sky2->speed = speed;
3589 sky2->duplex = ecmd->duplex;
3590 sky2->flags &= ~SKY2_FLAG_AUTO_SPEED;
3591 }
3592
3593 if (netif_running(dev)) {
3594 sky2_phy_reinit(sky2);
3595 sky2_set_multicast(dev);
3596 }
3597
3598 return 0;
3599 }
3600
3601 static void sky2_get_drvinfo(struct net_device *dev,
3602 struct ethtool_drvinfo *info)
3603 {
3604 struct sky2_port *sky2 = netdev_priv(dev);
3605
3606 strcpy(info->driver, DRV_NAME);
3607 strcpy(info->version, DRV_VERSION);
3608 strcpy(info->fw_version, "N/A");
3609 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
3610 }
3611
3612 static const struct sky2_stat {
3613 char name[ETH_GSTRING_LEN];
3614 u16 offset;
3615 } sky2_stats[] = {
3616 { "tx_bytes", GM_TXO_OK_HI },
3617 { "rx_bytes", GM_RXO_OK_HI },
3618 { "tx_broadcast", GM_TXF_BC_OK },
3619 { "rx_broadcast", GM_RXF_BC_OK },
3620 { "tx_multicast", GM_TXF_MC_OK },
3621 { "rx_multicast", GM_RXF_MC_OK },
3622 { "tx_unicast", GM_TXF_UC_OK },
3623 { "rx_unicast", GM_RXF_UC_OK },
3624 { "tx_mac_pause", GM_TXF_MPAUSE },
3625 { "rx_mac_pause", GM_RXF_MPAUSE },
3626 { "collisions", GM_TXF_COL },
3627 { "late_collision",GM_TXF_LAT_COL },
3628 { "aborted", GM_TXF_ABO_COL },
3629 { "single_collisions", GM_TXF_SNG_COL },
3630 { "multi_collisions", GM_TXF_MUL_COL },
3631
3632 { "rx_short", GM_RXF_SHT },
3633 { "rx_runt", GM_RXE_FRAG },
3634 { "rx_64_byte_packets", GM_RXF_64B },
3635 { "rx_65_to_127_byte_packets", GM_RXF_127B },
3636 { "rx_128_to_255_byte_packets", GM_RXF_255B },
3637 { "rx_256_to_511_byte_packets", GM_RXF_511B },
3638 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
3639 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
3640 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
3641 { "rx_too_long", GM_RXF_LNG_ERR },
3642 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
3643 { "rx_jabber", GM_RXF_JAB_PKT },
3644 { "rx_fcs_error", GM_RXF_FCS_ERR },
3645
3646 { "tx_64_byte_packets", GM_TXF_64B },
3647 { "tx_65_to_127_byte_packets", GM_TXF_127B },
3648 { "tx_128_to_255_byte_packets", GM_TXF_255B },
3649 { "tx_256_to_511_byte_packets", GM_TXF_511B },
3650 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
3651 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
3652 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
3653 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
3654 };
3655
3656 static u32 sky2_get_msglevel(struct net_device *netdev)
3657 {
3658 struct sky2_port *sky2 = netdev_priv(netdev);
3659 return sky2->msg_enable;
3660 }
3661
3662 static int sky2_nway_reset(struct net_device *dev)
3663 {
3664 struct sky2_port *sky2 = netdev_priv(dev);
3665
3666 if (!netif_running(dev) || !(sky2->flags & SKY2_FLAG_AUTO_SPEED))
3667 return -EINVAL;
3668
3669 sky2_phy_reinit(sky2);
3670 sky2_set_multicast(dev);
3671
3672 return 0;
3673 }
3674
3675 static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
3676 {
3677 struct sky2_hw *hw = sky2->hw;
3678 unsigned port = sky2->port;
3679 int i;
3680
3681 data[0] = get_stats64(hw, port, GM_TXO_OK_LO);
3682 data[1] = get_stats64(hw, port, GM_RXO_OK_LO);
3683
3684 for (i = 2; i < count; i++)
3685 data[i] = get_stats32(hw, port, sky2_stats[i].offset);
3686 }
3687
3688 static void sky2_set_msglevel(struct net_device *netdev, u32 value)
3689 {
3690 struct sky2_port *sky2 = netdev_priv(netdev);
3691 sky2->msg_enable = value;
3692 }
3693
3694 static int sky2_get_sset_count(struct net_device *dev, int sset)
3695 {
3696 switch (sset) {
3697 case ETH_SS_STATS:
3698 return ARRAY_SIZE(sky2_stats);
3699 default:
3700 return -EOPNOTSUPP;
3701 }
3702 }
3703
3704 static void sky2_get_ethtool_stats(struct net_device *dev,
3705 struct ethtool_stats *stats, u64 * data)
3706 {
3707 struct sky2_port *sky2 = netdev_priv(dev);
3708
3709 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
3710 }
3711
3712 static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
3713 {
3714 int i;
3715
3716 switch (stringset) {
3717 case ETH_SS_STATS:
3718 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
3719 memcpy(data + i * ETH_GSTRING_LEN,
3720 sky2_stats[i].name, ETH_GSTRING_LEN);
3721 break;
3722 }
3723 }
3724
3725 static int sky2_set_mac_address(struct net_device *dev, void *p)
3726 {
3727 struct sky2_port *sky2 = netdev_priv(dev);
3728 struct sky2_hw *hw = sky2->hw;
3729 unsigned port = sky2->port;
3730 const struct sockaddr *addr = p;
3731
3732 if (!is_valid_ether_addr(addr->sa_data))
3733 return -EADDRNOTAVAIL;
3734
3735 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
3736 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
3737 dev->dev_addr, ETH_ALEN);
3738 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
3739 dev->dev_addr, ETH_ALEN);
3740
3741 /* virtual address for data */
3742 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3743
3744 /* physical address: used for pause frames */
3745 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
3746
3747 return 0;
3748 }
3749
3750 static inline void sky2_add_filter(u8 filter[8], const u8 *addr)
3751 {
3752 u32 bit;
3753
3754 bit = ether_crc(ETH_ALEN, addr) & 63;
3755 filter[bit >> 3] |= 1 << (bit & 7);
3756 }
3757
3758 static void sky2_set_multicast(struct net_device *dev)
3759 {
3760 struct sky2_port *sky2 = netdev_priv(dev);
3761 struct sky2_hw *hw = sky2->hw;
3762 unsigned port = sky2->port;
3763 struct netdev_hw_addr *ha;
3764 u16 reg;
3765 u8 filter[8];
3766 int rx_pause;
3767 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
3768
3769 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
3770 memset(filter, 0, sizeof(filter));
3771
3772 reg = gma_read16(hw, port, GM_RX_CTRL);
3773 reg |= GM_RXCR_UCF_ENA;
3774
3775 if (dev->flags & IFF_PROMISC) /* promiscuous */
3776 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
3777 else if (dev->flags & IFF_ALLMULTI)
3778 memset(filter, 0xff, sizeof(filter));
3779 else if (netdev_mc_empty(dev) && !rx_pause)
3780 reg &= ~GM_RXCR_MCF_ENA;
3781 else {
3782 reg |= GM_RXCR_MCF_ENA;
3783
3784 if (rx_pause)
3785 sky2_add_filter(filter, pause_mc_addr);
3786
3787 netdev_for_each_mc_addr(ha, dev)
3788 sky2_add_filter(filter, ha->addr);
3789 }
3790
3791 gma_write16(hw, port, GM_MC_ADDR_H1,
3792 (u16) filter[0] | ((u16) filter[1] << 8));
3793 gma_write16(hw, port, GM_MC_ADDR_H2,
3794 (u16) filter[2] | ((u16) filter[3] << 8));
3795 gma_write16(hw, port, GM_MC_ADDR_H3,
3796 (u16) filter[4] | ((u16) filter[5] << 8));
3797 gma_write16(hw, port, GM_MC_ADDR_H4,
3798 (u16) filter[6] | ((u16) filter[7] << 8));
3799
3800 gma_write16(hw, port, GM_RX_CTRL, reg);
3801 }
3802
3803 static struct rtnl_link_stats64 *sky2_get_stats(struct net_device *dev,
3804 struct rtnl_link_stats64 *stats)
3805 {
3806 struct sky2_port *sky2 = netdev_priv(dev);
3807 struct sky2_hw *hw = sky2->hw;
3808 unsigned port = sky2->port;
3809 unsigned int start;
3810 u64 _bytes, _packets;
3811
3812 do {
3813 start = u64_stats_fetch_begin_bh(&sky2->rx_stats.syncp);
3814 _bytes = sky2->rx_stats.bytes;
3815 _packets = sky2->rx_stats.packets;
3816 } while (u64_stats_fetch_retry_bh(&sky2->rx_stats.syncp, start));
3817
3818 stats->rx_packets = _packets;
3819 stats->rx_bytes = _bytes;
3820
3821 do {
3822 start = u64_stats_fetch_begin_bh(&sky2->tx_stats.syncp);
3823 _bytes = sky2->tx_stats.bytes;
3824 _packets = sky2->tx_stats.packets;
3825 } while (u64_stats_fetch_retry_bh(&sky2->tx_stats.syncp, start));
3826
3827 stats->tx_packets = _packets;
3828 stats->tx_bytes = _bytes;
3829
3830 stats->multicast = get_stats32(hw, port, GM_RXF_MC_OK)
3831 + get_stats32(hw, port, GM_RXF_BC_OK);
3832
3833 stats->collisions = get_stats32(hw, port, GM_TXF_COL);
3834
3835 stats->rx_length_errors = get_stats32(hw, port, GM_RXF_LNG_ERR);
3836 stats->rx_crc_errors = get_stats32(hw, port, GM_RXF_FCS_ERR);
3837 stats->rx_frame_errors = get_stats32(hw, port, GM_RXF_SHT)
3838 + get_stats32(hw, port, GM_RXE_FRAG);
3839 stats->rx_over_errors = get_stats32(hw, port, GM_RXE_FIFO_OV);
3840
3841 stats->rx_dropped = dev->stats.rx_dropped;
3842 stats->rx_fifo_errors = dev->stats.rx_fifo_errors;
3843 stats->tx_fifo_errors = dev->stats.tx_fifo_errors;
3844
3845 return stats;
3846 }
3847
3848 /* Can have one global because blinking is controlled by
3849 * ethtool and that is always under RTNL mutex
3850 */
3851 static void sky2_led(struct sky2_port *sky2, enum led_mode mode)
3852 {
3853 struct sky2_hw *hw = sky2->hw;
3854 unsigned port = sky2->port;
3855
3856 spin_lock_bh(&sky2->phy_lock);
3857 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
3858 hw->chip_id == CHIP_ID_YUKON_EX ||
3859 hw->chip_id == CHIP_ID_YUKON_SUPR) {
3860 u16 pg;
3861 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3862 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3863
3864 switch (mode) {
3865 case MO_LED_OFF:
3866 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3867 PHY_M_LEDC_LOS_CTRL(8) |
3868 PHY_M_LEDC_INIT_CTRL(8) |
3869 PHY_M_LEDC_STA1_CTRL(8) |
3870 PHY_M_LEDC_STA0_CTRL(8));
3871 break;
3872 case MO_LED_ON:
3873 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3874 PHY_M_LEDC_LOS_CTRL(9) |
3875 PHY_M_LEDC_INIT_CTRL(9) |
3876 PHY_M_LEDC_STA1_CTRL(9) |
3877 PHY_M_LEDC_STA0_CTRL(9));
3878 break;
3879 case MO_LED_BLINK:
3880 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3881 PHY_M_LEDC_LOS_CTRL(0xa) |
3882 PHY_M_LEDC_INIT_CTRL(0xa) |
3883 PHY_M_LEDC_STA1_CTRL(0xa) |
3884 PHY_M_LEDC_STA0_CTRL(0xa));
3885 break;
3886 case MO_LED_NORM:
3887 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3888 PHY_M_LEDC_LOS_CTRL(1) |
3889 PHY_M_LEDC_INIT_CTRL(8) |
3890 PHY_M_LEDC_STA1_CTRL(7) |
3891 PHY_M_LEDC_STA0_CTRL(7));
3892 }
3893
3894 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3895 } else
3896 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
3897 PHY_M_LED_MO_DUP(mode) |
3898 PHY_M_LED_MO_10(mode) |
3899 PHY_M_LED_MO_100(mode) |
3900 PHY_M_LED_MO_1000(mode) |
3901 PHY_M_LED_MO_RX(mode) |
3902 PHY_M_LED_MO_TX(mode));
3903
3904 spin_unlock_bh(&sky2->phy_lock);
3905 }
3906
3907 /* blink LED's for finding board */
3908 static int sky2_set_phys_id(struct net_device *dev,
3909 enum ethtool_phys_id_state state)
3910 {
3911 struct sky2_port *sky2 = netdev_priv(dev);
3912
3913 switch (state) {
3914 case ETHTOOL_ID_ACTIVE:
3915 return 1; /* cycle on/off once per second */
3916 case ETHTOOL_ID_INACTIVE:
3917 sky2_led(sky2, MO_LED_NORM);
3918 break;
3919 case ETHTOOL_ID_ON:
3920 sky2_led(sky2, MO_LED_ON);
3921 break;
3922 case ETHTOOL_ID_OFF:
3923 sky2_led(sky2, MO_LED_OFF);
3924 break;
3925 }
3926
3927 return 0;
3928 }
3929
3930 static void sky2_get_pauseparam(struct net_device *dev,
3931 struct ethtool_pauseparam *ecmd)
3932 {
3933 struct sky2_port *sky2 = netdev_priv(dev);
3934
3935 switch (sky2->flow_mode) {
3936 case FC_NONE:
3937 ecmd->tx_pause = ecmd->rx_pause = 0;
3938 break;
3939 case FC_TX:
3940 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3941 break;
3942 case FC_RX:
3943 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3944 break;
3945 case FC_BOTH:
3946 ecmd->tx_pause = ecmd->rx_pause = 1;
3947 }
3948
3949 ecmd->autoneg = (sky2->flags & SKY2_FLAG_AUTO_PAUSE)
3950 ? AUTONEG_ENABLE : AUTONEG_DISABLE;
3951 }
3952
3953 static int sky2_set_pauseparam(struct net_device *dev,
3954 struct ethtool_pauseparam *ecmd)
3955 {
3956 struct sky2_port *sky2 = netdev_priv(dev);
3957
3958 if (ecmd->autoneg == AUTONEG_ENABLE)
3959 sky2->flags |= SKY2_FLAG_AUTO_PAUSE;
3960 else
3961 sky2->flags &= ~SKY2_FLAG_AUTO_PAUSE;
3962
3963 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
3964
3965 if (netif_running(dev))
3966 sky2_phy_reinit(sky2);
3967
3968 return 0;
3969 }
3970
3971 static int sky2_get_coalesce(struct net_device *dev,
3972 struct ethtool_coalesce *ecmd)
3973 {
3974 struct sky2_port *sky2 = netdev_priv(dev);
3975 struct sky2_hw *hw = sky2->hw;
3976
3977 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3978 ecmd->tx_coalesce_usecs = 0;
3979 else {
3980 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3981 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3982 }
3983 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3984
3985 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3986 ecmd->rx_coalesce_usecs = 0;
3987 else {
3988 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3989 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3990 }
3991 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3992
3993 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3994 ecmd->rx_coalesce_usecs_irq = 0;
3995 else {
3996 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3997 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3998 }
3999
4000 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
4001
4002 return 0;
4003 }
4004
4005 /* Note: this affect both ports */
4006 static int sky2_set_coalesce(struct net_device *dev,
4007 struct ethtool_coalesce *ecmd)
4008 {
4009 struct sky2_port *sky2 = netdev_priv(dev);
4010 struct sky2_hw *hw = sky2->hw;
4011 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
4012
4013 if (ecmd->tx_coalesce_usecs > tmax ||
4014 ecmd->rx_coalesce_usecs > tmax ||
4015 ecmd->rx_coalesce_usecs_irq > tmax)
4016 return -EINVAL;
4017
4018 if (ecmd->tx_max_coalesced_frames >= sky2->tx_ring_size-1)
4019 return -EINVAL;
4020 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
4021 return -EINVAL;
4022 if (ecmd->rx_max_coalesced_frames_irq > RX_MAX_PENDING)
4023 return -EINVAL;
4024
4025 if (ecmd->tx_coalesce_usecs == 0)
4026 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
4027 else {
4028 sky2_write32(hw, STAT_TX_TIMER_INI,
4029 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
4030 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
4031 }
4032 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
4033
4034 if (ecmd->rx_coalesce_usecs == 0)
4035 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
4036 else {
4037 sky2_write32(hw, STAT_LEV_TIMER_INI,
4038 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
4039 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
4040 }
4041 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
4042
4043 if (ecmd->rx_coalesce_usecs_irq == 0)
4044 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
4045 else {
4046 sky2_write32(hw, STAT_ISR_TIMER_INI,
4047 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
4048 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
4049 }
4050 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
4051 return 0;
4052 }
4053
4054 static void sky2_get_ringparam(struct net_device *dev,
4055 struct ethtool_ringparam *ering)
4056 {
4057 struct sky2_port *sky2 = netdev_priv(dev);
4058
4059 ering->rx_max_pending = RX_MAX_PENDING;
4060 ering->rx_mini_max_pending = 0;
4061 ering->rx_jumbo_max_pending = 0;
4062 ering->tx_max_pending = TX_MAX_PENDING;
4063
4064 ering->rx_pending = sky2->rx_pending;
4065 ering->rx_mini_pending = 0;
4066 ering->rx_jumbo_pending = 0;
4067 ering->tx_pending = sky2->tx_pending;
4068 }
4069
4070 static int sky2_set_ringparam(struct net_device *dev,
4071 struct ethtool_ringparam *ering)
4072 {
4073 struct sky2_port *sky2 = netdev_priv(dev);
4074
4075 if (ering->rx_pending > RX_MAX_PENDING ||
4076 ering->rx_pending < 8 ||
4077 ering->tx_pending < TX_MIN_PENDING ||
4078 ering->tx_pending > TX_MAX_PENDING)
4079 return -EINVAL;
4080
4081 sky2_detach(dev);
4082
4083 sky2->rx_pending = ering->rx_pending;
4084 sky2->tx_pending = ering->tx_pending;
4085 sky2->tx_ring_size = roundup_pow_of_two(sky2->tx_pending+1);
4086
4087 return sky2_reattach(dev);
4088 }
4089
4090 static int sky2_get_regs_len(struct net_device *dev)
4091 {
4092 return 0x4000;
4093 }
4094
4095 static int sky2_reg_access_ok(struct sky2_hw *hw, unsigned int b)
4096 {
4097 /* This complicated switch statement is to make sure and
4098 * only access regions that are unreserved.
4099 * Some blocks are only valid on dual port cards.
4100 */
4101 switch (b) {
4102 /* second port */
4103 case 5: /* Tx Arbiter 2 */
4104 case 9: /* RX2 */
4105 case 14 ... 15: /* TX2 */
4106 case 17: case 19: /* Ram Buffer 2 */
4107 case 22 ... 23: /* Tx Ram Buffer 2 */
4108 case 25: /* Rx MAC Fifo 1 */
4109 case 27: /* Tx MAC Fifo 2 */
4110 case 31: /* GPHY 2 */
4111 case 40 ... 47: /* Pattern Ram 2 */
4112 case 52: case 54: /* TCP Segmentation 2 */
4113 case 112 ... 116: /* GMAC 2 */
4114 return hw->ports > 1;
4115
4116 case 0: /* Control */
4117 case 2: /* Mac address */
4118 case 4: /* Tx Arbiter 1 */
4119 case 7: /* PCI express reg */
4120 case 8: /* RX1 */
4121 case 12 ... 13: /* TX1 */
4122 case 16: case 18:/* Rx Ram Buffer 1 */
4123 case 20 ... 21: /* Tx Ram Buffer 1 */
4124 case 24: /* Rx MAC Fifo 1 */
4125 case 26: /* Tx MAC Fifo 1 */
4126 case 28 ... 29: /* Descriptor and status unit */
4127 case 30: /* GPHY 1*/
4128 case 32 ... 39: /* Pattern Ram 1 */
4129 case 48: case 50: /* TCP Segmentation 1 */
4130 case 56 ... 60: /* PCI space */
4131 case 80 ... 84: /* GMAC 1 */
4132 return 1;
4133
4134 default:
4135 return 0;
4136 }
4137 }
4138
4139 /*
4140 * Returns copy of control register region
4141 * Note: ethtool_get_regs always provides full size (16k) buffer
4142 */
4143 static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
4144 void *p)
4145 {
4146 const struct sky2_port *sky2 = netdev_priv(dev);
4147 const void __iomem *io = sky2->hw->regs;
4148 unsigned int b;
4149
4150 regs->version = 1;
4151
4152 for (b = 0; b < 128; b++) {
4153 /* skip poisonous diagnostic ram region in block 3 */
4154 if (b == 3)
4155 memcpy_fromio(p + 0x10, io + 0x10, 128 - 0x10);
4156 else if (sky2_reg_access_ok(sky2->hw, b))
4157 memcpy_fromio(p, io, 128);
4158 else
4159 memset(p, 0, 128);
4160
4161 p += 128;
4162 io += 128;
4163 }
4164 }
4165
4166 static int sky2_get_eeprom_len(struct net_device *dev)
4167 {
4168 struct sky2_port *sky2 = netdev_priv(dev);
4169 struct sky2_hw *hw = sky2->hw;
4170 u16 reg2;
4171
4172 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
4173 return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
4174 }
4175
4176 static int sky2_vpd_wait(const struct sky2_hw *hw, int cap, u16 busy)
4177 {
4178 unsigned long start = jiffies;
4179
4180 while ( (sky2_pci_read16(hw, cap + PCI_VPD_ADDR) & PCI_VPD_ADDR_F) == busy) {
4181 /* Can take up to 10.6 ms for write */
4182 if (time_after(jiffies, start + HZ/4)) {
4183 dev_err(&hw->pdev->dev, "VPD cycle timed out\n");
4184 return -ETIMEDOUT;
4185 }
4186 mdelay(1);
4187 }
4188
4189 return 0;
4190 }
4191
4192 static int sky2_vpd_read(struct sky2_hw *hw, int cap, void *data,
4193 u16 offset, size_t length)
4194 {
4195 int rc = 0;
4196
4197 while (length > 0) {
4198 u32 val;
4199
4200 sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset);
4201 rc = sky2_vpd_wait(hw, cap, 0);
4202 if (rc)
4203 break;
4204
4205 val = sky2_pci_read32(hw, cap + PCI_VPD_DATA);
4206
4207 memcpy(data, &val, min(sizeof(val), length));
4208 offset += sizeof(u32);
4209 data += sizeof(u32);
4210 length -= sizeof(u32);
4211 }
4212
4213 return rc;
4214 }
4215
4216 static int sky2_vpd_write(struct sky2_hw *hw, int cap, const void *data,
4217 u16 offset, unsigned int length)
4218 {
4219 unsigned int i;
4220 int rc = 0;
4221
4222 for (i = 0; i < length; i += sizeof(u32)) {
4223 u32 val = *(u32 *)(data + i);
4224
4225 sky2_pci_write32(hw, cap + PCI_VPD_DATA, val);
4226 sky2_pci_write32(hw, cap + PCI_VPD_ADDR, offset | PCI_VPD_ADDR_F);
4227
4228 rc = sky2_vpd_wait(hw, cap, PCI_VPD_ADDR_F);
4229 if (rc)
4230 break;
4231 }
4232 return rc;
4233 }
4234
4235 static int sky2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
4236 u8 *data)
4237 {
4238 struct sky2_port *sky2 = netdev_priv(dev);
4239 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
4240
4241 if (!cap)
4242 return -EINVAL;
4243
4244 eeprom->magic = SKY2_EEPROM_MAGIC;
4245
4246 return sky2_vpd_read(sky2->hw, cap, data, eeprom->offset, eeprom->len);
4247 }
4248
4249 static int sky2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
4250 u8 *data)
4251 {
4252 struct sky2_port *sky2 = netdev_priv(dev);
4253 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
4254
4255 if (!cap)
4256 return -EINVAL;
4257
4258 if (eeprom->magic != SKY2_EEPROM_MAGIC)
4259 return -EINVAL;
4260
4261 /* Partial writes not supported */
4262 if ((eeprom->offset & 3) || (eeprom->len & 3))
4263 return -EINVAL;
4264
4265 return sky2_vpd_write(sky2->hw, cap, data, eeprom->offset, eeprom->len);
4266 }
4267
4268 static u32 sky2_fix_features(struct net_device *dev, u32 features)
4269 {
4270 const struct sky2_port *sky2 = netdev_priv(dev);
4271 const struct sky2_hw *hw = sky2->hw;
4272
4273 /* In order to do Jumbo packets on these chips, need to turn off the
4274 * transmit store/forward. Therefore checksum offload won't work.
4275 */
4276 if (dev->mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U) {
4277 netdev_info(dev, "checksum offload not possible with jumbo frames\n");
4278 features &= ~(NETIF_F_TSO|NETIF_F_SG|NETIF_F_ALL_CSUM);
4279 }
4280
4281 /* Some hardware requires receive checksum for RSS to work. */
4282 if ( (features & NETIF_F_RXHASH) &&
4283 !(features & NETIF_F_RXCSUM) &&
4284 (sky2->hw->flags & SKY2_HW_RSS_CHKSUM)) {
4285 netdev_info(dev, "receive hashing forces receive checksum\n");
4286 features |= NETIF_F_RXCSUM;
4287 }
4288
4289 return features;
4290 }
4291
4292 static int sky2_set_features(struct net_device *dev, u32 features)
4293 {
4294 struct sky2_port *sky2 = netdev_priv(dev);
4295 u32 changed = dev->features ^ features;
4296
4297 if (changed & NETIF_F_RXCSUM) {
4298 u32 on = features & NETIF_F_RXCSUM;
4299 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
4300 on ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
4301 }
4302
4303 if (changed & NETIF_F_RXHASH)
4304 rx_set_rss(dev, features);
4305
4306 if (changed & (NETIF_F_HW_VLAN_TX|NETIF_F_HW_VLAN_RX))
4307 sky2_vlan_mode(dev, features);
4308
4309 return 0;
4310 }
4311
4312 static const struct ethtool_ops sky2_ethtool_ops = {
4313 .get_settings = sky2_get_settings,
4314 .set_settings = sky2_set_settings,
4315 .get_drvinfo = sky2_get_drvinfo,
4316 .get_wol = sky2_get_wol,
4317 .set_wol = sky2_set_wol,
4318 .get_msglevel = sky2_get_msglevel,
4319 .set_msglevel = sky2_set_msglevel,
4320 .nway_reset = sky2_nway_reset,
4321 .get_regs_len = sky2_get_regs_len,
4322 .get_regs = sky2_get_regs,
4323 .get_link = ethtool_op_get_link,
4324 .get_eeprom_len = sky2_get_eeprom_len,
4325 .get_eeprom = sky2_get_eeprom,
4326 .set_eeprom = sky2_set_eeprom,
4327 .get_strings = sky2_get_strings,
4328 .get_coalesce = sky2_get_coalesce,
4329 .set_coalesce = sky2_set_coalesce,
4330 .get_ringparam = sky2_get_ringparam,
4331 .set_ringparam = sky2_set_ringparam,
4332 .get_pauseparam = sky2_get_pauseparam,
4333 .set_pauseparam = sky2_set_pauseparam,
4334 .set_phys_id = sky2_set_phys_id,
4335 .get_sset_count = sky2_get_sset_count,
4336 .get_ethtool_stats = sky2_get_ethtool_stats,
4337 };
4338
4339 #ifdef CONFIG_SKY2_DEBUG
4340
4341 static struct dentry *sky2_debug;
4342
4343
4344 /*
4345 * Read and parse the first part of Vital Product Data
4346 */
4347 #define VPD_SIZE 128
4348 #define VPD_MAGIC 0x82
4349
4350 static const struct vpd_tag {
4351 char tag[2];
4352 char *label;
4353 } vpd_tags[] = {
4354 { "PN", "Part Number" },
4355 { "EC", "Engineering Level" },
4356 { "MN", "Manufacturer" },
4357 { "SN", "Serial Number" },
4358 { "YA", "Asset Tag" },
4359 { "VL", "First Error Log Message" },
4360 { "VF", "Second Error Log Message" },
4361 { "VB", "Boot Agent ROM Configuration" },
4362 { "VE", "EFI UNDI Configuration" },
4363 };
4364
4365 static void sky2_show_vpd(struct seq_file *seq, struct sky2_hw *hw)
4366 {
4367 size_t vpd_size;
4368 loff_t offs;
4369 u8 len;
4370 unsigned char *buf;
4371 u16 reg2;
4372
4373 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
4374 vpd_size = 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
4375
4376 seq_printf(seq, "%s Product Data\n", pci_name(hw->pdev));
4377 buf = kmalloc(vpd_size, GFP_KERNEL);
4378 if (!buf) {
4379 seq_puts(seq, "no memory!\n");
4380 return;
4381 }
4382
4383 if (pci_read_vpd(hw->pdev, 0, vpd_size, buf) < 0) {
4384 seq_puts(seq, "VPD read failed\n");
4385 goto out;
4386 }
4387
4388 if (buf[0] != VPD_MAGIC) {
4389 seq_printf(seq, "VPD tag mismatch: %#x\n", buf[0]);
4390 goto out;
4391 }
4392 len = buf[1];
4393 if (len == 0 || len > vpd_size - 4) {
4394 seq_printf(seq, "Invalid id length: %d\n", len);
4395 goto out;
4396 }
4397
4398 seq_printf(seq, "%.*s\n", len, buf + 3);
4399 offs = len + 3;
4400
4401 while (offs < vpd_size - 4) {
4402 int i;
4403
4404 if (!memcmp("RW", buf + offs, 2)) /* end marker */
4405 break;
4406 len = buf[offs + 2];
4407 if (offs + len + 3 >= vpd_size)
4408 break;
4409
4410 for (i = 0; i < ARRAY_SIZE(vpd_tags); i++) {
4411 if (!memcmp(vpd_tags[i].tag, buf + offs, 2)) {
4412 seq_printf(seq, " %s: %.*s\n",
4413 vpd_tags[i].label, len, buf + offs + 3);
4414 break;
4415 }
4416 }
4417 offs += len + 3;
4418 }
4419 out:
4420 kfree(buf);
4421 }
4422
4423 static int sky2_debug_show(struct seq_file *seq, void *v)
4424 {
4425 struct net_device *dev = seq->private;
4426 const struct sky2_port *sky2 = netdev_priv(dev);
4427 struct sky2_hw *hw = sky2->hw;
4428 unsigned port = sky2->port;
4429 unsigned idx, last;
4430 int sop;
4431
4432 sky2_show_vpd(seq, hw);
4433
4434 seq_printf(seq, "\nIRQ src=%x mask=%x control=%x\n",
4435 sky2_read32(hw, B0_ISRC),
4436 sky2_read32(hw, B0_IMSK),
4437 sky2_read32(hw, B0_Y2_SP_ICR));
4438
4439 if (!netif_running(dev)) {
4440 seq_printf(seq, "network not running\n");
4441 return 0;
4442 }
4443
4444 napi_disable(&hw->napi);
4445 last = sky2_read16(hw, STAT_PUT_IDX);
4446
4447 seq_printf(seq, "Status ring %u\n", hw->st_size);
4448 if (hw->st_idx == last)
4449 seq_puts(seq, "Status ring (empty)\n");
4450 else {
4451 seq_puts(seq, "Status ring\n");
4452 for (idx = hw->st_idx; idx != last && idx < hw->st_size;
4453 idx = RING_NEXT(idx, hw->st_size)) {
4454 const struct sky2_status_le *le = hw->st_le + idx;
4455 seq_printf(seq, "[%d] %#x %d %#x\n",
4456 idx, le->opcode, le->length, le->status);
4457 }
4458 seq_puts(seq, "\n");
4459 }
4460
4461 seq_printf(seq, "Tx ring pending=%u...%u report=%d done=%d\n",
4462 sky2->tx_cons, sky2->tx_prod,
4463 sky2_read16(hw, port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
4464 sky2_read16(hw, Q_ADDR(txqaddr[port], Q_DONE)));
4465
4466 /* Dump contents of tx ring */
4467 sop = 1;
4468 for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < sky2->tx_ring_size;
4469 idx = RING_NEXT(idx, sky2->tx_ring_size)) {
4470 const struct sky2_tx_le *le = sky2->tx_le + idx;
4471 u32 a = le32_to_cpu(le->addr);
4472
4473 if (sop)
4474 seq_printf(seq, "%u:", idx);
4475 sop = 0;
4476
4477 switch (le->opcode & ~HW_OWNER) {
4478 case OP_ADDR64:
4479 seq_printf(seq, " %#x:", a);
4480 break;
4481 case OP_LRGLEN:
4482 seq_printf(seq, " mtu=%d", a);
4483 break;
4484 case OP_VLAN:
4485 seq_printf(seq, " vlan=%d", be16_to_cpu(le->length));
4486 break;
4487 case OP_TCPLISW:
4488 seq_printf(seq, " csum=%#x", a);
4489 break;
4490 case OP_LARGESEND:
4491 seq_printf(seq, " tso=%#x(%d)", a, le16_to_cpu(le->length));
4492 break;
4493 case OP_PACKET:
4494 seq_printf(seq, " %#x(%d)", a, le16_to_cpu(le->length));
4495 break;
4496 case OP_BUFFER:
4497 seq_printf(seq, " frag=%#x(%d)", a, le16_to_cpu(le->length));
4498 break;
4499 default:
4500 seq_printf(seq, " op=%#x,%#x(%d)", le->opcode,
4501 a, le16_to_cpu(le->length));
4502 }
4503
4504 if (le->ctrl & EOP) {
4505 seq_putc(seq, '\n');
4506 sop = 1;
4507 }
4508 }
4509
4510 seq_printf(seq, "\nRx ring hw get=%d put=%d last=%d\n",
4511 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_GET_IDX)),
4512 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX)),
4513 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_LAST_IDX)));
4514
4515 sky2_read32(hw, B0_Y2_SP_LISR);
4516 napi_enable(&hw->napi);
4517 return 0;
4518 }
4519
4520 static int sky2_debug_open(struct inode *inode, struct file *file)
4521 {
4522 return single_open(file, sky2_debug_show, inode->i_private);
4523 }
4524
4525 static const struct file_operations sky2_debug_fops = {
4526 .owner = THIS_MODULE,
4527 .open = sky2_debug_open,
4528 .read = seq_read,
4529 .llseek = seq_lseek,
4530 .release = single_release,
4531 };
4532
4533 /*
4534 * Use network device events to create/remove/rename
4535 * debugfs file entries
4536 */
4537 static int sky2_device_event(struct notifier_block *unused,
4538 unsigned long event, void *ptr)
4539 {
4540 struct net_device *dev = ptr;
4541 struct sky2_port *sky2 = netdev_priv(dev);
4542
4543 if (dev->netdev_ops->ndo_open != sky2_up || !sky2_debug)
4544 return NOTIFY_DONE;
4545
4546 switch (event) {
4547 case NETDEV_CHANGENAME:
4548 if (sky2->debugfs) {
4549 sky2->debugfs = debugfs_rename(sky2_debug, sky2->debugfs,
4550 sky2_debug, dev->name);
4551 }
4552 break;
4553
4554 case NETDEV_GOING_DOWN:
4555 if (sky2->debugfs) {
4556 netdev_printk(KERN_DEBUG, dev, "remove debugfs\n");
4557 debugfs_remove(sky2->debugfs);
4558 sky2->debugfs = NULL;
4559 }
4560 break;
4561
4562 case NETDEV_UP:
4563 sky2->debugfs = debugfs_create_file(dev->name, S_IRUGO,
4564 sky2_debug, dev,
4565 &sky2_debug_fops);
4566 if (IS_ERR(sky2->debugfs))
4567 sky2->debugfs = NULL;
4568 }
4569
4570 return NOTIFY_DONE;
4571 }
4572
4573 static struct notifier_block sky2_notifier = {
4574 .notifier_call = sky2_device_event,
4575 };
4576
4577
4578 static __init void sky2_debug_init(void)
4579 {
4580 struct dentry *ent;
4581
4582 ent = debugfs_create_dir("sky2", NULL);
4583 if (!ent || IS_ERR(ent))
4584 return;
4585
4586 sky2_debug = ent;
4587 register_netdevice_notifier(&sky2_notifier);
4588 }
4589
4590 static __exit void sky2_debug_cleanup(void)
4591 {
4592 if (sky2_debug) {
4593 unregister_netdevice_notifier(&sky2_notifier);
4594 debugfs_remove(sky2_debug);
4595 sky2_debug = NULL;
4596 }
4597 }
4598
4599 #else
4600 #define sky2_debug_init()
4601 #define sky2_debug_cleanup()
4602 #endif
4603
4604 /* Two copies of network device operations to handle special case of
4605 not allowing netpoll on second port */
4606 static const struct net_device_ops sky2_netdev_ops[2] = {
4607 {
4608 .ndo_open = sky2_up,
4609 .ndo_stop = sky2_down,
4610 .ndo_start_xmit = sky2_xmit_frame,
4611 .ndo_do_ioctl = sky2_ioctl,
4612 .ndo_validate_addr = eth_validate_addr,
4613 .ndo_set_mac_address = sky2_set_mac_address,
4614 .ndo_set_rx_mode = sky2_set_multicast,
4615 .ndo_change_mtu = sky2_change_mtu,
4616 .ndo_fix_features = sky2_fix_features,
4617 .ndo_set_features = sky2_set_features,
4618 .ndo_tx_timeout = sky2_tx_timeout,
4619 .ndo_get_stats64 = sky2_get_stats,
4620 #ifdef CONFIG_NET_POLL_CONTROLLER
4621 .ndo_poll_controller = sky2_netpoll,
4622 #endif
4623 },
4624 {
4625 .ndo_open = sky2_up,
4626 .ndo_stop = sky2_down,
4627 .ndo_start_xmit = sky2_xmit_frame,
4628 .ndo_do_ioctl = sky2_ioctl,
4629 .ndo_validate_addr = eth_validate_addr,
4630 .ndo_set_mac_address = sky2_set_mac_address,
4631 .ndo_set_rx_mode = sky2_set_multicast,
4632 .ndo_change_mtu = sky2_change_mtu,
4633 .ndo_fix_features = sky2_fix_features,
4634 .ndo_set_features = sky2_set_features,
4635 .ndo_tx_timeout = sky2_tx_timeout,
4636 .ndo_get_stats64 = sky2_get_stats,
4637 },
4638 };
4639
4640 /* Initialize network device */
4641 static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
4642 unsigned port,
4643 int highmem, int wol)
4644 {
4645 struct sky2_port *sky2;
4646 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
4647
4648 if (!dev) {
4649 dev_err(&hw->pdev->dev, "etherdev alloc failed\n");
4650 return NULL;
4651 }
4652
4653 SET_NETDEV_DEV(dev, &hw->pdev->dev);
4654 dev->irq = hw->pdev->irq;
4655 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
4656 dev->watchdog_timeo = TX_WATCHDOG;
4657 dev->netdev_ops = &sky2_netdev_ops[port];
4658
4659 sky2 = netdev_priv(dev);
4660 sky2->netdev = dev;
4661 sky2->hw = hw;
4662 sky2->msg_enable = netif_msg_init(debug, default_msg);
4663
4664 /* Auto speed and flow control */
4665 sky2->flags = SKY2_FLAG_AUTO_SPEED | SKY2_FLAG_AUTO_PAUSE;
4666 if (hw->chip_id != CHIP_ID_YUKON_XL)
4667 dev->hw_features |= NETIF_F_RXCSUM;
4668
4669 sky2->flow_mode = FC_BOTH;
4670
4671 sky2->duplex = -1;
4672 sky2->speed = -1;
4673 sky2->advertising = sky2_supported_modes(hw);
4674 sky2->wol = wol;
4675
4676 spin_lock_init(&sky2->phy_lock);
4677
4678 sky2->tx_pending = TX_DEF_PENDING;
4679 sky2->tx_ring_size = roundup_pow_of_two(TX_DEF_PENDING+1);
4680 sky2->rx_pending = RX_DEF_PENDING;
4681
4682 hw->dev[port] = dev;
4683
4684 sky2->port = port;
4685
4686 dev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_TSO;
4687
4688 if (highmem)
4689 dev->features |= NETIF_F_HIGHDMA;
4690
4691 /* Enable receive hashing unless hardware is known broken */
4692 if (!(hw->flags & SKY2_HW_RSS_BROKEN))
4693 dev->hw_features |= NETIF_F_RXHASH;
4694
4695 if (!(hw->flags & SKY2_HW_VLAN_BROKEN)) {
4696 dev->hw_features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
4697 dev->vlan_features |= SKY2_VLAN_OFFLOADS;
4698 }
4699
4700 dev->features |= dev->hw_features;
4701
4702 /* read the mac address */
4703 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
4704 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
4705
4706 return dev;
4707 }
4708
4709 static void __devinit sky2_show_addr(struct net_device *dev)
4710 {
4711 const struct sky2_port *sky2 = netdev_priv(dev);
4712
4713 netif_info(sky2, probe, dev, "addr %pM\n", dev->dev_addr);
4714 }
4715
4716 /* Handle software interrupt used during MSI test */
4717 static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
4718 {
4719 struct sky2_hw *hw = dev_id;
4720 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
4721
4722 if (status == 0)
4723 return IRQ_NONE;
4724
4725 if (status & Y2_IS_IRQ_SW) {
4726 hw->flags |= SKY2_HW_USE_MSI;
4727 wake_up(&hw->msi_wait);
4728 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4729 }
4730 sky2_write32(hw, B0_Y2_SP_ICR, 2);
4731
4732 return IRQ_HANDLED;
4733 }
4734
4735 /* Test interrupt path by forcing a a software IRQ */
4736 static int __devinit sky2_test_msi(struct sky2_hw *hw)
4737 {
4738 struct pci_dev *pdev = hw->pdev;
4739 int err;
4740
4741 init_waitqueue_head(&hw->msi_wait);
4742
4743 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
4744
4745 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
4746 if (err) {
4747 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
4748 return err;
4749 }
4750
4751 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
4752 sky2_read8(hw, B0_CTST);
4753
4754 wait_event_timeout(hw->msi_wait, (hw->flags & SKY2_HW_USE_MSI), HZ/10);
4755
4756 if (!(hw->flags & SKY2_HW_USE_MSI)) {
4757 /* MSI test failed, go back to INTx mode */
4758 dev_info(&pdev->dev, "No interrupt generated using MSI, "
4759 "switching to INTx mode.\n");
4760
4761 err = -EOPNOTSUPP;
4762 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4763 }
4764
4765 sky2_write32(hw, B0_IMSK, 0);
4766 sky2_read32(hw, B0_IMSK);
4767
4768 free_irq(pdev->irq, hw);
4769
4770 return err;
4771 }
4772
4773 /* This driver supports yukon2 chipset only */
4774 static const char *sky2_name(u8 chipid, char *buf, int sz)
4775 {
4776 const char *name[] = {
4777 "XL", /* 0xb3 */
4778 "EC Ultra", /* 0xb4 */
4779 "Extreme", /* 0xb5 */
4780 "EC", /* 0xb6 */
4781 "FE", /* 0xb7 */
4782 "FE+", /* 0xb8 */
4783 "Supreme", /* 0xb9 */
4784 "UL 2", /* 0xba */
4785 "Unknown", /* 0xbb */
4786 "Optima", /* 0xbc */
4787 "Optima Prime", /* 0xbd */
4788 "Optima 2", /* 0xbe */
4789 };
4790
4791 if (chipid >= CHIP_ID_YUKON_XL && chipid <= CHIP_ID_YUKON_OP_2)
4792 strncpy(buf, name[chipid - CHIP_ID_YUKON_XL], sz);
4793 else
4794 snprintf(buf, sz, "(chip %#x)", chipid);
4795 return buf;
4796 }
4797
4798 static int __devinit sky2_probe(struct pci_dev *pdev,
4799 const struct pci_device_id *ent)
4800 {
4801 struct net_device *dev;
4802 struct sky2_hw *hw;
4803 int err, using_dac = 0, wol_default;
4804 u32 reg;
4805 char buf1[16];
4806
4807 err = pci_enable_device(pdev);
4808 if (err) {
4809 dev_err(&pdev->dev, "cannot enable PCI device\n");
4810 goto err_out;
4811 }
4812
4813 /* Get configuration information
4814 * Note: only regular PCI config access once to test for HW issues
4815 * other PCI access through shared memory for speed and to
4816 * avoid MMCONFIG problems.
4817 */
4818 err = pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
4819 if (err) {
4820 dev_err(&pdev->dev, "PCI read config failed\n");
4821 goto err_out;
4822 }
4823
4824 if (~reg == 0) {
4825 dev_err(&pdev->dev, "PCI configuration read error\n");
4826 goto err_out;
4827 }
4828
4829 err = pci_request_regions(pdev, DRV_NAME);
4830 if (err) {
4831 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
4832 goto err_out_disable;
4833 }
4834
4835 pci_set_master(pdev);
4836
4837 if (sizeof(dma_addr_t) > sizeof(u32) &&
4838 !(err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)))) {
4839 using_dac = 1;
4840 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
4841 if (err < 0) {
4842 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
4843 "for consistent allocations\n");
4844 goto err_out_free_regions;
4845 }
4846 } else {
4847 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
4848 if (err) {
4849 dev_err(&pdev->dev, "no usable DMA configuration\n");
4850 goto err_out_free_regions;
4851 }
4852 }
4853
4854
4855 #ifdef __BIG_ENDIAN
4856 /* The sk98lin vendor driver uses hardware byte swapping but
4857 * this driver uses software swapping.
4858 */
4859 reg &= ~PCI_REV_DESC;
4860 err = pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
4861 if (err) {
4862 dev_err(&pdev->dev, "PCI write config failed\n");
4863 goto err_out_free_regions;
4864 }
4865 #endif
4866
4867 wol_default = device_may_wakeup(&pdev->dev) ? WAKE_MAGIC : 0;
4868
4869 err = -ENOMEM;
4870
4871 hw = kzalloc(sizeof(*hw) + strlen(DRV_NAME "@pci:")
4872 + strlen(pci_name(pdev)) + 1, GFP_KERNEL);
4873 if (!hw) {
4874 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
4875 goto err_out_free_regions;
4876 }
4877
4878 hw->pdev = pdev;
4879 sprintf(hw->irq_name, DRV_NAME "@pci:%s", pci_name(pdev));
4880
4881 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
4882 if (!hw->regs) {
4883 dev_err(&pdev->dev, "cannot map device registers\n");
4884 goto err_out_free_hw;
4885 }
4886
4887 err = sky2_init(hw);
4888 if (err)
4889 goto err_out_iounmap;
4890
4891 /* ring for status responses */
4892 hw->st_size = hw->ports * roundup_pow_of_two(3*RX_MAX_PENDING + TX_MAX_PENDING);
4893 hw->st_le = pci_alloc_consistent(pdev, hw->st_size * sizeof(struct sky2_status_le),
4894 &hw->st_dma);
4895 if (!hw->st_le)
4896 goto err_out_reset;
4897
4898 dev_info(&pdev->dev, "Yukon-2 %s chip revision %d\n",
4899 sky2_name(hw->chip_id, buf1, sizeof(buf1)), hw->chip_rev);
4900
4901 sky2_reset(hw);
4902
4903 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
4904 if (!dev) {
4905 err = -ENOMEM;
4906 goto err_out_free_pci;
4907 }
4908
4909 if (!disable_msi && pci_enable_msi(pdev) == 0) {
4910 err = sky2_test_msi(hw);
4911 if (err == -EOPNOTSUPP)
4912 pci_disable_msi(pdev);
4913 else if (err)
4914 goto err_out_free_netdev;
4915 }
4916
4917 err = register_netdev(dev);
4918 if (err) {
4919 dev_err(&pdev->dev, "cannot register net device\n");
4920 goto err_out_free_netdev;
4921 }
4922
4923 netif_carrier_off(dev);
4924
4925 netif_napi_add(dev, &hw->napi, sky2_poll, NAPI_WEIGHT);
4926
4927 err = request_irq(pdev->irq, sky2_intr,
4928 (hw->flags & SKY2_HW_USE_MSI) ? 0 : IRQF_SHARED,
4929 hw->irq_name, hw);
4930 if (err) {
4931 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
4932 goto err_out_unregister;
4933 }
4934 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
4935 napi_enable(&hw->napi);
4936
4937 sky2_show_addr(dev);
4938
4939 if (hw->ports > 1) {
4940 struct net_device *dev1;
4941
4942 err = -ENOMEM;
4943 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
4944 if (dev1 && (err = register_netdev(dev1)) == 0)
4945 sky2_show_addr(dev1);
4946 else {
4947 dev_warn(&pdev->dev,
4948 "register of second port failed (%d)\n", err);
4949 hw->dev[1] = NULL;
4950 hw->ports = 1;
4951 if (dev1)
4952 free_netdev(dev1);
4953 }
4954 }
4955
4956 setup_timer(&hw->watchdog_timer, sky2_watchdog, (unsigned long) hw);
4957 INIT_WORK(&hw->restart_work, sky2_restart);
4958
4959 pci_set_drvdata(pdev, hw);
4960 pdev->d3_delay = 150;
4961
4962 return 0;
4963
4964 err_out_unregister:
4965 if (hw->flags & SKY2_HW_USE_MSI)
4966 pci_disable_msi(pdev);
4967 unregister_netdev(dev);
4968 err_out_free_netdev:
4969 free_netdev(dev);
4970 err_out_free_pci:
4971 pci_free_consistent(pdev, hw->st_size * sizeof(struct sky2_status_le),
4972 hw->st_le, hw->st_dma);
4973 err_out_reset:
4974 sky2_write8(hw, B0_CTST, CS_RST_SET);
4975 err_out_iounmap:
4976 iounmap(hw->regs);
4977 err_out_free_hw:
4978 kfree(hw);
4979 err_out_free_regions:
4980 pci_release_regions(pdev);
4981 err_out_disable:
4982 pci_disable_device(pdev);
4983 err_out:
4984 pci_set_drvdata(pdev, NULL);
4985 return err;
4986 }
4987
4988 static void __devexit sky2_remove(struct pci_dev *pdev)
4989 {
4990 struct sky2_hw *hw = pci_get_drvdata(pdev);
4991 int i;
4992
4993 if (!hw)
4994 return;
4995
4996 del_timer_sync(&hw->watchdog_timer);
4997 cancel_work_sync(&hw->restart_work);
4998
4999 for (i = hw->ports-1; i >= 0; --i)
5000 unregister_netdev(hw->dev[i]);
5001
5002 sky2_write32(hw, B0_IMSK, 0);
5003
5004 sky2_power_aux(hw);
5005
5006 sky2_write8(hw, B0_CTST, CS_RST_SET);
5007 sky2_read8(hw, B0_CTST);
5008
5009 free_irq(pdev->irq, hw);
5010 if (hw->flags & SKY2_HW_USE_MSI)
5011 pci_disable_msi(pdev);
5012 pci_free_consistent(pdev, hw->st_size * sizeof(struct sky2_status_le),
5013 hw->st_le, hw->st_dma);
5014 pci_release_regions(pdev);
5015 pci_disable_device(pdev);
5016
5017 for (i = hw->ports-1; i >= 0; --i)
5018 free_netdev(hw->dev[i]);
5019
5020 iounmap(hw->regs);
5021 kfree(hw);
5022
5023 pci_set_drvdata(pdev, NULL);
5024 }
5025
5026 static int sky2_suspend(struct device *dev)
5027 {
5028 struct pci_dev *pdev = to_pci_dev(dev);
5029 struct sky2_hw *hw = pci_get_drvdata(pdev);
5030 int i;
5031
5032 if (!hw)
5033 return 0;
5034
5035 del_timer_sync(&hw->watchdog_timer);
5036 cancel_work_sync(&hw->restart_work);
5037
5038 rtnl_lock();
5039
5040 sky2_all_down(hw);
5041 for (i = 0; i < hw->ports; i++) {
5042 struct net_device *dev = hw->dev[i];
5043 struct sky2_port *sky2 = netdev_priv(dev);
5044
5045 if (sky2->wol)
5046 sky2_wol_init(sky2);
5047 }
5048
5049 sky2_power_aux(hw);
5050 rtnl_unlock();
5051
5052 return 0;
5053 }
5054
5055 #ifdef CONFIG_PM_SLEEP
5056 static int sky2_resume(struct device *dev)
5057 {
5058 struct pci_dev *pdev = to_pci_dev(dev);
5059 struct sky2_hw *hw = pci_get_drvdata(pdev);
5060 int err;
5061
5062 if (!hw)
5063 return 0;
5064
5065 /* Re-enable all clocks */
5066 err = pci_write_config_dword(pdev, PCI_DEV_REG3, 0);
5067 if (err) {
5068 dev_err(&pdev->dev, "PCI write config failed\n");
5069 goto out;
5070 }
5071
5072 rtnl_lock();
5073 sky2_reset(hw);
5074 sky2_all_up(hw);
5075 rtnl_unlock();
5076
5077 return 0;
5078 out:
5079
5080 dev_err(&pdev->dev, "resume failed (%d)\n", err);
5081 pci_disable_device(pdev);
5082 return err;
5083 }
5084
5085 static SIMPLE_DEV_PM_OPS(sky2_pm_ops, sky2_suspend, sky2_resume);
5086 #define SKY2_PM_OPS (&sky2_pm_ops)
5087
5088 #else
5089
5090 #define SKY2_PM_OPS NULL
5091 #endif
5092
5093 static void sky2_shutdown(struct pci_dev *pdev)
5094 {
5095 sky2_suspend(&pdev->dev);
5096 pci_wake_from_d3(pdev, device_may_wakeup(&pdev->dev));
5097 pci_set_power_state(pdev, PCI_D3hot);
5098 }
5099
5100 static struct pci_driver sky2_driver = {
5101 .name = DRV_NAME,
5102 .id_table = sky2_id_table,
5103 .probe = sky2_probe,
5104 .remove = __devexit_p(sky2_remove),
5105 .shutdown = sky2_shutdown,
5106 .driver.pm = SKY2_PM_OPS,
5107 };
5108
5109 static int __init sky2_init_module(void)
5110 {
5111 pr_info("driver version " DRV_VERSION "\n");
5112
5113 sky2_debug_init();
5114 return pci_register_driver(&sky2_driver);
5115 }
5116
5117 static void __exit sky2_cleanup_module(void)
5118 {
5119 pci_unregister_driver(&sky2_driver);
5120 sky2_debug_cleanup();
5121 }
5122
5123 module_init(sky2_init_module);
5124 module_exit(sky2_cleanup_module);
5125
5126 MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
5127 MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
5128 MODULE_LICENSE("GPL");
5129 MODULE_VERSION(DRV_VERSION);
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree