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drivers/misc/ep93xx_pwm.c: world-writable sysfs files
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / scsi / qla2xxx / qla_def.h
blobccfc8e78be21d3075d8fafa8ba9c1a3334a64baa
1 /*
2 * QLogic Fibre Channel HBA Driver
3 * Copyright (c) 2003-2010 QLogic Corporation
4 *
5 * See LICENSE.qla2xxx for copyright and licensing details.
6 */
7 #ifndef __QLA_DEF_H
8 #define __QLA_DEF_H
9
10 #include <linux/kernel.h>
11 #include <linux/init.h>
12 #include <linux/types.h>
13 #include <linux/module.h>
14 #include <linux/list.h>
15 #include <linux/pci.h>
16 #include <linux/dma-mapping.h>
17 #include <linux/sched.h>
18 #include <linux/slab.h>
19 #include <linux/dmapool.h>
20 #include <linux/mempool.h>
21 #include <linux/spinlock.h>
22 #include <linux/completion.h>
23 #include <linux/interrupt.h>
24 #include <linux/workqueue.h>
25 #include <linux/firmware.h>
26 #include <linux/aer.h>
27 #include <linux/mutex.h>
28
29 #include <scsi/scsi.h>
30 #include <scsi/scsi_host.h>
31 #include <scsi/scsi_device.h>
32 #include <scsi/scsi_cmnd.h>
33 #include <scsi/scsi_transport_fc.h>
34 #include <scsi/scsi_bsg_fc.h>
35
36 #include "qla_bsg.h"
37 #include "qla_nx.h"
38 #define QLA2XXX_DRIVER_NAME "qla2xxx"
39 #define QLA2XXX_APIDEV "ql2xapidev"
40
41 /*
42 * We have MAILBOX_REGISTER_COUNT sized arrays in a few places,
43 * but that's fine as we don't look at the last 24 ones for
44 * ISP2100 HBAs.
45 */
46 #define MAILBOX_REGISTER_COUNT_2100 8
47 #define MAILBOX_REGISTER_COUNT 32
48
49 #define QLA2200A_RISC_ROM_VER 4
50 #define FPM_2300 6
51 #define FPM_2310 7
52
53 #include "qla_settings.h"
54
55 /*
56 * Data bit definitions
57 */
58 #define BIT_0 0x1
59 #define BIT_1 0x2
60 #define BIT_2 0x4
61 #define BIT_3 0x8
62 #define BIT_4 0x10
63 #define BIT_5 0x20
64 #define BIT_6 0x40
65 #define BIT_7 0x80
66 #define BIT_8 0x100
67 #define BIT_9 0x200
68 #define BIT_10 0x400
69 #define BIT_11 0x800
70 #define BIT_12 0x1000
71 #define BIT_13 0x2000
72 #define BIT_14 0x4000
73 #define BIT_15 0x8000
74 #define BIT_16 0x10000
75 #define BIT_17 0x20000
76 #define BIT_18 0x40000
77 #define BIT_19 0x80000
78 #define BIT_20 0x100000
79 #define BIT_21 0x200000
80 #define BIT_22 0x400000
81 #define BIT_23 0x800000
82 #define BIT_24 0x1000000
83 #define BIT_25 0x2000000
84 #define BIT_26 0x4000000
85 #define BIT_27 0x8000000
86 #define BIT_28 0x10000000
87 #define BIT_29 0x20000000
88 #define BIT_30 0x40000000
89 #define BIT_31 0x80000000
90
91 #define LSB(x) ((uint8_t)(x))
92 #define MSB(x) ((uint8_t)((uint16_t)(x) >> 8))
93
94 #define LSW(x) ((uint16_t)(x))
95 #define MSW(x) ((uint16_t)((uint32_t)(x) >> 16))
96
97 #define LSD(x) ((uint32_t)((uint64_t)(x)))
98 #define MSD(x) ((uint32_t)((((uint64_t)(x)) >> 16) >> 16))
99
100 #define MAKE_HANDLE(x, y) ((uint32_t)((((uint32_t)(x)) << 16) | (uint32_t)(y)))
101
102 /*
103 * I/O register
104 */
105
106 #define RD_REG_BYTE(addr) readb(addr)
107 #define RD_REG_WORD(addr) readw(addr)
108 #define RD_REG_DWORD(addr) readl(addr)
109 #define RD_REG_BYTE_RELAXED(addr) readb_relaxed(addr)
110 #define RD_REG_WORD_RELAXED(addr) readw_relaxed(addr)
111 #define RD_REG_DWORD_RELAXED(addr) readl_relaxed(addr)
112 #define WRT_REG_BYTE(addr, data) writeb(data,addr)
113 #define WRT_REG_WORD(addr, data) writew(data,addr)
114 #define WRT_REG_DWORD(addr, data) writel(data,addr)
115
116 /*
117 * The ISP2312 v2 chip cannot access the FLASH/GPIO registers via MMIO in an
118 * 133Mhz slot.
119 */
120 #define RD_REG_WORD_PIO(addr) (inw((unsigned long)addr))
121 #define WRT_REG_WORD_PIO(addr, data) (outw(data,(unsigned long)addr))
122
123 /*
124 * Fibre Channel device definitions.
125 */
126 #define WWN_SIZE 8 /* Size of WWPN, WWN & WWNN */
127 #define MAX_FIBRE_DEVICES 512
128 #define MAX_FIBRE_LUNS 0xFFFF
129 #define MAX_RSCN_COUNT 32
130 #define MAX_HOST_COUNT 16
131
132 /*
133 * Host adapter default definitions.
134 */
135 #define MAX_BUSES 1 /* We only have one bus today */
136 #define MAX_TARGETS_2100 MAX_FIBRE_DEVICES
137 #define MAX_TARGETS_2200 MAX_FIBRE_DEVICES
138 #define MIN_LUNS 8
139 #define MAX_LUNS MAX_FIBRE_LUNS
140 #define MAX_CMDS_PER_LUN 255
141
142 /*
143 * Fibre Channel device definitions.
144 */
145 #define SNS_LAST_LOOP_ID_2100 0xfe
146 #define SNS_LAST_LOOP_ID_2300 0x7ff
147
148 #define LAST_LOCAL_LOOP_ID 0x7d
149 #define SNS_FL_PORT 0x7e
150 #define FABRIC_CONTROLLER 0x7f
151 #define SIMPLE_NAME_SERVER 0x80
152 #define SNS_FIRST_LOOP_ID 0x81
153 #define MANAGEMENT_SERVER 0xfe
154 #define BROADCAST 0xff
155
156 /*
157 * There is no correspondence between an N-PORT id and an AL_PA. Therefore the
158 * valid range of an N-PORT id is 0 through 0x7ef.
159 */
160 #define NPH_LAST_HANDLE 0x7ef
161 #define NPH_MGMT_SERVER 0x7fa /* FFFFFA */
162 #define NPH_SNS 0x7fc /* FFFFFC */
163 #define NPH_FABRIC_CONTROLLER 0x7fd /* FFFFFD */
164 #define NPH_F_PORT 0x7fe /* FFFFFE */
165 #define NPH_IP_BROADCAST 0x7ff /* FFFFFF */
166
167 #define MAX_CMDSZ 16 /* SCSI maximum CDB size. */
168 #include "qla_fw.h"
169
170 /*
171 * Timeout timer counts in seconds
172 */
173 #define PORT_RETRY_TIME 1
174 #define LOOP_DOWN_TIMEOUT 60
175 #define LOOP_DOWN_TIME 255 /* 240 */
176 #define LOOP_DOWN_RESET (LOOP_DOWN_TIME - 30)
177
178 /* Maximum outstanding commands in ISP queues (1-65535) */
179 #define MAX_OUTSTANDING_COMMANDS 1024
180
181 /* ISP request and response entry counts (37-65535) */
182 #define REQUEST_ENTRY_CNT_2100 128 /* Number of request entries. */
183 #define REQUEST_ENTRY_CNT_2200 2048 /* Number of request entries. */
184 #define REQUEST_ENTRY_CNT_24XX 2048 /* Number of request entries. */
185 #define RESPONSE_ENTRY_CNT_2100 64 /* Number of response entries.*/
186 #define RESPONSE_ENTRY_CNT_2300 512 /* Number of response entries.*/
187 #define RESPONSE_ENTRY_CNT_MQ 128 /* Number of response entries.*/
188
189 struct req_que;
190
191 /*
192 * (sd.h is not exported, hence local inclusion)
193 * Data Integrity Field tuple.
194 */
195 struct sd_dif_tuple {
196 __be16 guard_tag; /* Checksum */
197 __be16 app_tag; /* Opaque storage */
198 __be32 ref_tag; /* Target LBA or indirect LBA */
199 };
200
201 /*
202 * SCSI Request Block
203 */
204 typedef struct srb {
205 atomic_t ref_count;
206 struct fc_port *fcport;
207 uint32_t handle;
208
209 struct scsi_cmnd *cmd; /* Linux SCSI command pkt */
210
211 uint16_t flags;
212
213 uint32_t request_sense_length;
214 uint8_t *request_sense_ptr;
215
216 void *ctx;
217 } srb_t;
218
219 /*
220 * SRB flag definitions
221 */
222 #define SRB_DMA_VALID BIT_0 /* Command sent to ISP */
223 #define SRB_FCP_CMND_DMA_VALID BIT_12 /* DIF: DSD List valid */
224 #define SRB_CRC_CTX_DMA_VALID BIT_2 /* DIF: context DMA valid */
225 #define SRB_CRC_PROT_DMA_VALID BIT_4 /* DIF: prot DMA valid */
226 #define SRB_CRC_CTX_DSD_VALID BIT_5 /* DIF: dsd_list valid */
227
228 /* To identify if a srb is of T10-CRC type. @sp => srb_t pointer */
229 #define IS_PROT_IO(sp) (sp->flags & SRB_CRC_CTX_DSD_VALID)
230
231 /*
232 * SRB extensions.
233 */
234 struct srb_iocb {
235 union {
236 struct {
237 uint16_t flags;
238 #define SRB_LOGIN_RETRIED BIT_0
239 #define SRB_LOGIN_COND_PLOGI BIT_1
240 #define SRB_LOGIN_SKIP_PRLI BIT_2
241 uint16_t data[2];
242 } logio;
243 struct {
244 /*
245 * Values for flags field below are as
246 * defined in tsk_mgmt_entry struct
247 * for control_flags field in qla_fw.h.
248 */
249 uint32_t flags;
250 uint32_t lun;
251 uint32_t data;
252 } tmf;
253 } u;
254
255 struct timer_list timer;
256
257 void (*done)(srb_t *);
258 void (*free)(srb_t *);
259 void (*timeout)(srb_t *);
260 };
261
262 /* Values for srb_ctx type */
263 #define SRB_LOGIN_CMD 1
264 #define SRB_LOGOUT_CMD 2
265 #define SRB_ELS_CMD_RPT 3
266 #define SRB_ELS_CMD_HST 4
267 #define SRB_CT_CMD 5
268 #define SRB_ADISC_CMD 6
269 #define SRB_TM_CMD 7
270
271 struct srb_ctx {
272 uint16_t type;
273 char *name;
274 union {
275 struct srb_iocb *iocb_cmd;
276 struct fc_bsg_job *bsg_job;
277 } u;
278 };
279
280 struct msg_echo_lb {
281 dma_addr_t send_dma;
282 dma_addr_t rcv_dma;
283 uint16_t req_sg_cnt;
284 uint16_t rsp_sg_cnt;
285 uint16_t options;
286 uint32_t transfer_size;
287 };
288
289 /*
290 * ISP I/O Register Set structure definitions.
291 */
292 struct device_reg_2xxx {
293 uint16_t flash_address; /* Flash BIOS address */
294 uint16_t flash_data; /* Flash BIOS data */
295 uint16_t unused_1[1]; /* Gap */
296 uint16_t ctrl_status; /* Control/Status */
297 #define CSR_FLASH_64K_BANK BIT_3 /* Flash upper 64K bank select */
298 #define CSR_FLASH_ENABLE BIT_1 /* Flash BIOS Read/Write enable */
299 #define CSR_ISP_SOFT_RESET BIT_0 /* ISP soft reset */
300
301 uint16_t ictrl; /* Interrupt control */
302 #define ICR_EN_INT BIT_15 /* ISP enable interrupts. */
303 #define ICR_EN_RISC BIT_3 /* ISP enable RISC interrupts. */
304
305 uint16_t istatus; /* Interrupt status */
306 #define ISR_RISC_INT BIT_3 /* RISC interrupt */
307
308 uint16_t semaphore; /* Semaphore */
309 uint16_t nvram; /* NVRAM register. */
310 #define NVR_DESELECT 0
311 #define NVR_BUSY BIT_15
312 #define NVR_WRT_ENABLE BIT_14 /* Write enable */
313 #define NVR_PR_ENABLE BIT_13 /* Protection register enable */
314 #define NVR_DATA_IN BIT_3
315 #define NVR_DATA_OUT BIT_2
316 #define NVR_SELECT BIT_1
317 #define NVR_CLOCK BIT_0
318
319 #define NVR_WAIT_CNT 20000
320
321 union {
322 struct {
323 uint16_t mailbox0;
324 uint16_t mailbox1;
325 uint16_t mailbox2;
326 uint16_t mailbox3;
327 uint16_t mailbox4;
328 uint16_t mailbox5;
329 uint16_t mailbox6;
330 uint16_t mailbox7;
331 uint16_t unused_2[59]; /* Gap */
332 } __attribute__((packed)) isp2100;
333 struct {
334 /* Request Queue */
335 uint16_t req_q_in; /* In-Pointer */
336 uint16_t req_q_out; /* Out-Pointer */
337 /* Response Queue */
338 uint16_t rsp_q_in; /* In-Pointer */
339 uint16_t rsp_q_out; /* Out-Pointer */
340
341 /* RISC to Host Status */
342 uint32_t host_status;
343 #define HSR_RISC_INT BIT_15 /* RISC interrupt */
344 #define HSR_RISC_PAUSED BIT_8 /* RISC Paused */
345
346 /* Host to Host Semaphore */
347 uint16_t host_semaphore;
348 uint16_t unused_3[17]; /* Gap */
349 uint16_t mailbox0;
350 uint16_t mailbox1;
351 uint16_t mailbox2;
352 uint16_t mailbox3;
353 uint16_t mailbox4;
354 uint16_t mailbox5;
355 uint16_t mailbox6;
356 uint16_t mailbox7;
357 uint16_t mailbox8;
358 uint16_t mailbox9;
359 uint16_t mailbox10;
360 uint16_t mailbox11;
361 uint16_t mailbox12;
362 uint16_t mailbox13;
363 uint16_t mailbox14;
364 uint16_t mailbox15;
365 uint16_t mailbox16;
366 uint16_t mailbox17;
367 uint16_t mailbox18;
368 uint16_t mailbox19;
369 uint16_t mailbox20;
370 uint16_t mailbox21;
371 uint16_t mailbox22;
372 uint16_t mailbox23;
373 uint16_t mailbox24;
374 uint16_t mailbox25;
375 uint16_t mailbox26;
376 uint16_t mailbox27;
377 uint16_t mailbox28;
378 uint16_t mailbox29;
379 uint16_t mailbox30;
380 uint16_t mailbox31;
381 uint16_t fb_cmd;
382 uint16_t unused_4[10]; /* Gap */
383 } __attribute__((packed)) isp2300;
384 } u;
385
386 uint16_t fpm_diag_config;
387 uint16_t unused_5[0x4]; /* Gap */
388 uint16_t risc_hw;
389 uint16_t unused_5_1; /* Gap */
390 uint16_t pcr; /* Processor Control Register. */
391 uint16_t unused_6[0x5]; /* Gap */
392 uint16_t mctr; /* Memory Configuration and Timing. */
393 uint16_t unused_7[0x3]; /* Gap */
394 uint16_t fb_cmd_2100; /* Unused on 23XX */
395 uint16_t unused_8[0x3]; /* Gap */
396 uint16_t hccr; /* Host command & control register. */
397 #define HCCR_HOST_INT BIT_7 /* Host interrupt bit */
398 #define HCCR_RISC_PAUSE BIT_5 /* Pause mode bit */
399 /* HCCR commands */
400 #define HCCR_RESET_RISC 0x1000 /* Reset RISC */
401 #define HCCR_PAUSE_RISC 0x2000 /* Pause RISC */
402 #define HCCR_RELEASE_RISC 0x3000 /* Release RISC from reset. */
403 #define HCCR_SET_HOST_INT 0x5000 /* Set host interrupt */
404 #define HCCR_CLR_HOST_INT 0x6000 /* Clear HOST interrupt */
405 #define HCCR_CLR_RISC_INT 0x7000 /* Clear RISC interrupt */
406 #define HCCR_DISABLE_PARITY_PAUSE 0x4001 /* Disable parity error RISC pause. */
407 #define HCCR_ENABLE_PARITY 0xA000 /* Enable PARITY interrupt */
408
409 uint16_t unused_9[5]; /* Gap */
410 uint16_t gpiod; /* GPIO Data register. */
411 uint16_t gpioe; /* GPIO Enable register. */
412 #define GPIO_LED_MASK 0x00C0
413 #define GPIO_LED_GREEN_OFF_AMBER_OFF 0x0000
414 #define GPIO_LED_GREEN_ON_AMBER_OFF 0x0040
415 #define GPIO_LED_GREEN_OFF_AMBER_ON 0x0080
416 #define GPIO_LED_GREEN_ON_AMBER_ON 0x00C0
417 #define GPIO_LED_ALL_OFF 0x0000
418 #define GPIO_LED_RED_ON_OTHER_OFF 0x0001 /* isp2322 */
419 #define GPIO_LED_RGA_ON 0x00C1 /* isp2322: red green amber */
420
421 union {
422 struct {
423 uint16_t unused_10[8]; /* Gap */
424 uint16_t mailbox8;
425 uint16_t mailbox9;
426 uint16_t mailbox10;
427 uint16_t mailbox11;
428 uint16_t mailbox12;
429 uint16_t mailbox13;
430 uint16_t mailbox14;
431 uint16_t mailbox15;
432 uint16_t mailbox16;
433 uint16_t mailbox17;
434 uint16_t mailbox18;
435 uint16_t mailbox19;
436 uint16_t mailbox20;
437 uint16_t mailbox21;
438 uint16_t mailbox22;
439 uint16_t mailbox23; /* Also probe reg. */
440 } __attribute__((packed)) isp2200;
441 } u_end;
442 };
443
444 struct device_reg_25xxmq {
445 uint32_t req_q_in;
446 uint32_t req_q_out;
447 uint32_t rsp_q_in;
448 uint32_t rsp_q_out;
449 };
450
451 typedef union {
452 struct device_reg_2xxx isp;
453 struct device_reg_24xx isp24;
454 struct device_reg_25xxmq isp25mq;
455 struct device_reg_82xx isp82;
456 } device_reg_t;
457
458 #define ISP_REQ_Q_IN(ha, reg) \
459 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
460 &(reg)->u.isp2100.mailbox4 : \
461 &(reg)->u.isp2300.req_q_in)
462 #define ISP_REQ_Q_OUT(ha, reg) \
463 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
464 &(reg)->u.isp2100.mailbox4 : \
465 &(reg)->u.isp2300.req_q_out)
466 #define ISP_RSP_Q_IN(ha, reg) \
467 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
468 &(reg)->u.isp2100.mailbox5 : \
469 &(reg)->u.isp2300.rsp_q_in)
470 #define ISP_RSP_Q_OUT(ha, reg) \
471 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
472 &(reg)->u.isp2100.mailbox5 : \
473 &(reg)->u.isp2300.rsp_q_out)
474
475 #define MAILBOX_REG(ha, reg, num) \
476 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
477 (num < 8 ? \
478 &(reg)->u.isp2100.mailbox0 + (num) : \
479 &(reg)->u_end.isp2200.mailbox8 + (num) - 8) : \
480 &(reg)->u.isp2300.mailbox0 + (num))
481 #define RD_MAILBOX_REG(ha, reg, num) \
482 RD_REG_WORD(MAILBOX_REG(ha, reg, num))
483 #define WRT_MAILBOX_REG(ha, reg, num, data) \
484 WRT_REG_WORD(MAILBOX_REG(ha, reg, num), data)
485
486 #define FB_CMD_REG(ha, reg) \
487 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
488 &(reg)->fb_cmd_2100 : \
489 &(reg)->u.isp2300.fb_cmd)
490 #define RD_FB_CMD_REG(ha, reg) \
491 RD_REG_WORD(FB_CMD_REG(ha, reg))
492 #define WRT_FB_CMD_REG(ha, reg, data) \
493 WRT_REG_WORD(FB_CMD_REG(ha, reg), data)
494
495 typedef struct {
496 uint32_t out_mb; /* outbound from driver */
497 uint32_t in_mb; /* Incoming from RISC */
498 uint16_t mb[MAILBOX_REGISTER_COUNT];
499 long buf_size;
500 void *bufp;
501 uint32_t tov;
502 uint8_t flags;
503 #define MBX_DMA_IN BIT_0
504 #define MBX_DMA_OUT BIT_1
505 #define IOCTL_CMD BIT_2
506 } mbx_cmd_t;
507
508 #define MBX_TOV_SECONDS 30
509
510 /*
511 * ISP product identification definitions in mailboxes after reset.
512 */
513 #define PROD_ID_1 0x4953
514 #define PROD_ID_2 0x0000
515 #define PROD_ID_2a 0x5020
516 #define PROD_ID_3 0x2020
517
518 /*
519 * ISP mailbox Self-Test status codes
520 */
521 #define MBS_FRM_ALIVE 0 /* Firmware Alive. */
522 #define MBS_CHKSUM_ERR 1 /* Checksum Error. */
523 #define MBS_BUSY 4 /* Busy. */
524
525 /*
526 * ISP mailbox command complete status codes
527 */
528 #define MBS_COMMAND_COMPLETE 0x4000
529 #define MBS_INVALID_COMMAND 0x4001
530 #define MBS_HOST_INTERFACE_ERROR 0x4002
531 #define MBS_TEST_FAILED 0x4003
532 #define MBS_COMMAND_ERROR 0x4005
533 #define MBS_COMMAND_PARAMETER_ERROR 0x4006
534 #define MBS_PORT_ID_USED 0x4007
535 #define MBS_LOOP_ID_USED 0x4008
536 #define MBS_ALL_IDS_IN_USE 0x4009
537 #define MBS_NOT_LOGGED_IN 0x400A
538 #define MBS_LINK_DOWN_ERROR 0x400B
539 #define MBS_DIAG_ECHO_TEST_ERROR 0x400C
540
541 /*
542 * ISP mailbox asynchronous event status codes
543 */
544 #define MBA_ASYNC_EVENT 0x8000 /* Asynchronous event. */
545 #define MBA_RESET 0x8001 /* Reset Detected. */
546 #define MBA_SYSTEM_ERR 0x8002 /* System Error. */
547 #define MBA_REQ_TRANSFER_ERR 0x8003 /* Request Transfer Error. */
548 #define MBA_RSP_TRANSFER_ERR 0x8004 /* Response Transfer Error. */
549 #define MBA_WAKEUP_THRES 0x8005 /* Request Queue Wake-up. */
550 #define MBA_LIP_OCCURRED 0x8010 /* Loop Initialization Procedure */
551 /* occurred. */
552 #define MBA_LOOP_UP 0x8011 /* FC Loop UP. */
553 #define MBA_LOOP_DOWN 0x8012 /* FC Loop Down. */
554 #define MBA_LIP_RESET 0x8013 /* LIP reset occurred. */
555 #define MBA_PORT_UPDATE 0x8014 /* Port Database update. */
556 #define MBA_RSCN_UPDATE 0x8015 /* Register State Chg Notification. */
557 #define MBA_LIP_F8 0x8016 /* Received a LIP F8. */
558 #define MBA_LOOP_INIT_ERR 0x8017 /* Loop Initialization Error. */
559 #define MBA_FABRIC_AUTH_REQ 0x801b /* Fabric Authentication Required. */
560 #define MBA_SCSI_COMPLETION 0x8020 /* SCSI Command Complete. */
561 #define MBA_CTIO_COMPLETION 0x8021 /* CTIO Complete. */
562 #define MBA_IP_COMPLETION 0x8022 /* IP Transmit Command Complete. */
563 #define MBA_IP_RECEIVE 0x8023 /* IP Received. */
564 #define MBA_IP_BROADCAST 0x8024 /* IP Broadcast Received. */
565 #define MBA_IP_LOW_WATER_MARK 0x8025 /* IP Low Water Mark reached. */
566 #define MBA_IP_RCV_BUFFER_EMPTY 0x8026 /* IP receive buffer queue empty. */
567 #define MBA_IP_HDR_DATA_SPLIT 0x8027 /* IP header/data splitting feature */
568 /* used. */
569 #define MBA_TRACE_NOTIFICATION 0x8028 /* Trace/Diagnostic notification. */
570 #define MBA_POINT_TO_POINT 0x8030 /* Point to point mode. */
571 #define MBA_CMPLT_1_16BIT 0x8031 /* Completion 1 16bit IOSB. */
572 #define MBA_CMPLT_2_16BIT 0x8032 /* Completion 2 16bit IOSB. */
573 #define MBA_CMPLT_3_16BIT 0x8033 /* Completion 3 16bit IOSB. */
574 #define MBA_CMPLT_4_16BIT 0x8034 /* Completion 4 16bit IOSB. */
575 #define MBA_CMPLT_5_16BIT 0x8035 /* Completion 5 16bit IOSB. */
576 #define MBA_CHG_IN_CONNECTION 0x8036 /* Change in connection mode. */
577 #define MBA_RIO_RESPONSE 0x8040 /* RIO response queue update. */
578 #define MBA_ZIO_RESPONSE 0x8040 /* ZIO response queue update. */
579 #define MBA_CMPLT_2_32BIT 0x8042 /* Completion 2 32bit IOSB. */
580 #define MBA_BYPASS_NOTIFICATION 0x8043 /* Auto bypass notification. */
581 #define MBA_DISCARD_RND_FRAME 0x8048 /* discard RND frame due to error. */
582 #define MBA_REJECTED_FCP_CMD 0x8049 /* rejected FCP_CMD. */
583
584 /* ISP mailbox loopback echo diagnostic error code */
585 #define MBS_LB_RESET 0x17
586 /*
587 * Firmware options 1, 2, 3.
588 */
589 #define FO1_AE_ON_LIPF8 BIT_0
590 #define FO1_AE_ALL_LIP_RESET BIT_1
591 #define FO1_CTIO_RETRY BIT_3
592 #define FO1_DISABLE_LIP_F7_SW BIT_4
593 #define FO1_DISABLE_100MS_LOS_WAIT BIT_5
594 #define FO1_DISABLE_GPIO6_7 BIT_6 /* LED bits */
595 #define FO1_AE_ON_LOOP_INIT_ERR BIT_7
596 #define FO1_SET_EMPHASIS_SWING BIT_8
597 #define FO1_AE_AUTO_BYPASS BIT_9
598 #define FO1_ENABLE_PURE_IOCB BIT_10
599 #define FO1_AE_PLOGI_RJT BIT_11
600 #define FO1_ENABLE_ABORT_SEQUENCE BIT_12
601 #define FO1_AE_QUEUE_FULL BIT_13
602
603 #define FO2_ENABLE_ATIO_TYPE_3 BIT_0
604 #define FO2_REV_LOOPBACK BIT_1
605
606 #define FO3_ENABLE_EMERG_IOCB BIT_0
607 #define FO3_AE_RND_ERROR BIT_1
608
609 /* 24XX additional firmware options */
610 #define ADD_FO_COUNT 3
611 #define ADD_FO1_DISABLE_GPIO_LED_CTRL BIT_6 /* LED bits */
612 #define ADD_FO1_ENABLE_PUREX_IOCB BIT_10
613
614 #define ADD_FO2_ENABLE_SEL_CLS2 BIT_5
615
616 #define ADD_FO3_NO_ABT_ON_LINK_DOWN BIT_14
617
618 /*
619 * ISP mailbox commands
620 */
621 #define MBC_LOAD_RAM 1 /* Load RAM. */
622 #define MBC_EXECUTE_FIRMWARE 2 /* Execute firmware. */
623 #define MBC_WRITE_RAM_WORD 4 /* Write RAM word. */
624 #define MBC_READ_RAM_WORD 5 /* Read RAM word. */
625 #define MBC_MAILBOX_REGISTER_TEST 6 /* Wrap incoming mailboxes */
626 #define MBC_VERIFY_CHECKSUM 7 /* Verify checksum. */
627 #define MBC_GET_FIRMWARE_VERSION 8 /* Get firmware revision. */
628 #define MBC_LOAD_RISC_RAM 9 /* Load RAM command. */
629 #define MBC_DUMP_RISC_RAM 0xa /* Dump RAM command. */
630 #define MBC_LOAD_RISC_RAM_EXTENDED 0xb /* Load RAM extended. */
631 #define MBC_DUMP_RISC_RAM_EXTENDED 0xc /* Dump RAM extended. */
632 #define MBC_WRITE_RAM_WORD_EXTENDED 0xd /* Write RAM word extended */
633 #define MBC_READ_RAM_EXTENDED 0xf /* Read RAM extended. */
634 #define MBC_IOCB_COMMAND 0x12 /* Execute IOCB command. */
635 #define MBC_STOP_FIRMWARE 0x14 /* Stop firmware. */
636 #define MBC_ABORT_COMMAND 0x15 /* Abort IOCB command. */
637 #define MBC_ABORT_DEVICE 0x16 /* Abort device (ID/LUN). */
638 #define MBC_ABORT_TARGET 0x17 /* Abort target (ID). */
639 #define MBC_RESET 0x18 /* Reset. */
640 #define MBC_GET_ADAPTER_LOOP_ID 0x20 /* Get loop id of ISP2200. */
641 #define MBC_GET_RETRY_COUNT 0x22 /* Get f/w retry cnt/delay. */
642 #define MBC_DISABLE_VI 0x24 /* Disable VI operation. */
643 #define MBC_ENABLE_VI 0x25 /* Enable VI operation. */
644 #define MBC_GET_FIRMWARE_OPTION 0x28 /* Get Firmware Options. */
645 #define MBC_SET_FIRMWARE_OPTION 0x38 /* Set Firmware Options. */
646 #define MBC_LOOP_PORT_BYPASS 0x40 /* Loop Port Bypass. */
647 #define MBC_LOOP_PORT_ENABLE 0x41 /* Loop Port Enable. */
648 #define MBC_GET_RESOURCE_COUNTS 0x42 /* Get Resource Counts. */
649 #define MBC_NON_PARTICIPATE 0x43 /* Non-Participating Mode. */
650 #define MBC_DIAGNOSTIC_ECHO 0x44 /* Diagnostic echo. */
651 #define MBC_DIAGNOSTIC_LOOP_BACK 0x45 /* Diagnostic loop back. */
652 #define MBC_ONLINE_SELF_TEST 0x46 /* Online self-test. */
653 #define MBC_ENHANCED_GET_PORT_DATABASE 0x47 /* Get port database + login */
654 #define MBC_RESET_LINK_STATUS 0x52 /* Reset Link Error Status */
655 #define MBC_IOCB_COMMAND_A64 0x54 /* Execute IOCB command (64) */
656 #define MBC_SEND_RNID_ELS 0x57 /* Send RNID ELS request */
657 #define MBC_SET_RNID_PARAMS 0x59 /* Set RNID parameters */
658 #define MBC_GET_RNID_PARAMS 0x5a /* Data Rate */
659 #define MBC_DATA_RATE 0x5d /* Get RNID parameters */
660 #define MBC_INITIALIZE_FIRMWARE 0x60 /* Initialize firmware */
661 #define MBC_INITIATE_LIP 0x62 /* Initiate Loop */
662 /* Initialization Procedure */
663 #define MBC_GET_FC_AL_POSITION_MAP 0x63 /* Get FC_AL Position Map. */
664 #define MBC_GET_PORT_DATABASE 0x64 /* Get Port Database. */
665 #define MBC_CLEAR_ACA 0x65 /* Clear ACA. */
666 #define MBC_TARGET_RESET 0x66 /* Target Reset. */
667 #define MBC_CLEAR_TASK_SET 0x67 /* Clear Task Set. */
668 #define MBC_ABORT_TASK_SET 0x68 /* Abort Task Set. */
669 #define MBC_GET_FIRMWARE_STATE 0x69 /* Get firmware state. */
670 #define MBC_GET_PORT_NAME 0x6a /* Get port name. */
671 #define MBC_GET_LINK_STATUS 0x6b /* Get port link status. */
672 #define MBC_LIP_RESET 0x6c /* LIP reset. */
673 #define MBC_SEND_SNS_COMMAND 0x6e /* Send Simple Name Server */
674 /* commandd. */
675 #define MBC_LOGIN_FABRIC_PORT 0x6f /* Login fabric port. */
676 #define MBC_SEND_CHANGE_REQUEST 0x70 /* Send Change Request. */
677 #define MBC_LOGOUT_FABRIC_PORT 0x71 /* Logout fabric port. */
678 #define MBC_LIP_FULL_LOGIN 0x72 /* Full login LIP. */
679 #define MBC_LOGIN_LOOP_PORT 0x74 /* Login Loop Port. */
680 #define MBC_PORT_NODE_NAME_LIST 0x75 /* Get port/node name list. */
681 #define MBC_INITIALIZE_RECEIVE_QUEUE 0x77 /* Initialize receive queue */
682 #define MBC_UNLOAD_IP 0x79 /* Shutdown IP */
683 #define MBC_GET_ID_LIST 0x7C /* Get Port ID list. */
684 #define MBC_SEND_LFA_COMMAND 0x7D /* Send Loop Fabric Address */
685 #define MBC_LUN_RESET 0x7E /* Send LUN reset */
686
687 /*
688 * ISP24xx mailbox commands
689 */
690 #define MBC_SERDES_PARAMS 0x10 /* Serdes Tx Parameters. */
691 #define MBC_GET_IOCB_STATUS 0x12 /* Get IOCB status command. */
692 #define MBC_PORT_PARAMS 0x1A /* Port iDMA Parameters. */
693 #define MBC_GET_TIMEOUT_PARAMS 0x22 /* Get FW timeouts. */
694 #define MBC_TRACE_CONTROL 0x27 /* Trace control command. */
695 #define MBC_GEN_SYSTEM_ERROR 0x2a /* Generate System Error. */
696 #define MBC_WRITE_SFP 0x30 /* Write SFP Data. */
697 #define MBC_READ_SFP 0x31 /* Read SFP Data. */
698 #define MBC_SET_TIMEOUT_PARAMS 0x32 /* Set FW timeouts. */
699 #define MBC_MID_INITIALIZE_FIRMWARE 0x48 /* MID Initialize firmware. */
700 #define MBC_MID_GET_VP_DATABASE 0x49 /* MID Get VP Database. */
701 #define MBC_MID_GET_VP_ENTRY 0x4a /* MID Get VP Entry. */
702 #define MBC_HOST_MEMORY_COPY 0x53 /* Host Memory Copy. */
703 #define MBC_SEND_RNFT_ELS 0x5e /* Send RNFT ELS request */
704 #define MBC_GET_LINK_PRIV_STATS 0x6d /* Get link & private data. */
705 #define MBC_SET_VENDOR_ID 0x76 /* Set Vendor ID. */
706 #define MBC_SET_PORT_CONFIG 0x122 /* Set port configuration */
707 #define MBC_GET_PORT_CONFIG 0x123 /* Get port configuration */
708
709 /*
710 * ISP81xx mailbox commands
711 */
712 #define MBC_WRITE_MPI_REGISTER 0x01 /* Write MPI Register. */
713
714 /* Firmware return data sizes */
715 #define FCAL_MAP_SIZE 128
716
717 /* Mailbox bit definitions for out_mb and in_mb */
718 #define MBX_31 BIT_31
719 #define MBX_30 BIT_30
720 #define MBX_29 BIT_29
721 #define MBX_28 BIT_28
722 #define MBX_27 BIT_27
723 #define MBX_26 BIT_26
724 #define MBX_25 BIT_25
725 #define MBX_24 BIT_24
726 #define MBX_23 BIT_23
727 #define MBX_22 BIT_22
728 #define MBX_21 BIT_21
729 #define MBX_20 BIT_20
730 #define MBX_19 BIT_19
731 #define MBX_18 BIT_18
732 #define MBX_17 BIT_17
733 #define MBX_16 BIT_16
734 #define MBX_15 BIT_15
735 #define MBX_14 BIT_14
736 #define MBX_13 BIT_13
737 #define MBX_12 BIT_12
738 #define MBX_11 BIT_11
739 #define MBX_10 BIT_10
740 #define MBX_9 BIT_9
741 #define MBX_8 BIT_8
742 #define MBX_7 BIT_7
743 #define MBX_6 BIT_6
744 #define MBX_5 BIT_5
745 #define MBX_4 BIT_4
746 #define MBX_3 BIT_3
747 #define MBX_2 BIT_2
748 #define MBX_1 BIT_1
749 #define MBX_0 BIT_0
750
751 /*
752 * Firmware state codes from get firmware state mailbox command
753 */
754 #define FSTATE_CONFIG_WAIT 0
755 #define FSTATE_WAIT_AL_PA 1
756 #define FSTATE_WAIT_LOGIN 2
757 #define FSTATE_READY 3
758 #define FSTATE_LOSS_OF_SYNC 4
759 #define FSTATE_ERROR 5
760 #define FSTATE_REINIT 6
761 #define FSTATE_NON_PART 7
762
763 #define FSTATE_CONFIG_CORRECT 0
764 #define FSTATE_P2P_RCV_LIP 1
765 #define FSTATE_P2P_CHOOSE_LOOP 2
766 #define FSTATE_P2P_RCV_UNIDEN_LIP 3
767 #define FSTATE_FATAL_ERROR 4
768 #define FSTATE_LOOP_BACK_CONN 5
769
770 /*
771 * Port Database structure definition
772 * Little endian except where noted.
773 */
774 #define PORT_DATABASE_SIZE 128 /* bytes */
775 typedef struct {
776 uint8_t options;
777 uint8_t control;
778 uint8_t master_state;
779 uint8_t slave_state;
780 uint8_t reserved[2];
781 uint8_t hard_address;
782 uint8_t reserved_1;
783 uint8_t port_id[4];
784 uint8_t node_name[WWN_SIZE];
785 uint8_t port_name[WWN_SIZE];
786 uint16_t execution_throttle;
787 uint16_t execution_count;
788 uint8_t reset_count;
789 uint8_t reserved_2;
790 uint16_t resource_allocation;
791 uint16_t current_allocation;
792 uint16_t queue_head;
793 uint16_t queue_tail;
794 uint16_t transmit_execution_list_next;
795 uint16_t transmit_execution_list_previous;
796 uint16_t common_features;
797 uint16_t total_concurrent_sequences;
798 uint16_t RO_by_information_category;
799 uint8_t recipient;
800 uint8_t initiator;
801 uint16_t receive_data_size;
802 uint16_t concurrent_sequences;
803 uint16_t open_sequences_per_exchange;
804 uint16_t lun_abort_flags;
805 uint16_t lun_stop_flags;
806 uint16_t stop_queue_head;
807 uint16_t stop_queue_tail;
808 uint16_t port_retry_timer;
809 uint16_t next_sequence_id;
810 uint16_t frame_count;
811 uint16_t PRLI_payload_length;
812 uint8_t prli_svc_param_word_0[2]; /* Big endian */
813 /* Bits 15-0 of word 0 */
814 uint8_t prli_svc_param_word_3[2]; /* Big endian */
815 /* Bits 15-0 of word 3 */
816 uint16_t loop_id;
817 uint16_t extended_lun_info_list_pointer;
818 uint16_t extended_lun_stop_list_pointer;
819 } port_database_t;
820
821 /*
822 * Port database slave/master states
823 */
824 #define PD_STATE_DISCOVERY 0
825 #define PD_STATE_WAIT_DISCOVERY_ACK 1
826 #define PD_STATE_PORT_LOGIN 2
827 #define PD_STATE_WAIT_PORT_LOGIN_ACK 3
828 #define PD_STATE_PROCESS_LOGIN 4
829 #define PD_STATE_WAIT_PROCESS_LOGIN_ACK 5
830 #define PD_STATE_PORT_LOGGED_IN 6
831 #define PD_STATE_PORT_UNAVAILABLE 7
832 #define PD_STATE_PROCESS_LOGOUT 8
833 #define PD_STATE_WAIT_PROCESS_LOGOUT_ACK 9
834 #define PD_STATE_PORT_LOGOUT 10
835 #define PD_STATE_WAIT_PORT_LOGOUT_ACK 11
836
837
838 #define QLA_ZIO_MODE_6 (BIT_2 | BIT_1)
839 #define QLA_ZIO_DISABLED 0
840 #define QLA_ZIO_DEFAULT_TIMER 2
841
842 /*
843 * ISP Initialization Control Block.
844 * Little endian except where noted.
845 */
846 #define ICB_VERSION 1
847 typedef struct {
848 uint8_t version;
849 uint8_t reserved_1;
850
851 /*
852 * LSB BIT 0 = Enable Hard Loop Id
853 * LSB BIT 1 = Enable Fairness
854 * LSB BIT 2 = Enable Full-Duplex
855 * LSB BIT 3 = Enable Fast Posting
856 * LSB BIT 4 = Enable Target Mode
857 * LSB BIT 5 = Disable Initiator Mode
858 * LSB BIT 6 = Enable ADISC
859 * LSB BIT 7 = Enable Target Inquiry Data
860 *
861 * MSB BIT 0 = Enable PDBC Notify
862 * MSB BIT 1 = Non Participating LIP
863 * MSB BIT 2 = Descending Loop ID Search
864 * MSB BIT 3 = Acquire Loop ID in LIPA
865 * MSB BIT 4 = Stop PortQ on Full Status
866 * MSB BIT 5 = Full Login after LIP
867 * MSB BIT 6 = Node Name Option
868 * MSB BIT 7 = Ext IFWCB enable bit
869 */
870 uint8_t firmware_options[2];
871
872 uint16_t frame_payload_size;
873 uint16_t max_iocb_allocation;
874 uint16_t execution_throttle;
875 uint8_t retry_count;
876 uint8_t retry_delay; /* unused */
877 uint8_t port_name[WWN_SIZE]; /* Big endian. */
878 uint16_t hard_address;
879 uint8_t inquiry_data;
880 uint8_t login_timeout;
881 uint8_t node_name[WWN_SIZE]; /* Big endian. */
882
883 uint16_t request_q_outpointer;
884 uint16_t response_q_inpointer;
885 uint16_t request_q_length;
886 uint16_t response_q_length;
887 uint32_t request_q_address[2];
888 uint32_t response_q_address[2];
889
890 uint16_t lun_enables;
891 uint8_t command_resource_count;
892 uint8_t immediate_notify_resource_count;
893 uint16_t timeout;
894 uint8_t reserved_2[2];
895
896 /*
897 * LSB BIT 0 = Timer Operation mode bit 0
898 * LSB BIT 1 = Timer Operation mode bit 1
899 * LSB BIT 2 = Timer Operation mode bit 2
900 * LSB BIT 3 = Timer Operation mode bit 3
901 * LSB BIT 4 = Init Config Mode bit 0
902 * LSB BIT 5 = Init Config Mode bit 1
903 * LSB BIT 6 = Init Config Mode bit 2
904 * LSB BIT 7 = Enable Non part on LIHA failure
905 *
906 * MSB BIT 0 = Enable class 2
907 * MSB BIT 1 = Enable ACK0
908 * MSB BIT 2 =
909 * MSB BIT 3 =
910 * MSB BIT 4 = FC Tape Enable
911 * MSB BIT 5 = Enable FC Confirm
912 * MSB BIT 6 = Enable command queuing in target mode
913 * MSB BIT 7 = No Logo On Link Down
914 */
915 uint8_t add_firmware_options[2];
916
917 uint8_t response_accumulation_timer;
918 uint8_t interrupt_delay_timer;
919
920 /*
921 * LSB BIT 0 = Enable Read xfr_rdy
922 * LSB BIT 1 = Soft ID only
923 * LSB BIT 2 =
924 * LSB BIT 3 =
925 * LSB BIT 4 = FCP RSP Payload [0]
926 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200
927 * LSB BIT 6 = Enable Out-of-Order frame handling
928 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop
929 *
930 * MSB BIT 0 = Sbus enable - 2300
931 * MSB BIT 1 =
932 * MSB BIT 2 =
933 * MSB BIT 3 =
934 * MSB BIT 4 = LED mode
935 * MSB BIT 5 = enable 50 ohm termination
936 * MSB BIT 6 = Data Rate (2300 only)
937 * MSB BIT 7 = Data Rate (2300 only)
938 */
939 uint8_t special_options[2];
940
941 uint8_t reserved_3[26];
942 } init_cb_t;
943
944 /*
945 * Get Link Status mailbox command return buffer.
946 */
947 #define GLSO_SEND_RPS BIT_0
948 #define GLSO_USE_DID BIT_3
949
950 struct link_statistics {
951 uint32_t link_fail_cnt;
952 uint32_t loss_sync_cnt;
953 uint32_t loss_sig_cnt;
954 uint32_t prim_seq_err_cnt;
955 uint32_t inval_xmit_word_cnt;
956 uint32_t inval_crc_cnt;
957 uint32_t lip_cnt;
958 uint32_t unused1[0x1a];
959 uint32_t tx_frames;
960 uint32_t rx_frames;
961 uint32_t dumped_frames;
962 uint32_t unused2[2];
963 uint32_t nos_rcvd;
964 };
965
966 /*
967 * NVRAM Command values.
968 */
969 #define NV_START_BIT BIT_2
970 #define NV_WRITE_OP (BIT_26+BIT_24)
971 #define NV_READ_OP (BIT_26+BIT_25)
972 #define NV_ERASE_OP (BIT_26+BIT_25+BIT_24)
973 #define NV_MASK_OP (BIT_26+BIT_25+BIT_24)
974 #define NV_DELAY_COUNT 10
975
976 /*
977 * QLogic ISP2100, ISP2200 and ISP2300 NVRAM structure definition.
978 */
979 typedef struct {
980 /*
981 * NVRAM header
982 */
983 uint8_t id[4];
984 uint8_t nvram_version;
985 uint8_t reserved_0;
986
987 /*
988 * NVRAM RISC parameter block
989 */
990 uint8_t parameter_block_version;
991 uint8_t reserved_1;
992
993 /*
994 * LSB BIT 0 = Enable Hard Loop Id
995 * LSB BIT 1 = Enable Fairness
996 * LSB BIT 2 = Enable Full-Duplex
997 * LSB BIT 3 = Enable Fast Posting
998 * LSB BIT 4 = Enable Target Mode
999 * LSB BIT 5 = Disable Initiator Mode
1000 * LSB BIT 6 = Enable ADISC
1001 * LSB BIT 7 = Enable Target Inquiry Data
1002 *
1003 * MSB BIT 0 = Enable PDBC Notify
1004 * MSB BIT 1 = Non Participating LIP
1005 * MSB BIT 2 = Descending Loop ID Search
1006 * MSB BIT 3 = Acquire Loop ID in LIPA
1007 * MSB BIT 4 = Stop PortQ on Full Status
1008 * MSB BIT 5 = Full Login after LIP
1009 * MSB BIT 6 = Node Name Option
1010 * MSB BIT 7 = Ext IFWCB enable bit
1011 */
1012 uint8_t firmware_options[2];
1013
1014 uint16_t frame_payload_size;
1015 uint16_t max_iocb_allocation;
1016 uint16_t execution_throttle;
1017 uint8_t retry_count;
1018 uint8_t retry_delay; /* unused */
1019 uint8_t port_name[WWN_SIZE]; /* Big endian. */
1020 uint16_t hard_address;
1021 uint8_t inquiry_data;
1022 uint8_t login_timeout;
1023 uint8_t node_name[WWN_SIZE]; /* Big endian. */
1024
1025 /*
1026 * LSB BIT 0 = Timer Operation mode bit 0
1027 * LSB BIT 1 = Timer Operation mode bit 1
1028 * LSB BIT 2 = Timer Operation mode bit 2
1029 * LSB BIT 3 = Timer Operation mode bit 3
1030 * LSB BIT 4 = Init Config Mode bit 0
1031 * LSB BIT 5 = Init Config Mode bit 1
1032 * LSB BIT 6 = Init Config Mode bit 2
1033 * LSB BIT 7 = Enable Non part on LIHA failure
1034 *
1035 * MSB BIT 0 = Enable class 2
1036 * MSB BIT 1 = Enable ACK0
1037 * MSB BIT 2 =
1038 * MSB BIT 3 =
1039 * MSB BIT 4 = FC Tape Enable
1040 * MSB BIT 5 = Enable FC Confirm
1041 * MSB BIT 6 = Enable command queuing in target mode
1042 * MSB BIT 7 = No Logo On Link Down
1043 */
1044 uint8_t add_firmware_options[2];
1045
1046 uint8_t response_accumulation_timer;
1047 uint8_t interrupt_delay_timer;
1048
1049 /*
1050 * LSB BIT 0 = Enable Read xfr_rdy
1051 * LSB BIT 1 = Soft ID only
1052 * LSB BIT 2 =
1053 * LSB BIT 3 =
1054 * LSB BIT 4 = FCP RSP Payload [0]
1055 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200
1056 * LSB BIT 6 = Enable Out-of-Order frame handling
1057 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop
1058 *
1059 * MSB BIT 0 = Sbus enable - 2300
1060 * MSB BIT 1 =
1061 * MSB BIT 2 =
1062 * MSB BIT 3 =
1063 * MSB BIT 4 = LED mode
1064 * MSB BIT 5 = enable 50 ohm termination
1065 * MSB BIT 6 = Data Rate (2300 only)
1066 * MSB BIT 7 = Data Rate (2300 only)
1067 */
1068 uint8_t special_options[2];
1069
1070 /* Reserved for expanded RISC parameter block */
1071 uint8_t reserved_2[22];
1072
1073 /*
1074 * LSB BIT 0 = Tx Sensitivity 1G bit 0
1075 * LSB BIT 1 = Tx Sensitivity 1G bit 1
1076 * LSB BIT 2 = Tx Sensitivity 1G bit 2
1077 * LSB BIT 3 = Tx Sensitivity 1G bit 3
1078 * LSB BIT 4 = Rx Sensitivity 1G bit 0
1079 * LSB BIT 5 = Rx Sensitivity 1G bit 1
1080 * LSB BIT 6 = Rx Sensitivity 1G bit 2
1081 * LSB BIT 7 = Rx Sensitivity 1G bit 3
1082 *
1083 * MSB BIT 0 = Tx Sensitivity 2G bit 0
1084 * MSB BIT 1 = Tx Sensitivity 2G bit 1
1085 * MSB BIT 2 = Tx Sensitivity 2G bit 2
1086 * MSB BIT 3 = Tx Sensitivity 2G bit 3
1087 * MSB BIT 4 = Rx Sensitivity 2G bit 0
1088 * MSB BIT 5 = Rx Sensitivity 2G bit 1
1089 * MSB BIT 6 = Rx Sensitivity 2G bit 2
1090 * MSB BIT 7 = Rx Sensitivity 2G bit 3
1091 *
1092 * LSB BIT 0 = Output Swing 1G bit 0
1093 * LSB BIT 1 = Output Swing 1G bit 1
1094 * LSB BIT 2 = Output Swing 1G bit 2
1095 * LSB BIT 3 = Output Emphasis 1G bit 0
1096 * LSB BIT 4 = Output Emphasis 1G bit 1
1097 * LSB BIT 5 = Output Swing 2G bit 0
1098 * LSB BIT 6 = Output Swing 2G bit 1
1099 * LSB BIT 7 = Output Swing 2G bit 2
1100 *
1101 * MSB BIT 0 = Output Emphasis 2G bit 0
1102 * MSB BIT 1 = Output Emphasis 2G bit 1
1103 * MSB BIT 2 = Output Enable
1104 * MSB BIT 3 =
1105 * MSB BIT 4 =
1106 * MSB BIT 5 =
1107 * MSB BIT 6 =
1108 * MSB BIT 7 =
1109 */
1110 uint8_t seriallink_options[4];
1111
1112 /*
1113 * NVRAM host parameter block
1114 *
1115 * LSB BIT 0 = Enable spinup delay
1116 * LSB BIT 1 = Disable BIOS
1117 * LSB BIT 2 = Enable Memory Map BIOS
1118 * LSB BIT 3 = Enable Selectable Boot
1119 * LSB BIT 4 = Disable RISC code load
1120 * LSB BIT 5 = Set cache line size 1
1121 * LSB BIT 6 = PCI Parity Disable
1122 * LSB BIT 7 = Enable extended logging
1123 *
1124 * MSB BIT 0 = Enable 64bit addressing
1125 * MSB BIT 1 = Enable lip reset
1126 * MSB BIT 2 = Enable lip full login
1127 * MSB BIT 3 = Enable target reset
1128 * MSB BIT 4 = Enable database storage
1129 * MSB BIT 5 = Enable cache flush read
1130 * MSB BIT 6 = Enable database load
1131 * MSB BIT 7 = Enable alternate WWN
1132 */
1133 uint8_t host_p[2];
1134
1135 uint8_t boot_node_name[WWN_SIZE];
1136 uint8_t boot_lun_number;
1137 uint8_t reset_delay;
1138 uint8_t port_down_retry_count;
1139 uint8_t boot_id_number;
1140 uint16_t max_luns_per_target;
1141 uint8_t fcode_boot_port_name[WWN_SIZE];
1142 uint8_t alternate_port_name[WWN_SIZE];
1143 uint8_t alternate_node_name[WWN_SIZE];
1144
1145 /*
1146 * BIT 0 = Selective Login
1147 * BIT 1 = Alt-Boot Enable
1148 * BIT 2 =
1149 * BIT 3 = Boot Order List
1150 * BIT 4 =
1151 * BIT 5 = Selective LUN
1152 * BIT 6 =
1153 * BIT 7 = unused
1154 */
1155 uint8_t efi_parameters;
1156
1157 uint8_t link_down_timeout;
1158
1159 uint8_t adapter_id[16];
1160
1161 uint8_t alt1_boot_node_name[WWN_SIZE];
1162 uint16_t alt1_boot_lun_number;
1163 uint8_t alt2_boot_node_name[WWN_SIZE];
1164 uint16_t alt2_boot_lun_number;
1165 uint8_t alt3_boot_node_name[WWN_SIZE];
1166 uint16_t alt3_boot_lun_number;
1167 uint8_t alt4_boot_node_name[WWN_SIZE];
1168 uint16_t alt4_boot_lun_number;
1169 uint8_t alt5_boot_node_name[WWN_SIZE];
1170 uint16_t alt5_boot_lun_number;
1171 uint8_t alt6_boot_node_name[WWN_SIZE];
1172 uint16_t alt6_boot_lun_number;
1173 uint8_t alt7_boot_node_name[WWN_SIZE];
1174 uint16_t alt7_boot_lun_number;
1175
1176 uint8_t reserved_3[2];
1177
1178 /* Offset 200-215 : Model Number */
1179 uint8_t model_number[16];
1180
1181 /* OEM related items */
1182 uint8_t oem_specific[16];
1183
1184 /*
1185 * NVRAM Adapter Features offset 232-239
1186 *
1187 * LSB BIT 0 = External GBIC
1188 * LSB BIT 1 = Risc RAM parity
1189 * LSB BIT 2 = Buffer Plus Module
1190 * LSB BIT 3 = Multi Chip Adapter
1191 * LSB BIT 4 = Internal connector
1192 * LSB BIT 5 =
1193 * LSB BIT 6 =
1194 * LSB BIT 7 =
1195 *
1196 * MSB BIT 0 =
1197 * MSB BIT 1 =
1198 * MSB BIT 2 =
1199 * MSB BIT 3 =
1200 * MSB BIT 4 =
1201 * MSB BIT 5 =
1202 * MSB BIT 6 =
1203 * MSB BIT 7 =
1204 */
1205 uint8_t adapter_features[2];
1206
1207 uint8_t reserved_4[16];
1208
1209 /* Subsystem vendor ID for ISP2200 */
1210 uint16_t subsystem_vendor_id_2200;
1211
1212 /* Subsystem device ID for ISP2200 */
1213 uint16_t subsystem_device_id_2200;
1214
1215 uint8_t reserved_5;
1216 uint8_t checksum;
1217 } nvram_t;
1218
1219 /*
1220 * ISP queue - response queue entry definition.
1221 */
1222 typedef struct {
1223 uint8_t data[60];
1224 uint32_t signature;
1225 #define RESPONSE_PROCESSED 0xDEADDEAD /* Signature */
1226 } response_t;
1227
1228 typedef union {
1229 uint16_t extended;
1230 struct {
1231 uint8_t reserved;
1232 uint8_t standard;
1233 } id;
1234 } target_id_t;
1235
1236 #define SET_TARGET_ID(ha, to, from) \
1237 do { \
1238 if (HAS_EXTENDED_IDS(ha)) \
1239 to.extended = cpu_to_le16(from); \
1240 else \
1241 to.id.standard = (uint8_t)from; \
1242 } while (0)
1243
1244 /*
1245 * ISP queue - command entry structure definition.
1246 */
1247 #define COMMAND_TYPE 0x11 /* Command entry */
1248 typedef struct {
1249 uint8_t entry_type; /* Entry type. */
1250 uint8_t entry_count; /* Entry count. */
1251 uint8_t sys_define; /* System defined. */
1252 uint8_t entry_status; /* Entry Status. */
1253 uint32_t handle; /* System handle. */
1254 target_id_t target; /* SCSI ID */
1255 uint16_t lun; /* SCSI LUN */
1256 uint16_t control_flags; /* Control flags. */
1257 #define CF_WRITE BIT_6
1258 #define CF_READ BIT_5
1259 #define CF_SIMPLE_TAG BIT_3
1260 #define CF_ORDERED_TAG BIT_2
1261 #define CF_HEAD_TAG BIT_1
1262 uint16_t reserved_1;
1263 uint16_t timeout; /* Command timeout. */
1264 uint16_t dseg_count; /* Data segment count. */
1265 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */
1266 uint32_t byte_count; /* Total byte count. */
1267 uint32_t dseg_0_address; /* Data segment 0 address. */
1268 uint32_t dseg_0_length; /* Data segment 0 length. */
1269 uint32_t dseg_1_address; /* Data segment 1 address. */
1270 uint32_t dseg_1_length; /* Data segment 1 length. */
1271 uint32_t dseg_2_address; /* Data segment 2 address. */
1272 uint32_t dseg_2_length; /* Data segment 2 length. */
1273 } cmd_entry_t;
1274
1275 /*
1276 * ISP queue - 64-Bit addressing, command entry structure definition.
1277 */
1278 #define COMMAND_A64_TYPE 0x19 /* Command A64 entry */
1279 typedef struct {
1280 uint8_t entry_type; /* Entry type. */
1281 uint8_t entry_count; /* Entry count. */
1282 uint8_t sys_define; /* System defined. */
1283 uint8_t entry_status; /* Entry Status. */
1284 uint32_t handle; /* System handle. */
1285 target_id_t target; /* SCSI ID */
1286 uint16_t lun; /* SCSI LUN */
1287 uint16_t control_flags; /* Control flags. */
1288 uint16_t reserved_1;
1289 uint16_t timeout; /* Command timeout. */
1290 uint16_t dseg_count; /* Data segment count. */
1291 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */
1292 uint32_t byte_count; /* Total byte count. */
1293 uint32_t dseg_0_address[2]; /* Data segment 0 address. */
1294 uint32_t dseg_0_length; /* Data segment 0 length. */
1295 uint32_t dseg_1_address[2]; /* Data segment 1 address. */
1296 uint32_t dseg_1_length; /* Data segment 1 length. */
1297 } cmd_a64_entry_t, request_t;
1298
1299 /*
1300 * ISP queue - continuation entry structure definition.
1301 */
1302 #define CONTINUE_TYPE 0x02 /* Continuation entry. */
1303 typedef struct {
1304 uint8_t entry_type; /* Entry type. */
1305 uint8_t entry_count; /* Entry count. */
1306 uint8_t sys_define; /* System defined. */
1307 uint8_t entry_status; /* Entry Status. */
1308 uint32_t reserved;
1309 uint32_t dseg_0_address; /* Data segment 0 address. */
1310 uint32_t dseg_0_length; /* Data segment 0 length. */
1311 uint32_t dseg_1_address; /* Data segment 1 address. */
1312 uint32_t dseg_1_length; /* Data segment 1 length. */
1313 uint32_t dseg_2_address; /* Data segment 2 address. */
1314 uint32_t dseg_2_length; /* Data segment 2 length. */
1315 uint32_t dseg_3_address; /* Data segment 3 address. */
1316 uint32_t dseg_3_length; /* Data segment 3 length. */
1317 uint32_t dseg_4_address; /* Data segment 4 address. */
1318 uint32_t dseg_4_length; /* Data segment 4 length. */
1319 uint32_t dseg_5_address; /* Data segment 5 address. */
1320 uint32_t dseg_5_length; /* Data segment 5 length. */
1321 uint32_t dseg_6_address; /* Data segment 6 address. */
1322 uint32_t dseg_6_length; /* Data segment 6 length. */
1323 } cont_entry_t;
1324
1325 /*
1326 * ISP queue - 64-Bit addressing, continuation entry structure definition.
1327 */
1328 #define CONTINUE_A64_TYPE 0x0A /* Continuation A64 entry. */
1329 typedef struct {
1330 uint8_t entry_type; /* Entry type. */
1331 uint8_t entry_count; /* Entry count. */
1332 uint8_t sys_define; /* System defined. */
1333 uint8_t entry_status; /* Entry Status. */
1334 uint32_t dseg_0_address[2]; /* Data segment 0 address. */
1335 uint32_t dseg_0_length; /* Data segment 0 length. */
1336 uint32_t dseg_1_address[2]; /* Data segment 1 address. */
1337 uint32_t dseg_1_length; /* Data segment 1 length. */
1338 uint32_t dseg_2_address [2]; /* Data segment 2 address. */
1339 uint32_t dseg_2_length; /* Data segment 2 length. */
1340 uint32_t dseg_3_address[2]; /* Data segment 3 address. */
1341 uint32_t dseg_3_length; /* Data segment 3 length. */
1342 uint32_t dseg_4_address[2]; /* Data segment 4 address. */
1343 uint32_t dseg_4_length; /* Data segment 4 length. */
1344 } cont_a64_entry_t;
1345
1346 #define PO_MODE_DIF_INSERT 0
1347 #define PO_MODE_DIF_REMOVE BIT_0
1348 #define PO_MODE_DIF_PASS BIT_1
1349 #define PO_MODE_DIF_REPLACE (BIT_0 + BIT_1)
1350 #define PO_ENABLE_DIF_BUNDLING BIT_8
1351 #define PO_ENABLE_INCR_GUARD_SEED BIT_3
1352 #define PO_DISABLE_INCR_REF_TAG BIT_5
1353 #define PO_DISABLE_GUARD_CHECK BIT_4
1354 /*
1355 * ISP queue - 64-Bit addressing, continuation crc entry structure definition.
1356 */
1357 struct crc_context {
1358 uint32_t handle; /* System handle. */
1359 uint32_t ref_tag;
1360 uint16_t app_tag;
1361 uint8_t ref_tag_mask[4]; /* Validation/Replacement Mask*/
1362 uint8_t app_tag_mask[2]; /* Validation/Replacement Mask*/
1363 uint16_t guard_seed; /* Initial Guard Seed */
1364 uint16_t prot_opts; /* Requested Data Protection Mode */
1365 uint16_t blk_size; /* Data size in bytes */
1366 uint16_t runt_blk_guard; /* Guard value for runt block (tape
1367 * only) */
1368 uint32_t byte_count; /* Total byte count/ total data
1369 * transfer count */
1370 union {
1371 struct {
1372 uint32_t reserved_1;
1373 uint16_t reserved_2;
1374 uint16_t reserved_3;
1375 uint32_t reserved_4;
1376 uint32_t data_address[2];
1377 uint32_t data_length;
1378 uint32_t reserved_5[2];
1379 uint32_t reserved_6;
1380 } nobundling;
1381 struct {
1382 uint32_t dif_byte_count; /* Total DIF byte
1383 * count */
1384 uint16_t reserved_1;
1385 uint16_t dseg_count; /* Data segment count */
1386 uint32_t reserved_2;
1387 uint32_t data_address[2];
1388 uint32_t data_length;
1389 uint32_t dif_address[2];
1390 uint32_t dif_length; /* Data segment 0
1391 * length */
1392 } bundling;
1393 } u;
1394
1395 struct fcp_cmnd fcp_cmnd;
1396 dma_addr_t crc_ctx_dma;
1397 /* List of DMA context transfers */
1398 struct list_head dsd_list;
1399
1400 /* This structure should not exceed 512 bytes */
1401 };
1402
1403 #define CRC_CONTEXT_LEN_FW (offsetof(struct crc_context, fcp_cmnd.lun))
1404 #define CRC_CONTEXT_FCPCMND_OFF (offsetof(struct crc_context, fcp_cmnd.lun))
1405
1406 /*
1407 * ISP queue - status entry structure definition.
1408 */
1409 #define STATUS_TYPE 0x03 /* Status entry. */
1410 typedef struct {
1411 uint8_t entry_type; /* Entry type. */
1412 uint8_t entry_count; /* Entry count. */
1413 uint8_t sys_define; /* System defined. */
1414 uint8_t entry_status; /* Entry Status. */
1415 uint32_t handle; /* System handle. */
1416 uint16_t scsi_status; /* SCSI status. */
1417 uint16_t comp_status; /* Completion status. */
1418 uint16_t state_flags; /* State flags. */
1419 uint16_t status_flags; /* Status flags. */
1420 uint16_t rsp_info_len; /* Response Info Length. */
1421 uint16_t req_sense_length; /* Request sense data length. */
1422 uint32_t residual_length; /* Residual transfer length. */
1423 uint8_t rsp_info[8]; /* FCP response information. */
1424 uint8_t req_sense_data[32]; /* Request sense data. */
1425 } sts_entry_t;
1426
1427 /*
1428 * Status entry entry status
1429 */
1430 #define RF_RQ_DMA_ERROR BIT_6 /* Request Queue DMA error. */
1431 #define RF_INV_E_ORDER BIT_5 /* Invalid entry order. */
1432 #define RF_INV_E_COUNT BIT_4 /* Invalid entry count. */
1433 #define RF_INV_E_PARAM BIT_3 /* Invalid entry parameter. */
1434 #define RF_INV_E_TYPE BIT_2 /* Invalid entry type. */
1435 #define RF_BUSY BIT_1 /* Busy */
1436 #define RF_MASK (RF_RQ_DMA_ERROR | RF_INV_E_ORDER | RF_INV_E_COUNT | \
1437 RF_INV_E_PARAM | RF_INV_E_TYPE | RF_BUSY)
1438 #define RF_MASK_24XX (RF_INV_E_ORDER | RF_INV_E_COUNT | RF_INV_E_PARAM | \
1439 RF_INV_E_TYPE)
1440
1441 /*
1442 * Status entry SCSI status bit definitions.
1443 */
1444 #define SS_MASK 0xfff /* Reserved bits BIT_12-BIT_15*/
1445 #define SS_RESIDUAL_UNDER BIT_11
1446 #define SS_RESIDUAL_OVER BIT_10
1447 #define SS_SENSE_LEN_VALID BIT_9
1448 #define SS_RESPONSE_INFO_LEN_VALID BIT_8
1449
1450 #define SS_RESERVE_CONFLICT (BIT_4 | BIT_3)
1451 #define SS_BUSY_CONDITION BIT_3
1452 #define SS_CONDITION_MET BIT_2
1453 #define SS_CHECK_CONDITION BIT_1
1454
1455 /*
1456 * Status entry completion status
1457 */
1458 #define CS_COMPLETE 0x0 /* No errors */
1459 #define CS_INCOMPLETE 0x1 /* Incomplete transfer of cmd. */
1460 #define CS_DMA 0x2 /* A DMA direction error. */
1461 #define CS_TRANSPORT 0x3 /* Transport error. */
1462 #define CS_RESET 0x4 /* SCSI bus reset occurred */
1463 #define CS_ABORTED 0x5 /* System aborted command. */
1464 #define CS_TIMEOUT 0x6 /* Timeout error. */
1465 #define CS_DATA_OVERRUN 0x7 /* Data overrun. */
1466 #define CS_DIF_ERROR 0xC /* DIF error detected */
1467
1468 #define CS_DATA_UNDERRUN 0x15 /* Data Underrun. */
1469 #define CS_QUEUE_FULL 0x1C /* Queue Full. */
1470 #define CS_PORT_UNAVAILABLE 0x28 /* Port unavailable */
1471 /* (selection timeout) */
1472 #define CS_PORT_LOGGED_OUT 0x29 /* Port Logged Out */
1473 #define CS_PORT_CONFIG_CHG 0x2A /* Port Configuration Changed */
1474 #define CS_PORT_BUSY 0x2B /* Port Busy */
1475 #define CS_COMPLETE_CHKCOND 0x30 /* Error? */
1476 #define CS_BAD_PAYLOAD 0x80 /* Driver defined */
1477 #define CS_UNKNOWN 0x81 /* Driver defined */
1478 #define CS_RETRY 0x82 /* Driver defined */
1479 #define CS_LOOP_DOWN_ABORT 0x83 /* Driver defined */
1480
1481 /*
1482 * Status entry status flags
1483 */
1484 #define SF_ABTS_TERMINATED BIT_10
1485 #define SF_LOGOUT_SENT BIT_13
1486
1487 /*
1488 * ISP queue - status continuation entry structure definition.
1489 */
1490 #define STATUS_CONT_TYPE 0x10 /* Status continuation entry. */
1491 typedef struct {
1492 uint8_t entry_type; /* Entry type. */
1493 uint8_t entry_count; /* Entry count. */
1494 uint8_t sys_define; /* System defined. */
1495 uint8_t entry_status; /* Entry Status. */
1496 uint8_t data[60]; /* data */
1497 } sts_cont_entry_t;
1498
1499 /*
1500 * ISP queue - RIO Type 1 status entry (32 bit I/O entry handles)
1501 * structure definition.
1502 */
1503 #define STATUS_TYPE_21 0x21 /* Status entry. */
1504 typedef struct {
1505 uint8_t entry_type; /* Entry type. */
1506 uint8_t entry_count; /* Entry count. */
1507 uint8_t handle_count; /* Handle count. */
1508 uint8_t entry_status; /* Entry Status. */
1509 uint32_t handle[15]; /* System handles. */
1510 } sts21_entry_t;
1511
1512 /*
1513 * ISP queue - RIO Type 2 status entry (16 bit I/O entry handles)
1514 * structure definition.
1515 */
1516 #define STATUS_TYPE_22 0x22 /* Status entry. */
1517 typedef struct {
1518 uint8_t entry_type; /* Entry type. */
1519 uint8_t entry_count; /* Entry count. */
1520 uint8_t handle_count; /* Handle count. */
1521 uint8_t entry_status; /* Entry Status. */
1522 uint16_t handle[30]; /* System handles. */
1523 } sts22_entry_t;
1524
1525 /*
1526 * ISP queue - marker entry structure definition.
1527 */
1528 #define MARKER_TYPE 0x04 /* Marker entry. */
1529 typedef struct {
1530 uint8_t entry_type; /* Entry type. */
1531 uint8_t entry_count; /* Entry count. */
1532 uint8_t handle_count; /* Handle count. */
1533 uint8_t entry_status; /* Entry Status. */
1534 uint32_t sys_define_2; /* System defined. */
1535 target_id_t target; /* SCSI ID */
1536 uint8_t modifier; /* Modifier (7-0). */
1537 #define MK_SYNC_ID_LUN 0 /* Synchronize ID/LUN */
1538 #define MK_SYNC_ID 1 /* Synchronize ID */
1539 #define MK_SYNC_ALL 2 /* Synchronize all ID/LUN */
1540 #define MK_SYNC_LIP 3 /* Synchronize all ID/LUN, */
1541 /* clear port changed, */
1542 /* use sequence number. */
1543 uint8_t reserved_1;
1544 uint16_t sequence_number; /* Sequence number of event */
1545 uint16_t lun; /* SCSI LUN */
1546 uint8_t reserved_2[48];
1547 } mrk_entry_t;
1548
1549 /*
1550 * ISP queue - Management Server entry structure definition.
1551 */
1552 #define MS_IOCB_TYPE 0x29 /* Management Server IOCB entry */
1553 typedef struct {
1554 uint8_t entry_type; /* Entry type. */
1555 uint8_t entry_count; /* Entry count. */
1556 uint8_t handle_count; /* Handle count. */
1557 uint8_t entry_status; /* Entry Status. */
1558 uint32_t handle1; /* System handle. */
1559 target_id_t loop_id;
1560 uint16_t status;
1561 uint16_t control_flags; /* Control flags. */
1562 uint16_t reserved2;
1563 uint16_t timeout;
1564 uint16_t cmd_dsd_count;
1565 uint16_t total_dsd_count;
1566 uint8_t type;
1567 uint8_t r_ctl;
1568 uint16_t rx_id;
1569 uint16_t reserved3;
1570 uint32_t handle2;
1571 uint32_t rsp_bytecount;
1572 uint32_t req_bytecount;
1573 uint32_t dseg_req_address[2]; /* Data segment 0 address. */
1574 uint32_t dseg_req_length; /* Data segment 0 length. */
1575 uint32_t dseg_rsp_address[2]; /* Data segment 1 address. */
1576 uint32_t dseg_rsp_length; /* Data segment 1 length. */
1577 } ms_iocb_entry_t;
1578
1579
1580 /*
1581 * ISP queue - Mailbox Command entry structure definition.
1582 */
1583 #define MBX_IOCB_TYPE 0x39
1584 struct mbx_entry {
1585 uint8_t entry_type;
1586 uint8_t entry_count;
1587 uint8_t sys_define1;
1588 /* Use sys_define1 for source type */
1589 #define SOURCE_SCSI 0x00
1590 #define SOURCE_IP 0x01
1591 #define SOURCE_VI 0x02
1592 #define SOURCE_SCTP 0x03
1593 #define SOURCE_MP 0x04
1594 #define SOURCE_MPIOCTL 0x05
1595 #define SOURCE_ASYNC_IOCB 0x07
1596
1597 uint8_t entry_status;
1598
1599 uint32_t handle;
1600 target_id_t loop_id;
1601
1602 uint16_t status;
1603 uint16_t state_flags;
1604 uint16_t status_flags;
1605
1606 uint32_t sys_define2[2];
1607
1608 uint16_t mb0;
1609 uint16_t mb1;
1610 uint16_t mb2;
1611 uint16_t mb3;
1612 uint16_t mb6;
1613 uint16_t mb7;
1614 uint16_t mb9;
1615 uint16_t mb10;
1616 uint32_t reserved_2[2];
1617 uint8_t node_name[WWN_SIZE];
1618 uint8_t port_name[WWN_SIZE];
1619 };
1620
1621 /*
1622 * ISP request and response queue entry sizes
1623 */
1624 #define RESPONSE_ENTRY_SIZE (sizeof(response_t))
1625 #define REQUEST_ENTRY_SIZE (sizeof(request_t))
1626
1627
1628 /*
1629 * 24 bit port ID type definition.
1630 */
1631 typedef union {
1632 uint32_t b24 : 24;
1633
1634 struct {
1635 #ifdef __BIG_ENDIAN
1636 uint8_t domain;
1637 uint8_t area;
1638 uint8_t al_pa;
1639 #elif defined(__LITTLE_ENDIAN)
1640 uint8_t al_pa;
1641 uint8_t area;
1642 uint8_t domain;
1643 #else
1644 #error "__BIG_ENDIAN or __LITTLE_ENDIAN must be defined!"
1645 #endif
1646 uint8_t rsvd_1;
1647 } b;
1648 } port_id_t;
1649 #define INVALID_PORT_ID 0xFFFFFF
1650
1651 /*
1652 * Switch info gathering structure.
1653 */
1654 typedef struct {
1655 port_id_t d_id;
1656 uint8_t node_name[WWN_SIZE];
1657 uint8_t port_name[WWN_SIZE];
1658 uint8_t fabric_port_name[WWN_SIZE];
1659 uint16_t fp_speed;
1660 uint8_t fc4_type;
1661 } sw_info_t;
1662
1663 /* FCP-4 types */
1664 #define FC4_TYPE_FCP_SCSI 0x08
1665 #define FC4_TYPE_OTHER 0x0
1666 #define FC4_TYPE_UNKNOWN 0xff
1667
1668 /*
1669 * Fibre channel port type.
1670 */
1671 typedef enum {
1672 FCT_UNKNOWN,
1673 FCT_RSCN,
1674 FCT_SWITCH,
1675 FCT_BROADCAST,
1676 FCT_INITIATOR,
1677 FCT_TARGET
1678 } fc_port_type_t;
1679
1680 /*
1681 * Fibre channel port structure.
1682 */
1683 typedef struct fc_port {
1684 struct list_head list;
1685 struct scsi_qla_host *vha;
1686
1687 uint8_t node_name[WWN_SIZE];
1688 uint8_t port_name[WWN_SIZE];
1689 port_id_t d_id;
1690 uint16_t loop_id;
1691 uint16_t old_loop_id;
1692
1693 uint8_t fcp_prio;
1694
1695 uint8_t fabric_port_name[WWN_SIZE];
1696 uint16_t fp_speed;
1697
1698 fc_port_type_t port_type;
1699
1700 atomic_t state;
1701 uint32_t flags;
1702
1703 int login_retry;
1704
1705 struct fc_rport *rport, *drport;
1706 u32 supported_classes;
1707
1708 uint16_t vp_idx;
1709 uint8_t fc4_type;
1710 } fc_port_t;
1711
1712 /*
1713 * Fibre channel port/lun states.
1714 */
1715 #define FCS_UNCONFIGURED 1
1716 #define FCS_DEVICE_DEAD 2
1717 #define FCS_DEVICE_LOST 3
1718 #define FCS_ONLINE 4
1719
1720 /*
1721 * FC port flags.
1722 */
1723 #define FCF_FABRIC_DEVICE BIT_0
1724 #define FCF_LOGIN_NEEDED BIT_1
1725 #define FCF_FCP2_DEVICE BIT_2
1726 #define FCF_ASYNC_SENT BIT_3
1727
1728 /* No loop ID flag. */
1729 #define FC_NO_LOOP_ID 0x1000
1730
1731 /*
1732 * FC-CT interface
1733 *
1734 * NOTE: All structures are big-endian in form.
1735 */
1736
1737 #define CT_REJECT_RESPONSE 0x8001
1738 #define CT_ACCEPT_RESPONSE 0x8002
1739 #define CT_REASON_INVALID_COMMAND_CODE 0x01
1740 #define CT_REASON_CANNOT_PERFORM 0x09
1741 #define CT_REASON_COMMAND_UNSUPPORTED 0x0b
1742 #define CT_EXPL_ALREADY_REGISTERED 0x10
1743
1744 #define NS_N_PORT_TYPE 0x01
1745 #define NS_NL_PORT_TYPE 0x02
1746 #define NS_NX_PORT_TYPE 0x7F
1747
1748 #define GA_NXT_CMD 0x100
1749 #define GA_NXT_REQ_SIZE (16 + 4)
1750 #define GA_NXT_RSP_SIZE (16 + 620)
1751
1752 #define GID_PT_CMD 0x1A1
1753 #define GID_PT_REQ_SIZE (16 + 4)
1754 #define GID_PT_RSP_SIZE (16 + (MAX_FIBRE_DEVICES * 4))
1755
1756 #define GPN_ID_CMD 0x112
1757 #define GPN_ID_REQ_SIZE (16 + 4)
1758 #define GPN_ID_RSP_SIZE (16 + 8)
1759
1760 #define GNN_ID_CMD 0x113
1761 #define GNN_ID_REQ_SIZE (16 + 4)
1762 #define GNN_ID_RSP_SIZE (16 + 8)
1763
1764 #define GFT_ID_CMD 0x117
1765 #define GFT_ID_REQ_SIZE (16 + 4)
1766 #define GFT_ID_RSP_SIZE (16 + 32)
1767
1768 #define RFT_ID_CMD 0x217
1769 #define RFT_ID_REQ_SIZE (16 + 4 + 32)
1770 #define RFT_ID_RSP_SIZE 16
1771
1772 #define RFF_ID_CMD 0x21F
1773 #define RFF_ID_REQ_SIZE (16 + 4 + 2 + 1 + 1)
1774 #define RFF_ID_RSP_SIZE 16
1775
1776 #define RNN_ID_CMD 0x213
1777 #define RNN_ID_REQ_SIZE (16 + 4 + 8)
1778 #define RNN_ID_RSP_SIZE 16
1779
1780 #define RSNN_NN_CMD 0x239
1781 #define RSNN_NN_REQ_SIZE (16 + 8 + 1 + 255)
1782 #define RSNN_NN_RSP_SIZE 16
1783
1784 #define GFPN_ID_CMD 0x11C
1785 #define GFPN_ID_REQ_SIZE (16 + 4)
1786 #define GFPN_ID_RSP_SIZE (16 + 8)
1787
1788 #define GPSC_CMD 0x127
1789 #define GPSC_REQ_SIZE (16 + 8)
1790 #define GPSC_RSP_SIZE (16 + 2 + 2)
1791
1792 #define GFF_ID_CMD 0x011F
1793 #define GFF_ID_REQ_SIZE (16 + 4)
1794 #define GFF_ID_RSP_SIZE (16 + 128)
1795
1796 /*
1797 * HBA attribute types.
1798 */
1799 #define FDMI_HBA_ATTR_COUNT 9
1800 #define FDMI_HBA_NODE_NAME 1
1801 #define FDMI_HBA_MANUFACTURER 2
1802 #define FDMI_HBA_SERIAL_NUMBER 3
1803 #define FDMI_HBA_MODEL 4
1804 #define FDMI_HBA_MODEL_DESCRIPTION 5
1805 #define FDMI_HBA_HARDWARE_VERSION 6
1806 #define FDMI_HBA_DRIVER_VERSION 7
1807 #define FDMI_HBA_OPTION_ROM_VERSION 8
1808 #define FDMI_HBA_FIRMWARE_VERSION 9
1809 #define FDMI_HBA_OS_NAME_AND_VERSION 0xa
1810 #define FDMI_HBA_MAXIMUM_CT_PAYLOAD_LENGTH 0xb
1811
1812 struct ct_fdmi_hba_attr {
1813 uint16_t type;
1814 uint16_t len;
1815 union {
1816 uint8_t node_name[WWN_SIZE];
1817 uint8_t manufacturer[32];
1818 uint8_t serial_num[8];
1819 uint8_t model[16];
1820 uint8_t model_desc[80];
1821 uint8_t hw_version[16];
1822 uint8_t driver_version[32];
1823 uint8_t orom_version[16];
1824 uint8_t fw_version[16];
1825 uint8_t os_version[128];
1826 uint8_t max_ct_len[4];
1827 } a;
1828 };
1829
1830 struct ct_fdmi_hba_attributes {
1831 uint32_t count;
1832 struct ct_fdmi_hba_attr entry[FDMI_HBA_ATTR_COUNT];
1833 };
1834
1835 /*
1836 * Port attribute types.
1837 */
1838 #define FDMI_PORT_ATTR_COUNT 6
1839 #define FDMI_PORT_FC4_TYPES 1
1840 #define FDMI_PORT_SUPPORT_SPEED 2
1841 #define FDMI_PORT_CURRENT_SPEED 3
1842 #define FDMI_PORT_MAX_FRAME_SIZE 4
1843 #define FDMI_PORT_OS_DEVICE_NAME 5
1844 #define FDMI_PORT_HOST_NAME 6
1845
1846 #define FDMI_PORT_SPEED_1GB 0x1
1847 #define FDMI_PORT_SPEED_2GB 0x2
1848 #define FDMI_PORT_SPEED_10GB 0x4
1849 #define FDMI_PORT_SPEED_4GB 0x8
1850 #define FDMI_PORT_SPEED_8GB 0x10
1851 #define FDMI_PORT_SPEED_16GB 0x20
1852 #define FDMI_PORT_SPEED_UNKNOWN 0x8000
1853
1854 struct ct_fdmi_port_attr {
1855 uint16_t type;
1856 uint16_t len;
1857 union {
1858 uint8_t fc4_types[32];
1859 uint32_t sup_speed;
1860 uint32_t cur_speed;
1861 uint32_t max_frame_size;
1862 uint8_t os_dev_name[32];
1863 uint8_t host_name[32];
1864 } a;
1865 };
1866
1867 /*
1868 * Port Attribute Block.
1869 */
1870 struct ct_fdmi_port_attributes {
1871 uint32_t count;
1872 struct ct_fdmi_port_attr entry[FDMI_PORT_ATTR_COUNT];
1873 };
1874
1875 /* FDMI definitions. */
1876 #define GRHL_CMD 0x100
1877 #define GHAT_CMD 0x101
1878 #define GRPL_CMD 0x102
1879 #define GPAT_CMD 0x110
1880
1881 #define RHBA_CMD 0x200
1882 #define RHBA_RSP_SIZE 16
1883
1884 #define RHAT_CMD 0x201
1885 #define RPRT_CMD 0x210
1886
1887 #define RPA_CMD 0x211
1888 #define RPA_RSP_SIZE 16
1889
1890 #define DHBA_CMD 0x300
1891 #define DHBA_REQ_SIZE (16 + 8)
1892 #define DHBA_RSP_SIZE 16
1893
1894 #define DHAT_CMD 0x301
1895 #define DPRT_CMD 0x310
1896 #define DPA_CMD 0x311
1897
1898 /* CT command header -- request/response common fields */
1899 struct ct_cmd_hdr {
1900 uint8_t revision;
1901 uint8_t in_id[3];
1902 uint8_t gs_type;
1903 uint8_t gs_subtype;
1904 uint8_t options;
1905 uint8_t reserved;
1906 };
1907
1908 /* CT command request */
1909 struct ct_sns_req {
1910 struct ct_cmd_hdr header;
1911 uint16_t command;
1912 uint16_t max_rsp_size;
1913 uint8_t fragment_id;
1914 uint8_t reserved[3];
1915
1916 union {
1917 /* GA_NXT, GPN_ID, GNN_ID, GFT_ID, GFPN_ID */
1918 struct {
1919 uint8_t reserved;
1920 uint8_t port_id[3];
1921 } port_id;
1922
1923 struct {
1924 uint8_t port_type;
1925 uint8_t domain;
1926 uint8_t area;
1927 uint8_t reserved;
1928 } gid_pt;
1929
1930 struct {
1931 uint8_t reserved;
1932 uint8_t port_id[3];
1933 uint8_t fc4_types[32];
1934 } rft_id;
1935
1936 struct {
1937 uint8_t reserved;
1938 uint8_t port_id[3];
1939 uint16_t reserved2;
1940 uint8_t fc4_feature;
1941 uint8_t fc4_type;
1942 } rff_id;
1943
1944 struct {
1945 uint8_t reserved;
1946 uint8_t port_id[3];
1947 uint8_t node_name[8];
1948 } rnn_id;
1949
1950 struct {
1951 uint8_t node_name[8];
1952 uint8_t name_len;
1953 uint8_t sym_node_name[255];
1954 } rsnn_nn;
1955
1956 struct {
1957 uint8_t hba_indentifier[8];
1958 } ghat;
1959
1960 struct {
1961 uint8_t hba_identifier[8];
1962 uint32_t entry_count;
1963 uint8_t port_name[8];
1964 struct ct_fdmi_hba_attributes attrs;
1965 } rhba;
1966
1967 struct {
1968 uint8_t hba_identifier[8];
1969 struct ct_fdmi_hba_attributes attrs;
1970 } rhat;
1971
1972 struct {
1973 uint8_t port_name[8];
1974 struct ct_fdmi_port_attributes attrs;
1975 } rpa;
1976
1977 struct {
1978 uint8_t port_name[8];
1979 } dhba;
1980
1981 struct {
1982 uint8_t port_name[8];
1983 } dhat;
1984
1985 struct {
1986 uint8_t port_name[8];
1987 } dprt;
1988
1989 struct {
1990 uint8_t port_name[8];
1991 } dpa;
1992
1993 struct {
1994 uint8_t port_name[8];
1995 } gpsc;
1996
1997 struct {
1998 uint8_t reserved;
1999 uint8_t port_name[3];
2000 } gff_id;
2001 } req;
2002 };
2003
2004 /* CT command response header */
2005 struct ct_rsp_hdr {
2006 struct ct_cmd_hdr header;
2007 uint16_t response;
2008 uint16_t residual;
2009 uint8_t fragment_id;
2010 uint8_t reason_code;
2011 uint8_t explanation_code;
2012 uint8_t vendor_unique;
2013 };
2014
2015 struct ct_sns_gid_pt_data {
2016 uint8_t control_byte;
2017 uint8_t port_id[3];
2018 };
2019
2020 struct ct_sns_rsp {
2021 struct ct_rsp_hdr header;
2022
2023 union {
2024 struct {
2025 uint8_t port_type;
2026 uint8_t port_id[3];
2027 uint8_t port_name[8];
2028 uint8_t sym_port_name_len;
2029 uint8_t sym_port_name[255];
2030 uint8_t node_name[8];
2031 uint8_t sym_node_name_len;
2032 uint8_t sym_node_name[255];
2033 uint8_t init_proc_assoc[8];
2034 uint8_t node_ip_addr[16];
2035 uint8_t class_of_service[4];
2036 uint8_t fc4_types[32];
2037 uint8_t ip_address[16];
2038 uint8_t fabric_port_name[8];
2039 uint8_t reserved;
2040 uint8_t hard_address[3];
2041 } ga_nxt;
2042
2043 struct {
2044 struct ct_sns_gid_pt_data entries[MAX_FIBRE_DEVICES];
2045 } gid_pt;
2046
2047 struct {
2048 uint8_t port_name[8];
2049 } gpn_id;
2050
2051 struct {
2052 uint8_t node_name[8];
2053 } gnn_id;
2054
2055 struct {
2056 uint8_t fc4_types[32];
2057 } gft_id;
2058
2059 struct {
2060 uint32_t entry_count;
2061 uint8_t port_name[8];
2062 struct ct_fdmi_hba_attributes attrs;
2063 } ghat;
2064
2065 struct {
2066 uint8_t port_name[8];
2067 } gfpn_id;
2068
2069 struct {
2070 uint16_t speeds;
2071 uint16_t speed;
2072 } gpsc;
2073
2074 #define GFF_FCP_SCSI_OFFSET 7
2075 struct {
2076 uint8_t fc4_features[128];
2077 } gff_id;
2078 } rsp;
2079 };
2080
2081 struct ct_sns_pkt {
2082 union {
2083 struct ct_sns_req req;
2084 struct ct_sns_rsp rsp;
2085 } p;
2086 };
2087
2088 /*
2089 * SNS command structures -- for 2200 compatability.
2090 */
2091 #define RFT_ID_SNS_SCMD_LEN 22
2092 #define RFT_ID_SNS_CMD_SIZE 60
2093 #define RFT_ID_SNS_DATA_SIZE 16
2094
2095 #define RNN_ID_SNS_SCMD_LEN 10
2096 #define RNN_ID_SNS_CMD_SIZE 36
2097 #define RNN_ID_SNS_DATA_SIZE 16
2098
2099 #define GA_NXT_SNS_SCMD_LEN 6
2100 #define GA_NXT_SNS_CMD_SIZE 28
2101 #define GA_NXT_SNS_DATA_SIZE (620 + 16)
2102
2103 #define GID_PT_SNS_SCMD_LEN 6
2104 #define GID_PT_SNS_CMD_SIZE 28
2105 #define GID_PT_SNS_DATA_SIZE (MAX_FIBRE_DEVICES * 4 + 16)
2106
2107 #define GPN_ID_SNS_SCMD_LEN 6
2108 #define GPN_ID_SNS_CMD_SIZE 28
2109 #define GPN_ID_SNS_DATA_SIZE (8 + 16)
2110
2111 #define GNN_ID_SNS_SCMD_LEN 6
2112 #define GNN_ID_SNS_CMD_SIZE 28
2113 #define GNN_ID_SNS_DATA_SIZE (8 + 16)
2114
2115 struct sns_cmd_pkt {
2116 union {
2117 struct {
2118 uint16_t buffer_length;
2119 uint16_t reserved_1;
2120 uint32_t buffer_address[2];
2121 uint16_t subcommand_length;
2122 uint16_t reserved_2;
2123 uint16_t subcommand;
2124 uint16_t size;
2125 uint32_t reserved_3;
2126 uint8_t param[36];
2127 } cmd;
2128
2129 uint8_t rft_data[RFT_ID_SNS_DATA_SIZE];
2130 uint8_t rnn_data[RNN_ID_SNS_DATA_SIZE];
2131 uint8_t gan_data[GA_NXT_SNS_DATA_SIZE];
2132 uint8_t gid_data[GID_PT_SNS_DATA_SIZE];
2133 uint8_t gpn_data[GPN_ID_SNS_DATA_SIZE];
2134 uint8_t gnn_data[GNN_ID_SNS_DATA_SIZE];
2135 } p;
2136 };
2137
2138 struct fw_blob {
2139 char *name;
2140 uint32_t segs[4];
2141 const struct firmware *fw;
2142 };
2143
2144 /* Return data from MBC_GET_ID_LIST call. */
2145 struct gid_list_info {
2146 uint8_t al_pa;
2147 uint8_t area;
2148 uint8_t domain;
2149 uint8_t loop_id_2100; /* ISP2100/ISP2200 -- 4 bytes. */
2150 uint16_t loop_id; /* ISP23XX -- 6 bytes. */
2151 uint16_t reserved_1; /* ISP24XX -- 8 bytes. */
2152 };
2153 #define GID_LIST_SIZE (sizeof(struct gid_list_info) * MAX_FIBRE_DEVICES)
2154
2155 /* NPIV */
2156 typedef struct vport_info {
2157 uint8_t port_name[WWN_SIZE];
2158 uint8_t node_name[WWN_SIZE];
2159 int vp_id;
2160 uint16_t loop_id;
2161 unsigned long host_no;
2162 uint8_t port_id[3];
2163 int loop_state;
2164 } vport_info_t;
2165
2166 typedef struct vport_params {
2167 uint8_t port_name[WWN_SIZE];
2168 uint8_t node_name[WWN_SIZE];
2169 uint32_t options;
2170 #define VP_OPTS_RETRY_ENABLE BIT_0
2171 #define VP_OPTS_VP_DISABLE BIT_1
2172 } vport_params_t;
2173
2174 /* NPIV - return codes of VP create and modify */
2175 #define VP_RET_CODE_OK 0
2176 #define VP_RET_CODE_FATAL 1
2177 #define VP_RET_CODE_WRONG_ID 2
2178 #define VP_RET_CODE_WWPN 3
2179 #define VP_RET_CODE_RESOURCES 4
2180 #define VP_RET_CODE_NO_MEM 5
2181 #define VP_RET_CODE_NOT_FOUND 6
2182
2183 struct qla_hw_data;
2184 struct rsp_que;
2185 /*
2186 * ISP operations
2187 */
2188 struct isp_operations {
2189
2190 int (*pci_config) (struct scsi_qla_host *);
2191 void (*reset_chip) (struct scsi_qla_host *);
2192 int (*chip_diag) (struct scsi_qla_host *);
2193 void (*config_rings) (struct scsi_qla_host *);
2194 void (*reset_adapter) (struct scsi_qla_host *);
2195 int (*nvram_config) (struct scsi_qla_host *);
2196 void (*update_fw_options) (struct scsi_qla_host *);
2197 int (*load_risc) (struct scsi_qla_host *, uint32_t *);
2198
2199 char * (*pci_info_str) (struct scsi_qla_host *, char *);
2200 char * (*fw_version_str) (struct scsi_qla_host *, char *);
2201
2202 irq_handler_t intr_handler;
2203 void (*enable_intrs) (struct qla_hw_data *);
2204 void (*disable_intrs) (struct qla_hw_data *);
2205
2206 int (*abort_command) (srb_t *);
2207 int (*target_reset) (struct fc_port *, unsigned int, int);
2208 int (*lun_reset) (struct fc_port *, unsigned int, int);
2209 int (*fabric_login) (struct scsi_qla_host *, uint16_t, uint8_t,
2210 uint8_t, uint8_t, uint16_t *, uint8_t);
2211 int (*fabric_logout) (struct scsi_qla_host *, uint16_t, uint8_t,
2212 uint8_t, uint8_t);
2213
2214 uint16_t (*calc_req_entries) (uint16_t);
2215 void (*build_iocbs) (srb_t *, cmd_entry_t *, uint16_t);
2216 void * (*prep_ms_iocb) (struct scsi_qla_host *, uint32_t, uint32_t);
2217 void * (*prep_ms_fdmi_iocb) (struct scsi_qla_host *, uint32_t,
2218 uint32_t);
2219
2220 uint8_t * (*read_nvram) (struct scsi_qla_host *, uint8_t *,
2221 uint32_t, uint32_t);
2222 int (*write_nvram) (struct scsi_qla_host *, uint8_t *, uint32_t,
2223 uint32_t);
2224
2225 void (*fw_dump) (struct scsi_qla_host *, int);
2226
2227 int (*beacon_on) (struct scsi_qla_host *);
2228 int (*beacon_off) (struct scsi_qla_host *);
2229 void (*beacon_blink) (struct scsi_qla_host *);
2230
2231 uint8_t * (*read_optrom) (struct scsi_qla_host *, uint8_t *,
2232 uint32_t, uint32_t);
2233 int (*write_optrom) (struct scsi_qla_host *, uint8_t *, uint32_t,
2234 uint32_t);
2235
2236 int (*get_flash_version) (struct scsi_qla_host *, void *);
2237 int (*start_scsi) (srb_t *);
2238 int (*abort_isp) (struct scsi_qla_host *);
2239 };
2240
2241 /* MSI-X Support *************************************************************/
2242
2243 #define QLA_MSIX_CHIP_REV_24XX 3
2244 #define QLA_MSIX_FW_MODE(m) (((m) & (BIT_7|BIT_8|BIT_9)) >> 7)
2245 #define QLA_MSIX_FW_MODE_1(m) (QLA_MSIX_FW_MODE(m) == 1)
2246
2247 #define QLA_MSIX_DEFAULT 0x00
2248 #define QLA_MSIX_RSP_Q 0x01
2249
2250 #define QLA_MIDX_DEFAULT 0
2251 #define QLA_MIDX_RSP_Q 1
2252 #define QLA_PCI_MSIX_CONTROL 0xa2
2253
2254 struct scsi_qla_host;
2255
2256 struct qla_msix_entry {
2257 int have_irq;
2258 uint32_t vector;
2259 uint16_t entry;
2260 struct rsp_que *rsp;
2261 };
2262
2263 #define WATCH_INTERVAL 1 /* number of seconds */
2264
2265 /* Work events. */
2266 enum qla_work_type {
2267 QLA_EVT_AEN,
2268 QLA_EVT_IDC_ACK,
2269 QLA_EVT_ASYNC_LOGIN,
2270 QLA_EVT_ASYNC_LOGIN_DONE,
2271 QLA_EVT_ASYNC_LOGOUT,
2272 QLA_EVT_ASYNC_LOGOUT_DONE,
2273 QLA_EVT_ASYNC_ADISC,
2274 QLA_EVT_ASYNC_ADISC_DONE,
2275 QLA_EVT_UEVENT,
2276 };
2277
2278
2279 struct qla_work_evt {
2280 struct list_head list;
2281 enum qla_work_type type;
2282 u32 flags;
2283 #define QLA_EVT_FLAG_FREE 0x1
2284
2285 union {
2286 struct {
2287 enum fc_host_event_code code;
2288 u32 data;
2289 } aen;
2290 struct {
2291 #define QLA_IDC_ACK_REGS 7
2292 uint16_t mb[QLA_IDC_ACK_REGS];
2293 } idc_ack;
2294 struct {
2295 struct fc_port *fcport;
2296 #define QLA_LOGIO_LOGIN_RETRIED BIT_0
2297 u16 data[2];
2298 } logio;
2299 struct {
2300 u32 code;
2301 #define QLA_UEVENT_CODE_FW_DUMP 0
2302 } uevent;
2303 } u;
2304 };
2305
2306 struct qla_chip_state_84xx {
2307 struct list_head list;
2308 struct kref kref;
2309
2310 void *bus;
2311 spinlock_t access_lock;
2312 struct mutex fw_update_mutex;
2313 uint32_t fw_update;
2314 uint32_t op_fw_version;
2315 uint32_t op_fw_size;
2316 uint32_t op_fw_seq_size;
2317 uint32_t diag_fw_version;
2318 uint32_t gold_fw_version;
2319 };
2320
2321 struct qla_statistics {
2322 uint32_t total_isp_aborts;
2323 uint64_t input_bytes;
2324 uint64_t output_bytes;
2325 };
2326
2327 /* Multi queue support */
2328 #define MBC_INITIALIZE_MULTIQ 0x1f
2329 #define QLA_QUE_PAGE 0X1000
2330 #define QLA_MQ_SIZE 32
2331 #define QLA_MAX_QUEUES 256
2332 #define ISP_QUE_REG(ha, id) \
2333 ((ha->mqenable) ? \
2334 ((void *)(ha->mqiobase) +\
2335 (QLA_QUE_PAGE * id)) :\
2336 ((void *)(ha->iobase)))
2337 #define QLA_REQ_QUE_ID(tag) \
2338 ((tag < QLA_MAX_QUEUES && tag > 0) ? tag : 0)
2339 #define QLA_DEFAULT_QUE_QOS 5
2340 #define QLA_PRECONFIG_VPORTS 32
2341 #define QLA_MAX_VPORTS_QLA24XX 128
2342 #define QLA_MAX_VPORTS_QLA25XX 256
2343 /* Response queue data structure */
2344 struct rsp_que {
2345 dma_addr_t dma;
2346 response_t *ring;
2347 response_t *ring_ptr;
2348 uint32_t __iomem *rsp_q_in; /* FWI2-capable only. */
2349 uint32_t __iomem *rsp_q_out;
2350 uint16_t ring_index;
2351 uint16_t out_ptr;
2352 uint16_t length;
2353 uint16_t options;
2354 uint16_t rid;
2355 uint16_t id;
2356 uint16_t vp_idx;
2357 struct qla_hw_data *hw;
2358 struct qla_msix_entry *msix;
2359 struct req_que *req;
2360 srb_t *status_srb; /* status continuation entry */
2361 struct work_struct q_work;
2362 };
2363
2364 /* Request queue data structure */
2365 struct req_que {
2366 dma_addr_t dma;
2367 request_t *ring;
2368 request_t *ring_ptr;
2369 uint32_t __iomem *req_q_in; /* FWI2-capable only. */
2370 uint32_t __iomem *req_q_out;
2371 uint16_t ring_index;
2372 uint16_t in_ptr;
2373 uint16_t cnt;
2374 uint16_t length;
2375 uint16_t options;
2376 uint16_t rid;
2377 uint16_t id;
2378 uint16_t qos;
2379 uint16_t vp_idx;
2380 struct rsp_que *rsp;
2381 srb_t *outstanding_cmds[MAX_OUTSTANDING_COMMANDS];
2382 uint32_t current_outstanding_cmd;
2383 int max_q_depth;
2384 };
2385
2386 /* Place holder for FW buffer parameters */
2387 struct qlfc_fw {
2388 void *fw_buf;
2389 dma_addr_t fw_dma;
2390 uint32_t len;
2391 };
2392
2393 /*
2394 * Qlogic host adapter specific data structure.
2395 */
2396 struct qla_hw_data {
2397 struct pci_dev *pdev;
2398 /* SRB cache. */
2399 #define SRB_MIN_REQ 128
2400 mempool_t *srb_mempool;
2401
2402 volatile struct {
2403 uint32_t mbox_int :1;
2404 uint32_t mbox_busy :1;
2405
2406 uint32_t disable_risc_code_load :1;
2407 uint32_t enable_64bit_addressing :1;
2408 uint32_t enable_lip_reset :1;
2409 uint32_t enable_target_reset :1;
2410 uint32_t enable_lip_full_login :1;
2411 uint32_t enable_led_scheme :1;
2412 uint32_t msi_enabled :1;
2413 uint32_t msix_enabled :1;
2414 uint32_t disable_serdes :1;
2415 uint32_t gpsc_supported :1;
2416 uint32_t npiv_supported :1;
2417 uint32_t pci_channel_io_perm_failure :1;
2418 uint32_t fce_enabled :1;
2419 uint32_t fac_supported :1;
2420 uint32_t chip_reset_done :1;
2421 uint32_t port0 :1;
2422 uint32_t running_gold_fw :1;
2423 uint32_t eeh_busy :1;
2424 uint32_t cpu_affinity_enabled :1;
2425 uint32_t disable_msix_handshake :1;
2426 uint32_t fcp_prio_enabled :1;
2427 uint32_t fw_hung :1;
2428 uint32_t quiesce_owner:1;
2429 uint32_t thermal_supported:1;
2430 /* 26 bits */
2431 } flags;
2432
2433 /* This spinlock is used to protect "io transactions", you must
2434 * acquire it before doing any IO to the card, eg with RD_REG*() and
2435 * WRT_REG*() for the duration of your entire commandtransaction.
2436 *
2437 * This spinlock is of lower priority than the io request lock.
2438 */
2439
2440 spinlock_t hardware_lock ____cacheline_aligned;
2441 int bars;
2442 int mem_only;
2443 device_reg_t __iomem *iobase; /* Base I/O address */
2444 resource_size_t pio_address;
2445
2446 #define MIN_IOBASE_LEN 0x100
2447 /* Multi queue data structs */
2448 device_reg_t __iomem *mqiobase;
2449 uint16_t msix_count;
2450 uint8_t mqenable;
2451 struct req_que **req_q_map;
2452 struct rsp_que **rsp_q_map;
2453 unsigned long req_qid_map[(QLA_MAX_QUEUES / 8) / sizeof(unsigned long)];
2454 unsigned long rsp_qid_map[(QLA_MAX_QUEUES / 8) / sizeof(unsigned long)];
2455 uint8_t max_req_queues;
2456 uint8_t max_rsp_queues;
2457 struct qla_npiv_entry *npiv_info;
2458 uint16_t nvram_npiv_size;
2459
2460 uint16_t switch_cap;
2461 #define FLOGI_SEQ_DEL BIT_8
2462 #define FLOGI_MID_SUPPORT BIT_10
2463 #define FLOGI_VSAN_SUPPORT BIT_12
2464 #define FLOGI_SP_SUPPORT BIT_13
2465
2466 uint8_t port_no; /* Physical port of adapter */
2467
2468 /* Timeout timers. */
2469 uint8_t loop_down_abort_time; /* port down timer */
2470 atomic_t loop_down_timer; /* loop down timer */
2471 uint8_t link_down_timeout; /* link down timeout */
2472 uint16_t max_loop_id;
2473
2474 uint16_t fb_rev;
2475 uint16_t min_external_loopid; /* First external loop Id */
2476
2477 #define PORT_SPEED_UNKNOWN 0xFFFF
2478 #define PORT_SPEED_1GB 0x00
2479 #define PORT_SPEED_2GB 0x01
2480 #define PORT_SPEED_4GB 0x03
2481 #define PORT_SPEED_8GB 0x04
2482 #define PORT_SPEED_10GB 0x13
2483 uint16_t link_data_rate; /* F/W operating speed */
2484
2485 uint8_t current_topology;
2486 uint8_t prev_topology;
2487 #define ISP_CFG_NL 1
2488 #define ISP_CFG_N 2
2489 #define ISP_CFG_FL 4
2490 #define ISP_CFG_F 8
2491
2492 uint8_t operating_mode; /* F/W operating mode */
2493 #define LOOP 0
2494 #define P2P 1
2495 #define LOOP_P2P 2
2496 #define P2P_LOOP 3
2497 uint8_t interrupts_on;
2498 uint32_t isp_abort_cnt;
2499
2500 #define PCI_DEVICE_ID_QLOGIC_ISP2532 0x2532
2501 #define PCI_DEVICE_ID_QLOGIC_ISP8432 0x8432
2502 #define PCI_DEVICE_ID_QLOGIC_ISP8001 0x8001
2503 uint32_t device_type;
2504 #define DT_ISP2100 BIT_0
2505 #define DT_ISP2200 BIT_1
2506 #define DT_ISP2300 BIT_2
2507 #define DT_ISP2312 BIT_3
2508 #define DT_ISP2322 BIT_4
2509 #define DT_ISP6312 BIT_5
2510 #define DT_ISP6322 BIT_6
2511 #define DT_ISP2422 BIT_7
2512 #define DT_ISP2432 BIT_8
2513 #define DT_ISP5422 BIT_9
2514 #define DT_ISP5432 BIT_10
2515 #define DT_ISP2532 BIT_11
2516 #define DT_ISP8432 BIT_12
2517 #define DT_ISP8001 BIT_13
2518 #define DT_ISP8021 BIT_14
2519 #define DT_ISP_LAST (DT_ISP8021 << 1)
2520
2521 #define DT_IIDMA BIT_26
2522 #define DT_FWI2 BIT_27
2523 #define DT_ZIO_SUPPORTED BIT_28
2524 #define DT_OEM_001 BIT_29
2525 #define DT_ISP2200A BIT_30
2526 #define DT_EXTENDED_IDS BIT_31
2527 #define DT_MASK(ha) ((ha)->device_type & (DT_ISP_LAST - 1))
2528 #define IS_QLA2100(ha) (DT_MASK(ha) & DT_ISP2100)
2529 #define IS_QLA2200(ha) (DT_MASK(ha) & DT_ISP2200)
2530 #define IS_QLA2300(ha) (DT_MASK(ha) & DT_ISP2300)
2531 #define IS_QLA2312(ha) (DT_MASK(ha) & DT_ISP2312)
2532 #define IS_QLA2322(ha) (DT_MASK(ha) & DT_ISP2322)
2533 #define IS_QLA6312(ha) (DT_MASK(ha) & DT_ISP6312)
2534 #define IS_QLA6322(ha) (DT_MASK(ha) & DT_ISP6322)
2535 #define IS_QLA2422(ha) (DT_MASK(ha) & DT_ISP2422)
2536 #define IS_QLA2432(ha) (DT_MASK(ha) & DT_ISP2432)
2537 #define IS_QLA5422(ha) (DT_MASK(ha) & DT_ISP5422)
2538 #define IS_QLA5432(ha) (DT_MASK(ha) & DT_ISP5432)
2539 #define IS_QLA2532(ha) (DT_MASK(ha) & DT_ISP2532)
2540 #define IS_QLA8432(ha) (DT_MASK(ha) & DT_ISP8432)
2541 #define IS_QLA8001(ha) (DT_MASK(ha) & DT_ISP8001)
2542 #define IS_QLA82XX(ha) (DT_MASK(ha) & DT_ISP8021)
2543
2544 #define IS_QLA23XX(ha) (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA2322(ha) || \
2545 IS_QLA6312(ha) || IS_QLA6322(ha))
2546 #define IS_QLA24XX(ha) (IS_QLA2422(ha) || IS_QLA2432(ha))
2547 #define IS_QLA54XX(ha) (IS_QLA5422(ha) || IS_QLA5432(ha))
2548 #define IS_QLA25XX(ha) (IS_QLA2532(ha))
2549 #define IS_QLA84XX(ha) (IS_QLA8432(ha))
2550 #define IS_QLA24XX_TYPE(ha) (IS_QLA24XX(ha) || IS_QLA54XX(ha) || \
2551 IS_QLA84XX(ha))
2552 #define IS_QLA81XX(ha) (IS_QLA8001(ha))
2553 #define IS_QLA8XXX_TYPE(ha) (IS_QLA81XX(ha) || IS_QLA82XX(ha))
2554 #define IS_QLA2XXX_MIDTYPE(ha) (IS_QLA24XX(ha) || IS_QLA84XX(ha) || \
2555 IS_QLA25XX(ha) || IS_QLA81XX(ha) || \
2556 IS_QLA82XX(ha))
2557 #define IS_MSIX_NACK_CAPABLE(ha) (IS_QLA81XX(ha))
2558 #define IS_NOPOLLING_TYPE(ha) ((IS_QLA25XX(ha) || IS_QLA81XX(ha)) && \
2559 (ha)->flags.msix_enabled)
2560 #define IS_FAC_REQUIRED(ha) (IS_QLA81XX(ha))
2561 #define IS_NOCACHE_VPD_TYPE(ha) (IS_QLA81XX(ha))
2562 #define IS_ALOGIO_CAPABLE(ha) (IS_QLA23XX(ha) || IS_FWI2_CAPABLE(ha))
2563
2564 #define IS_IIDMA_CAPABLE(ha) ((ha)->device_type & DT_IIDMA)
2565 #define IS_FWI2_CAPABLE(ha) ((ha)->device_type & DT_FWI2)
2566 #define IS_ZIO_SUPPORTED(ha) ((ha)->device_type & DT_ZIO_SUPPORTED)
2567 #define IS_OEM_001(ha) ((ha)->device_type & DT_OEM_001)
2568 #define HAS_EXTENDED_IDS(ha) ((ha)->device_type & DT_EXTENDED_IDS)
2569
2570 /* HBA serial number */
2571 uint8_t serial0;
2572 uint8_t serial1;
2573 uint8_t serial2;
2574
2575 /* NVRAM configuration data */
2576 #define MAX_NVRAM_SIZE 4096
2577 #define VPD_OFFSET MAX_NVRAM_SIZE / 2
2578 uint16_t nvram_size;
2579 uint16_t nvram_base;
2580 void *nvram;
2581 uint16_t vpd_size;
2582 uint16_t vpd_base;
2583 void *vpd;
2584
2585 uint16_t loop_reset_delay;
2586 uint8_t retry_count;
2587 uint8_t login_timeout;
2588 uint16_t r_a_tov;
2589 int port_down_retry_count;
2590 uint8_t mbx_count;
2591
2592 uint32_t login_retry_count;
2593 /* SNS command interfaces. */
2594 ms_iocb_entry_t *ms_iocb;
2595 dma_addr_t ms_iocb_dma;
2596 struct ct_sns_pkt *ct_sns;
2597 dma_addr_t ct_sns_dma;
2598 /* SNS command interfaces for 2200. */
2599 struct sns_cmd_pkt *sns_cmd;
2600 dma_addr_t sns_cmd_dma;
2601
2602 #define SFP_DEV_SIZE 256
2603 #define SFP_BLOCK_SIZE 64
2604 void *sfp_data;
2605 dma_addr_t sfp_data_dma;
2606
2607 uint8_t *edc_data;
2608 dma_addr_t edc_data_dma;
2609 uint16_t edc_data_len;
2610
2611 #define XGMAC_DATA_SIZE 4096
2612 void *xgmac_data;
2613 dma_addr_t xgmac_data_dma;
2614
2615 #define DCBX_TLV_DATA_SIZE 4096
2616 void *dcbx_tlv;
2617 dma_addr_t dcbx_tlv_dma;
2618
2619 struct task_struct *dpc_thread;
2620 uint8_t dpc_active; /* DPC routine is active */
2621
2622 dma_addr_t gid_list_dma;
2623 struct gid_list_info *gid_list;
2624 int gid_list_info_size;
2625
2626 /* Small DMA pool allocations -- maximum 256 bytes in length. */
2627 #define DMA_POOL_SIZE 256
2628 struct dma_pool *s_dma_pool;
2629
2630 dma_addr_t init_cb_dma;
2631 init_cb_t *init_cb;
2632 int init_cb_size;
2633 dma_addr_t ex_init_cb_dma;
2634 struct ex_init_cb_81xx *ex_init_cb;
2635
2636 void *async_pd;
2637 dma_addr_t async_pd_dma;
2638
2639 /* These are used by mailbox operations. */
2640 volatile uint16_t mailbox_out[MAILBOX_REGISTER_COUNT];
2641
2642 mbx_cmd_t *mcp;
2643 unsigned long mbx_cmd_flags;
2644 #define MBX_INTERRUPT 1
2645 #define MBX_INTR_WAIT 2
2646 #define MBX_UPDATE_FLASH_ACTIVE 3
2647
2648 struct mutex vport_lock; /* Virtual port synchronization */
2649 spinlock_t vport_slock; /* order is hardware_lock, then vport_slock */
2650 struct completion mbx_cmd_comp; /* Serialize mbx access */
2651 struct completion mbx_intr_comp; /* Used for completion notification */
2652 struct completion dcbx_comp; /* For set port config notification */
2653 int notify_dcbx_comp;
2654
2655 /* Basic firmware related information. */
2656 uint16_t fw_major_version;
2657 uint16_t fw_minor_version;
2658 uint16_t fw_subminor_version;
2659 uint16_t fw_attributes;
2660 uint32_t fw_memory_size;
2661 uint32_t fw_transfer_size;
2662 uint32_t fw_srisc_address;
2663 #define RISC_START_ADDRESS_2100 0x1000
2664 #define RISC_START_ADDRESS_2300 0x800
2665 #define RISC_START_ADDRESS_2400 0x100000
2666 uint16_t fw_xcb_count;
2667
2668 uint16_t fw_options[16]; /* slots: 1,2,3,10,11 */
2669 uint8_t fw_seriallink_options[4];
2670 uint16_t fw_seriallink_options24[4];
2671
2672 uint8_t mpi_version[3];
2673 uint32_t mpi_capabilities;
2674 uint8_t phy_version[3];
2675
2676 /* Firmware dump information. */
2677 struct qla2xxx_fw_dump *fw_dump;
2678 uint32_t fw_dump_len;
2679 int fw_dumped;
2680 int fw_dump_reading;
2681 dma_addr_t eft_dma;
2682 void *eft;
2683
2684 uint32_t chain_offset;
2685 struct dentry *dfs_dir;
2686 struct dentry *dfs_fce;
2687 dma_addr_t fce_dma;
2688 void *fce;
2689 uint32_t fce_bufs;
2690 uint16_t fce_mb[8];
2691 uint64_t fce_wr, fce_rd;
2692 struct mutex fce_mutex;
2693
2694 uint32_t pci_attr;
2695 uint16_t chip_revision;
2696
2697 uint16_t product_id[4];
2698
2699 uint8_t model_number[16+1];
2700 #define BINZERO "\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0"
2701 char model_desc[80];
2702 uint8_t adapter_id[16+1];
2703
2704 /* Option ROM information. */
2705 char *optrom_buffer;
2706 uint32_t optrom_size;
2707 int optrom_state;
2708 #define QLA_SWAITING 0
2709 #define QLA_SREADING 1
2710 #define QLA_SWRITING 2
2711 uint32_t optrom_region_start;
2712 uint32_t optrom_region_size;
2713
2714 /* PCI expansion ROM image information. */
2715 #define ROM_CODE_TYPE_BIOS 0
2716 #define ROM_CODE_TYPE_FCODE 1
2717 #define ROM_CODE_TYPE_EFI 3
2718 uint8_t bios_revision[2];
2719 uint8_t efi_revision[2];
2720 uint8_t fcode_revision[16];
2721 uint32_t fw_revision[4];
2722
2723 uint32_t gold_fw_version[4];
2724
2725 /* Offsets for flash/nvram access (set to ~0 if not used). */
2726 uint32_t flash_conf_off;
2727 uint32_t flash_data_off;
2728 uint32_t nvram_conf_off;
2729 uint32_t nvram_data_off;
2730
2731 uint32_t fdt_wrt_disable;
2732 uint32_t fdt_erase_cmd;
2733 uint32_t fdt_block_size;
2734 uint32_t fdt_unprotect_sec_cmd;
2735 uint32_t fdt_protect_sec_cmd;
2736
2737 uint32_t flt_region_flt;
2738 uint32_t flt_region_fdt;
2739 uint32_t flt_region_boot;
2740 uint32_t flt_region_fw;
2741 uint32_t flt_region_vpd_nvram;
2742 uint32_t flt_region_vpd;
2743 uint32_t flt_region_nvram;
2744 uint32_t flt_region_npiv_conf;
2745 uint32_t flt_region_gold_fw;
2746 uint32_t flt_region_fcp_prio;
2747 uint32_t flt_region_bootload;
2748
2749 /* Needed for BEACON */
2750 uint16_t beacon_blink_led;
2751 uint8_t beacon_color_state;
2752 #define QLA_LED_GRN_ON 0x01
2753 #define QLA_LED_YLW_ON 0x02
2754 #define QLA_LED_ABR_ON 0x04
2755 #define QLA_LED_ALL_ON 0x07 /* yellow, green, amber. */
2756 /* ISP2322: red, green, amber. */
2757 uint16_t zio_mode;
2758 uint16_t zio_timer;
2759 struct fc_host_statistics fc_host_stat;
2760
2761 struct qla_msix_entry *msix_entries;
2762
2763 struct list_head vp_list; /* list of VP */
2764 unsigned long vp_idx_map[(MAX_MULTI_ID_FABRIC / 8) /
2765 sizeof(unsigned long)];
2766 uint16_t num_vhosts; /* number of vports created */
2767 uint16_t num_vsans; /* number of vsan created */
2768 uint16_t max_npiv_vports; /* 63 or 125 per topoloty */
2769 int cur_vport_count;
2770
2771 struct qla_chip_state_84xx *cs84xx;
2772 struct qla_statistics qla_stats;
2773 struct isp_operations *isp_ops;
2774 struct workqueue_struct *wq;
2775 struct qlfc_fw fw_buf;
2776
2777 /* FCP_CMND priority support */
2778 struct qla_fcp_prio_cfg *fcp_prio_cfg;
2779
2780 struct dma_pool *dl_dma_pool;
2781 #define DSD_LIST_DMA_POOL_SIZE 512
2782
2783 struct dma_pool *fcp_cmnd_dma_pool;
2784 mempool_t *ctx_mempool;
2785 #define FCP_CMND_DMA_POOL_SIZE 512
2786
2787 unsigned long nx_pcibase; /* Base I/O address */
2788 uint8_t *nxdb_rd_ptr; /* Doorbell read pointer */
2789 unsigned long nxdb_wr_ptr; /* Door bell write pointer */
2790
2791 uint32_t crb_win;
2792 uint32_t curr_window;
2793 uint32_t ddr_mn_window;
2794 unsigned long mn_win_crb;
2795 unsigned long ms_win_crb;
2796 int qdr_sn_window;
2797 uint32_t nx_dev_init_timeout;
2798 uint32_t nx_reset_timeout;
2799 rwlock_t hw_lock;
2800 uint16_t portnum; /* port number */
2801 int link_width;
2802 struct fw_blob *hablob;
2803 struct qla82xx_legacy_intr_set nx_legacy_intr;
2804
2805 uint16_t gbl_dsd_inuse;
2806 uint16_t gbl_dsd_avail;
2807 struct list_head gbl_dsd_list;
2808 #define NUM_DSD_CHAIN 4096
2809
2810 uint8_t fw_type;
2811 __le32 file_prd_off; /* File firmware product offset */
2812 };
2813
2814 /*
2815 * Qlogic scsi host structure
2816 */
2817 typedef struct scsi_qla_host {
2818 struct list_head list;
2819 struct list_head vp_fcports; /* list of fcports */
2820 struct list_head work_list;
2821 spinlock_t work_lock;
2822
2823 /* Commonly used flags and state information. */
2824 struct Scsi_Host *host;
2825 unsigned long host_no;
2826 uint8_t host_str[16];
2827
2828 volatile struct {
2829 uint32_t init_done :1;
2830 uint32_t online :1;
2831 uint32_t rscn_queue_overflow :1;
2832 uint32_t reset_active :1;
2833
2834 uint32_t management_server_logged_in :1;
2835 uint32_t process_response_queue :1;
2836 uint32_t difdix_supported:1;
2837 uint32_t delete_progress:1;
2838 } flags;
2839
2840 atomic_t loop_state;
2841 #define LOOP_TIMEOUT 1
2842 #define LOOP_DOWN 2
2843 #define LOOP_UP 3
2844 #define LOOP_UPDATE 4
2845 #define LOOP_READY 5
2846 #define LOOP_DEAD 6
2847
2848 unsigned long dpc_flags;
2849 #define RESET_MARKER_NEEDED 0 /* Send marker to ISP. */
2850 #define RESET_ACTIVE 1
2851 #define ISP_ABORT_NEEDED 2 /* Initiate ISP abort. */
2852 #define ABORT_ISP_ACTIVE 3 /* ISP abort in progress. */
2853 #define LOOP_RESYNC_NEEDED 4 /* Device Resync needed. */
2854 #define LOOP_RESYNC_ACTIVE 5
2855 #define LOCAL_LOOP_UPDATE 6 /* Perform a local loop update. */
2856 #define RSCN_UPDATE 7 /* Perform an RSCN update. */
2857 #define RELOGIN_NEEDED 8
2858 #define REGISTER_FC4_NEEDED 9 /* SNS FC4 registration required. */
2859 #define ISP_ABORT_RETRY 10 /* ISP aborted. */
2860 #define BEACON_BLINK_NEEDED 11
2861 #define REGISTER_FDMI_NEEDED 12
2862 #define FCPORT_UPDATE_NEEDED 13
2863 #define VP_DPC_NEEDED 14 /* wake up for VP dpc handling */
2864 #define UNLOADING 15
2865 #define NPIV_CONFIG_NEEDED 16
2866 #define ISP_UNRECOVERABLE 17
2867 #define FCOE_CTX_RESET_NEEDED 18 /* Initiate FCoE context reset */
2868 #define MPI_RESET_NEEDED 19 /* Initiate MPI FW reset */
2869 #define ISP_QUIESCE_NEEDED 20 /* Driver need some quiescence */
2870
2871 uint32_t device_flags;
2872 #define SWITCH_FOUND BIT_0
2873 #define DFLG_NO_CABLE BIT_1
2874 #define DFLG_DEV_FAILED BIT_5
2875
2876 /* ISP configuration data. */
2877 uint16_t loop_id; /* Host adapter loop id */
2878
2879 port_id_t d_id; /* Host adapter port id */
2880 uint8_t marker_needed;
2881 uint16_t mgmt_svr_loop_id;
2882
2883
2884
2885 /* RSCN queue. */
2886 uint32_t rscn_queue[MAX_RSCN_COUNT];
2887 uint8_t rscn_in_ptr;
2888 uint8_t rscn_out_ptr;
2889
2890 /* Timeout timers. */
2891 uint8_t loop_down_abort_time; /* port down timer */
2892 atomic_t loop_down_timer; /* loop down timer */
2893 uint8_t link_down_timeout; /* link down timeout */
2894
2895 uint32_t timer_active;
2896 struct timer_list timer;
2897
2898 uint8_t node_name[WWN_SIZE];
2899 uint8_t port_name[WWN_SIZE];
2900 uint8_t fabric_node_name[WWN_SIZE];
2901
2902 uint16_t fcoe_vlan_id;
2903 uint16_t fcoe_fcf_idx;
2904 uint8_t fcoe_vn_port_mac[6];
2905
2906 uint32_t vp_abort_cnt;
2907
2908 struct fc_vport *fc_vport; /* holds fc_vport * for each vport */
2909 uint16_t vp_idx; /* vport ID */
2910
2911 unsigned long vp_flags;
2912 #define VP_IDX_ACQUIRED 0 /* bit no 0 */
2913 #define VP_CREATE_NEEDED 1
2914 #define VP_BIND_NEEDED 2
2915 #define VP_DELETE_NEEDED 3
2916 #define VP_SCR_NEEDED 4 /* State Change Request registration */
2917 atomic_t vp_state;
2918 #define VP_OFFLINE 0
2919 #define VP_ACTIVE 1
2920 #define VP_FAILED 2
2921 // #define VP_DISABLE 3
2922 uint16_t vp_err_state;
2923 uint16_t vp_prev_err_state;
2924 #define VP_ERR_UNKWN 0
2925 #define VP_ERR_PORTDWN 1
2926 #define VP_ERR_FAB_UNSUPPORTED 2
2927 #define VP_ERR_FAB_NORESOURCES 3
2928 #define VP_ERR_FAB_LOGOUT 4
2929 #define VP_ERR_ADAP_NORESOURCES 5
2930 struct qla_hw_data *hw;
2931 struct req_que *req;
2932 int fw_heartbeat_counter;
2933 int seconds_since_last_heartbeat;
2934
2935 atomic_t vref_count;
2936 } scsi_qla_host_t;
2937
2938 /*
2939 * Macros to help code, maintain, etc.
2940 */
2941 #define LOOP_TRANSITION(ha) \
2942 (test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \
2943 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags) || \
2944 atomic_read(&ha->loop_state) == LOOP_DOWN)
2945
2946 #define QLA_VHA_MARK_BUSY(__vha, __bail) do { \
2947 atomic_inc(&__vha->vref_count); \
2948 mb(); \
2949 if (__vha->flags.delete_progress) { \
2950 atomic_dec(&__vha->vref_count); \
2951 __bail = 1; \
2952 } else { \
2953 __bail = 0; \
2954 } \
2955 } while (0)
2956
2957 #define QLA_VHA_MARK_NOT_BUSY(__vha) do { \
2958 atomic_dec(&__vha->vref_count); \
2959 } while (0)
2960
2961
2962 #define qla_printk(level, ha, format, arg...) \
2963 dev_printk(level , &((ha)->pdev->dev) , format , ## arg)
2964
2965 /*
2966 * qla2x00 local function return status codes
2967 */
2968 #define MBS_MASK 0x3fff
2969
2970 #define QLA_SUCCESS (MBS_COMMAND_COMPLETE & MBS_MASK)
2971 #define QLA_INVALID_COMMAND (MBS_INVALID_COMMAND & MBS_MASK)
2972 #define QLA_INTERFACE_ERROR (MBS_HOST_INTERFACE_ERROR & MBS_MASK)
2973 #define QLA_TEST_FAILED (MBS_TEST_FAILED & MBS_MASK)
2974 #define QLA_COMMAND_ERROR (MBS_COMMAND_ERROR & MBS_MASK)
2975 #define QLA_PARAMETER_ERROR (MBS_COMMAND_PARAMETER_ERROR & MBS_MASK)
2976 #define QLA_PORT_ID_USED (MBS_PORT_ID_USED & MBS_MASK)
2977 #define QLA_LOOP_ID_USED (MBS_LOOP_ID_USED & MBS_MASK)
2978 #define QLA_ALL_IDS_IN_USE (MBS_ALL_IDS_IN_USE & MBS_MASK)
2979 #define QLA_NOT_LOGGED_IN (MBS_NOT_LOGGED_IN & MBS_MASK)
2980
2981 #define QLA_FUNCTION_TIMEOUT 0x100
2982 #define QLA_FUNCTION_PARAMETER_ERROR 0x101
2983 #define QLA_FUNCTION_FAILED 0x102
2984 #define QLA_MEMORY_ALLOC_FAILED 0x103
2985 #define QLA_LOCK_TIMEOUT 0x104
2986 #define QLA_ABORTED 0x105
2987 #define QLA_SUSPENDED 0x106
2988 #define QLA_BUSY 0x107
2989 #define QLA_RSCNS_HANDLED 0x108
2990 #define QLA_ALREADY_REGISTERED 0x109
2991
2992 #define NVRAM_DELAY() udelay(10)
2993
2994 #define INVALID_HANDLE (MAX_OUTSTANDING_COMMANDS+1)
2995
2996 /*
2997 * Flash support definitions
2998 */
2999 #define OPTROM_SIZE_2300 0x20000
3000 #define OPTROM_SIZE_2322 0x100000
3001 #define OPTROM_SIZE_24XX 0x100000
3002 #define OPTROM_SIZE_25XX 0x200000
3003 #define OPTROM_SIZE_81XX 0x400000
3004 #define OPTROM_SIZE_82XX 0x800000
3005
3006 #define OPTROM_BURST_SIZE 0x1000
3007 #define OPTROM_BURST_DWORDS (OPTROM_BURST_SIZE / 4)
3008
3009 #define QLA_DSDS_PER_IOCB 37
3010
3011 #define CMD_SP(Cmnd) ((Cmnd)->SCp.ptr)
3012
3013 #define QLA_SG_ALL 1024
3014
3015 enum nexus_wait_type {
3016 WAIT_HOST = 0,
3017 WAIT_TARGET,
3018 WAIT_LUN,
3019 };
3020
3021 #include "qla_gbl.h"
3022 #include "qla_dbg.h"
3023 #include "qla_inline.h"
3024 #endif
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree