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jme: Fix unmap error (Causing system freeze)
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / jme.c
blob19738143aa91b4ea46adc39c2074087abc692f00
1 /*
2 * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
3 *
4 * Copyright 2008 JMicron Technology Corporation
5 * http://www.jmicron.com/
6 * Copyright (c) 2009 - 2010 Guo-Fu Tseng <cooldavid@cooldavid.org>
7 *
8 * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 *
23 */
24
25 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
26
27 #include <linux/module.h>
28 #include <linux/kernel.h>
29 #include <linux/pci.h>
30 #include <linux/netdevice.h>
31 #include <linux/etherdevice.h>
32 #include <linux/ethtool.h>
33 #include <linux/mii.h>
34 #include <linux/crc32.h>
35 #include <linux/delay.h>
36 #include <linux/spinlock.h>
37 #include <linux/in.h>
38 #include <linux/ip.h>
39 #include <linux/ipv6.h>
40 #include <linux/tcp.h>
41 #include <linux/udp.h>
42 #include <linux/if_vlan.h>
43 #include <linux/slab.h>
44 #include <net/ip6_checksum.h>
45 #include "jme.h"
46
47 static int force_pseudohp = -1;
48 static int no_pseudohp = -1;
49 static int no_extplug = -1;
50 module_param(force_pseudohp, int, 0);
51 MODULE_PARM_DESC(force_pseudohp,
52 "Enable pseudo hot-plug feature manually by driver instead of BIOS.");
53 module_param(no_pseudohp, int, 0);
54 MODULE_PARM_DESC(no_pseudohp, "Disable pseudo hot-plug feature.");
55 module_param(no_extplug, int, 0);
56 MODULE_PARM_DESC(no_extplug,
57 "Do not use external plug signal for pseudo hot-plug.");
58
59 static int
60 jme_mdio_read(struct net_device *netdev, int phy, int reg)
61 {
62 struct jme_adapter *jme = netdev_priv(netdev);
63 int i, val, again = (reg == MII_BMSR) ? 1 : 0;
64
65 read_again:
66 jwrite32(jme, JME_SMI, SMI_OP_REQ |
67 smi_phy_addr(phy) |
68 smi_reg_addr(reg));
69
70 wmb();
71 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
72 udelay(20);
73 val = jread32(jme, JME_SMI);
74 if ((val & SMI_OP_REQ) == 0)
75 break;
76 }
77
78 if (i == 0) {
79 pr_err("phy(%d) read timeout : %d\n", phy, reg);
80 return 0;
81 }
82
83 if (again--)
84 goto read_again;
85
86 return (val & SMI_DATA_MASK) >> SMI_DATA_SHIFT;
87 }
88
89 static void
90 jme_mdio_write(struct net_device *netdev,
91 int phy, int reg, int val)
92 {
93 struct jme_adapter *jme = netdev_priv(netdev);
94 int i;
95
96 jwrite32(jme, JME_SMI, SMI_OP_WRITE | SMI_OP_REQ |
97 ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) |
98 smi_phy_addr(phy) | smi_reg_addr(reg));
99
100 wmb();
101 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
102 udelay(20);
103 if ((jread32(jme, JME_SMI) & SMI_OP_REQ) == 0)
104 break;
105 }
106
107 if (i == 0)
108 pr_err("phy(%d) write timeout : %d\n", phy, reg);
109 }
110
111 static inline void
112 jme_reset_phy_processor(struct jme_adapter *jme)
113 {
114 u32 val;
115
116 jme_mdio_write(jme->dev,
117 jme->mii_if.phy_id,
118 MII_ADVERTISE, ADVERTISE_ALL |
119 ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
120
121 if (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
122 jme_mdio_write(jme->dev,
123 jme->mii_if.phy_id,
124 MII_CTRL1000,
125 ADVERTISE_1000FULL | ADVERTISE_1000HALF);
126
127 val = jme_mdio_read(jme->dev,
128 jme->mii_if.phy_id,
129 MII_BMCR);
130
131 jme_mdio_write(jme->dev,
132 jme->mii_if.phy_id,
133 MII_BMCR, val | BMCR_RESET);
134 }
135
136 static void
137 jme_setup_wakeup_frame(struct jme_adapter *jme,
138 const u32 *mask, u32 crc, int fnr)
139 {
140 int i;
141
142 /*
143 * Setup CRC pattern
144 */
145 jwrite32(jme, JME_WFOI, WFOI_CRC_SEL | (fnr & WFOI_FRAME_SEL));
146 wmb();
147 jwrite32(jme, JME_WFODP, crc);
148 wmb();
149
150 /*
151 * Setup Mask
152 */
153 for (i = 0 ; i < WAKEUP_FRAME_MASK_DWNR ; ++i) {
154 jwrite32(jme, JME_WFOI,
155 ((i << WFOI_MASK_SHIFT) & WFOI_MASK_SEL) |
156 (fnr & WFOI_FRAME_SEL));
157 wmb();
158 jwrite32(jme, JME_WFODP, mask[i]);
159 wmb();
160 }
161 }
162
163 static inline void
164 jme_mac_rxclk_off(struct jme_adapter *jme)
165 {
166 jme->reg_gpreg1 |= GPREG1_RXCLKOFF;
167 jwrite32f(jme, JME_GPREG1, jme->reg_gpreg1);
168 }
169
170 static inline void
171 jme_mac_rxclk_on(struct jme_adapter *jme)
172 {
173 jme->reg_gpreg1 &= ~GPREG1_RXCLKOFF;
174 jwrite32f(jme, JME_GPREG1, jme->reg_gpreg1);
175 }
176
177 static inline void
178 jme_mac_txclk_off(struct jme_adapter *jme)
179 {
180 jme->reg_ghc &= ~(GHC_TO_CLK_SRC | GHC_TXMAC_CLK_SRC);
181 jwrite32f(jme, JME_GHC, jme->reg_ghc);
182 }
183
184 static inline void
185 jme_mac_txclk_on(struct jme_adapter *jme)
186 {
187 u32 speed = jme->reg_ghc & GHC_SPEED;
188 if (speed == GHC_SPEED_1000M)
189 jme->reg_ghc |= GHC_TO_CLK_GPHY | GHC_TXMAC_CLK_GPHY;
190 else
191 jme->reg_ghc |= GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE;
192 jwrite32f(jme, JME_GHC, jme->reg_ghc);
193 }
194
195 static inline void
196 jme_reset_ghc_speed(struct jme_adapter *jme)
197 {
198 jme->reg_ghc &= ~(GHC_SPEED | GHC_DPX);
199 jwrite32f(jme, JME_GHC, jme->reg_ghc);
200 }
201
202 static inline void
203 jme_reset_250A2_workaround(struct jme_adapter *jme)
204 {
205 jme->reg_gpreg1 &= ~(GPREG1_HALFMODEPATCH |
206 GPREG1_RSSPATCH);
207 jwrite32(jme, JME_GPREG1, jme->reg_gpreg1);
208 }
209
210 static inline void
211 jme_assert_ghc_reset(struct jme_adapter *jme)
212 {
213 jme->reg_ghc |= GHC_SWRST;
214 jwrite32f(jme, JME_GHC, jme->reg_ghc);
215 }
216
217 static inline void
218 jme_clear_ghc_reset(struct jme_adapter *jme)
219 {
220 jme->reg_ghc &= ~GHC_SWRST;
221 jwrite32f(jme, JME_GHC, jme->reg_ghc);
222 }
223
224 static inline void
225 jme_reset_mac_processor(struct jme_adapter *jme)
226 {
227 static const u32 mask[WAKEUP_FRAME_MASK_DWNR] = {0, 0, 0, 0};
228 u32 crc = 0xCDCDCDCD;
229 u32 gpreg0;
230 int i;
231
232 jme_reset_ghc_speed(jme);
233 jme_reset_250A2_workaround(jme);
234
235 jme_mac_rxclk_on(jme);
236 jme_mac_txclk_on(jme);
237 udelay(1);
238 jme_assert_ghc_reset(jme);
239 udelay(1);
240 jme_mac_rxclk_off(jme);
241 jme_mac_txclk_off(jme);
242 udelay(1);
243 jme_clear_ghc_reset(jme);
244 udelay(1);
245 jme_mac_rxclk_on(jme);
246 jme_mac_txclk_on(jme);
247 udelay(1);
248 jme_mac_rxclk_off(jme);
249 jme_mac_txclk_off(jme);
250
251 jwrite32(jme, JME_RXDBA_LO, 0x00000000);
252 jwrite32(jme, JME_RXDBA_HI, 0x00000000);
253 jwrite32(jme, JME_RXQDC, 0x00000000);
254 jwrite32(jme, JME_RXNDA, 0x00000000);
255 jwrite32(jme, JME_TXDBA_LO, 0x00000000);
256 jwrite32(jme, JME_TXDBA_HI, 0x00000000);
257 jwrite32(jme, JME_TXQDC, 0x00000000);
258 jwrite32(jme, JME_TXNDA, 0x00000000);
259
260 jwrite32(jme, JME_RXMCHT_LO, 0x00000000);
261 jwrite32(jme, JME_RXMCHT_HI, 0x00000000);
262 for (i = 0 ; i < WAKEUP_FRAME_NR ; ++i)
263 jme_setup_wakeup_frame(jme, mask, crc, i);
264 if (jme->fpgaver)
265 gpreg0 = GPREG0_DEFAULT | GPREG0_LNKINTPOLL;
266 else
267 gpreg0 = GPREG0_DEFAULT;
268 jwrite32(jme, JME_GPREG0, gpreg0);
269 }
270
271 static inline void
272 jme_clear_pm(struct jme_adapter *jme)
273 {
274 jwrite32(jme, JME_PMCS, 0xFFFF0000 | jme->reg_pmcs);
275 pci_set_power_state(jme->pdev, PCI_D0);
276 device_set_wakeup_enable(&jme->pdev->dev, false);
277 }
278
279 static int
280 jme_reload_eeprom(struct jme_adapter *jme)
281 {
282 u32 val;
283 int i;
284
285 val = jread32(jme, JME_SMBCSR);
286
287 if (val & SMBCSR_EEPROMD) {
288 val |= SMBCSR_CNACK;
289 jwrite32(jme, JME_SMBCSR, val);
290 val |= SMBCSR_RELOAD;
291 jwrite32(jme, JME_SMBCSR, val);
292 mdelay(12);
293
294 for (i = JME_EEPROM_RELOAD_TIMEOUT; i > 0; --i) {
295 mdelay(1);
296 if ((jread32(jme, JME_SMBCSR) & SMBCSR_RELOAD) == 0)
297 break;
298 }
299
300 if (i == 0) {
301 pr_err("eeprom reload timeout\n");
302 return -EIO;
303 }
304 }
305
306 return 0;
307 }
308
309 static void
310 jme_load_macaddr(struct net_device *netdev)
311 {
312 struct jme_adapter *jme = netdev_priv(netdev);
313 unsigned char macaddr[6];
314 u32 val;
315
316 spin_lock_bh(&jme->macaddr_lock);
317 val = jread32(jme, JME_RXUMA_LO);
318 macaddr[0] = (val >> 0) & 0xFF;
319 macaddr[1] = (val >> 8) & 0xFF;
320 macaddr[2] = (val >> 16) & 0xFF;
321 macaddr[3] = (val >> 24) & 0xFF;
322 val = jread32(jme, JME_RXUMA_HI);
323 macaddr[4] = (val >> 0) & 0xFF;
324 macaddr[5] = (val >> 8) & 0xFF;
325 memcpy(netdev->dev_addr, macaddr, 6);
326 spin_unlock_bh(&jme->macaddr_lock);
327 }
328
329 static inline void
330 jme_set_rx_pcc(struct jme_adapter *jme, int p)
331 {
332 switch (p) {
333 case PCC_OFF:
334 jwrite32(jme, JME_PCCRX0,
335 ((PCC_OFF_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
336 ((PCC_OFF_CNT << PCCRX_SHIFT) & PCCRX_MASK));
337 break;
338 case PCC_P1:
339 jwrite32(jme, JME_PCCRX0,
340 ((PCC_P1_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
341 ((PCC_P1_CNT << PCCRX_SHIFT) & PCCRX_MASK));
342 break;
343 case PCC_P2:
344 jwrite32(jme, JME_PCCRX0,
345 ((PCC_P2_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
346 ((PCC_P2_CNT << PCCRX_SHIFT) & PCCRX_MASK));
347 break;
348 case PCC_P3:
349 jwrite32(jme, JME_PCCRX0,
350 ((PCC_P3_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
351 ((PCC_P3_CNT << PCCRX_SHIFT) & PCCRX_MASK));
352 break;
353 default:
354 break;
355 }
356 wmb();
357
358 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
359 netif_info(jme, rx_status, jme->dev, "Switched to PCC_P%d\n", p);
360 }
361
362 static void
363 jme_start_irq(struct jme_adapter *jme)
364 {
365 register struct dynpcc_info *dpi = &(jme->dpi);
366
367 jme_set_rx_pcc(jme, PCC_P1);
368 dpi->cur = PCC_P1;
369 dpi->attempt = PCC_P1;
370 dpi->cnt = 0;
371
372 jwrite32(jme, JME_PCCTX,
373 ((PCC_TX_TO << PCCTXTO_SHIFT) & PCCTXTO_MASK) |
374 ((PCC_TX_CNT << PCCTX_SHIFT) & PCCTX_MASK) |
375 PCCTXQ0_EN
376 );
377
378 /*
379 * Enable Interrupts
380 */
381 jwrite32(jme, JME_IENS, INTR_ENABLE);
382 }
383
384 static inline void
385 jme_stop_irq(struct jme_adapter *jme)
386 {
387 /*
388 * Disable Interrupts
389 */
390 jwrite32f(jme, JME_IENC, INTR_ENABLE);
391 }
392
393 static u32
394 jme_linkstat_from_phy(struct jme_adapter *jme)
395 {
396 u32 phylink, bmsr;
397
398 phylink = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 17);
399 bmsr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMSR);
400 if (bmsr & BMSR_ANCOMP)
401 phylink |= PHY_LINK_AUTONEG_COMPLETE;
402
403 return phylink;
404 }
405
406 static inline void
407 jme_set_phyfifo_5level(struct jme_adapter *jme)
408 {
409 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0004);
410 }
411
412 static inline void
413 jme_set_phyfifo_8level(struct jme_adapter *jme)
414 {
415 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0000);
416 }
417
418 static int
419 jme_check_link(struct net_device *netdev, int testonly)
420 {
421 struct jme_adapter *jme = netdev_priv(netdev);
422 u32 phylink, cnt = JME_SPDRSV_TIMEOUT, bmcr;
423 char linkmsg[64];
424 int rc = 0;
425
426 linkmsg[0] = '\0';
427
428 if (jme->fpgaver)
429 phylink = jme_linkstat_from_phy(jme);
430 else
431 phylink = jread32(jme, JME_PHY_LINK);
432
433 if (phylink & PHY_LINK_UP) {
434 if (!(phylink & PHY_LINK_AUTONEG_COMPLETE)) {
435 /*
436 * If we did not enable AN
437 * Speed/Duplex Info should be obtained from SMI
438 */
439 phylink = PHY_LINK_UP;
440
441 bmcr = jme_mdio_read(jme->dev,
442 jme->mii_if.phy_id,
443 MII_BMCR);
444
445 phylink |= ((bmcr & BMCR_SPEED1000) &&
446 (bmcr & BMCR_SPEED100) == 0) ?
447 PHY_LINK_SPEED_1000M :
448 (bmcr & BMCR_SPEED100) ?
449 PHY_LINK_SPEED_100M :
450 PHY_LINK_SPEED_10M;
451
452 phylink |= (bmcr & BMCR_FULLDPLX) ?
453 PHY_LINK_DUPLEX : 0;
454
455 strcat(linkmsg, "Forced: ");
456 } else {
457 /*
458 * Keep polling for speed/duplex resolve complete
459 */
460 while (!(phylink & PHY_LINK_SPEEDDPU_RESOLVED) &&
461 --cnt) {
462
463 udelay(1);
464
465 if (jme->fpgaver)
466 phylink = jme_linkstat_from_phy(jme);
467 else
468 phylink = jread32(jme, JME_PHY_LINK);
469 }
470 if (!cnt)
471 pr_err("Waiting speed resolve timeout\n");
472
473 strcat(linkmsg, "ANed: ");
474 }
475
476 if (jme->phylink == phylink) {
477 rc = 1;
478 goto out;
479 }
480 if (testonly)
481 goto out;
482
483 jme->phylink = phylink;
484
485 /*
486 * The speed/duplex setting of jme->reg_ghc already cleared
487 * by jme_reset_mac_processor()
488 */
489 switch (phylink & PHY_LINK_SPEED_MASK) {
490 case PHY_LINK_SPEED_10M:
491 jme->reg_ghc |= GHC_SPEED_10M;
492 strcat(linkmsg, "10 Mbps, ");
493 break;
494 case PHY_LINK_SPEED_100M:
495 jme->reg_ghc |= GHC_SPEED_100M;
496 strcat(linkmsg, "100 Mbps, ");
497 break;
498 case PHY_LINK_SPEED_1000M:
499 jme->reg_ghc |= GHC_SPEED_1000M;
500 strcat(linkmsg, "1000 Mbps, ");
501 break;
502 default:
503 break;
504 }
505
506 if (phylink & PHY_LINK_DUPLEX) {
507 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT);
508 jwrite32(jme, JME_TXTRHD, TXTRHD_FULLDUPLEX);
509 jme->reg_ghc |= GHC_DPX;
510 } else {
511 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT |
512 TXMCS_BACKOFF |
513 TXMCS_CARRIERSENSE |
514 TXMCS_COLLISION);
515 jwrite32(jme, JME_TXTRHD, TXTRHD_HALFDUPLEX);
516 }
517
518 jwrite32(jme, JME_GHC, jme->reg_ghc);
519
520 if (is_buggy250(jme->pdev->device, jme->chiprev)) {
521 jme->reg_gpreg1 &= ~(GPREG1_HALFMODEPATCH |
522 GPREG1_RSSPATCH);
523 if (!(phylink & PHY_LINK_DUPLEX))
524 jme->reg_gpreg1 |= GPREG1_HALFMODEPATCH;
525 switch (phylink & PHY_LINK_SPEED_MASK) {
526 case PHY_LINK_SPEED_10M:
527 jme_set_phyfifo_8level(jme);
528 jme->reg_gpreg1 |= GPREG1_RSSPATCH;
529 break;
530 case PHY_LINK_SPEED_100M:
531 jme_set_phyfifo_5level(jme);
532 jme->reg_gpreg1 |= GPREG1_RSSPATCH;
533 break;
534 case PHY_LINK_SPEED_1000M:
535 jme_set_phyfifo_8level(jme);
536 break;
537 default:
538 break;
539 }
540 }
541 jwrite32(jme, JME_GPREG1, jme->reg_gpreg1);
542
543 strcat(linkmsg, (phylink & PHY_LINK_DUPLEX) ?
544 "Full-Duplex, " :
545 "Half-Duplex, ");
546 strcat(linkmsg, (phylink & PHY_LINK_MDI_STAT) ?
547 "MDI-X" :
548 "MDI");
549 netif_info(jme, link, jme->dev, "Link is up at %s\n", linkmsg);
550 netif_carrier_on(netdev);
551 } else {
552 if (testonly)
553 goto out;
554
555 netif_info(jme, link, jme->dev, "Link is down\n");
556 jme->phylink = 0;
557 netif_carrier_off(netdev);
558 }
559
560 out:
561 return rc;
562 }
563
564 static int
565 jme_setup_tx_resources(struct jme_adapter *jme)
566 {
567 struct jme_ring *txring = &(jme->txring[0]);
568
569 txring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
570 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
571 &(txring->dmaalloc),
572 GFP_ATOMIC);
573
574 if (!txring->alloc)
575 goto err_set_null;
576
577 /*
578 * 16 Bytes align
579 */
580 txring->desc = (void *)ALIGN((unsigned long)(txring->alloc),
581 RING_DESC_ALIGN);
582 txring->dma = ALIGN(txring->dmaalloc, RING_DESC_ALIGN);
583 txring->next_to_use = 0;
584 atomic_set(&txring->next_to_clean, 0);
585 atomic_set(&txring->nr_free, jme->tx_ring_size);
586
587 txring->bufinf = kmalloc(sizeof(struct jme_buffer_info) *
588 jme->tx_ring_size, GFP_ATOMIC);
589 if (unlikely(!(txring->bufinf)))
590 goto err_free_txring;
591
592 /*
593 * Initialize Transmit Descriptors
594 */
595 memset(txring->alloc, 0, TX_RING_ALLOC_SIZE(jme->tx_ring_size));
596 memset(txring->bufinf, 0,
597 sizeof(struct jme_buffer_info) * jme->tx_ring_size);
598
599 return 0;
600
601 err_free_txring:
602 dma_free_coherent(&(jme->pdev->dev),
603 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
604 txring->alloc,
605 txring->dmaalloc);
606
607 err_set_null:
608 txring->desc = NULL;
609 txring->dmaalloc = 0;
610 txring->dma = 0;
611 txring->bufinf = NULL;
612
613 return -ENOMEM;
614 }
615
616 static void
617 jme_free_tx_resources(struct jme_adapter *jme)
618 {
619 int i;
620 struct jme_ring *txring = &(jme->txring[0]);
621 struct jme_buffer_info *txbi;
622
623 if (txring->alloc) {
624 if (txring->bufinf) {
625 for (i = 0 ; i < jme->tx_ring_size ; ++i) {
626 txbi = txring->bufinf + i;
627 if (txbi->skb) {
628 dev_kfree_skb(txbi->skb);
629 txbi->skb = NULL;
630 }
631 txbi->mapping = 0;
632 txbi->len = 0;
633 txbi->nr_desc = 0;
634 txbi->start_xmit = 0;
635 }
636 kfree(txring->bufinf);
637 }
638
639 dma_free_coherent(&(jme->pdev->dev),
640 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
641 txring->alloc,
642 txring->dmaalloc);
643
644 txring->alloc = NULL;
645 txring->desc = NULL;
646 txring->dmaalloc = 0;
647 txring->dma = 0;
648 txring->bufinf = NULL;
649 }
650 txring->next_to_use = 0;
651 atomic_set(&txring->next_to_clean, 0);
652 atomic_set(&txring->nr_free, 0);
653 }
654
655 static inline void
656 jme_enable_tx_engine(struct jme_adapter *jme)
657 {
658 /*
659 * Select Queue 0
660 */
661 jwrite32(jme, JME_TXCS, TXCS_DEFAULT | TXCS_SELECT_QUEUE0);
662 wmb();
663
664 /*
665 * Setup TX Queue 0 DMA Bass Address
666 */
667 jwrite32(jme, JME_TXDBA_LO, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
668 jwrite32(jme, JME_TXDBA_HI, (__u64)(jme->txring[0].dma) >> 32);
669 jwrite32(jme, JME_TXNDA, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
670
671 /*
672 * Setup TX Descptor Count
673 */
674 jwrite32(jme, JME_TXQDC, jme->tx_ring_size);
675
676 /*
677 * Enable TX Engine
678 */
679 wmb();
680 jwrite32f(jme, JME_TXCS, jme->reg_txcs |
681 TXCS_SELECT_QUEUE0 |
682 TXCS_ENABLE);
683
684 /*
685 * Start clock for TX MAC Processor
686 */
687 jme_mac_txclk_on(jme);
688 }
689
690 static inline void
691 jme_restart_tx_engine(struct jme_adapter *jme)
692 {
693 /*
694 * Restart TX Engine
695 */
696 jwrite32(jme, JME_TXCS, jme->reg_txcs |
697 TXCS_SELECT_QUEUE0 |
698 TXCS_ENABLE);
699 }
700
701 static inline void
702 jme_disable_tx_engine(struct jme_adapter *jme)
703 {
704 int i;
705 u32 val;
706
707 /*
708 * Disable TX Engine
709 */
710 jwrite32(jme, JME_TXCS, jme->reg_txcs | TXCS_SELECT_QUEUE0);
711 wmb();
712
713 val = jread32(jme, JME_TXCS);
714 for (i = JME_TX_DISABLE_TIMEOUT ; (val & TXCS_ENABLE) && i > 0 ; --i) {
715 mdelay(1);
716 val = jread32(jme, JME_TXCS);
717 rmb();
718 }
719
720 if (!i)
721 pr_err("Disable TX engine timeout\n");
722
723 /*
724 * Stop clock for TX MAC Processor
725 */
726 jme_mac_txclk_off(jme);
727 }
728
729 static void
730 jme_set_clean_rxdesc(struct jme_adapter *jme, int i)
731 {
732 struct jme_ring *rxring = &(jme->rxring[0]);
733 register struct rxdesc *rxdesc = rxring->desc;
734 struct jme_buffer_info *rxbi = rxring->bufinf;
735 rxdesc += i;
736 rxbi += i;
737
738 rxdesc->dw[0] = 0;
739 rxdesc->dw[1] = 0;
740 rxdesc->desc1.bufaddrh = cpu_to_le32((__u64)rxbi->mapping >> 32);
741 rxdesc->desc1.bufaddrl = cpu_to_le32(
742 (__u64)rxbi->mapping & 0xFFFFFFFFUL);
743 rxdesc->desc1.datalen = cpu_to_le16(rxbi->len);
744 if (jme->dev->features & NETIF_F_HIGHDMA)
745 rxdesc->desc1.flags = RXFLAG_64BIT;
746 wmb();
747 rxdesc->desc1.flags |= RXFLAG_OWN | RXFLAG_INT;
748 }
749
750 static int
751 jme_make_new_rx_buf(struct jme_adapter *jme, int i)
752 {
753 struct jme_ring *rxring = &(jme->rxring[0]);
754 struct jme_buffer_info *rxbi = rxring->bufinf + i;
755 struct sk_buff *skb;
756 dma_addr_t mapping;
757
758 skb = netdev_alloc_skb(jme->dev,
759 jme->dev->mtu + RX_EXTRA_LEN);
760 if (unlikely(!skb))
761 return -ENOMEM;
762
763 mapping = pci_map_page(jme->pdev, virt_to_page(skb->data),
764 offset_in_page(skb->data), skb_tailroom(skb),
765 PCI_DMA_FROMDEVICE);
766 if (unlikely(pci_dma_mapping_error(jme->pdev, mapping))) {
767 dev_kfree_skb(skb);
768 return -ENOMEM;
769 }
770
771 if (likely(rxbi->mapping))
772 pci_unmap_page(jme->pdev, rxbi->mapping,
773 rxbi->len, PCI_DMA_FROMDEVICE);
774
775 rxbi->skb = skb;
776 rxbi->len = skb_tailroom(skb);
777 rxbi->mapping = mapping;
778 return 0;
779 }
780
781 static void
782 jme_free_rx_buf(struct jme_adapter *jme, int i)
783 {
784 struct jme_ring *rxring = &(jme->rxring[0]);
785 struct jme_buffer_info *rxbi = rxring->bufinf;
786 rxbi += i;
787
788 if (rxbi->skb) {
789 pci_unmap_page(jme->pdev,
790 rxbi->mapping,
791 rxbi->len,
792 PCI_DMA_FROMDEVICE);
793 dev_kfree_skb(rxbi->skb);
794 rxbi->skb = NULL;
795 rxbi->mapping = 0;
796 rxbi->len = 0;
797 }
798 }
799
800 static void
801 jme_free_rx_resources(struct jme_adapter *jme)
802 {
803 int i;
804 struct jme_ring *rxring = &(jme->rxring[0]);
805
806 if (rxring->alloc) {
807 if (rxring->bufinf) {
808 for (i = 0 ; i < jme->rx_ring_size ; ++i)
809 jme_free_rx_buf(jme, i);
810 kfree(rxring->bufinf);
811 }
812
813 dma_free_coherent(&(jme->pdev->dev),
814 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
815 rxring->alloc,
816 rxring->dmaalloc);
817 rxring->alloc = NULL;
818 rxring->desc = NULL;
819 rxring->dmaalloc = 0;
820 rxring->dma = 0;
821 rxring->bufinf = NULL;
822 }
823 rxring->next_to_use = 0;
824 atomic_set(&rxring->next_to_clean, 0);
825 }
826
827 static int
828 jme_setup_rx_resources(struct jme_adapter *jme)
829 {
830 int i;
831 struct jme_ring *rxring = &(jme->rxring[0]);
832
833 rxring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
834 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
835 &(rxring->dmaalloc),
836 GFP_ATOMIC);
837 if (!rxring->alloc)
838 goto err_set_null;
839
840 /*
841 * 16 Bytes align
842 */
843 rxring->desc = (void *)ALIGN((unsigned long)(rxring->alloc),
844 RING_DESC_ALIGN);
845 rxring->dma = ALIGN(rxring->dmaalloc, RING_DESC_ALIGN);
846 rxring->next_to_use = 0;
847 atomic_set(&rxring->next_to_clean, 0);
848
849 rxring->bufinf = kmalloc(sizeof(struct jme_buffer_info) *
850 jme->rx_ring_size, GFP_ATOMIC);
851 if (unlikely(!(rxring->bufinf)))
852 goto err_free_rxring;
853
854 /*
855 * Initiallize Receive Descriptors
856 */
857 memset(rxring->bufinf, 0,
858 sizeof(struct jme_buffer_info) * jme->rx_ring_size);
859 for (i = 0 ; i < jme->rx_ring_size ; ++i) {
860 if (unlikely(jme_make_new_rx_buf(jme, i))) {
861 jme_free_rx_resources(jme);
862 return -ENOMEM;
863 }
864
865 jme_set_clean_rxdesc(jme, i);
866 }
867
868 return 0;
869
870 err_free_rxring:
871 dma_free_coherent(&(jme->pdev->dev),
872 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
873 rxring->alloc,
874 rxring->dmaalloc);
875 err_set_null:
876 rxring->desc = NULL;
877 rxring->dmaalloc = 0;
878 rxring->dma = 0;
879 rxring->bufinf = NULL;
880
881 return -ENOMEM;
882 }
883
884 static inline void
885 jme_enable_rx_engine(struct jme_adapter *jme)
886 {
887 /*
888 * Select Queue 0
889 */
890 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
891 RXCS_QUEUESEL_Q0);
892 wmb();
893
894 /*
895 * Setup RX DMA Bass Address
896 */
897 jwrite32(jme, JME_RXDBA_LO, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
898 jwrite32(jme, JME_RXDBA_HI, (__u64)(jme->rxring[0].dma) >> 32);
899 jwrite32(jme, JME_RXNDA, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
900
901 /*
902 * Setup RX Descriptor Count
903 */
904 jwrite32(jme, JME_RXQDC, jme->rx_ring_size);
905
906 /*
907 * Setup Unicast Filter
908 */
909 jme_set_unicastaddr(jme->dev);
910 jme_set_multi(jme->dev);
911
912 /*
913 * Enable RX Engine
914 */
915 wmb();
916 jwrite32f(jme, JME_RXCS, jme->reg_rxcs |
917 RXCS_QUEUESEL_Q0 |
918 RXCS_ENABLE |
919 RXCS_QST);
920
921 /*
922 * Start clock for RX MAC Processor
923 */
924 jme_mac_rxclk_on(jme);
925 }
926
927 static inline void
928 jme_restart_rx_engine(struct jme_adapter *jme)
929 {
930 /*
931 * Start RX Engine
932 */
933 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
934 RXCS_QUEUESEL_Q0 |
935 RXCS_ENABLE |
936 RXCS_QST);
937 }
938
939 static inline void
940 jme_disable_rx_engine(struct jme_adapter *jme)
941 {
942 int i;
943 u32 val;
944
945 /*
946 * Disable RX Engine
947 */
948 jwrite32(jme, JME_RXCS, jme->reg_rxcs);
949 wmb();
950
951 val = jread32(jme, JME_RXCS);
952 for (i = JME_RX_DISABLE_TIMEOUT ; (val & RXCS_ENABLE) && i > 0 ; --i) {
953 mdelay(1);
954 val = jread32(jme, JME_RXCS);
955 rmb();
956 }
957
958 if (!i)
959 pr_err("Disable RX engine timeout\n");
960
961 /*
962 * Stop clock for RX MAC Processor
963 */
964 jme_mac_rxclk_off(jme);
965 }
966
967 static u16
968 jme_udpsum(struct sk_buff *skb)
969 {
970 u16 csum = 0xFFFFu;
971
972 if (skb->len < (ETH_HLEN + sizeof(struct iphdr)))
973 return csum;
974 if (skb->protocol != htons(ETH_P_IP))
975 return csum;
976 skb_set_network_header(skb, ETH_HLEN);
977 if ((ip_hdr(skb)->protocol != IPPROTO_UDP) ||
978 (skb->len < (ETH_HLEN +
979 (ip_hdr(skb)->ihl << 2) +
980 sizeof(struct udphdr)))) {
981 skb_reset_network_header(skb);
982 return csum;
983 }
984 skb_set_transport_header(skb,
985 ETH_HLEN + (ip_hdr(skb)->ihl << 2));
986 csum = udp_hdr(skb)->check;
987 skb_reset_transport_header(skb);
988 skb_reset_network_header(skb);
989
990 return csum;
991 }
992
993 static int
994 jme_rxsum_ok(struct jme_adapter *jme, u16 flags, struct sk_buff *skb)
995 {
996 if (!(flags & (RXWBFLAG_TCPON | RXWBFLAG_UDPON | RXWBFLAG_IPV4)))
997 return false;
998
999 if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_TCPON | RXWBFLAG_TCPCS))
1000 == RXWBFLAG_TCPON)) {
1001 if (flags & RXWBFLAG_IPV4)
1002 netif_err(jme, rx_err, jme->dev, "TCP Checksum error\n");
1003 return false;
1004 }
1005
1006 if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_UDPON | RXWBFLAG_UDPCS))
1007 == RXWBFLAG_UDPON) && jme_udpsum(skb)) {
1008 if (flags & RXWBFLAG_IPV4)
1009 netif_err(jme, rx_err, jme->dev, "UDP Checksum error\n");
1010 return false;
1011 }
1012
1013 if (unlikely((flags & (RXWBFLAG_IPV4 | RXWBFLAG_IPCS))
1014 == RXWBFLAG_IPV4)) {
1015 netif_err(jme, rx_err, jme->dev, "IPv4 Checksum error\n");
1016 return false;
1017 }
1018
1019 return true;
1020 }
1021
1022 static void
1023 jme_alloc_and_feed_skb(struct jme_adapter *jme, int idx)
1024 {
1025 struct jme_ring *rxring = &(jme->rxring[0]);
1026 struct rxdesc *rxdesc = rxring->desc;
1027 struct jme_buffer_info *rxbi = rxring->bufinf;
1028 struct sk_buff *skb;
1029 int framesize;
1030
1031 rxdesc += idx;
1032 rxbi += idx;
1033
1034 skb = rxbi->skb;
1035 pci_dma_sync_single_for_cpu(jme->pdev,
1036 rxbi->mapping,
1037 rxbi->len,
1038 PCI_DMA_FROMDEVICE);
1039
1040 if (unlikely(jme_make_new_rx_buf(jme, idx))) {
1041 pci_dma_sync_single_for_device(jme->pdev,
1042 rxbi->mapping,
1043 rxbi->len,
1044 PCI_DMA_FROMDEVICE);
1045
1046 ++(NET_STAT(jme).rx_dropped);
1047 } else {
1048 framesize = le16_to_cpu(rxdesc->descwb.framesize)
1049 - RX_PREPAD_SIZE;
1050
1051 skb_reserve(skb, RX_PREPAD_SIZE);
1052 skb_put(skb, framesize);
1053 skb->protocol = eth_type_trans(skb, jme->dev);
1054
1055 if (jme_rxsum_ok(jme, le16_to_cpu(rxdesc->descwb.flags), skb))
1056 skb->ip_summed = CHECKSUM_UNNECESSARY;
1057 else
1058 skb_checksum_none_assert(skb);
1059
1060 if (rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_TAGON)) {
1061 if (jme->vlgrp) {
1062 jme->jme_vlan_rx(skb, jme->vlgrp,
1063 le16_to_cpu(rxdesc->descwb.vlan));
1064 NET_STAT(jme).rx_bytes += 4;
1065 } else {
1066 dev_kfree_skb(skb);
1067 }
1068 } else {
1069 jme->jme_rx(skb);
1070 }
1071
1072 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_DEST)) ==
1073 cpu_to_le16(RXWBFLAG_DEST_MUL))
1074 ++(NET_STAT(jme).multicast);
1075
1076 NET_STAT(jme).rx_bytes += framesize;
1077 ++(NET_STAT(jme).rx_packets);
1078 }
1079
1080 jme_set_clean_rxdesc(jme, idx);
1081
1082 }
1083
1084 static int
1085 jme_process_receive(struct jme_adapter *jme, int limit)
1086 {
1087 struct jme_ring *rxring = &(jme->rxring[0]);
1088 struct rxdesc *rxdesc = rxring->desc;
1089 int i, j, ccnt, desccnt, mask = jme->rx_ring_mask;
1090
1091 if (unlikely(!atomic_dec_and_test(&jme->rx_cleaning)))
1092 goto out_inc;
1093
1094 if (unlikely(atomic_read(&jme->link_changing) != 1))
1095 goto out_inc;
1096
1097 if (unlikely(!netif_carrier_ok(jme->dev)))
1098 goto out_inc;
1099
1100 i = atomic_read(&rxring->next_to_clean);
1101 while (limit > 0) {
1102 rxdesc = rxring->desc;
1103 rxdesc += i;
1104
1105 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_OWN)) ||
1106 !(rxdesc->descwb.desccnt & RXWBDCNT_WBCPL))
1107 goto out;
1108 --limit;
1109
1110 rmb();
1111 desccnt = rxdesc->descwb.desccnt & RXWBDCNT_DCNT;
1112
1113 if (unlikely(desccnt > 1 ||
1114 rxdesc->descwb.errstat & RXWBERR_ALLERR)) {
1115
1116 if (rxdesc->descwb.errstat & RXWBERR_CRCERR)
1117 ++(NET_STAT(jme).rx_crc_errors);
1118 else if (rxdesc->descwb.errstat & RXWBERR_OVERUN)
1119 ++(NET_STAT(jme).rx_fifo_errors);
1120 else
1121 ++(NET_STAT(jme).rx_errors);
1122
1123 if (desccnt > 1)
1124 limit -= desccnt - 1;
1125
1126 for (j = i, ccnt = desccnt ; ccnt-- ; ) {
1127 jme_set_clean_rxdesc(jme, j);
1128 j = (j + 1) & (mask);
1129 }
1130
1131 } else {
1132 jme_alloc_and_feed_skb(jme, i);
1133 }
1134
1135 i = (i + desccnt) & (mask);
1136 }
1137
1138 out:
1139 atomic_set(&rxring->next_to_clean, i);
1140
1141 out_inc:
1142 atomic_inc(&jme->rx_cleaning);
1143
1144 return limit > 0 ? limit : 0;
1145
1146 }
1147
1148 static void
1149 jme_attempt_pcc(struct dynpcc_info *dpi, int atmp)
1150 {
1151 if (likely(atmp == dpi->cur)) {
1152 dpi->cnt = 0;
1153 return;
1154 }
1155
1156 if (dpi->attempt == atmp) {
1157 ++(dpi->cnt);
1158 } else {
1159 dpi->attempt = atmp;
1160 dpi->cnt = 0;
1161 }
1162
1163 }
1164
1165 static void
1166 jme_dynamic_pcc(struct jme_adapter *jme)
1167 {
1168 register struct dynpcc_info *dpi = &(jme->dpi);
1169
1170 if ((NET_STAT(jme).rx_bytes - dpi->last_bytes) > PCC_P3_THRESHOLD)
1171 jme_attempt_pcc(dpi, PCC_P3);
1172 else if ((NET_STAT(jme).rx_packets - dpi->last_pkts) > PCC_P2_THRESHOLD ||
1173 dpi->intr_cnt > PCC_INTR_THRESHOLD)
1174 jme_attempt_pcc(dpi, PCC_P2);
1175 else
1176 jme_attempt_pcc(dpi, PCC_P1);
1177
1178 if (unlikely(dpi->attempt != dpi->cur && dpi->cnt > 5)) {
1179 if (dpi->attempt < dpi->cur)
1180 tasklet_schedule(&jme->rxclean_task);
1181 jme_set_rx_pcc(jme, dpi->attempt);
1182 dpi->cur = dpi->attempt;
1183 dpi->cnt = 0;
1184 }
1185 }
1186
1187 static void
1188 jme_start_pcc_timer(struct jme_adapter *jme)
1189 {
1190 struct dynpcc_info *dpi = &(jme->dpi);
1191 dpi->last_bytes = NET_STAT(jme).rx_bytes;
1192 dpi->last_pkts = NET_STAT(jme).rx_packets;
1193 dpi->intr_cnt = 0;
1194 jwrite32(jme, JME_TMCSR,
1195 TMCSR_EN | ((0xFFFFFF - PCC_INTERVAL_US) & TMCSR_CNT));
1196 }
1197
1198 static inline void
1199 jme_stop_pcc_timer(struct jme_adapter *jme)
1200 {
1201 jwrite32(jme, JME_TMCSR, 0);
1202 }
1203
1204 static void
1205 jme_shutdown_nic(struct jme_adapter *jme)
1206 {
1207 u32 phylink;
1208
1209 phylink = jme_linkstat_from_phy(jme);
1210
1211 if (!(phylink & PHY_LINK_UP)) {
1212 /*
1213 * Disable all interrupt before issue timer
1214 */
1215 jme_stop_irq(jme);
1216 jwrite32(jme, JME_TIMER2, TMCSR_EN | 0xFFFFFE);
1217 }
1218 }
1219
1220 static void
1221 jme_pcc_tasklet(unsigned long arg)
1222 {
1223 struct jme_adapter *jme = (struct jme_adapter *)arg;
1224 struct net_device *netdev = jme->dev;
1225
1226 if (unlikely(test_bit(JME_FLAG_SHUTDOWN, &jme->flags))) {
1227 jme_shutdown_nic(jme);
1228 return;
1229 }
1230
1231 if (unlikely(!netif_carrier_ok(netdev) ||
1232 (atomic_read(&jme->link_changing) != 1)
1233 )) {
1234 jme_stop_pcc_timer(jme);
1235 return;
1236 }
1237
1238 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
1239 jme_dynamic_pcc(jme);
1240
1241 jme_start_pcc_timer(jme);
1242 }
1243
1244 static inline void
1245 jme_polling_mode(struct jme_adapter *jme)
1246 {
1247 jme_set_rx_pcc(jme, PCC_OFF);
1248 }
1249
1250 static inline void
1251 jme_interrupt_mode(struct jme_adapter *jme)
1252 {
1253 jme_set_rx_pcc(jme, PCC_P1);
1254 }
1255
1256 static inline int
1257 jme_pseudo_hotplug_enabled(struct jme_adapter *jme)
1258 {
1259 u32 apmc;
1260 apmc = jread32(jme, JME_APMC);
1261 return apmc & JME_APMC_PSEUDO_HP_EN;
1262 }
1263
1264 static void
1265 jme_start_shutdown_timer(struct jme_adapter *jme)
1266 {
1267 u32 apmc;
1268
1269 apmc = jread32(jme, JME_APMC) | JME_APMC_PCIE_SD_EN;
1270 apmc &= ~JME_APMC_EPIEN_CTRL;
1271 if (!no_extplug) {
1272 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_EN);
1273 wmb();
1274 }
1275 jwrite32f(jme, JME_APMC, apmc);
1276
1277 jwrite32f(jme, JME_TIMER2, 0);
1278 set_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1279 jwrite32(jme, JME_TMCSR,
1280 TMCSR_EN | ((0xFFFFFF - APMC_PHP_SHUTDOWN_DELAY) & TMCSR_CNT));
1281 }
1282
1283 static void
1284 jme_stop_shutdown_timer(struct jme_adapter *jme)
1285 {
1286 u32 apmc;
1287
1288 jwrite32f(jme, JME_TMCSR, 0);
1289 jwrite32f(jme, JME_TIMER2, 0);
1290 clear_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1291
1292 apmc = jread32(jme, JME_APMC);
1293 apmc &= ~(JME_APMC_PCIE_SD_EN | JME_APMC_EPIEN_CTRL);
1294 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_DIS);
1295 wmb();
1296 jwrite32f(jme, JME_APMC, apmc);
1297 }
1298
1299 static void
1300 jme_link_change_tasklet(unsigned long arg)
1301 {
1302 struct jme_adapter *jme = (struct jme_adapter *)arg;
1303 struct net_device *netdev = jme->dev;
1304 int rc;
1305
1306 while (!atomic_dec_and_test(&jme->link_changing)) {
1307 atomic_inc(&jme->link_changing);
1308 netif_info(jme, intr, jme->dev, "Get link change lock failed\n");
1309 while (atomic_read(&jme->link_changing) != 1)
1310 netif_info(jme, intr, jme->dev, "Waiting link change lock\n");
1311 }
1312
1313 if (jme_check_link(netdev, 1) && jme->old_mtu == netdev->mtu)
1314 goto out;
1315
1316 jme->old_mtu = netdev->mtu;
1317 netif_stop_queue(netdev);
1318 if (jme_pseudo_hotplug_enabled(jme))
1319 jme_stop_shutdown_timer(jme);
1320
1321 jme_stop_pcc_timer(jme);
1322 tasklet_disable(&jme->txclean_task);
1323 tasklet_disable(&jme->rxclean_task);
1324 tasklet_disable(&jme->rxempty_task);
1325
1326 if (netif_carrier_ok(netdev)) {
1327 jme_disable_rx_engine(jme);
1328 jme_disable_tx_engine(jme);
1329 jme_reset_mac_processor(jme);
1330 jme_free_rx_resources(jme);
1331 jme_free_tx_resources(jme);
1332
1333 if (test_bit(JME_FLAG_POLL, &jme->flags))
1334 jme_polling_mode(jme);
1335
1336 netif_carrier_off(netdev);
1337 }
1338
1339 jme_check_link(netdev, 0);
1340 if (netif_carrier_ok(netdev)) {
1341 rc = jme_setup_rx_resources(jme);
1342 if (rc) {
1343 pr_err("Allocating resources for RX error, Device STOPPED!\n");
1344 goto out_enable_tasklet;
1345 }
1346
1347 rc = jme_setup_tx_resources(jme);
1348 if (rc) {
1349 pr_err("Allocating resources for TX error, Device STOPPED!\n");
1350 goto err_out_free_rx_resources;
1351 }
1352
1353 jme_enable_rx_engine(jme);
1354 jme_enable_tx_engine(jme);
1355
1356 netif_start_queue(netdev);
1357
1358 if (test_bit(JME_FLAG_POLL, &jme->flags))
1359 jme_interrupt_mode(jme);
1360
1361 jme_start_pcc_timer(jme);
1362 } else if (jme_pseudo_hotplug_enabled(jme)) {
1363 jme_start_shutdown_timer(jme);
1364 }
1365
1366 goto out_enable_tasklet;
1367
1368 err_out_free_rx_resources:
1369 jme_free_rx_resources(jme);
1370 out_enable_tasklet:
1371 tasklet_enable(&jme->txclean_task);
1372 tasklet_hi_enable(&jme->rxclean_task);
1373 tasklet_hi_enable(&jme->rxempty_task);
1374 out:
1375 atomic_inc(&jme->link_changing);
1376 }
1377
1378 static void
1379 jme_rx_clean_tasklet(unsigned long arg)
1380 {
1381 struct jme_adapter *jme = (struct jme_adapter *)arg;
1382 struct dynpcc_info *dpi = &(jme->dpi);
1383
1384 jme_process_receive(jme, jme->rx_ring_size);
1385 ++(dpi->intr_cnt);
1386
1387 }
1388
1389 static int
1390 jme_poll(JME_NAPI_HOLDER(holder), JME_NAPI_WEIGHT(budget))
1391 {
1392 struct jme_adapter *jme = jme_napi_priv(holder);
1393 int rest;
1394
1395 rest = jme_process_receive(jme, JME_NAPI_WEIGHT_VAL(budget));
1396
1397 while (atomic_read(&jme->rx_empty) > 0) {
1398 atomic_dec(&jme->rx_empty);
1399 ++(NET_STAT(jme).rx_dropped);
1400 jme_restart_rx_engine(jme);
1401 }
1402 atomic_inc(&jme->rx_empty);
1403
1404 if (rest) {
1405 JME_RX_COMPLETE(netdev, holder);
1406 jme_interrupt_mode(jme);
1407 }
1408
1409 JME_NAPI_WEIGHT_SET(budget, rest);
1410 return JME_NAPI_WEIGHT_VAL(budget) - rest;
1411 }
1412
1413 static void
1414 jme_rx_empty_tasklet(unsigned long arg)
1415 {
1416 struct jme_adapter *jme = (struct jme_adapter *)arg;
1417
1418 if (unlikely(atomic_read(&jme->link_changing) != 1))
1419 return;
1420
1421 if (unlikely(!netif_carrier_ok(jme->dev)))
1422 return;
1423
1424 netif_info(jme, rx_status, jme->dev, "RX Queue Full!\n");
1425
1426 jme_rx_clean_tasklet(arg);
1427
1428 while (atomic_read(&jme->rx_empty) > 0) {
1429 atomic_dec(&jme->rx_empty);
1430 ++(NET_STAT(jme).rx_dropped);
1431 jme_restart_rx_engine(jme);
1432 }
1433 atomic_inc(&jme->rx_empty);
1434 }
1435
1436 static void
1437 jme_wake_queue_if_stopped(struct jme_adapter *jme)
1438 {
1439 struct jme_ring *txring = &(jme->txring[0]);
1440
1441 smp_wmb();
1442 if (unlikely(netif_queue_stopped(jme->dev) &&
1443 atomic_read(&txring->nr_free) >= (jme->tx_wake_threshold))) {
1444 netif_info(jme, tx_done, jme->dev, "TX Queue Waked\n");
1445 netif_wake_queue(jme->dev);
1446 }
1447
1448 }
1449
1450 static void
1451 jme_tx_clean_tasklet(unsigned long arg)
1452 {
1453 struct jme_adapter *jme = (struct jme_adapter *)arg;
1454 struct jme_ring *txring = &(jme->txring[0]);
1455 struct txdesc *txdesc = txring->desc;
1456 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi, *ttxbi;
1457 int i, j, cnt = 0, max, err, mask;
1458
1459 tx_dbg(jme, "Into txclean\n");
1460
1461 if (unlikely(!atomic_dec_and_test(&jme->tx_cleaning)))
1462 goto out;
1463
1464 if (unlikely(atomic_read(&jme->link_changing) != 1))
1465 goto out;
1466
1467 if (unlikely(!netif_carrier_ok(jme->dev)))
1468 goto out;
1469
1470 max = jme->tx_ring_size - atomic_read(&txring->nr_free);
1471 mask = jme->tx_ring_mask;
1472
1473 for (i = atomic_read(&txring->next_to_clean) ; cnt < max ; ) {
1474
1475 ctxbi = txbi + i;
1476
1477 if (likely(ctxbi->skb &&
1478 !(txdesc[i].descwb.flags & TXWBFLAG_OWN))) {
1479
1480 tx_dbg(jme, "txclean: %d+%d@%lu\n",
1481 i, ctxbi->nr_desc, jiffies);
1482
1483 err = txdesc[i].descwb.flags & TXWBFLAG_ALLERR;
1484
1485 for (j = 1 ; j < ctxbi->nr_desc ; ++j) {
1486 ttxbi = txbi + ((i + j) & (mask));
1487 txdesc[(i + j) & (mask)].dw[0] = 0;
1488
1489 pci_unmap_page(jme->pdev,
1490 ttxbi->mapping,
1491 ttxbi->len,
1492 PCI_DMA_TODEVICE);
1493
1494 ttxbi->mapping = 0;
1495 ttxbi->len = 0;
1496 }
1497
1498 dev_kfree_skb(ctxbi->skb);
1499
1500 cnt += ctxbi->nr_desc;
1501
1502 if (unlikely(err)) {
1503 ++(NET_STAT(jme).tx_carrier_errors);
1504 } else {
1505 ++(NET_STAT(jme).tx_packets);
1506 NET_STAT(jme).tx_bytes += ctxbi->len;
1507 }
1508
1509 ctxbi->skb = NULL;
1510 ctxbi->len = 0;
1511 ctxbi->start_xmit = 0;
1512
1513 } else {
1514 break;
1515 }
1516
1517 i = (i + ctxbi->nr_desc) & mask;
1518
1519 ctxbi->nr_desc = 0;
1520 }
1521
1522 tx_dbg(jme, "txclean: done %d@%lu\n", i, jiffies);
1523 atomic_set(&txring->next_to_clean, i);
1524 atomic_add(cnt, &txring->nr_free);
1525
1526 jme_wake_queue_if_stopped(jme);
1527
1528 out:
1529 atomic_inc(&jme->tx_cleaning);
1530 }
1531
1532 static void
1533 jme_intr_msi(struct jme_adapter *jme, u32 intrstat)
1534 {
1535 /*
1536 * Disable interrupt
1537 */
1538 jwrite32f(jme, JME_IENC, INTR_ENABLE);
1539
1540 if (intrstat & (INTR_LINKCH | INTR_SWINTR)) {
1541 /*
1542 * Link change event is critical
1543 * all other events are ignored
1544 */
1545 jwrite32(jme, JME_IEVE, intrstat);
1546 tasklet_schedule(&jme->linkch_task);
1547 goto out_reenable;
1548 }
1549
1550 if (intrstat & INTR_TMINTR) {
1551 jwrite32(jme, JME_IEVE, INTR_TMINTR);
1552 tasklet_schedule(&jme->pcc_task);
1553 }
1554
1555 if (intrstat & (INTR_PCCTXTO | INTR_PCCTX)) {
1556 jwrite32(jme, JME_IEVE, INTR_PCCTXTO | INTR_PCCTX | INTR_TX0);
1557 tasklet_schedule(&jme->txclean_task);
1558 }
1559
1560 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1561 jwrite32(jme, JME_IEVE, (intrstat & (INTR_PCCRX0TO |
1562 INTR_PCCRX0 |
1563 INTR_RX0EMP)) |
1564 INTR_RX0);
1565 }
1566
1567 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
1568 if (intrstat & INTR_RX0EMP)
1569 atomic_inc(&jme->rx_empty);
1570
1571 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1572 if (likely(JME_RX_SCHEDULE_PREP(jme))) {
1573 jme_polling_mode(jme);
1574 JME_RX_SCHEDULE(jme);
1575 }
1576 }
1577 } else {
1578 if (intrstat & INTR_RX0EMP) {
1579 atomic_inc(&jme->rx_empty);
1580 tasklet_hi_schedule(&jme->rxempty_task);
1581 } else if (intrstat & (INTR_PCCRX0TO | INTR_PCCRX0)) {
1582 tasklet_hi_schedule(&jme->rxclean_task);
1583 }
1584 }
1585
1586 out_reenable:
1587 /*
1588 * Re-enable interrupt
1589 */
1590 jwrite32f(jme, JME_IENS, INTR_ENABLE);
1591 }
1592
1593 static irqreturn_t
1594 jme_intr(int irq, void *dev_id)
1595 {
1596 struct net_device *netdev = dev_id;
1597 struct jme_adapter *jme = netdev_priv(netdev);
1598 u32 intrstat;
1599
1600 intrstat = jread32(jme, JME_IEVE);
1601
1602 /*
1603 * Check if it's really an interrupt for us
1604 */
1605 if (unlikely((intrstat & INTR_ENABLE) == 0))
1606 return IRQ_NONE;
1607
1608 /*
1609 * Check if the device still exist
1610 */
1611 if (unlikely(intrstat == ~((typeof(intrstat))0)))
1612 return IRQ_NONE;
1613
1614 jme_intr_msi(jme, intrstat);
1615
1616 return IRQ_HANDLED;
1617 }
1618
1619 static irqreturn_t
1620 jme_msi(int irq, void *dev_id)
1621 {
1622 struct net_device *netdev = dev_id;
1623 struct jme_adapter *jme = netdev_priv(netdev);
1624 u32 intrstat;
1625
1626 intrstat = jread32(jme, JME_IEVE);
1627
1628 jme_intr_msi(jme, intrstat);
1629
1630 return IRQ_HANDLED;
1631 }
1632
1633 static void
1634 jme_reset_link(struct jme_adapter *jme)
1635 {
1636 jwrite32(jme, JME_TMCSR, TMCSR_SWIT);
1637 }
1638
1639 static void
1640 jme_restart_an(struct jme_adapter *jme)
1641 {
1642 u32 bmcr;
1643
1644 spin_lock_bh(&jme->phy_lock);
1645 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1646 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1647 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1648 spin_unlock_bh(&jme->phy_lock);
1649 }
1650
1651 static int
1652 jme_request_irq(struct jme_adapter *jme)
1653 {
1654 int rc;
1655 struct net_device *netdev = jme->dev;
1656 irq_handler_t handler = jme_intr;
1657 int irq_flags = IRQF_SHARED;
1658
1659 if (!pci_enable_msi(jme->pdev)) {
1660 set_bit(JME_FLAG_MSI, &jme->flags);
1661 handler = jme_msi;
1662 irq_flags = 0;
1663 }
1664
1665 rc = request_irq(jme->pdev->irq, handler, irq_flags, netdev->name,
1666 netdev);
1667 if (rc) {
1668 netdev_err(netdev,
1669 "Unable to request %s interrupt (return: %d)\n",
1670 test_bit(JME_FLAG_MSI, &jme->flags) ? "MSI" : "INTx",
1671 rc);
1672
1673 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1674 pci_disable_msi(jme->pdev);
1675 clear_bit(JME_FLAG_MSI, &jme->flags);
1676 }
1677 } else {
1678 netdev->irq = jme->pdev->irq;
1679 }
1680
1681 return rc;
1682 }
1683
1684 static void
1685 jme_free_irq(struct jme_adapter *jme)
1686 {
1687 free_irq(jme->pdev->irq, jme->dev);
1688 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1689 pci_disable_msi(jme->pdev);
1690 clear_bit(JME_FLAG_MSI, &jme->flags);
1691 jme->dev->irq = jme->pdev->irq;
1692 }
1693 }
1694
1695 static inline void
1696 jme_new_phy_on(struct jme_adapter *jme)
1697 {
1698 u32 reg;
1699
1700 reg = jread32(jme, JME_PHY_PWR);
1701 reg &= ~(PHY_PWR_DWN1SEL | PHY_PWR_DWN1SW |
1702 PHY_PWR_DWN2 | PHY_PWR_CLKSEL);
1703 jwrite32(jme, JME_PHY_PWR, reg);
1704
1705 pci_read_config_dword(jme->pdev, PCI_PRIV_PE1, &reg);
1706 reg &= ~PE1_GPREG0_PBG;
1707 reg |= PE1_GPREG0_ENBG;
1708 pci_write_config_dword(jme->pdev, PCI_PRIV_PE1, reg);
1709 }
1710
1711 static inline void
1712 jme_new_phy_off(struct jme_adapter *jme)
1713 {
1714 u32 reg;
1715
1716 reg = jread32(jme, JME_PHY_PWR);
1717 reg |= PHY_PWR_DWN1SEL | PHY_PWR_DWN1SW |
1718 PHY_PWR_DWN2 | PHY_PWR_CLKSEL;
1719 jwrite32(jme, JME_PHY_PWR, reg);
1720
1721 pci_read_config_dword(jme->pdev, PCI_PRIV_PE1, &reg);
1722 reg &= ~PE1_GPREG0_PBG;
1723 reg |= PE1_GPREG0_PDD3COLD;
1724 pci_write_config_dword(jme->pdev, PCI_PRIV_PE1, reg);
1725 }
1726
1727 static inline void
1728 jme_phy_on(struct jme_adapter *jme)
1729 {
1730 u32 bmcr;
1731
1732 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1733 bmcr &= ~BMCR_PDOWN;
1734 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1735
1736 if (new_phy_power_ctrl(jme->chip_main_rev))
1737 jme_new_phy_on(jme);
1738 }
1739
1740 static inline void
1741 jme_phy_off(struct jme_adapter *jme)
1742 {
1743 u32 bmcr;
1744
1745 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1746 bmcr |= BMCR_PDOWN;
1747 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1748
1749 if (new_phy_power_ctrl(jme->chip_main_rev))
1750 jme_new_phy_off(jme);
1751 }
1752
1753 static int
1754 jme_open(struct net_device *netdev)
1755 {
1756 struct jme_adapter *jme = netdev_priv(netdev);
1757 int rc;
1758
1759 jme_clear_pm(jme);
1760 JME_NAPI_ENABLE(jme);
1761
1762 tasklet_enable(&jme->linkch_task);
1763 tasklet_enable(&jme->txclean_task);
1764 tasklet_hi_enable(&jme->rxclean_task);
1765 tasklet_hi_enable(&jme->rxempty_task);
1766
1767 rc = jme_request_irq(jme);
1768 if (rc)
1769 goto err_out;
1770
1771 jme_start_irq(jme);
1772
1773 jme_phy_on(jme);
1774 if (test_bit(JME_FLAG_SSET, &jme->flags))
1775 jme_set_settings(netdev, &jme->old_ecmd);
1776 else
1777 jme_reset_phy_processor(jme);
1778
1779 jme_reset_link(jme);
1780
1781 return 0;
1782
1783 err_out:
1784 netif_stop_queue(netdev);
1785 netif_carrier_off(netdev);
1786 return rc;
1787 }
1788
1789 static void
1790 jme_set_100m_half(struct jme_adapter *jme)
1791 {
1792 u32 bmcr, tmp;
1793
1794 jme_phy_on(jme);
1795 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1796 tmp = bmcr & ~(BMCR_ANENABLE | BMCR_SPEED100 |
1797 BMCR_SPEED1000 | BMCR_FULLDPLX);
1798 tmp |= BMCR_SPEED100;
1799
1800 if (bmcr != tmp)
1801 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, tmp);
1802
1803 if (jme->fpgaver)
1804 jwrite32(jme, JME_GHC, GHC_SPEED_100M | GHC_LINK_POLL);
1805 else
1806 jwrite32(jme, JME_GHC, GHC_SPEED_100M);
1807 }
1808
1809 #define JME_WAIT_LINK_TIME 2000 /* 2000ms */
1810 static void
1811 jme_wait_link(struct jme_adapter *jme)
1812 {
1813 u32 phylink, to = JME_WAIT_LINK_TIME;
1814
1815 mdelay(1000);
1816 phylink = jme_linkstat_from_phy(jme);
1817 while (!(phylink & PHY_LINK_UP) && (to -= 10) > 0) {
1818 mdelay(10);
1819 phylink = jme_linkstat_from_phy(jme);
1820 }
1821 }
1822
1823 static void
1824 jme_powersave_phy(struct jme_adapter *jme)
1825 {
1826 if (jme->reg_pmcs) {
1827 jme_set_100m_half(jme);
1828
1829 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
1830 jme_wait_link(jme);
1831
1832 jwrite32(jme, JME_PMCS, jme->reg_pmcs);
1833 } else {
1834 jme_phy_off(jme);
1835 }
1836 }
1837
1838 static int
1839 jme_close(struct net_device *netdev)
1840 {
1841 struct jme_adapter *jme = netdev_priv(netdev);
1842
1843 netif_stop_queue(netdev);
1844 netif_carrier_off(netdev);
1845
1846 jme_stop_irq(jme);
1847 jme_free_irq(jme);
1848
1849 JME_NAPI_DISABLE(jme);
1850
1851 tasklet_disable(&jme->linkch_task);
1852 tasklet_disable(&jme->txclean_task);
1853 tasklet_disable(&jme->rxclean_task);
1854 tasklet_disable(&jme->rxempty_task);
1855
1856 jme_disable_rx_engine(jme);
1857 jme_disable_tx_engine(jme);
1858 jme_reset_mac_processor(jme);
1859 jme_free_rx_resources(jme);
1860 jme_free_tx_resources(jme);
1861 jme->phylink = 0;
1862 jme_phy_off(jme);
1863
1864 return 0;
1865 }
1866
1867 static int
1868 jme_alloc_txdesc(struct jme_adapter *jme,
1869 struct sk_buff *skb)
1870 {
1871 struct jme_ring *txring = &(jme->txring[0]);
1872 int idx, nr_alloc, mask = jme->tx_ring_mask;
1873
1874 idx = txring->next_to_use;
1875 nr_alloc = skb_shinfo(skb)->nr_frags + 2;
1876
1877 if (unlikely(atomic_read(&txring->nr_free) < nr_alloc))
1878 return -1;
1879
1880 atomic_sub(nr_alloc, &txring->nr_free);
1881
1882 txring->next_to_use = (txring->next_to_use + nr_alloc) & mask;
1883
1884 return idx;
1885 }
1886
1887 static void
1888 jme_fill_tx_map(struct pci_dev *pdev,
1889 struct txdesc *txdesc,
1890 struct jme_buffer_info *txbi,
1891 struct page *page,
1892 u32 page_offset,
1893 u32 len,
1894 u8 hidma)
1895 {
1896 dma_addr_t dmaaddr;
1897
1898 dmaaddr = pci_map_page(pdev,
1899 page,
1900 page_offset,
1901 len,
1902 PCI_DMA_TODEVICE);
1903
1904 pci_dma_sync_single_for_device(pdev,
1905 dmaaddr,
1906 len,
1907 PCI_DMA_TODEVICE);
1908
1909 txdesc->dw[0] = 0;
1910 txdesc->dw[1] = 0;
1911 txdesc->desc2.flags = TXFLAG_OWN;
1912 txdesc->desc2.flags |= (hidma) ? TXFLAG_64BIT : 0;
1913 txdesc->desc2.datalen = cpu_to_le16(len);
1914 txdesc->desc2.bufaddrh = cpu_to_le32((__u64)dmaaddr >> 32);
1915 txdesc->desc2.bufaddrl = cpu_to_le32(
1916 (__u64)dmaaddr & 0xFFFFFFFFUL);
1917
1918 txbi->mapping = dmaaddr;
1919 txbi->len = len;
1920 }
1921
1922 static void
1923 jme_map_tx_skb(struct jme_adapter *jme, struct sk_buff *skb, int idx)
1924 {
1925 struct jme_ring *txring = &(jme->txring[0]);
1926 struct txdesc *txdesc = txring->desc, *ctxdesc;
1927 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi;
1928 u8 hidma = jme->dev->features & NETIF_F_HIGHDMA;
1929 int i, nr_frags = skb_shinfo(skb)->nr_frags;
1930 int mask = jme->tx_ring_mask;
1931 struct skb_frag_struct *frag;
1932 u32 len;
1933
1934 for (i = 0 ; i < nr_frags ; ++i) {
1935 frag = &skb_shinfo(skb)->frags[i];
1936 ctxdesc = txdesc + ((idx + i + 2) & (mask));
1937 ctxbi = txbi + ((idx + i + 2) & (mask));
1938
1939 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, frag->page,
1940 frag->page_offset, frag->size, hidma);
1941 }
1942
1943 len = skb_is_nonlinear(skb) ? skb_headlen(skb) : skb->len;
1944 ctxdesc = txdesc + ((idx + 1) & (mask));
1945 ctxbi = txbi + ((idx + 1) & (mask));
1946 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, virt_to_page(skb->data),
1947 offset_in_page(skb->data), len, hidma);
1948
1949 }
1950
1951 static int
1952 jme_expand_header(struct jme_adapter *jme, struct sk_buff *skb)
1953 {
1954 if (unlikely(skb_shinfo(skb)->gso_size &&
1955 skb_header_cloned(skb) &&
1956 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))) {
1957 dev_kfree_skb(skb);
1958 return -1;
1959 }
1960
1961 return 0;
1962 }
1963
1964 static int
1965 jme_tx_tso(struct sk_buff *skb, __le16 *mss, u8 *flags)
1966 {
1967 *mss = cpu_to_le16(skb_shinfo(skb)->gso_size << TXDESC_MSS_SHIFT);
1968 if (*mss) {
1969 *flags |= TXFLAG_LSEN;
1970
1971 if (skb->protocol == htons(ETH_P_IP)) {
1972 struct iphdr *iph = ip_hdr(skb);
1973
1974 iph->check = 0;
1975 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
1976 iph->daddr, 0,
1977 IPPROTO_TCP,
1978 0);
1979 } else {
1980 struct ipv6hdr *ip6h = ipv6_hdr(skb);
1981
1982 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ip6h->saddr,
1983 &ip6h->daddr, 0,
1984 IPPROTO_TCP,
1985 0);
1986 }
1987
1988 return 0;
1989 }
1990
1991 return 1;
1992 }
1993
1994 static void
1995 jme_tx_csum(struct jme_adapter *jme, struct sk_buff *skb, u8 *flags)
1996 {
1997 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1998 u8 ip_proto;
1999
2000 switch (skb->protocol) {
2001 case htons(ETH_P_IP):
2002 ip_proto = ip_hdr(skb)->protocol;
2003 break;
2004 case htons(ETH_P_IPV6):
2005 ip_proto = ipv6_hdr(skb)->nexthdr;
2006 break;
2007 default:
2008 ip_proto = 0;
2009 break;
2010 }
2011
2012 switch (ip_proto) {
2013 case IPPROTO_TCP:
2014 *flags |= TXFLAG_TCPCS;
2015 break;
2016 case IPPROTO_UDP:
2017 *flags |= TXFLAG_UDPCS;
2018 break;
2019 default:
2020 netif_err(jme, tx_err, jme->dev, "Error upper layer protocol\n");
2021 break;
2022 }
2023 }
2024 }
2025
2026 static inline void
2027 jme_tx_vlan(struct sk_buff *skb, __le16 *vlan, u8 *flags)
2028 {
2029 if (vlan_tx_tag_present(skb)) {
2030 *flags |= TXFLAG_TAGON;
2031 *vlan = cpu_to_le16(vlan_tx_tag_get(skb));
2032 }
2033 }
2034
2035 static int
2036 jme_fill_tx_desc(struct jme_adapter *jme, struct sk_buff *skb, int idx)
2037 {
2038 struct jme_ring *txring = &(jme->txring[0]);
2039 struct txdesc *txdesc;
2040 struct jme_buffer_info *txbi;
2041 u8 flags;
2042
2043 txdesc = (struct txdesc *)txring->desc + idx;
2044 txbi = txring->bufinf + idx;
2045
2046 txdesc->dw[0] = 0;
2047 txdesc->dw[1] = 0;
2048 txdesc->dw[2] = 0;
2049 txdesc->dw[3] = 0;
2050 txdesc->desc1.pktsize = cpu_to_le16(skb->len);
2051 /*
2052 * Set OWN bit at final.
2053 * When kernel transmit faster than NIC.
2054 * And NIC trying to send this descriptor before we tell
2055 * it to start sending this TX queue.
2056 * Other fields are already filled correctly.
2057 */
2058 wmb();
2059 flags = TXFLAG_OWN | TXFLAG_INT;
2060 /*
2061 * Set checksum flags while not tso
2062 */
2063 if (jme_tx_tso(skb, &txdesc->desc1.mss, &flags))
2064 jme_tx_csum(jme, skb, &flags);
2065 jme_tx_vlan(skb, &txdesc->desc1.vlan, &flags);
2066 jme_map_tx_skb(jme, skb, idx);
2067 txdesc->desc1.flags = flags;
2068 /*
2069 * Set tx buffer info after telling NIC to send
2070 * For better tx_clean timing
2071 */
2072 wmb();
2073 txbi->nr_desc = skb_shinfo(skb)->nr_frags + 2;
2074 txbi->skb = skb;
2075 txbi->len = skb->len;
2076 txbi->start_xmit = jiffies;
2077 if (!txbi->start_xmit)
2078 txbi->start_xmit = (0UL-1);
2079
2080 return 0;
2081 }
2082
2083 static void
2084 jme_stop_queue_if_full(struct jme_adapter *jme)
2085 {
2086 struct jme_ring *txring = &(jme->txring[0]);
2087 struct jme_buffer_info *txbi = txring->bufinf;
2088 int idx = atomic_read(&txring->next_to_clean);
2089
2090 txbi += idx;
2091
2092 smp_wmb();
2093 if (unlikely(atomic_read(&txring->nr_free) < (MAX_SKB_FRAGS+2))) {
2094 netif_stop_queue(jme->dev);
2095 netif_info(jme, tx_queued, jme->dev, "TX Queue Paused\n");
2096 smp_wmb();
2097 if (atomic_read(&txring->nr_free)
2098 >= (jme->tx_wake_threshold)) {
2099 netif_wake_queue(jme->dev);
2100 netif_info(jme, tx_queued, jme->dev, "TX Queue Fast Waked\n");
2101 }
2102 }
2103
2104 if (unlikely(txbi->start_xmit &&
2105 (jiffies - txbi->start_xmit) >= TX_TIMEOUT &&
2106 txbi->skb)) {
2107 netif_stop_queue(jme->dev);
2108 netif_info(jme, tx_queued, jme->dev,
2109 "TX Queue Stopped %d@%lu\n", idx, jiffies);
2110 }
2111 }
2112
2113 /*
2114 * This function is already protected by netif_tx_lock()
2115 */
2116
2117 static netdev_tx_t
2118 jme_start_xmit(struct sk_buff *skb, struct net_device *netdev)
2119 {
2120 struct jme_adapter *jme = netdev_priv(netdev);
2121 int idx;
2122
2123 if (unlikely(jme_expand_header(jme, skb))) {
2124 ++(NET_STAT(jme).tx_dropped);
2125 return NETDEV_TX_OK;
2126 }
2127
2128 idx = jme_alloc_txdesc(jme, skb);
2129
2130 if (unlikely(idx < 0)) {
2131 netif_stop_queue(netdev);
2132 netif_err(jme, tx_err, jme->dev,
2133 "BUG! Tx ring full when queue awake!\n");
2134
2135 return NETDEV_TX_BUSY;
2136 }
2137
2138 jme_fill_tx_desc(jme, skb, idx);
2139
2140 jwrite32(jme, JME_TXCS, jme->reg_txcs |
2141 TXCS_SELECT_QUEUE0 |
2142 TXCS_QUEUE0S |
2143 TXCS_ENABLE);
2144
2145 tx_dbg(jme, "xmit: %d+%d@%lu\n",
2146 idx, skb_shinfo(skb)->nr_frags + 2, jiffies);
2147 jme_stop_queue_if_full(jme);
2148
2149 return NETDEV_TX_OK;
2150 }
2151
2152 static void
2153 jme_set_unicastaddr(struct net_device *netdev)
2154 {
2155 struct jme_adapter *jme = netdev_priv(netdev);
2156 u32 val;
2157
2158 val = (netdev->dev_addr[3] & 0xff) << 24 |
2159 (netdev->dev_addr[2] & 0xff) << 16 |
2160 (netdev->dev_addr[1] & 0xff) << 8 |
2161 (netdev->dev_addr[0] & 0xff);
2162 jwrite32(jme, JME_RXUMA_LO, val);
2163 val = (netdev->dev_addr[5] & 0xff) << 8 |
2164 (netdev->dev_addr[4] & 0xff);
2165 jwrite32(jme, JME_RXUMA_HI, val);
2166 }
2167
2168 static int
2169 jme_set_macaddr(struct net_device *netdev, void *p)
2170 {
2171 struct jme_adapter *jme = netdev_priv(netdev);
2172 struct sockaddr *addr = p;
2173
2174 if (netif_running(netdev))
2175 return -EBUSY;
2176
2177 spin_lock_bh(&jme->macaddr_lock);
2178 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2179 jme_set_unicastaddr(netdev);
2180 spin_unlock_bh(&jme->macaddr_lock);
2181
2182 return 0;
2183 }
2184
2185 static void
2186 jme_set_multi(struct net_device *netdev)
2187 {
2188 struct jme_adapter *jme = netdev_priv(netdev);
2189 u32 mc_hash[2] = {};
2190
2191 spin_lock_bh(&jme->rxmcs_lock);
2192
2193 jme->reg_rxmcs |= RXMCS_BRDFRAME | RXMCS_UNIFRAME;
2194
2195 if (netdev->flags & IFF_PROMISC) {
2196 jme->reg_rxmcs |= RXMCS_ALLFRAME;
2197 } else if (netdev->flags & IFF_ALLMULTI) {
2198 jme->reg_rxmcs |= RXMCS_ALLMULFRAME;
2199 } else if (netdev->flags & IFF_MULTICAST) {
2200 struct netdev_hw_addr *ha;
2201 int bit_nr;
2202
2203 jme->reg_rxmcs |= RXMCS_MULFRAME | RXMCS_MULFILTERED;
2204 netdev_for_each_mc_addr(ha, netdev) {
2205 bit_nr = ether_crc(ETH_ALEN, ha->addr) & 0x3F;
2206 mc_hash[bit_nr >> 5] |= 1 << (bit_nr & 0x1F);
2207 }
2208
2209 jwrite32(jme, JME_RXMCHT_LO, mc_hash[0]);
2210 jwrite32(jme, JME_RXMCHT_HI, mc_hash[1]);
2211 }
2212
2213 wmb();
2214 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2215
2216 spin_unlock_bh(&jme->rxmcs_lock);
2217 }
2218
2219 static int
2220 jme_change_mtu(struct net_device *netdev, int new_mtu)
2221 {
2222 struct jme_adapter *jme = netdev_priv(netdev);
2223
2224 if (new_mtu == jme->old_mtu)
2225 return 0;
2226
2227 if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
2228 ((new_mtu) < IPV6_MIN_MTU))
2229 return -EINVAL;
2230
2231 if (new_mtu > 4000) {
2232 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2233 jme->reg_rxcs |= RXCS_FIFOTHNP_64QW;
2234 jme_restart_rx_engine(jme);
2235 } else {
2236 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2237 jme->reg_rxcs |= RXCS_FIFOTHNP_128QW;
2238 jme_restart_rx_engine(jme);
2239 }
2240
2241 netdev->mtu = new_mtu;
2242 netdev_update_features(netdev);
2243
2244 jme_reset_link(jme);
2245
2246 return 0;
2247 }
2248
2249 static void
2250 jme_tx_timeout(struct net_device *netdev)
2251 {
2252 struct jme_adapter *jme = netdev_priv(netdev);
2253
2254 jme->phylink = 0;
2255 jme_reset_phy_processor(jme);
2256 if (test_bit(JME_FLAG_SSET, &jme->flags))
2257 jme_set_settings(netdev, &jme->old_ecmd);
2258
2259 /*
2260 * Force to Reset the link again
2261 */
2262 jme_reset_link(jme);
2263 }
2264
2265 static inline void jme_pause_rx(struct jme_adapter *jme)
2266 {
2267 atomic_dec(&jme->link_changing);
2268
2269 jme_set_rx_pcc(jme, PCC_OFF);
2270 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2271 JME_NAPI_DISABLE(jme);
2272 } else {
2273 tasklet_disable(&jme->rxclean_task);
2274 tasklet_disable(&jme->rxempty_task);
2275 }
2276 }
2277
2278 static inline void jme_resume_rx(struct jme_adapter *jme)
2279 {
2280 struct dynpcc_info *dpi = &(jme->dpi);
2281
2282 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2283 JME_NAPI_ENABLE(jme);
2284 } else {
2285 tasklet_hi_enable(&jme->rxclean_task);
2286 tasklet_hi_enable(&jme->rxempty_task);
2287 }
2288 dpi->cur = PCC_P1;
2289 dpi->attempt = PCC_P1;
2290 dpi->cnt = 0;
2291 jme_set_rx_pcc(jme, PCC_P1);
2292
2293 atomic_inc(&jme->link_changing);
2294 }
2295
2296 static void
2297 jme_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp)
2298 {
2299 struct jme_adapter *jme = netdev_priv(netdev);
2300
2301 jme_pause_rx(jme);
2302 jme->vlgrp = grp;
2303 jme_resume_rx(jme);
2304 }
2305
2306 static void
2307 jme_get_drvinfo(struct net_device *netdev,
2308 struct ethtool_drvinfo *info)
2309 {
2310 struct jme_adapter *jme = netdev_priv(netdev);
2311
2312 strcpy(info->driver, DRV_NAME);
2313 strcpy(info->version, DRV_VERSION);
2314 strcpy(info->bus_info, pci_name(jme->pdev));
2315 }
2316
2317 static int
2318 jme_get_regs_len(struct net_device *netdev)
2319 {
2320 return JME_REG_LEN;
2321 }
2322
2323 static void
2324 mmapio_memcpy(struct jme_adapter *jme, u32 *p, u32 reg, int len)
2325 {
2326 int i;
2327
2328 for (i = 0 ; i < len ; i += 4)
2329 p[i >> 2] = jread32(jme, reg + i);
2330 }
2331
2332 static void
2333 mdio_memcpy(struct jme_adapter *jme, u32 *p, int reg_nr)
2334 {
2335 int i;
2336 u16 *p16 = (u16 *)p;
2337
2338 for (i = 0 ; i < reg_nr ; ++i)
2339 p16[i] = jme_mdio_read(jme->dev, jme->mii_if.phy_id, i);
2340 }
2341
2342 static void
2343 jme_get_regs(struct net_device *netdev, struct ethtool_regs *regs, void *p)
2344 {
2345 struct jme_adapter *jme = netdev_priv(netdev);
2346 u32 *p32 = (u32 *)p;
2347
2348 memset(p, 0xFF, JME_REG_LEN);
2349
2350 regs->version = 1;
2351 mmapio_memcpy(jme, p32, JME_MAC, JME_MAC_LEN);
2352
2353 p32 += 0x100 >> 2;
2354 mmapio_memcpy(jme, p32, JME_PHY, JME_PHY_LEN);
2355
2356 p32 += 0x100 >> 2;
2357 mmapio_memcpy(jme, p32, JME_MISC, JME_MISC_LEN);
2358
2359 p32 += 0x100 >> 2;
2360 mmapio_memcpy(jme, p32, JME_RSS, JME_RSS_LEN);
2361
2362 p32 += 0x100 >> 2;
2363 mdio_memcpy(jme, p32, JME_PHY_REG_NR);
2364 }
2365
2366 static int
2367 jme_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2368 {
2369 struct jme_adapter *jme = netdev_priv(netdev);
2370
2371 ecmd->tx_coalesce_usecs = PCC_TX_TO;
2372 ecmd->tx_max_coalesced_frames = PCC_TX_CNT;
2373
2374 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2375 ecmd->use_adaptive_rx_coalesce = false;
2376 ecmd->rx_coalesce_usecs = 0;
2377 ecmd->rx_max_coalesced_frames = 0;
2378 return 0;
2379 }
2380
2381 ecmd->use_adaptive_rx_coalesce = true;
2382
2383 switch (jme->dpi.cur) {
2384 case PCC_P1:
2385 ecmd->rx_coalesce_usecs = PCC_P1_TO;
2386 ecmd->rx_max_coalesced_frames = PCC_P1_CNT;
2387 break;
2388 case PCC_P2:
2389 ecmd->rx_coalesce_usecs = PCC_P2_TO;
2390 ecmd->rx_max_coalesced_frames = PCC_P2_CNT;
2391 break;
2392 case PCC_P3:
2393 ecmd->rx_coalesce_usecs = PCC_P3_TO;
2394 ecmd->rx_max_coalesced_frames = PCC_P3_CNT;
2395 break;
2396 default:
2397 break;
2398 }
2399
2400 return 0;
2401 }
2402
2403 static int
2404 jme_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2405 {
2406 struct jme_adapter *jme = netdev_priv(netdev);
2407 struct dynpcc_info *dpi = &(jme->dpi);
2408
2409 if (netif_running(netdev))
2410 return -EBUSY;
2411
2412 if (ecmd->use_adaptive_rx_coalesce &&
2413 test_bit(JME_FLAG_POLL, &jme->flags)) {
2414 clear_bit(JME_FLAG_POLL, &jme->flags);
2415 jme->jme_rx = netif_rx;
2416 jme->jme_vlan_rx = vlan_hwaccel_rx;
2417 dpi->cur = PCC_P1;
2418 dpi->attempt = PCC_P1;
2419 dpi->cnt = 0;
2420 jme_set_rx_pcc(jme, PCC_P1);
2421 jme_interrupt_mode(jme);
2422 } else if (!(ecmd->use_adaptive_rx_coalesce) &&
2423 !(test_bit(JME_FLAG_POLL, &jme->flags))) {
2424 set_bit(JME_FLAG_POLL, &jme->flags);
2425 jme->jme_rx = netif_receive_skb;
2426 jme->jme_vlan_rx = vlan_hwaccel_receive_skb;
2427 jme_interrupt_mode(jme);
2428 }
2429
2430 return 0;
2431 }
2432
2433 static void
2434 jme_get_pauseparam(struct net_device *netdev,
2435 struct ethtool_pauseparam *ecmd)
2436 {
2437 struct jme_adapter *jme = netdev_priv(netdev);
2438 u32 val;
2439
2440 ecmd->tx_pause = (jme->reg_txpfc & TXPFC_PF_EN) != 0;
2441 ecmd->rx_pause = (jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0;
2442
2443 spin_lock_bh(&jme->phy_lock);
2444 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2445 spin_unlock_bh(&jme->phy_lock);
2446
2447 ecmd->autoneg =
2448 (val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0;
2449 }
2450
2451 static int
2452 jme_set_pauseparam(struct net_device *netdev,
2453 struct ethtool_pauseparam *ecmd)
2454 {
2455 struct jme_adapter *jme = netdev_priv(netdev);
2456 u32 val;
2457
2458 if (((jme->reg_txpfc & TXPFC_PF_EN) != 0) ^
2459 (ecmd->tx_pause != 0)) {
2460
2461 if (ecmd->tx_pause)
2462 jme->reg_txpfc |= TXPFC_PF_EN;
2463 else
2464 jme->reg_txpfc &= ~TXPFC_PF_EN;
2465
2466 jwrite32(jme, JME_TXPFC, jme->reg_txpfc);
2467 }
2468
2469 spin_lock_bh(&jme->rxmcs_lock);
2470 if (((jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0) ^
2471 (ecmd->rx_pause != 0)) {
2472
2473 if (ecmd->rx_pause)
2474 jme->reg_rxmcs |= RXMCS_FLOWCTRL;
2475 else
2476 jme->reg_rxmcs &= ~RXMCS_FLOWCTRL;
2477
2478 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2479 }
2480 spin_unlock_bh(&jme->rxmcs_lock);
2481
2482 spin_lock_bh(&jme->phy_lock);
2483 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2484 if (((val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0) ^
2485 (ecmd->autoneg != 0)) {
2486
2487 if (ecmd->autoneg)
2488 val |= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2489 else
2490 val &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2491
2492 jme_mdio_write(jme->dev, jme->mii_if.phy_id,
2493 MII_ADVERTISE, val);
2494 }
2495 spin_unlock_bh(&jme->phy_lock);
2496
2497 return 0;
2498 }
2499
2500 static void
2501 jme_get_wol(struct net_device *netdev,
2502 struct ethtool_wolinfo *wol)
2503 {
2504 struct jme_adapter *jme = netdev_priv(netdev);
2505
2506 wol->supported = WAKE_MAGIC | WAKE_PHY;
2507
2508 wol->wolopts = 0;
2509
2510 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
2511 wol->wolopts |= WAKE_PHY;
2512
2513 if (jme->reg_pmcs & PMCS_MFEN)
2514 wol->wolopts |= WAKE_MAGIC;
2515
2516 }
2517
2518 static int
2519 jme_set_wol(struct net_device *netdev,
2520 struct ethtool_wolinfo *wol)
2521 {
2522 struct jme_adapter *jme = netdev_priv(netdev);
2523
2524 if (wol->wolopts & (WAKE_MAGICSECURE |
2525 WAKE_UCAST |
2526 WAKE_MCAST |
2527 WAKE_BCAST |
2528 WAKE_ARP))
2529 return -EOPNOTSUPP;
2530
2531 jme->reg_pmcs = 0;
2532
2533 if (wol->wolopts & WAKE_PHY)
2534 jme->reg_pmcs |= PMCS_LFEN | PMCS_LREN;
2535
2536 if (wol->wolopts & WAKE_MAGIC)
2537 jme->reg_pmcs |= PMCS_MFEN;
2538
2539 jwrite32(jme, JME_PMCS, jme->reg_pmcs);
2540
2541 device_set_wakeup_enable(&jme->pdev->dev, jme->reg_pmcs);
2542
2543 return 0;
2544 }
2545
2546 static int
2547 jme_get_settings(struct net_device *netdev,
2548 struct ethtool_cmd *ecmd)
2549 {
2550 struct jme_adapter *jme = netdev_priv(netdev);
2551 int rc;
2552
2553 spin_lock_bh(&jme->phy_lock);
2554 rc = mii_ethtool_gset(&(jme->mii_if), ecmd);
2555 spin_unlock_bh(&jme->phy_lock);
2556 return rc;
2557 }
2558
2559 static int
2560 jme_set_settings(struct net_device *netdev,
2561 struct ethtool_cmd *ecmd)
2562 {
2563 struct jme_adapter *jme = netdev_priv(netdev);
2564 int rc, fdc = 0;
2565
2566 if (ethtool_cmd_speed(ecmd) == SPEED_1000
2567 && ecmd->autoneg != AUTONEG_ENABLE)
2568 return -EINVAL;
2569
2570 /*
2571 * Check If user changed duplex only while force_media.
2572 * Hardware would not generate link change interrupt.
2573 */
2574 if (jme->mii_if.force_media &&
2575 ecmd->autoneg != AUTONEG_ENABLE &&
2576 (jme->mii_if.full_duplex != ecmd->duplex))
2577 fdc = 1;
2578
2579 spin_lock_bh(&jme->phy_lock);
2580 rc = mii_ethtool_sset(&(jme->mii_if), ecmd);
2581 spin_unlock_bh(&jme->phy_lock);
2582
2583 if (!rc) {
2584 if (fdc)
2585 jme_reset_link(jme);
2586 jme->old_ecmd = *ecmd;
2587 set_bit(JME_FLAG_SSET, &jme->flags);
2588 }
2589
2590 return rc;
2591 }
2592
2593 static int
2594 jme_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
2595 {
2596 int rc;
2597 struct jme_adapter *jme = netdev_priv(netdev);
2598 struct mii_ioctl_data *mii_data = if_mii(rq);
2599 unsigned int duplex_chg;
2600
2601 if (cmd == SIOCSMIIREG) {
2602 u16 val = mii_data->val_in;
2603 if (!(val & (BMCR_RESET|BMCR_ANENABLE)) &&
2604 (val & BMCR_SPEED1000))
2605 return -EINVAL;
2606 }
2607
2608 spin_lock_bh(&jme->phy_lock);
2609 rc = generic_mii_ioctl(&jme->mii_if, mii_data, cmd, &duplex_chg);
2610 spin_unlock_bh(&jme->phy_lock);
2611
2612 if (!rc && (cmd == SIOCSMIIREG)) {
2613 if (duplex_chg)
2614 jme_reset_link(jme);
2615 jme_get_settings(netdev, &jme->old_ecmd);
2616 set_bit(JME_FLAG_SSET, &jme->flags);
2617 }
2618
2619 return rc;
2620 }
2621
2622 static u32
2623 jme_get_link(struct net_device *netdev)
2624 {
2625 struct jme_adapter *jme = netdev_priv(netdev);
2626 return jread32(jme, JME_PHY_LINK) & PHY_LINK_UP;
2627 }
2628
2629 static u32
2630 jme_get_msglevel(struct net_device *netdev)
2631 {
2632 struct jme_adapter *jme = netdev_priv(netdev);
2633 return jme->msg_enable;
2634 }
2635
2636 static void
2637 jme_set_msglevel(struct net_device *netdev, u32 value)
2638 {
2639 struct jme_adapter *jme = netdev_priv(netdev);
2640 jme->msg_enable = value;
2641 }
2642
2643 static u32
2644 jme_fix_features(struct net_device *netdev, u32 features)
2645 {
2646 if (netdev->mtu > 1900)
2647 features &= ~(NETIF_F_ALL_TSO | NETIF_F_ALL_CSUM);
2648 return features;
2649 }
2650
2651 static int
2652 jme_set_features(struct net_device *netdev, u32 features)
2653 {
2654 struct jme_adapter *jme = netdev_priv(netdev);
2655
2656 spin_lock_bh(&jme->rxmcs_lock);
2657 if (features & NETIF_F_RXCSUM)
2658 jme->reg_rxmcs |= RXMCS_CHECKSUM;
2659 else
2660 jme->reg_rxmcs &= ~RXMCS_CHECKSUM;
2661 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2662 spin_unlock_bh(&jme->rxmcs_lock);
2663
2664 return 0;
2665 }
2666
2667 static int
2668 jme_nway_reset(struct net_device *netdev)
2669 {
2670 struct jme_adapter *jme = netdev_priv(netdev);
2671 jme_restart_an(jme);
2672 return 0;
2673 }
2674
2675 static u8
2676 jme_smb_read(struct jme_adapter *jme, unsigned int addr)
2677 {
2678 u32 val;
2679 int to;
2680
2681 val = jread32(jme, JME_SMBCSR);
2682 to = JME_SMB_BUSY_TIMEOUT;
2683 while ((val & SMBCSR_BUSY) && --to) {
2684 msleep(1);
2685 val = jread32(jme, JME_SMBCSR);
2686 }
2687 if (!to) {
2688 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2689 return 0xFF;
2690 }
2691
2692 jwrite32(jme, JME_SMBINTF,
2693 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2694 SMBINTF_HWRWN_READ |
2695 SMBINTF_HWCMD);
2696
2697 val = jread32(jme, JME_SMBINTF);
2698 to = JME_SMB_BUSY_TIMEOUT;
2699 while ((val & SMBINTF_HWCMD) && --to) {
2700 msleep(1);
2701 val = jread32(jme, JME_SMBINTF);
2702 }
2703 if (!to) {
2704 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2705 return 0xFF;
2706 }
2707
2708 return (val & SMBINTF_HWDATR) >> SMBINTF_HWDATR_SHIFT;
2709 }
2710
2711 static void
2712 jme_smb_write(struct jme_adapter *jme, unsigned int addr, u8 data)
2713 {
2714 u32 val;
2715 int to;
2716
2717 val = jread32(jme, JME_SMBCSR);
2718 to = JME_SMB_BUSY_TIMEOUT;
2719 while ((val & SMBCSR_BUSY) && --to) {
2720 msleep(1);
2721 val = jread32(jme, JME_SMBCSR);
2722 }
2723 if (!to) {
2724 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2725 return;
2726 }
2727
2728 jwrite32(jme, JME_SMBINTF,
2729 ((data << SMBINTF_HWDATW_SHIFT) & SMBINTF_HWDATW) |
2730 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2731 SMBINTF_HWRWN_WRITE |
2732 SMBINTF_HWCMD);
2733
2734 val = jread32(jme, JME_SMBINTF);
2735 to = JME_SMB_BUSY_TIMEOUT;
2736 while ((val & SMBINTF_HWCMD) && --to) {
2737 msleep(1);
2738 val = jread32(jme, JME_SMBINTF);
2739 }
2740 if (!to) {
2741 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2742 return;
2743 }
2744
2745 mdelay(2);
2746 }
2747
2748 static int
2749 jme_get_eeprom_len(struct net_device *netdev)
2750 {
2751 struct jme_adapter *jme = netdev_priv(netdev);
2752 u32 val;
2753 val = jread32(jme, JME_SMBCSR);
2754 return (val & SMBCSR_EEPROMD) ? JME_SMB_LEN : 0;
2755 }
2756
2757 static int
2758 jme_get_eeprom(struct net_device *netdev,
2759 struct ethtool_eeprom *eeprom, u8 *data)
2760 {
2761 struct jme_adapter *jme = netdev_priv(netdev);
2762 int i, offset = eeprom->offset, len = eeprom->len;
2763
2764 /*
2765 * ethtool will check the boundary for us
2766 */
2767 eeprom->magic = JME_EEPROM_MAGIC;
2768 for (i = 0 ; i < len ; ++i)
2769 data[i] = jme_smb_read(jme, i + offset);
2770
2771 return 0;
2772 }
2773
2774 static int
2775 jme_set_eeprom(struct net_device *netdev,
2776 struct ethtool_eeprom *eeprom, u8 *data)
2777 {
2778 struct jme_adapter *jme = netdev_priv(netdev);
2779 int i, offset = eeprom->offset, len = eeprom->len;
2780
2781 if (eeprom->magic != JME_EEPROM_MAGIC)
2782 return -EINVAL;
2783
2784 /*
2785 * ethtool will check the boundary for us
2786 */
2787 for (i = 0 ; i < len ; ++i)
2788 jme_smb_write(jme, i + offset, data[i]);
2789
2790 return 0;
2791 }
2792
2793 static const struct ethtool_ops jme_ethtool_ops = {
2794 .get_drvinfo = jme_get_drvinfo,
2795 .get_regs_len = jme_get_regs_len,
2796 .get_regs = jme_get_regs,
2797 .get_coalesce = jme_get_coalesce,
2798 .set_coalesce = jme_set_coalesce,
2799 .get_pauseparam = jme_get_pauseparam,
2800 .set_pauseparam = jme_set_pauseparam,
2801 .get_wol = jme_get_wol,
2802 .set_wol = jme_set_wol,
2803 .get_settings = jme_get_settings,
2804 .set_settings = jme_set_settings,
2805 .get_link = jme_get_link,
2806 .get_msglevel = jme_get_msglevel,
2807 .set_msglevel = jme_set_msglevel,
2808 .nway_reset = jme_nway_reset,
2809 .get_eeprom_len = jme_get_eeprom_len,
2810 .get_eeprom = jme_get_eeprom,
2811 .set_eeprom = jme_set_eeprom,
2812 };
2813
2814 static int
2815 jme_pci_dma64(struct pci_dev *pdev)
2816 {
2817 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
2818 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)))
2819 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)))
2820 return 1;
2821
2822 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
2823 !pci_set_dma_mask(pdev, DMA_BIT_MASK(40)))
2824 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(40)))
2825 return 1;
2826
2827 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32)))
2828 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)))
2829 return 0;
2830
2831 return -1;
2832 }
2833
2834 static inline void
2835 jme_phy_init(struct jme_adapter *jme)
2836 {
2837 u16 reg26;
2838
2839 reg26 = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 26);
2840 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 26, reg26 | 0x1000);
2841 }
2842
2843 static inline void
2844 jme_check_hw_ver(struct jme_adapter *jme)
2845 {
2846 u32 chipmode;
2847
2848 chipmode = jread32(jme, JME_CHIPMODE);
2849
2850 jme->fpgaver = (chipmode & CM_FPGAVER_MASK) >> CM_FPGAVER_SHIFT;
2851 jme->chiprev = (chipmode & CM_CHIPREV_MASK) >> CM_CHIPREV_SHIFT;
2852 jme->chip_main_rev = jme->chiprev & 0xF;
2853 jme->chip_sub_rev = (jme->chiprev >> 4) & 0xF;
2854 }
2855
2856 static const struct net_device_ops jme_netdev_ops = {
2857 .ndo_open = jme_open,
2858 .ndo_stop = jme_close,
2859 .ndo_validate_addr = eth_validate_addr,
2860 .ndo_do_ioctl = jme_ioctl,
2861 .ndo_start_xmit = jme_start_xmit,
2862 .ndo_set_mac_address = jme_set_macaddr,
2863 .ndo_set_multicast_list = jme_set_multi,
2864 .ndo_change_mtu = jme_change_mtu,
2865 .ndo_tx_timeout = jme_tx_timeout,
2866 .ndo_vlan_rx_register = jme_vlan_rx_register,
2867 .ndo_fix_features = jme_fix_features,
2868 .ndo_set_features = jme_set_features,
2869 };
2870
2871 static int __devinit
2872 jme_init_one(struct pci_dev *pdev,
2873 const struct pci_device_id *ent)
2874 {
2875 int rc = 0, using_dac, i;
2876 struct net_device *netdev;
2877 struct jme_adapter *jme;
2878 u16 bmcr, bmsr;
2879 u32 apmc;
2880
2881 /*
2882 * set up PCI device basics
2883 */
2884 rc = pci_enable_device(pdev);
2885 if (rc) {
2886 pr_err("Cannot enable PCI device\n");
2887 goto err_out;
2888 }
2889
2890 using_dac = jme_pci_dma64(pdev);
2891 if (using_dac < 0) {
2892 pr_err("Cannot set PCI DMA Mask\n");
2893 rc = -EIO;
2894 goto err_out_disable_pdev;
2895 }
2896
2897 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
2898 pr_err("No PCI resource region found\n");
2899 rc = -ENOMEM;
2900 goto err_out_disable_pdev;
2901 }
2902
2903 rc = pci_request_regions(pdev, DRV_NAME);
2904 if (rc) {
2905 pr_err("Cannot obtain PCI resource region\n");
2906 goto err_out_disable_pdev;
2907 }
2908
2909 pci_set_master(pdev);
2910
2911 /*
2912 * alloc and init net device
2913 */
2914 netdev = alloc_etherdev(sizeof(*jme));
2915 if (!netdev) {
2916 pr_err("Cannot allocate netdev structure\n");
2917 rc = -ENOMEM;
2918 goto err_out_release_regions;
2919 }
2920 netdev->netdev_ops = &jme_netdev_ops;
2921 netdev->ethtool_ops = &jme_ethtool_ops;
2922 netdev->watchdog_timeo = TX_TIMEOUT;
2923 netdev->hw_features = NETIF_F_IP_CSUM |
2924 NETIF_F_IPV6_CSUM |
2925 NETIF_F_SG |
2926 NETIF_F_TSO |
2927 NETIF_F_TSO6 |
2928 NETIF_F_RXCSUM;
2929 netdev->features = NETIF_F_IP_CSUM |
2930 NETIF_F_IPV6_CSUM |
2931 NETIF_F_SG |
2932 NETIF_F_TSO |
2933 NETIF_F_TSO6 |
2934 NETIF_F_HW_VLAN_TX |
2935 NETIF_F_HW_VLAN_RX;
2936 if (using_dac)
2937 netdev->features |= NETIF_F_HIGHDMA;
2938
2939 SET_NETDEV_DEV(netdev, &pdev->dev);
2940 pci_set_drvdata(pdev, netdev);
2941
2942 /*
2943 * init adapter info
2944 */
2945 jme = netdev_priv(netdev);
2946 jme->pdev = pdev;
2947 jme->dev = netdev;
2948 jme->jme_rx = netif_rx;
2949 jme->jme_vlan_rx = vlan_hwaccel_rx;
2950 jme->old_mtu = netdev->mtu = 1500;
2951 jme->phylink = 0;
2952 jme->tx_ring_size = 1 << 10;
2953 jme->tx_ring_mask = jme->tx_ring_size - 1;
2954 jme->tx_wake_threshold = 1 << 9;
2955 jme->rx_ring_size = 1 << 9;
2956 jme->rx_ring_mask = jme->rx_ring_size - 1;
2957 jme->msg_enable = JME_DEF_MSG_ENABLE;
2958 jme->regs = ioremap(pci_resource_start(pdev, 0),
2959 pci_resource_len(pdev, 0));
2960 if (!(jme->regs)) {
2961 pr_err("Mapping PCI resource region error\n");
2962 rc = -ENOMEM;
2963 goto err_out_free_netdev;
2964 }
2965
2966 if (no_pseudohp) {
2967 apmc = jread32(jme, JME_APMC) & ~JME_APMC_PSEUDO_HP_EN;
2968 jwrite32(jme, JME_APMC, apmc);
2969 } else if (force_pseudohp) {
2970 apmc = jread32(jme, JME_APMC) | JME_APMC_PSEUDO_HP_EN;
2971 jwrite32(jme, JME_APMC, apmc);
2972 }
2973
2974 NETIF_NAPI_SET(netdev, &jme->napi, jme_poll, jme->rx_ring_size >> 2)
2975
2976 spin_lock_init(&jme->phy_lock);
2977 spin_lock_init(&jme->macaddr_lock);
2978 spin_lock_init(&jme->rxmcs_lock);
2979
2980 atomic_set(&jme->link_changing, 1);
2981 atomic_set(&jme->rx_cleaning, 1);
2982 atomic_set(&jme->tx_cleaning, 1);
2983 atomic_set(&jme->rx_empty, 1);
2984
2985 tasklet_init(&jme->pcc_task,
2986 jme_pcc_tasklet,
2987 (unsigned long) jme);
2988 tasklet_init(&jme->linkch_task,
2989 jme_link_change_tasklet,
2990 (unsigned long) jme);
2991 tasklet_init(&jme->txclean_task,
2992 jme_tx_clean_tasklet,
2993 (unsigned long) jme);
2994 tasklet_init(&jme->rxclean_task,
2995 jme_rx_clean_tasklet,
2996 (unsigned long) jme);
2997 tasklet_init(&jme->rxempty_task,
2998 jme_rx_empty_tasklet,
2999 (unsigned long) jme);
3000 tasklet_disable_nosync(&jme->linkch_task);
3001 tasklet_disable_nosync(&jme->txclean_task);
3002 tasklet_disable_nosync(&jme->rxclean_task);
3003 tasklet_disable_nosync(&jme->rxempty_task);
3004 jme->dpi.cur = PCC_P1;
3005
3006 jme->reg_ghc = 0;
3007 jme->reg_rxcs = RXCS_DEFAULT;
3008 jme->reg_rxmcs = RXMCS_DEFAULT;
3009 jme->reg_txpfc = 0;
3010 jme->reg_pmcs = PMCS_MFEN;
3011 jme->reg_gpreg1 = GPREG1_DEFAULT;
3012
3013 if (jme->reg_rxmcs & RXMCS_CHECKSUM)
3014 netdev->features |= NETIF_F_RXCSUM;
3015
3016 /*
3017 * Get Max Read Req Size from PCI Config Space
3018 */
3019 pci_read_config_byte(pdev, PCI_DCSR_MRRS, &jme->mrrs);
3020 jme->mrrs &= PCI_DCSR_MRRS_MASK;
3021 switch (jme->mrrs) {
3022 case MRRS_128B:
3023 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_128B;
3024 break;
3025 case MRRS_256B:
3026 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_256B;
3027 break;
3028 default:
3029 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_512B;
3030 break;
3031 }
3032
3033 /*
3034 * Must check before reset_mac_processor
3035 */
3036 jme_check_hw_ver(jme);
3037 jme->mii_if.dev = netdev;
3038 if (jme->fpgaver) {
3039 jme->mii_if.phy_id = 0;
3040 for (i = 1 ; i < 32 ; ++i) {
3041 bmcr = jme_mdio_read(netdev, i, MII_BMCR);
3042 bmsr = jme_mdio_read(netdev, i, MII_BMSR);
3043 if (bmcr != 0xFFFFU && (bmcr != 0 || bmsr != 0)) {
3044 jme->mii_if.phy_id = i;
3045 break;
3046 }
3047 }
3048
3049 if (!jme->mii_if.phy_id) {
3050 rc = -EIO;
3051 pr_err("Can not find phy_id\n");
3052 goto err_out_unmap;
3053 }
3054
3055 jme->reg_ghc |= GHC_LINK_POLL;
3056 } else {
3057 jme->mii_if.phy_id = 1;
3058 }
3059 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
3060 jme->mii_if.supports_gmii = true;
3061 else
3062 jme->mii_if.supports_gmii = false;
3063 jme->mii_if.phy_id_mask = 0x1F;
3064 jme->mii_if.reg_num_mask = 0x1F;
3065 jme->mii_if.mdio_read = jme_mdio_read;
3066 jme->mii_if.mdio_write = jme_mdio_write;
3067
3068 jme_clear_pm(jme);
3069 jme_set_phyfifo_5level(jme);
3070 jme->pcirev = pdev->revision;
3071 if (!jme->fpgaver)
3072 jme_phy_init(jme);
3073 jme_phy_off(jme);
3074
3075 /*
3076 * Reset MAC processor and reload EEPROM for MAC Address
3077 */
3078 jme_reset_mac_processor(jme);
3079 rc = jme_reload_eeprom(jme);
3080 if (rc) {
3081 pr_err("Reload eeprom for reading MAC Address error\n");
3082 goto err_out_unmap;
3083 }
3084 jme_load_macaddr(netdev);
3085
3086 /*
3087 * Tell stack that we are not ready to work until open()
3088 */
3089 netif_carrier_off(netdev);
3090
3091 rc = register_netdev(netdev);
3092 if (rc) {
3093 pr_err("Cannot register net device\n");
3094 goto err_out_unmap;
3095 }
3096
3097 netif_info(jme, probe, jme->dev, "%s%s chiprev:%x pcirev:%x macaddr:%pM\n",
3098 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250) ?
3099 "JMC250 Gigabit Ethernet" :
3100 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC260) ?
3101 "JMC260 Fast Ethernet" : "Unknown",
3102 (jme->fpgaver != 0) ? " (FPGA)" : "",
3103 (jme->fpgaver != 0) ? jme->fpgaver : jme->chiprev,
3104 jme->pcirev, netdev->dev_addr);
3105
3106 return 0;
3107
3108 err_out_unmap:
3109 iounmap(jme->regs);
3110 err_out_free_netdev:
3111 pci_set_drvdata(pdev, NULL);
3112 free_netdev(netdev);
3113 err_out_release_regions:
3114 pci_release_regions(pdev);
3115 err_out_disable_pdev:
3116 pci_disable_device(pdev);
3117 err_out:
3118 return rc;
3119 }
3120
3121 static void __devexit
3122 jme_remove_one(struct pci_dev *pdev)
3123 {
3124 struct net_device *netdev = pci_get_drvdata(pdev);
3125 struct jme_adapter *jme = netdev_priv(netdev);
3126
3127 unregister_netdev(netdev);
3128 iounmap(jme->regs);
3129 pci_set_drvdata(pdev, NULL);
3130 free_netdev(netdev);
3131 pci_release_regions(pdev);
3132 pci_disable_device(pdev);
3133
3134 }
3135
3136 static void
3137 jme_shutdown(struct pci_dev *pdev)
3138 {
3139 struct net_device *netdev = pci_get_drvdata(pdev);
3140 struct jme_adapter *jme = netdev_priv(netdev);
3141
3142 jme_powersave_phy(jme);
3143 pci_pme_active(pdev, true);
3144 }
3145
3146 #ifdef CONFIG_PM
3147 static int jme_suspend(struct device *dev)
3148 {
3149 struct pci_dev *pdev = to_pci_dev(dev);
3150 struct net_device *netdev = pci_get_drvdata(pdev);
3151 struct jme_adapter *jme = netdev_priv(netdev);
3152
3153 atomic_dec(&jme->link_changing);
3154
3155 netif_device_detach(netdev);
3156 netif_stop_queue(netdev);
3157 jme_stop_irq(jme);
3158
3159 tasklet_disable(&jme->txclean_task);
3160 tasklet_disable(&jme->rxclean_task);
3161 tasklet_disable(&jme->rxempty_task);
3162
3163 if (netif_carrier_ok(netdev)) {
3164 if (test_bit(JME_FLAG_POLL, &jme->flags))
3165 jme_polling_mode(jme);
3166
3167 jme_stop_pcc_timer(jme);
3168 jme_disable_rx_engine(jme);
3169 jme_disable_tx_engine(jme);
3170 jme_reset_mac_processor(jme);
3171 jme_free_rx_resources(jme);
3172 jme_free_tx_resources(jme);
3173 netif_carrier_off(netdev);
3174 jme->phylink = 0;
3175 }
3176
3177 tasklet_enable(&jme->txclean_task);
3178 tasklet_hi_enable(&jme->rxclean_task);
3179 tasklet_hi_enable(&jme->rxempty_task);
3180
3181 jme_powersave_phy(jme);
3182
3183 return 0;
3184 }
3185
3186 static int jme_resume(struct device *dev)
3187 {
3188 struct pci_dev *pdev = to_pci_dev(dev);
3189 struct net_device *netdev = pci_get_drvdata(pdev);
3190 struct jme_adapter *jme = netdev_priv(netdev);
3191
3192 jwrite32(jme, JME_PMCS, 0xFFFF0000 | jme->reg_pmcs);
3193
3194 jme_phy_on(jme);
3195 if (test_bit(JME_FLAG_SSET, &jme->flags))
3196 jme_set_settings(netdev, &jme->old_ecmd);
3197 else
3198 jme_reset_phy_processor(jme);
3199
3200 jme_start_irq(jme);
3201 netif_device_attach(netdev);
3202
3203 atomic_inc(&jme->link_changing);
3204
3205 jme_reset_link(jme);
3206
3207 return 0;
3208 }
3209
3210 static SIMPLE_DEV_PM_OPS(jme_pm_ops, jme_suspend, jme_resume);
3211 #define JME_PM_OPS (&jme_pm_ops)
3212
3213 #else
3214
3215 #define JME_PM_OPS NULL
3216 #endif
3217
3218 static DEFINE_PCI_DEVICE_TABLE(jme_pci_tbl) = {
3219 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC250) },
3220 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC260) },
3221 { }
3222 };
3223
3224 static struct pci_driver jme_driver = {
3225 .name = DRV_NAME,
3226 .id_table = jme_pci_tbl,
3227 .probe = jme_init_one,
3228 .remove = __devexit_p(jme_remove_one),
3229 .shutdown = jme_shutdown,
3230 .driver.pm = JME_PM_OPS,
3231 };
3232
3233 static int __init
3234 jme_init_module(void)
3235 {
3236 pr_info("JMicron JMC2XX ethernet driver version %s\n", DRV_VERSION);
3237 return pci_register_driver(&jme_driver);
3238 }
3239
3240 static void __exit
3241 jme_cleanup_module(void)
3242 {
3243 pci_unregister_driver(&jme_driver);
3244 }
3245
3246 module_init(jme_init_module);
3247 module_exit(jme_cleanup_module);
3248
3249 MODULE_AUTHOR("Guo-Fu Tseng <cooldavid@cooldavid.org>");
3250 MODULE_DESCRIPTION("JMicron JMC2x0 PCI Express Ethernet driver");
3251 MODULE_LICENSE("GPL");
3252 MODULE_VERSION(DRV_VERSION);
3253 MODULE_DEVICE_TABLE(pci, jme_pci_tbl);
3254
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree