arch/x86/kernel/irqinit.c

   1 #include <linux/linkage.h>
   2 #include <linux/errno.h>
   3 #include <linux/signal.h>
   4 #include <linux/sched.h>
   5 #include <linux/ioport.h>
   6 #include <linux/interrupt.h>
   7 #include <linux/timex.h>
   8 #include <linux/slab.h>
   9 #include <linux/random.h>
  10 #include <linux/kprobes.h>
  11 #include <linux/init.h>
  12 #include <linux/kernel_stat.h>
  13 #include <linux/sysdev.h>
  14 #include <linux/bitops.h>
  15 #include <linux/acpi.h>
  16 #include <linux/io.h>
  17 #include <linux/delay.h>
  18
  19 #include <asm/atomic.h>
  20 #include <asm/system.h>
  21 #include <asm/timer.h>
  22 #include <asm/hw_irq.h>
  23 #include <asm/pgtable.h>
  24 #include <asm/desc.h>
  25 #include <asm/apic.h>
  26 #include <asm/setup.h>
  27 #include <asm/i8259.h>
  28 #include <asm/traps.h>
  29
  30 /*
  31  * ISA PIC or low IO-APIC triggered (INTA-cycle or APIC) interrupts:
  32  * (these are usually mapped to vectors 0x30-0x3f)
  33  */
  34
  35 /*
  36  * The IO-APIC gives us many more interrupt sources. Most of these
  37  * are unused but an SMP system is supposed to have enough memory ...
  38  * sometimes (mostly wrt. hw bugs) we get corrupted vectors all
  39  * across the spectrum, so we really want to be prepared to get all
  40  * of these. Plus, more powerful systems might have more than 64
  41  * IO-APIC registers.
  42  *
  43  * (these are usually mapped into the 0x30-0xff vector range)
  44  */
  45
  46 #ifdef CONFIG_X86_32
  47 /*
  48  * Note that on a 486, we don't want to do a SIGFPE on an irq13
  49  * as the irq is unreliable, and exception 16 works correctly
  50  * (ie as explained in the intel literature). On a 386, you
  51  * can't use exception 16 due to bad IBM design, so we have to
  52  * rely on the less exact irq13.
  53  *
  54  * Careful.. Not only is IRQ13 unreliable, but it is also
  55  * leads to races. IBM designers who came up with it should
  56  * be shot.
  57  */
  58
  59 static irqreturn_t math_error_irq(int cpl, void *dev_id)
  60 {
  61         outb(0, 0xF0);
  62         if (ignore_fpu_irq || !boot_cpu_data.hard_math)
  63                 return IRQ_NONE;
  64         math_error((void __user *)get_irq_regs()->ip);
  65         return IRQ_HANDLED;
  66 }
  67
  68 /*
  69  * New motherboards sometimes make IRQ 13 be a PCI interrupt,
  70  * so allow interrupt sharing.
  71  */
  72 static struct irqaction fpu_irq = {
  73         .handler = math_error_irq,
  74         .name = "fpu",
  75 };
  76 #endif
  77
  78 /*
  79  * IRQ2 is cascade interrupt to second interrupt controller
  80  */
  81 static struct irqaction irq2 = {
  82         .handler = no_action,
  83         .name = "cascade",
  84 };
  85
  86 DEFINE_PER_CPU(vector_irq_t, vector_irq) = {
  87         [0 ... IRQ0_VECTOR - 1] = -1,
  88         [IRQ0_VECTOR] = 0,
  89         [IRQ1_VECTOR] = 1,
  90         [IRQ2_VECTOR] = 2,
  91         [IRQ3_VECTOR] = 3,
  92         [IRQ4_VECTOR] = 4,
  93         [IRQ5_VECTOR] = 5,
  94         [IRQ6_VECTOR] = 6,
  95         [IRQ7_VECTOR] = 7,
  96         [IRQ8_VECTOR] = 8,
  97         [IRQ9_VECTOR] = 9,
  98         [IRQ10_VECTOR] = 10,
  99         [IRQ11_VECTOR] = 11,
 100         [IRQ12_VECTOR] = 12,
 101         [IRQ13_VECTOR] = 13,
 102         [IRQ14_VECTOR] = 14,
 103         [IRQ15_VECTOR] = 15,
 104         [IRQ15_VECTOR + 1 ... NR_VECTORS - 1] = -1
 105 };
 106
 107 int vector_used_by_percpu_irq(unsigned int vector)
 108 {
 109         int cpu;
 110
 111         for_each_online_cpu(cpu) {
 112                 if (per_cpu(vector_irq, cpu)[vector] != -1)
 113                         return 1;
 114         }
 115
 116         return 0;
 117 }
 118
 119 static void __init init_ISA_irqs(void)
 120 {
 121         int i;
 122
 123 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_LOCAL_APIC)
 124         init_bsp_APIC();
 125 #endif
 126         init_8259A(0);
 127
 128         /*
 129          * 16 old-style INTA-cycle interrupts:
 130          */
 131         for (i = 0; i < NR_IRQS_LEGACY; i++) {
 132                 struct irq_desc *desc = irq_to_desc(i);
 133
 134                 desc->status = IRQ_DISABLED;
 135                 desc->action = NULL;
 136                 desc->depth = 1;
 137
 138                 set_irq_chip_and_handler_name(i, &i8259A_chip,
 139                                               handle_level_irq, "XT");
 140         }
 141 }
 142
 143 /* Overridden in paravirt.c */
 144 void init_IRQ(void) __attribute__((weak, alias("native_init_IRQ")));
 145
 146 static void __init smp_intr_init(void)
 147 {
 148 #ifdef CONFIG_SMP
 149 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_LOCAL_APIC)
 150         /*
 151          * The reschedule interrupt is a CPU-to-CPU reschedule-helper
 152          * IPI, driven by wakeup.
 153          */
 154         alloc_intr_gate(RESCHEDULE_VECTOR, reschedule_interrupt);
 155
 156         /* IPIs for invalidation */
 157         alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+0, invalidate_interrupt0);
 158         alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+1, invalidate_interrupt1);
 159         alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+2, invalidate_interrupt2);
 160         alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+3, invalidate_interrupt3);
 161         alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+4, invalidate_interrupt4);
 162         alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+5, invalidate_interrupt5);
 163         alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+6, invalidate_interrupt6);
 164         alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+7, invalidate_interrupt7);
 165
 166         /* IPI for generic function call */
 167         alloc_intr_gate(CALL_FUNCTION_VECTOR, call_function_interrupt);
 168
 169         /* IPI for generic single function call */
 170         alloc_intr_gate(CALL_FUNCTION_SINGLE_VECTOR,
 171                         call_function_single_interrupt);
 172
 173         /* Low priority IPI to cleanup after moving an irq */
 174         set_intr_gate(IRQ_MOVE_CLEANUP_VECTOR, irq_move_cleanup_interrupt);
 175         set_bit(IRQ_MOVE_CLEANUP_VECTOR, used_vectors);
 176 #endif
 177 #endif /* CONFIG_SMP */
 178 }
 179
 180 static void __init apic_intr_init(void)
 181 {
 182         smp_intr_init();
 183
 184 #ifdef CONFIG_X86_THERMAL_VECTOR
 185         alloc_intr_gate(THERMAL_APIC_VECTOR, thermal_interrupt);
 186 #endif
 187 #ifdef CONFIG_X86_THRESHOLD
 188         alloc_intr_gate(THRESHOLD_APIC_VECTOR, threshold_interrupt);
 189 #endif
 190 #if defined(CONFIG_X86_NEW_MCE) && defined(CONFIG_X86_LOCAL_APIC)
 191         alloc_intr_gate(MCE_SELF_VECTOR, mce_self_interrupt);
 192 #endif
 193
 194 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_LOCAL_APIC)
 195         /* self generated IPI for local APIC timer */
 196         alloc_intr_gate(LOCAL_TIMER_VECTOR, apic_timer_interrupt);
 197
 198         /* generic IPI for platform specific use */
 199         alloc_intr_gate(GENERIC_INTERRUPT_VECTOR, generic_interrupt);
 200
 201         /* IPI vectors for APIC spurious and error interrupts */
 202         alloc_intr_gate(SPURIOUS_APIC_VECTOR, spurious_interrupt);
 203         alloc_intr_gate(ERROR_APIC_VECTOR, error_interrupt);
 204
 205         /* Performance monitoring interrupts: */
 206 # ifdef CONFIG_PERF_COUNTERS
 207         alloc_intr_gate(LOCAL_PENDING_VECTOR, perf_pending_interrupt);
 208 # endif
 209
 210 #endif
 211 }
 212
 213 /**
 214  * x86_quirk_pre_intr_init - initialisation prior to setting up interrupt vectors
 215  *
 216  * Description:
 217  *      Perform any necessary interrupt initialisation prior to setting up
 218  *      the "ordinary" interrupt call gates.  For legacy reasons, the ISA
 219  *      interrupts should be initialised here if the machine emulates a PC
 220  *      in any way.
 221  **/
 222 static void __init x86_quirk_pre_intr_init(void)
 223 {
 224 #ifdef CONFIG_X86_32
 225         if (x86_quirks->arch_pre_intr_init) {
 226                 if (x86_quirks->arch_pre_intr_init())
 227                         return;
 228         }
 229 #endif
 230         init_ISA_irqs();
 231 }
 232
 233 void __init native_init_IRQ(void)
 234 {
 235         int i;
 236
 237         /* Execute any quirks before the call gates are initialised: */
 238         x86_quirk_pre_intr_init();
 239
 240         apic_intr_init();
 241
 242         /*
 243          * Cover the whole vector space, no vector can escape
 244          * us. (some of these will be overridden and become
 245          * 'special' SMP interrupts)
 246          */
 247         for (i = FIRST_EXTERNAL_VECTOR; i < NR_VECTORS; i++) {
 248                 /* IA32_SYSCALL_VECTOR could be used in trap_init already. */
 249                 if (!test_bit(i, used_vectors))
 250                         set_intr_gate(i, interrupt[i-FIRST_EXTERNAL_VECTOR]);
 251         }
 252
 253         if (!acpi_ioapic)
 254                 setup_irq(2, &irq2);
 255
 256 #ifdef CONFIG_X86_32
 257         /*
 258          * Call quirks after call gates are initialised (usually add in
 259          * the architecture specific gates):
 260          */
 261         x86_quirk_intr_init();
 262
 263         /*
 264          * External FPU? Set up irq13 if so, for
 265          * original braindamaged IBM FERR coupling.
 266          */
 267         if (boot_cpu_data.hard_math && !cpu_has_fpu)
 268                 setup_irq(FPU_IRQ, &fpu_irq);
 269
 270         irq_ctx_init(smp_processor_id());
 271 #endif
 272 }