1 /* NXP PCF50633 Power Management Unit (PMU) driver
3 * (C) 2006-2008 by Openmoko, Inc.
4 * Author: Harald Welte <laforge@openmoko.org>
5 * Balaji Rao <balajirrao@openmoko.org>
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
15 #include <linux/interrupt.h>
16 #include <linux/kernel.h>
17 #include <linux/mutex.h>
18 #include <linux/export.h>
19 #include <linux/slab.h>
21 #include <linux/mfd/pcf50633/core.h>
23 /* Two MBCS registers used during cold start */
24 #define PCF50633_REG_MBCS1 0x4b
25 #define PCF50633_REG_MBCS2 0x4c
26 #define PCF50633_MBCS1_USBPRES 0x01
27 #define PCF50633_MBCS1_ADAPTPRES 0x01
29 int pcf50633_register_irq(struct pcf50633
*pcf
, int irq
,
30 void (*handler
) (int, void *), void *data
)
32 if (irq
< 0 || irq
>= PCF50633_NUM_IRQ
|| !handler
)
35 if (WARN_ON(pcf
->irq_handler
[irq
].handler
))
38 mutex_lock(&pcf
->lock
);
39 pcf
->irq_handler
[irq
].handler
= handler
;
40 pcf
->irq_handler
[irq
].data
= data
;
41 mutex_unlock(&pcf
->lock
);
45 EXPORT_SYMBOL_GPL(pcf50633_register_irq
);
47 int pcf50633_free_irq(struct pcf50633
*pcf
, int irq
)
49 if (irq
< 0 || irq
>= PCF50633_NUM_IRQ
)
52 mutex_lock(&pcf
->lock
);
53 pcf
->irq_handler
[irq
].handler
= NULL
;
54 mutex_unlock(&pcf
->lock
);
58 EXPORT_SYMBOL_GPL(pcf50633_free_irq
);
60 static int __pcf50633_irq_mask_set(struct pcf50633
*pcf
, int irq
, u8 mask
)
66 reg
= PCF50633_REG_INT1M
+ idx
;
67 bit
= 1 << (irq
& 0x07);
69 pcf50633_reg_set_bit_mask(pcf
, reg
, bit
, mask
? bit
: 0);
71 mutex_lock(&pcf
->lock
);
74 pcf
->mask_regs
[idx
] |= bit
;
76 pcf
->mask_regs
[idx
] &= ~bit
;
78 mutex_unlock(&pcf
->lock
);
83 int pcf50633_irq_mask(struct pcf50633
*pcf
, int irq
)
85 dev_dbg(pcf
->dev
, "Masking IRQ %d\n", irq
);
87 return __pcf50633_irq_mask_set(pcf
, irq
, 1);
89 EXPORT_SYMBOL_GPL(pcf50633_irq_mask
);
91 int pcf50633_irq_unmask(struct pcf50633
*pcf
, int irq
)
93 dev_dbg(pcf
->dev
, "Unmasking IRQ %d\n", irq
);
95 return __pcf50633_irq_mask_set(pcf
, irq
, 0);
97 EXPORT_SYMBOL_GPL(pcf50633_irq_unmask
);
99 int pcf50633_irq_mask_get(struct pcf50633
*pcf
, int irq
)
104 bits
= 1 << (irq
& 0x07);
106 return pcf
->mask_regs
[reg
] & bits
;
108 EXPORT_SYMBOL_GPL(pcf50633_irq_mask_get
);
110 static void pcf50633_irq_call_handler(struct pcf50633
*pcf
, int irq
)
112 if (pcf
->irq_handler
[irq
].handler
)
113 pcf
->irq_handler
[irq
].handler(irq
, pcf
->irq_handler
[irq
].data
);
116 /* Maximum amount of time ONKEY is held before emergency action is taken */
117 #define PCF50633_ONKEY1S_TIMEOUT 8
119 static irqreturn_t
pcf50633_irq(int irq
, void *data
)
121 struct pcf50633
*pcf
= data
;
123 u8 pcf_int
[5], chgstat
;
125 /* Read the 5 INT regs in one transaction */
126 ret
= pcf50633_read_block(pcf
, PCF50633_REG_INT1
,
127 ARRAY_SIZE(pcf_int
), pcf_int
);
128 if (ret
!= ARRAY_SIZE(pcf_int
)) {
129 dev_err(pcf
->dev
, "Error reading INT registers\n");
132 * If this doesn't ACK the interrupt to the chip, we'll be
133 * called once again as we're level triggered.
138 /* defeat 8s death from lowsys on A5 */
139 pcf50633_reg_write(pcf
, PCF50633_REG_OOCSHDWN
, 0x04);
141 /* We immediately read the usb and adapter status. We thus make sure
142 * only of USBINS/USBREM IRQ handlers are called */
143 if (pcf_int
[0] & (PCF50633_INT1_USBINS
| PCF50633_INT1_USBREM
)) {
144 chgstat
= pcf50633_reg_read(pcf
, PCF50633_REG_MBCS2
);
145 if (chgstat
& (0x3 << 4))
146 pcf_int
[0] &= ~PCF50633_INT1_USBREM
;
148 pcf_int
[0] &= ~PCF50633_INT1_USBINS
;
151 /* Make sure only one of ADPINS or ADPREM is set */
152 if (pcf_int
[0] & (PCF50633_INT1_ADPINS
| PCF50633_INT1_ADPREM
)) {
153 chgstat
= pcf50633_reg_read(pcf
, PCF50633_REG_MBCS2
);
154 if (chgstat
& (0x3 << 4))
155 pcf_int
[0] &= ~PCF50633_INT1_ADPREM
;
157 pcf_int
[0] &= ~PCF50633_INT1_ADPINS
;
160 dev_dbg(pcf
->dev
, "INT1=0x%02x INT2=0x%02x INT3=0x%02x "
161 "INT4=0x%02x INT5=0x%02x\n", pcf_int
[0],
162 pcf_int
[1], pcf_int
[2], pcf_int
[3], pcf_int
[4]);
164 /* Some revisions of the chip don't have a 8s standby mode on
165 * ONKEY1S press. We try to manually do it in such cases. */
166 if ((pcf_int
[0] & PCF50633_INT1_SECOND
) && pcf
->onkey1s_held
) {
167 dev_info(pcf
->dev
, "ONKEY1S held for %d secs\n",
169 if (pcf
->onkey1s_held
++ == PCF50633_ONKEY1S_TIMEOUT
)
170 if (pcf
->pdata
->force_shutdown
)
171 pcf
->pdata
->force_shutdown(pcf
);
174 if (pcf_int
[2] & PCF50633_INT3_ONKEY1S
) {
175 dev_info(pcf
->dev
, "ONKEY1S held\n");
176 pcf
->onkey1s_held
= 1 ;
178 /* Unmask IRQ_SECOND */
179 pcf50633_reg_clear_bits(pcf
, PCF50633_REG_INT1M
,
180 PCF50633_INT1_SECOND
);
182 /* Unmask IRQ_ONKEYR */
183 pcf50633_reg_clear_bits(pcf
, PCF50633_REG_INT2M
,
184 PCF50633_INT2_ONKEYR
);
187 if ((pcf_int
[1] & PCF50633_INT2_ONKEYR
) && pcf
->onkey1s_held
) {
188 pcf
->onkey1s_held
= 0;
190 /* Mask SECOND and ONKEYR interrupts */
191 if (pcf
->mask_regs
[0] & PCF50633_INT1_SECOND
)
192 pcf50633_reg_set_bit_mask(pcf
,
194 PCF50633_INT1_SECOND
,
195 PCF50633_INT1_SECOND
);
197 if (pcf
->mask_regs
[1] & PCF50633_INT2_ONKEYR
)
198 pcf50633_reg_set_bit_mask(pcf
,
200 PCF50633_INT2_ONKEYR
,
201 PCF50633_INT2_ONKEYR
);
204 /* Have we just resumed ? */
205 if (pcf
->is_suspended
) {
206 pcf
->is_suspended
= 0;
208 /* Set the resume reason filtering out non resumers */
209 for (i
= 0; i
< ARRAY_SIZE(pcf_int
); i
++)
210 pcf
->resume_reason
[i
] = pcf_int
[i
] &
211 pcf
->pdata
->resumers
[i
];
213 /* Make sure we don't pass on any ONKEY events to
215 pcf_int
[1] &= ~(PCF50633_INT2_ONKEYR
| PCF50633_INT2_ONKEYF
);
218 for (i
= 0; i
< ARRAY_SIZE(pcf_int
); i
++) {
219 /* Unset masked interrupts */
220 pcf_int
[i
] &= ~pcf
->mask_regs
[i
];
222 for (j
= 0; j
< 8 ; j
++)
223 if (pcf_int
[i
] & (1 << j
))
224 pcf50633_irq_call_handler(pcf
, (i
* 8) + j
);
233 int pcf50633_irq_suspend(struct pcf50633
*pcf
)
240 /* Make sure our interrupt handlers are not called
242 disable_irq(pcf
->irq
);
245 ret
= pcf50633_read_block(pcf
, PCF50633_REG_INT1M
,
246 ARRAY_SIZE(pcf
->suspend_irq_masks
),
247 pcf
->suspend_irq_masks
);
249 dev_err(pcf
->dev
, "error saving irq masks\n");
253 /* Write wakeup irq masks */
254 for (i
= 0; i
< ARRAY_SIZE(res
); i
++)
255 res
[i
] = ~pcf
->pdata
->resumers
[i
];
257 ret
= pcf50633_write_block(pcf
, PCF50633_REG_INT1M
,
258 ARRAY_SIZE(res
), &res
[0]);
260 dev_err(pcf
->dev
, "error writing wakeup irq masks\n");
264 pcf
->is_suspended
= 1;
270 int pcf50633_irq_resume(struct pcf50633
*pcf
)
274 /* Write the saved mask registers */
275 ret
= pcf50633_write_block(pcf
, PCF50633_REG_INT1M
,
276 ARRAY_SIZE(pcf
->suspend_irq_masks
),
277 pcf
->suspend_irq_masks
);
279 dev_err(pcf
->dev
, "Error restoring saved suspend masks\n");
281 enable_irq(pcf
->irq
);
288 int pcf50633_irq_init(struct pcf50633
*pcf
, int irq
)
294 /* Enable all interrupts except RTC SECOND */
295 pcf
->mask_regs
[0] = 0x80;
296 pcf50633_reg_write(pcf
, PCF50633_REG_INT1M
, pcf
->mask_regs
[0]);
297 pcf50633_reg_write(pcf
, PCF50633_REG_INT2M
, 0x00);
298 pcf50633_reg_write(pcf
, PCF50633_REG_INT3M
, 0x00);
299 pcf50633_reg_write(pcf
, PCF50633_REG_INT4M
, 0x00);
300 pcf50633_reg_write(pcf
, PCF50633_REG_INT5M
, 0x00);
302 ret
= request_threaded_irq(irq
, NULL
, pcf50633_irq
,
303 IRQF_TRIGGER_LOW
| IRQF_ONESHOT
,
307 dev_err(pcf
->dev
, "Failed to request IRQ %d\n", ret
);
309 if (enable_irq_wake(irq
) < 0)
310 dev_err(pcf
->dev
, "IRQ %u cannot be enabled as wake-up source"
311 "in this hardware revision", irq
);
316 void pcf50633_irq_free(struct pcf50633
*pcf
)
318 free_irq(pcf
->irq
, pcf
);