2 * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
3 * JZ4740 SoC ADC driver
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
10 * You should have received a copy of the GNU General Public License along
11 * with this program; if not, write to the Free Software Foundation, Inc.,
12 * 675 Mass Ave, Cambridge, MA 02139, USA.
14 * This driver synchronizes access to the JZ4740 ADC core between the
15 * JZ4740 battery and hwmon drivers.
18 #include <linux/err.h>
19 #include <linux/irq.h>
20 #include <linux/interrupt.h>
21 #include <linux/kernel.h>
22 #include <linux/module.h>
23 #include <linux/platform_device.h>
24 #include <linux/slab.h>
25 #include <linux/spinlock.h>
27 #include <linux/clk.h>
28 #include <linux/mfd/core.h>
30 #include <linux/jz4740-adc.h>
33 #define JZ_REG_ADC_ENABLE 0x00
34 #define JZ_REG_ADC_CFG 0x04
35 #define JZ_REG_ADC_CTRL 0x08
36 #define JZ_REG_ADC_STATUS 0x0c
38 #define JZ_REG_ADC_TOUCHSCREEN_BASE 0x10
39 #define JZ_REG_ADC_BATTERY_BASE 0x1c
40 #define JZ_REG_ADC_HWMON_BASE 0x20
42 #define JZ_ADC_ENABLE_TOUCH BIT(2)
43 #define JZ_ADC_ENABLE_BATTERY BIT(1)
44 #define JZ_ADC_ENABLE_ADCIN BIT(0)
59 struct irq_chip_generic
*gc
;
67 static void jz4740_adc_irq_demux(unsigned int irq
, struct irq_desc
*desc
)
69 struct irq_chip_generic
*gc
= irq_desc_get_handler_data(desc
);
73 status
= readb(gc
->reg_base
+ JZ_REG_ADC_STATUS
);
75 for (i
= 0; i
< 5; ++i
) {
77 generic_handle_irq(gc
->irq_base
+ i
);
82 /* Refcounting for the ADC clock is done in here instead of in the clock
83 * framework, because it is the only clock which is shared between multiple
84 * devices and thus is the only clock which needs refcounting */
85 static inline void jz4740_adc_clk_enable(struct jz4740_adc
*adc
)
87 if (atomic_inc_return(&adc
->clk_ref
) == 1)
91 static inline void jz4740_adc_clk_disable(struct jz4740_adc
*adc
)
93 if (atomic_dec_return(&adc
->clk_ref
) == 0)
94 clk_disable(adc
->clk
);
97 static inline void jz4740_adc_set_enabled(struct jz4740_adc
*adc
, int engine
,
103 spin_lock_irqsave(&adc
->lock
, flags
);
105 val
= readb(adc
->base
+ JZ_REG_ADC_ENABLE
);
110 writeb(val
, adc
->base
+ JZ_REG_ADC_ENABLE
);
112 spin_unlock_irqrestore(&adc
->lock
, flags
);
115 static int jz4740_adc_cell_enable(struct platform_device
*pdev
)
117 struct jz4740_adc
*adc
= dev_get_drvdata(pdev
->dev
.parent
);
119 jz4740_adc_clk_enable(adc
);
120 jz4740_adc_set_enabled(adc
, pdev
->id
, true);
125 static int jz4740_adc_cell_disable(struct platform_device
*pdev
)
127 struct jz4740_adc
*adc
= dev_get_drvdata(pdev
->dev
.parent
);
129 jz4740_adc_set_enabled(adc
, pdev
->id
, false);
130 jz4740_adc_clk_disable(adc
);
135 int jz4740_adc_set_config(struct device
*dev
, uint32_t mask
, uint32_t val
)
137 struct jz4740_adc
*adc
= dev_get_drvdata(dev
);
144 spin_lock_irqsave(&adc
->lock
, flags
);
146 cfg
= readl(adc
->base
+ JZ_REG_ADC_CFG
);
151 writel(cfg
, adc
->base
+ JZ_REG_ADC_CFG
);
153 spin_unlock_irqrestore(&adc
->lock
, flags
);
157 EXPORT_SYMBOL_GPL(jz4740_adc_set_config
);
159 static struct resource jz4740_hwmon_resources
[] = {
161 .start
= JZ_ADC_IRQ_ADCIN
,
162 .flags
= IORESOURCE_IRQ
,
165 .start
= JZ_REG_ADC_HWMON_BASE
,
166 .end
= JZ_REG_ADC_HWMON_BASE
+ 3,
167 .flags
= IORESOURCE_MEM
,
171 static struct resource jz4740_battery_resources
[] = {
173 .start
= JZ_ADC_IRQ_BATTERY
,
174 .flags
= IORESOURCE_IRQ
,
177 .start
= JZ_REG_ADC_BATTERY_BASE
,
178 .end
= JZ_REG_ADC_BATTERY_BASE
+ 3,
179 .flags
= IORESOURCE_MEM
,
183 const struct mfd_cell jz4740_adc_cells
[] = {
186 .name
= "jz4740-hwmon",
187 .num_resources
= ARRAY_SIZE(jz4740_hwmon_resources
),
188 .resources
= jz4740_hwmon_resources
,
190 .enable
= jz4740_adc_cell_enable
,
191 .disable
= jz4740_adc_cell_disable
,
195 .name
= "jz4740-battery",
196 .num_resources
= ARRAY_SIZE(jz4740_battery_resources
),
197 .resources
= jz4740_battery_resources
,
199 .enable
= jz4740_adc_cell_enable
,
200 .disable
= jz4740_adc_cell_disable
,
204 static int __devinit
jz4740_adc_probe(struct platform_device
*pdev
)
206 struct irq_chip_generic
*gc
;
207 struct irq_chip_type
*ct
;
208 struct jz4740_adc
*adc
;
209 struct resource
*mem_base
;
213 adc
= kmalloc(sizeof(*adc
), GFP_KERNEL
);
215 dev_err(&pdev
->dev
, "Failed to allocate driver structure\n");
219 adc
->irq
= platform_get_irq(pdev
, 0);
222 dev_err(&pdev
->dev
, "Failed to get platform irq: %d\n", ret
);
226 irq_base
= platform_get_irq(pdev
, 1);
229 dev_err(&pdev
->dev
, "Failed to get irq base: %d\n", ret
);
233 mem_base
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
236 dev_err(&pdev
->dev
, "Failed to get platform mmio resource\n");
240 /* Only request the shared registers for the MFD driver */
241 adc
->mem
= request_mem_region(mem_base
->start
, JZ_REG_ADC_STATUS
,
245 dev_err(&pdev
->dev
, "Failed to request mmio memory region\n");
249 adc
->base
= ioremap_nocache(adc
->mem
->start
, resource_size(adc
->mem
));
252 dev_err(&pdev
->dev
, "Failed to ioremap mmio memory\n");
253 goto err_release_mem_region
;
256 adc
->clk
= clk_get(&pdev
->dev
, "adc");
257 if (IS_ERR(adc
->clk
)) {
258 ret
= PTR_ERR(adc
->clk
);
259 dev_err(&pdev
->dev
, "Failed to get clock: %d\n", ret
);
263 spin_lock_init(&adc
->lock
);
264 atomic_set(&adc
->clk_ref
, 0);
266 platform_set_drvdata(pdev
, adc
);
268 gc
= irq_alloc_generic_chip("INTC", 1, irq_base
, adc
->base
,
272 ct
->regs
.mask
= JZ_REG_ADC_CTRL
;
273 ct
->regs
.ack
= JZ_REG_ADC_STATUS
;
274 ct
->chip
.irq_mask
= irq_gc_mask_set_bit
;
275 ct
->chip
.irq_unmask
= irq_gc_mask_clr_bit
;
276 ct
->chip
.irq_ack
= irq_gc_ack_set_bit
;
278 irq_setup_generic_chip(gc
, IRQ_MSK(5), 0, 0, IRQ_NOPROBE
| IRQ_LEVEL
);
282 irq_set_handler_data(adc
->irq
, gc
);
283 irq_set_chained_handler(adc
->irq
, jz4740_adc_irq_demux
);
285 writeb(0x00, adc
->base
+ JZ_REG_ADC_ENABLE
);
286 writeb(0xff, adc
->base
+ JZ_REG_ADC_CTRL
);
288 ret
= mfd_add_devices(&pdev
->dev
, 0, jz4740_adc_cells
,
289 ARRAY_SIZE(jz4740_adc_cells
), mem_base
, irq_base
);
298 platform_set_drvdata(pdev
, NULL
);
300 err_release_mem_region
:
301 release_mem_region(adc
->mem
->start
, resource_size(adc
->mem
));
308 static int __devexit
jz4740_adc_remove(struct platform_device
*pdev
)
310 struct jz4740_adc
*adc
= platform_get_drvdata(pdev
);
312 mfd_remove_devices(&pdev
->dev
);
314 irq_remove_generic_chip(adc
->gc
, IRQ_MSK(5), IRQ_NOPROBE
| IRQ_LEVEL
, 0);
316 irq_set_handler_data(adc
->irq
, NULL
);
317 irq_set_chained_handler(adc
->irq
, NULL
);
320 release_mem_region(adc
->mem
->start
, resource_size(adc
->mem
));
324 platform_set_drvdata(pdev
, NULL
);
331 static struct platform_driver jz4740_adc_driver
= {
332 .probe
= jz4740_adc_probe
,
333 .remove
= __devexit_p(jz4740_adc_remove
),
335 .name
= "jz4740-adc",
336 .owner
= THIS_MODULE
,
340 static int __init
jz4740_adc_init(void)
342 return platform_driver_register(&jz4740_adc_driver
);
344 module_init(jz4740_adc_init
);
346 static void __exit
jz4740_adc_exit(void)
348 platform_driver_unregister(&jz4740_adc_driver
);
350 module_exit(jz4740_adc_exit
);
352 MODULE_DESCRIPTION("JZ4740 SoC ADC driver");
353 MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
354 MODULE_LICENSE("GPL");
355 MODULE_ALIAS("platform:jz4740-adc");