2 * Machine check handler.
4 * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs.
5 * Rest from unknown author(s).
6 * 2004 Andi Kleen. Rewrote most of it.
7 * Copyright 2008 Intel Corporation
10 #include <linux/thread_info.h>
11 #include <linux/capability.h>
12 #include <linux/miscdevice.h>
13 #include <linux/ratelimit.h>
14 #include <linux/kallsyms.h>
15 #include <linux/rcupdate.h>
16 #include <linux/kobject.h>
17 #include <linux/uaccess.h>
18 #include <linux/kdebug.h>
19 #include <linux/kernel.h>
20 #include <linux/percpu.h>
21 #include <linux/string.h>
22 #include <linux/sysdev.h>
23 #include <linux/syscore_ops.h>
24 #include <linux/delay.h>
25 #include <linux/ctype.h>
26 #include <linux/sched.h>
27 #include <linux/sysfs.h>
28 #include <linux/types.h>
29 #include <linux/slab.h>
30 #include <linux/init.h>
31 #include <linux/kmod.h>
32 #include <linux/poll.h>
33 #include <linux/nmi.h>
34 #include <linux/cpu.h>
35 #include <linux/smp.h>
38 #include <linux/debugfs.h>
39 #include <linux/edac_mce.h>
40 #include <linux/irq_work.h>
42 #include <asm/processor.h>
46 #include "mce-internal.h"
48 static DEFINE_MUTEX(mce_chrdev_read_mutex
);
50 #define rcu_dereference_check_mce(p) \
51 rcu_dereference_index_check((p), \
52 rcu_read_lock_sched_held() || \
53 lockdep_is_held(&mce_chrdev_read_mutex))
55 #define CREATE_TRACE_POINTS
56 #include <trace/events/mce.h>
58 int mce_disabled __read_mostly
;
60 #define MISC_MCELOG_MINOR 227
62 #define SPINUNIT 100 /* 100ns */
66 DEFINE_PER_CPU(unsigned, mce_exception_count
);
70 * 0: always panic on uncorrected errors, log corrected errors
71 * 1: panic or SIGBUS on uncorrected errors, log corrected errors
72 * 2: SIGBUS or log uncorrected errors (if possible), log corrected errors
73 * 3: never panic or SIGBUS, log all errors (for testing only)
75 static int tolerant __read_mostly
= 1;
76 static int banks __read_mostly
;
77 static int rip_msr __read_mostly
;
78 static int mce_bootlog __read_mostly
= -1;
79 static int monarch_timeout __read_mostly
= -1;
80 static int mce_panic_timeout __read_mostly
;
81 static int mce_dont_log_ce __read_mostly
;
82 int mce_cmci_disabled __read_mostly
;
83 int mce_ignore_ce __read_mostly
;
84 int mce_ser __read_mostly
;
86 struct mce_bank
*mce_banks __read_mostly
;
88 /* User mode helper program triggered by machine check event */
89 static unsigned long mce_need_notify
;
90 static char mce_helper
[128];
91 static char *mce_helper_argv
[2] = { mce_helper
, NULL
};
93 static DECLARE_WAIT_QUEUE_HEAD(mce_chrdev_wait
);
95 static DEFINE_PER_CPU(struct mce
, mces_seen
);
96 static int cpu_missing
;
99 * CPU/chipset specific EDAC code can register a notifier call here to print
100 * MCE errors in a human-readable form.
102 ATOMIC_NOTIFIER_HEAD(x86_mce_decoder_chain
);
103 EXPORT_SYMBOL_GPL(x86_mce_decoder_chain
);
105 /* MCA banks polled by the period polling timer for corrected events */
106 DEFINE_PER_CPU(mce_banks_t
, mce_poll_banks
) = {
107 [0 ... BITS_TO_LONGS(MAX_NR_BANKS
)-1] = ~0UL
110 static DEFINE_PER_CPU(struct work_struct
, mce_work
);
112 /* Do initial initialization of a struct mce */
113 void mce_setup(struct mce
*m
)
115 memset(m
, 0, sizeof(struct mce
));
116 m
->cpu
= m
->extcpu
= smp_processor_id();
118 /* We hope get_seconds stays lockless */
119 m
->time
= get_seconds();
120 m
->cpuvendor
= boot_cpu_data
.x86_vendor
;
121 m
->cpuid
= cpuid_eax(1);
123 m
->socketid
= cpu_data(m
->extcpu
).phys_proc_id
;
125 m
->apicid
= cpu_data(m
->extcpu
).initial_apicid
;
126 rdmsrl(MSR_IA32_MCG_CAP
, m
->mcgcap
);
129 DEFINE_PER_CPU(struct mce
, injectm
);
130 EXPORT_PER_CPU_SYMBOL_GPL(injectm
);
133 * Lockless MCE logging infrastructure.
134 * This avoids deadlocks on printk locks without having to break locks. Also
135 * separate MCEs from kernel messages to avoid bogus bug reports.
138 static struct mce_log mcelog
= {
139 .signature
= MCE_LOG_SIGNATURE
,
141 .recordlen
= sizeof(struct mce
),
144 void mce_log(struct mce
*mce
)
146 unsigned next
, entry
;
148 /* Emit the trace record: */
149 trace_mce_record(mce
);
154 entry
= rcu_dereference_check_mce(mcelog
.next
);
157 * If edac_mce is enabled, it will check the error type
158 * and will process it, if it is a known error.
159 * Otherwise, the error will be sent through mcelog
162 if (edac_mce_parse(mce
))
166 * When the buffer fills up discard new entries.
167 * Assume that the earlier errors are the more
170 if (entry
>= MCE_LOG_LEN
) {
171 set_bit(MCE_OVERFLOW
,
172 (unsigned long *)&mcelog
.flags
);
175 /* Old left over entry. Skip: */
176 if (mcelog
.entry
[entry
].finished
) {
184 if (cmpxchg(&mcelog
.next
, entry
, next
) == entry
)
187 memcpy(mcelog
.entry
+ entry
, mce
, sizeof(struct mce
));
189 mcelog
.entry
[entry
].finished
= 1;
193 set_bit(0, &mce_need_notify
);
196 static void print_mce(struct mce
*m
)
200 pr_emerg(HW_ERR
"CPU %d: Machine Check Exception: %Lx Bank %d: %016Lx\n",
201 m
->extcpu
, m
->mcgstatus
, m
->bank
, m
->status
);
204 pr_emerg(HW_ERR
"RIP%s %02x:<%016Lx> ",
205 !(m
->mcgstatus
& MCG_STATUS_EIPV
) ? " !INEXACT!" : "",
208 if (m
->cs
== __KERNEL_CS
)
209 print_symbol("{%s}", m
->ip
);
213 pr_emerg(HW_ERR
"TSC %llx ", m
->tsc
);
215 pr_cont("ADDR %llx ", m
->addr
);
217 pr_cont("MISC %llx ", m
->misc
);
220 pr_emerg(HW_ERR
"PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x\n",
221 m
->cpuvendor
, m
->cpuid
, m
->time
, m
->socketid
, m
->apicid
);
224 * Print out human-readable details about the MCE error,
225 * (if the CPU has an implementation for that)
227 ret
= atomic_notifier_call_chain(&x86_mce_decoder_chain
, 0, m
);
228 if (ret
== NOTIFY_STOP
)
231 pr_emerg_ratelimited(HW_ERR
"Run the above through 'mcelog --ascii'\n");
234 #define PANIC_TIMEOUT 5 /* 5 seconds */
236 static atomic_t mce_paniced
;
238 static int fake_panic
;
239 static atomic_t mce_fake_paniced
;
241 /* Panic in progress. Enable interrupts and wait for final IPI */
242 static void wait_for_panic(void)
244 long timeout
= PANIC_TIMEOUT
*USEC_PER_SEC
;
248 while (timeout
-- > 0)
250 if (panic_timeout
== 0)
251 panic_timeout
= mce_panic_timeout
;
252 panic("Panicing machine check CPU died");
255 static void mce_panic(char *msg
, struct mce
*final
, char *exp
)
261 * Make sure only one CPU runs in machine check panic
263 if (atomic_inc_return(&mce_paniced
) > 1)
270 /* Don't log too much for fake panic */
271 if (atomic_inc_return(&mce_fake_paniced
) > 1)
274 /* First print corrected ones that are still unlogged */
275 for (i
= 0; i
< MCE_LOG_LEN
; i
++) {
276 struct mce
*m
= &mcelog
.entry
[i
];
277 if (!(m
->status
& MCI_STATUS_VAL
))
279 if (!(m
->status
& MCI_STATUS_UC
)) {
282 apei_err
= apei_write_mce(m
);
285 /* Now print uncorrected but with the final one last */
286 for (i
= 0; i
< MCE_LOG_LEN
; i
++) {
287 struct mce
*m
= &mcelog
.entry
[i
];
288 if (!(m
->status
& MCI_STATUS_VAL
))
290 if (!(m
->status
& MCI_STATUS_UC
))
292 if (!final
|| memcmp(m
, final
, sizeof(struct mce
))) {
295 apei_err
= apei_write_mce(m
);
301 apei_err
= apei_write_mce(final
);
304 pr_emerg(HW_ERR
"Some CPUs didn't answer in synchronization\n");
306 pr_emerg(HW_ERR
"Machine check: %s\n", exp
);
308 if (panic_timeout
== 0)
309 panic_timeout
= mce_panic_timeout
;
312 pr_emerg(HW_ERR
"Fake kernel panic: %s\n", msg
);
315 /* Support code for software error injection */
317 static int msr_to_offset(u32 msr
)
319 unsigned bank
= __this_cpu_read(injectm
.bank
);
322 return offsetof(struct mce
, ip
);
323 if (msr
== MSR_IA32_MCx_STATUS(bank
))
324 return offsetof(struct mce
, status
);
325 if (msr
== MSR_IA32_MCx_ADDR(bank
))
326 return offsetof(struct mce
, addr
);
327 if (msr
== MSR_IA32_MCx_MISC(bank
))
328 return offsetof(struct mce
, misc
);
329 if (msr
== MSR_IA32_MCG_STATUS
)
330 return offsetof(struct mce
, mcgstatus
);
334 /* MSR access wrappers used for error injection */
335 static u64
mce_rdmsrl(u32 msr
)
339 if (__this_cpu_read(injectm
.finished
)) {
340 int offset
= msr_to_offset(msr
);
344 return *(u64
*)((char *)&__get_cpu_var(injectm
) + offset
);
347 if (rdmsrl_safe(msr
, &v
)) {
348 WARN_ONCE(1, "mce: Unable to read msr %d!\n", msr
);
350 * Return zero in case the access faulted. This should
351 * not happen normally but can happen if the CPU does
352 * something weird, or if the code is buggy.
360 static void mce_wrmsrl(u32 msr
, u64 v
)
362 if (__this_cpu_read(injectm
.finished
)) {
363 int offset
= msr_to_offset(msr
);
366 *(u64
*)((char *)&__get_cpu_var(injectm
) + offset
) = v
;
373 * Collect all global (w.r.t. this processor) status about this machine
374 * check into our "mce" struct so that we can use it later to assess
375 * the severity of the problem as we read per-bank specific details.
377 static inline void mce_gather_info(struct mce
*m
, struct pt_regs
*regs
)
381 m
->mcgstatus
= mce_rdmsrl(MSR_IA32_MCG_STATUS
);
384 * Get the address of the instruction at the time of
385 * the machine check error.
387 if (m
->mcgstatus
& (MCG_STATUS_RIPV
|MCG_STATUS_EIPV
)) {
391 /* Use accurate RIP reporting if available. */
393 m
->ip
= mce_rdmsrl(rip_msr
);
398 * Simple lockless ring to communicate PFNs from the exception handler with the
399 * process context work function. This is vastly simplified because there's
400 * only a single reader and a single writer.
402 #define MCE_RING_SIZE 16 /* we use one entry less */
405 unsigned short start
;
407 unsigned long ring
[MCE_RING_SIZE
];
409 static DEFINE_PER_CPU(struct mce_ring
, mce_ring
);
411 /* Runs with CPU affinity in workqueue */
412 static int mce_ring_empty(void)
414 struct mce_ring
*r
= &__get_cpu_var(mce_ring
);
416 return r
->start
== r
->end
;
419 static int mce_ring_get(unsigned long *pfn
)
426 r
= &__get_cpu_var(mce_ring
);
427 if (r
->start
== r
->end
)
429 *pfn
= r
->ring
[r
->start
];
430 r
->start
= (r
->start
+ 1) % MCE_RING_SIZE
;
437 /* Always runs in MCE context with preempt off */
438 static int mce_ring_add(unsigned long pfn
)
440 struct mce_ring
*r
= &__get_cpu_var(mce_ring
);
443 next
= (r
->end
+ 1) % MCE_RING_SIZE
;
444 if (next
== r
->start
)
446 r
->ring
[r
->end
] = pfn
;
452 int mce_available(struct cpuinfo_x86
*c
)
456 return cpu_has(c
, X86_FEATURE_MCE
) && cpu_has(c
, X86_FEATURE_MCA
);
459 static void mce_schedule_work(void)
461 if (!mce_ring_empty()) {
462 struct work_struct
*work
= &__get_cpu_var(mce_work
);
463 if (!work_pending(work
))
468 DEFINE_PER_CPU(struct irq_work
, mce_irq_work
);
470 static void mce_irq_work_cb(struct irq_work
*entry
)
476 static void mce_report_event(struct pt_regs
*regs
)
478 if (regs
->flags
& (X86_VM_MASK
|X86_EFLAGS_IF
)) {
481 * Triggering the work queue here is just an insurance
482 * policy in case the syscall exit notify handler
483 * doesn't run soon enough or ends up running on the
484 * wrong CPU (can happen when audit sleeps)
490 irq_work_queue(&__get_cpu_var(mce_irq_work
));
493 DEFINE_PER_CPU(unsigned, mce_poll_count
);
496 * Poll for corrected events or events that happened before reset.
497 * Those are just logged through /dev/mcelog.
499 * This is executed in standard interrupt context.
501 * Note: spec recommends to panic for fatal unsignalled
502 * errors here. However this would be quite problematic --
503 * we would need to reimplement the Monarch handling and
504 * it would mess up the exclusion between exception handler
505 * and poll hander -- * so we skip this for now.
506 * These cases should not happen anyways, or only when the CPU
507 * is already totally * confused. In this case it's likely it will
508 * not fully execute the machine check handler either.
510 void machine_check_poll(enum mcp_flags flags
, mce_banks_t
*b
)
515 percpu_inc(mce_poll_count
);
517 mce_gather_info(&m
, NULL
);
519 for (i
= 0; i
< banks
; i
++) {
520 if (!mce_banks
[i
].ctl
|| !test_bit(i
, *b
))
529 m
.status
= mce_rdmsrl(MSR_IA32_MCx_STATUS(i
));
530 if (!(m
.status
& MCI_STATUS_VAL
))
534 * Uncorrected or signalled events are handled by the exception
535 * handler when it is enabled, so don't process those here.
537 * TBD do the same check for MCI_STATUS_EN here?
539 if (!(flags
& MCP_UC
) &&
540 (m
.status
& (mce_ser
? MCI_STATUS_S
: MCI_STATUS_UC
)))
543 if (m
.status
& MCI_STATUS_MISCV
)
544 m
.misc
= mce_rdmsrl(MSR_IA32_MCx_MISC(i
));
545 if (m
.status
& MCI_STATUS_ADDRV
)
546 m
.addr
= mce_rdmsrl(MSR_IA32_MCx_ADDR(i
));
548 if (!(flags
& MCP_TIMESTAMP
))
551 * Don't get the IP here because it's unlikely to
552 * have anything to do with the actual error location.
554 if (!(flags
& MCP_DONTLOG
) && !mce_dont_log_ce
) {
556 atomic_notifier_call_chain(&x86_mce_decoder_chain
, 0, &m
);
560 * Clear state for this bank.
562 mce_wrmsrl(MSR_IA32_MCx_STATUS(i
), 0);
566 * Don't clear MCG_STATUS here because it's only defined for
572 EXPORT_SYMBOL_GPL(machine_check_poll
);
575 * Do a quick check if any of the events requires a panic.
576 * This decides if we keep the events around or clear them.
578 static int mce_no_way_out(struct mce
*m
, char **msg
)
582 for (i
= 0; i
< banks
; i
++) {
583 m
->status
= mce_rdmsrl(MSR_IA32_MCx_STATUS(i
));
584 if (mce_severity(m
, tolerant
, msg
) >= MCE_PANIC_SEVERITY
)
591 * Variable to establish order between CPUs while scanning.
592 * Each CPU spins initially until executing is equal its number.
594 static atomic_t mce_executing
;
597 * Defines order of CPUs on entry. First CPU becomes Monarch.
599 static atomic_t mce_callin
;
602 * Check if a timeout waiting for other CPUs happened.
604 static int mce_timed_out(u64
*t
)
607 * The others already did panic for some reason.
608 * Bail out like in a timeout.
609 * rmb() to tell the compiler that system_state
610 * might have been modified by someone else.
613 if (atomic_read(&mce_paniced
))
615 if (!monarch_timeout
)
617 if ((s64
)*t
< SPINUNIT
) {
618 /* CHECKME: Make panic default for 1 too? */
620 mce_panic("Timeout synchronizing machine check over CPUs",
627 touch_nmi_watchdog();
632 * The Monarch's reign. The Monarch is the CPU who entered
633 * the machine check handler first. It waits for the others to
634 * raise the exception too and then grades them. When any
635 * error is fatal panic. Only then let the others continue.
637 * The other CPUs entering the MCE handler will be controlled by the
638 * Monarch. They are called Subjects.
640 * This way we prevent any potential data corruption in a unrecoverable case
641 * and also makes sure always all CPU's errors are examined.
643 * Also this detects the case of a machine check event coming from outer
644 * space (not detected by any CPUs) In this case some external agent wants
645 * us to shut down, so panic too.
647 * The other CPUs might still decide to panic if the handler happens
648 * in a unrecoverable place, but in this case the system is in a semi-stable
649 * state and won't corrupt anything by itself. It's ok to let the others
650 * continue for a bit first.
652 * All the spin loops have timeouts; when a timeout happens a CPU
653 * typically elects itself to be Monarch.
655 static void mce_reign(void)
658 struct mce
*m
= NULL
;
659 int global_worst
= 0;
664 * This CPU is the Monarch and the other CPUs have run
665 * through their handlers.
666 * Grade the severity of the errors of all the CPUs.
668 for_each_possible_cpu(cpu
) {
669 int severity
= mce_severity(&per_cpu(mces_seen
, cpu
), tolerant
,
671 if (severity
> global_worst
) {
673 global_worst
= severity
;
674 m
= &per_cpu(mces_seen
, cpu
);
679 * Cannot recover? Panic here then.
680 * This dumps all the mces in the log buffer and stops the
683 if (m
&& global_worst
>= MCE_PANIC_SEVERITY
&& tolerant
< 3)
684 mce_panic("Fatal Machine check", m
, msg
);
687 * For UC somewhere we let the CPU who detects it handle it.
688 * Also must let continue the others, otherwise the handling
689 * CPU could deadlock on a lock.
693 * No machine check event found. Must be some external
694 * source or one CPU is hung. Panic.
696 if (global_worst
<= MCE_KEEP_SEVERITY
&& tolerant
< 3)
697 mce_panic("Machine check from unknown source", NULL
, NULL
);
700 * Now clear all the mces_seen so that they don't reappear on
703 for_each_possible_cpu(cpu
)
704 memset(&per_cpu(mces_seen
, cpu
), 0, sizeof(struct mce
));
707 static atomic_t global_nwo
;
710 * Start of Monarch synchronization. This waits until all CPUs have
711 * entered the exception handler and then determines if any of them
712 * saw a fatal event that requires panic. Then it executes them
713 * in the entry order.
714 * TBD double check parallel CPU hotunplug
716 static int mce_start(int *no_way_out
)
719 int cpus
= num_online_cpus();
720 u64 timeout
= (u64
)monarch_timeout
* NSEC_PER_USEC
;
725 atomic_add(*no_way_out
, &global_nwo
);
727 * global_nwo should be updated before mce_callin
730 order
= atomic_inc_return(&mce_callin
);
735 while (atomic_read(&mce_callin
) != cpus
) {
736 if (mce_timed_out(&timeout
)) {
737 atomic_set(&global_nwo
, 0);
744 * mce_callin should be read before global_nwo
750 * Monarch: Starts executing now, the others wait.
752 atomic_set(&mce_executing
, 1);
755 * Subject: Now start the scanning loop one by one in
756 * the original callin order.
757 * This way when there are any shared banks it will be
758 * only seen by one CPU before cleared, avoiding duplicates.
760 while (atomic_read(&mce_executing
) < order
) {
761 if (mce_timed_out(&timeout
)) {
762 atomic_set(&global_nwo
, 0);
770 * Cache the global no_way_out state.
772 *no_way_out
= atomic_read(&global_nwo
);
778 * Synchronize between CPUs after main scanning loop.
779 * This invokes the bulk of the Monarch processing.
781 static int mce_end(int order
)
784 u64 timeout
= (u64
)monarch_timeout
* NSEC_PER_USEC
;
792 * Allow others to run.
794 atomic_inc(&mce_executing
);
797 /* CHECKME: Can this race with a parallel hotplug? */
798 int cpus
= num_online_cpus();
801 * Monarch: Wait for everyone to go through their scanning
804 while (atomic_read(&mce_executing
) <= cpus
) {
805 if (mce_timed_out(&timeout
))
815 * Subject: Wait for Monarch to finish.
817 while (atomic_read(&mce_executing
) != 0) {
818 if (mce_timed_out(&timeout
))
824 * Don't reset anything. That's done by the Monarch.
830 * Reset all global state.
833 atomic_set(&global_nwo
, 0);
834 atomic_set(&mce_callin
, 0);
838 * Let others run again.
840 atomic_set(&mce_executing
, 0);
845 * Check if the address reported by the CPU is in a format we can parse.
846 * It would be possible to add code for most other cases, but all would
847 * be somewhat complicated (e.g. segment offset would require an instruction
848 * parser). So only support physical addresses up to page granuality for now.
850 static int mce_usable_address(struct mce
*m
)
852 if (!(m
->status
& MCI_STATUS_MISCV
) || !(m
->status
& MCI_STATUS_ADDRV
))
854 if (MCI_MISC_ADDR_LSB(m
->misc
) > PAGE_SHIFT
)
856 if (MCI_MISC_ADDR_MODE(m
->misc
) != MCI_MISC_ADDR_PHYS
)
861 static void mce_clear_state(unsigned long *toclear
)
865 for (i
= 0; i
< banks
; i
++) {
866 if (test_bit(i
, toclear
))
867 mce_wrmsrl(MSR_IA32_MCx_STATUS(i
), 0);
872 * The actual machine check handler. This only handles real
873 * exceptions when something got corrupted coming in through int 18.
875 * This is executed in NMI context not subject to normal locking rules. This
876 * implies that most kernel services cannot be safely used. Don't even
877 * think about putting a printk in there!
879 * On Intel systems this is entered on all CPUs in parallel through
880 * MCE broadcast. However some CPUs might be broken beyond repair,
881 * so be always careful when synchronizing with others.
883 void do_machine_check(struct pt_regs
*regs
, long error_code
)
885 struct mce m
, *final
;
890 * Establish sequential order between the CPUs entering the machine
895 * If no_way_out gets set, there is no safe way to recover from this
896 * MCE. If tolerant is cranked up, we'll try anyway.
900 * If kill_it gets set, there might be a way to recover from this
904 DECLARE_BITMAP(toclear
, MAX_NR_BANKS
);
905 char *msg
= "Unknown";
907 atomic_inc(&mce_entry
);
909 percpu_inc(mce_exception_count
);
911 if (notify_die(DIE_NMI
, "machine check", regs
, error_code
,
912 18, SIGKILL
) == NOTIFY_STOP
)
917 mce_gather_info(&m
, regs
);
919 final
= &__get_cpu_var(mces_seen
);
922 no_way_out
= mce_no_way_out(&m
, &msg
);
927 * When no restart IP must always kill or panic.
929 if (!(m
.mcgstatus
& MCG_STATUS_RIPV
))
933 * Go through all the banks in exclusion of the other CPUs.
934 * This way we don't report duplicated events on shared banks
935 * because the first one to see it will clear it.
937 order
= mce_start(&no_way_out
);
938 for (i
= 0; i
< banks
; i
++) {
939 __clear_bit(i
, toclear
);
940 if (!mce_banks
[i
].ctl
)
947 m
.status
= mce_rdmsrl(MSR_IA32_MCx_STATUS(i
));
948 if ((m
.status
& MCI_STATUS_VAL
) == 0)
952 * Non uncorrected or non signaled errors are handled by
953 * machine_check_poll. Leave them alone, unless this panics.
955 if (!(m
.status
& (mce_ser
? MCI_STATUS_S
: MCI_STATUS_UC
)) &&
960 * Set taint even when machine check was not enabled.
962 add_taint(TAINT_MACHINE_CHECK
);
964 severity
= mce_severity(&m
, tolerant
, NULL
);
967 * When machine check was for corrected handler don't touch,
968 * unless we're panicing.
970 if (severity
== MCE_KEEP_SEVERITY
&& !no_way_out
)
972 __set_bit(i
, toclear
);
973 if (severity
== MCE_NO_SEVERITY
) {
975 * Machine check event was not enabled. Clear, but
982 * Kill on action required.
984 if (severity
== MCE_AR_SEVERITY
)
987 if (m
.status
& MCI_STATUS_MISCV
)
988 m
.misc
= mce_rdmsrl(MSR_IA32_MCx_MISC(i
));
989 if (m
.status
& MCI_STATUS_ADDRV
)
990 m
.addr
= mce_rdmsrl(MSR_IA32_MCx_ADDR(i
));
993 * Action optional error. Queue address for later processing.
994 * When the ring overflows we just ignore the AO error.
995 * RED-PEN add some logging mechanism when
996 * usable_address or mce_add_ring fails.
997 * RED-PEN don't ignore overflow for tolerant == 0
999 if (severity
== MCE_AO_SEVERITY
&& mce_usable_address(&m
))
1000 mce_ring_add(m
.addr
>> PAGE_SHIFT
);
1004 if (severity
> worst
) {
1011 mce_clear_state(toclear
);
1014 * Do most of the synchronization with other CPUs.
1015 * When there's any problem use only local no_way_out state.
1017 if (mce_end(order
) < 0)
1018 no_way_out
= worst
>= MCE_PANIC_SEVERITY
;
1021 * If we have decided that we just CAN'T continue, and the user
1022 * has not set tolerant to an insane level, give up and die.
1024 * This is mainly used in the case when the system doesn't
1025 * support MCE broadcasting or it has been disabled.
1027 if (no_way_out
&& tolerant
< 3)
1028 mce_panic("Fatal machine check on current CPU", final
, msg
);
1031 * If the error seems to be unrecoverable, something should be
1032 * done. Try to kill as little as possible. If we can kill just
1033 * one task, do that. If the user has set the tolerance very
1034 * high, don't try to do anything at all.
1037 if (kill_it
&& tolerant
< 3)
1038 force_sig(SIGBUS
, current
);
1040 /* notify userspace ASAP */
1041 set_thread_flag(TIF_MCE_NOTIFY
);
1044 mce_report_event(regs
);
1045 mce_wrmsrl(MSR_IA32_MCG_STATUS
, 0);
1047 atomic_dec(&mce_entry
);
1050 EXPORT_SYMBOL_GPL(do_machine_check
);
1052 /* dummy to break dependency. actual code is in mm/memory-failure.c */
1053 void __attribute__((weak
)) memory_failure(unsigned long pfn
, int vector
)
1055 printk(KERN_ERR
"Action optional memory failure at %lx ignored\n", pfn
);
1059 * Called after mce notification in process context. This code
1060 * is allowed to sleep. Call the high level VM handler to process
1061 * any corrupted pages.
1062 * Assume that the work queue code only calls this one at a time
1064 * Note we don't disable preemption, so this code might run on the wrong
1065 * CPU. In this case the event is picked up by the scheduled work queue.
1066 * This is merely a fast path to expedite processing in some common
1069 void mce_notify_process(void)
1073 while (mce_ring_get(&pfn
))
1074 memory_failure(pfn
, MCE_VECTOR
);
1077 static void mce_process_work(struct work_struct
*dummy
)
1079 mce_notify_process();
1082 #ifdef CONFIG_X86_MCE_INTEL
1084 * mce_log_therm_throt_event - Logs the thermal throttling event to mcelog
1085 * @cpu: The CPU on which the event occurred.
1086 * @status: Event status information
1088 * This function should be called by the thermal interrupt after the
1089 * event has been processed and the decision was made to log the event
1092 * The status parameter will be saved to the 'status' field of 'struct mce'
1093 * and historically has been the register value of the
1094 * MSR_IA32_THERMAL_STATUS (Intel) msr.
1096 void mce_log_therm_throt_event(__u64 status
)
1101 m
.bank
= MCE_THERMAL_BANK
;
1105 #endif /* CONFIG_X86_MCE_INTEL */
1108 * Periodic polling timer for "silent" machine check errors. If the
1109 * poller finds an MCE, poll 2x faster. When the poller finds no more
1110 * errors, poll 2x slower (up to check_interval seconds).
1112 static int check_interval
= 5 * 60; /* 5 minutes */
1114 static DEFINE_PER_CPU(int, mce_next_interval
); /* in jiffies */
1115 static DEFINE_PER_CPU(struct timer_list
, mce_timer
);
1117 static void mce_start_timer(unsigned long data
)
1119 struct timer_list
*t
= &per_cpu(mce_timer
, data
);
1122 WARN_ON(smp_processor_id() != data
);
1124 if (mce_available(__this_cpu_ptr(&cpu_info
))) {
1125 machine_check_poll(MCP_TIMESTAMP
,
1126 &__get_cpu_var(mce_poll_banks
));
1130 * Alert userspace if needed. If we logged an MCE, reduce the
1131 * polling interval, otherwise increase the polling interval.
1133 n
= &__get_cpu_var(mce_next_interval
);
1134 if (mce_notify_irq())
1135 *n
= max(*n
/2, HZ
/100);
1137 *n
= min(*n
*2, (int)round_jiffies_relative(check_interval
*HZ
));
1139 t
->expires
= jiffies
+ *n
;
1140 add_timer_on(t
, smp_processor_id());
1143 static void mce_do_trigger(struct work_struct
*work
)
1145 call_usermodehelper(mce_helper
, mce_helper_argv
, NULL
, UMH_NO_WAIT
);
1148 static DECLARE_WORK(mce_trigger_work
, mce_do_trigger
);
1151 * Notify the user(s) about new machine check events.
1152 * Can be called from interrupt context, but not from machine check/NMI
1155 int mce_notify_irq(void)
1157 /* Not more than two messages every minute */
1158 static DEFINE_RATELIMIT_STATE(ratelimit
, 60*HZ
, 2);
1160 clear_thread_flag(TIF_MCE_NOTIFY
);
1162 if (test_and_clear_bit(0, &mce_need_notify
)) {
1163 /* wake processes polling /dev/mcelog */
1164 wake_up_interruptible(&mce_chrdev_wait
);
1167 * There is no risk of missing notifications because
1168 * work_pending is always cleared before the function is
1171 if (mce_helper
[0] && !work_pending(&mce_trigger_work
))
1172 schedule_work(&mce_trigger_work
);
1174 if (__ratelimit(&ratelimit
))
1175 pr_info(HW_ERR
"Machine check events logged\n");
1181 EXPORT_SYMBOL_GPL(mce_notify_irq
);
1183 static int __cpuinit
__mcheck_cpu_mce_banks_init(void)
1187 mce_banks
= kzalloc(banks
* sizeof(struct mce_bank
), GFP_KERNEL
);
1190 for (i
= 0; i
< banks
; i
++) {
1191 struct mce_bank
*b
= &mce_banks
[i
];
1200 * Initialize Machine Checks for a CPU.
1202 static int __cpuinit
__mcheck_cpu_cap_init(void)
1207 rdmsrl(MSR_IA32_MCG_CAP
, cap
);
1209 b
= cap
& MCG_BANKCNT_MASK
;
1211 printk(KERN_INFO
"mce: CPU supports %d MCE banks\n", b
);
1213 if (b
> MAX_NR_BANKS
) {
1215 "MCE: Using only %u machine check banks out of %u\n",
1220 /* Don't support asymmetric configurations today */
1221 WARN_ON(banks
!= 0 && b
!= banks
);
1224 int err
= __mcheck_cpu_mce_banks_init();
1230 /* Use accurate RIP reporting if available. */
1231 if ((cap
& MCG_EXT_P
) && MCG_EXT_CNT(cap
) >= 9)
1232 rip_msr
= MSR_IA32_MCG_EIP
;
1234 if (cap
& MCG_SER_P
)
1240 static void __mcheck_cpu_init_generic(void)
1242 mce_banks_t all_banks
;
1247 * Log the machine checks left over from the previous reset.
1249 bitmap_fill(all_banks
, MAX_NR_BANKS
);
1250 machine_check_poll(MCP_UC
|(!mce_bootlog
? MCP_DONTLOG
: 0), &all_banks
);
1252 set_in_cr4(X86_CR4_MCE
);
1254 rdmsrl(MSR_IA32_MCG_CAP
, cap
);
1255 if (cap
& MCG_CTL_P
)
1256 wrmsr(MSR_IA32_MCG_CTL
, 0xffffffff, 0xffffffff);
1258 for (i
= 0; i
< banks
; i
++) {
1259 struct mce_bank
*b
= &mce_banks
[i
];
1263 wrmsrl(MSR_IA32_MCx_CTL(i
), b
->ctl
);
1264 wrmsrl(MSR_IA32_MCx_STATUS(i
), 0);
1268 /* Add per CPU specific workarounds here */
1269 static int __cpuinit
__mcheck_cpu_apply_quirks(struct cpuinfo_x86
*c
)
1271 if (c
->x86_vendor
== X86_VENDOR_UNKNOWN
) {
1272 pr_info("MCE: unknown CPU type - not enabling MCE support.\n");
1276 /* This should be disabled by the BIOS, but isn't always */
1277 if (c
->x86_vendor
== X86_VENDOR_AMD
) {
1278 if (c
->x86
== 15 && banks
> 4) {
1280 * disable GART TBL walk error reporting, which
1281 * trips off incorrectly with the IOMMU & 3ware
1284 clear_bit(10, (unsigned long *)&mce_banks
[4].ctl
);
1286 if (c
->x86
<= 17 && mce_bootlog
< 0) {
1288 * Lots of broken BIOS around that don't clear them
1289 * by default and leave crap in there. Don't log:
1294 * Various K7s with broken bank 0 around. Always disable
1297 if (c
->x86
== 6 && banks
> 0)
1298 mce_banks
[0].ctl
= 0;
1301 if (c
->x86_vendor
== X86_VENDOR_INTEL
) {
1303 * SDM documents that on family 6 bank 0 should not be written
1304 * because it aliases to another special BIOS controlled
1306 * But it's not aliased anymore on model 0x1a+
1307 * Don't ignore bank 0 completely because there could be a
1308 * valid event later, merely don't write CTL0.
1311 if (c
->x86
== 6 && c
->x86_model
< 0x1A && banks
> 0)
1312 mce_banks
[0].init
= 0;
1315 * All newer Intel systems support MCE broadcasting. Enable
1316 * synchronization with a one second timeout.
1318 if ((c
->x86
> 6 || (c
->x86
== 6 && c
->x86_model
>= 0xe)) &&
1319 monarch_timeout
< 0)
1320 monarch_timeout
= USEC_PER_SEC
;
1323 * There are also broken BIOSes on some Pentium M and
1326 if (c
->x86
== 6 && c
->x86_model
<= 13 && mce_bootlog
< 0)
1329 if (monarch_timeout
< 0)
1330 monarch_timeout
= 0;
1331 if (mce_bootlog
!= 0)
1332 mce_panic_timeout
= 30;
1337 static int __cpuinit
__mcheck_cpu_ancient_init(struct cpuinfo_x86
*c
)
1342 switch (c
->x86_vendor
) {
1343 case X86_VENDOR_INTEL
:
1344 intel_p5_mcheck_init(c
);
1347 case X86_VENDOR_CENTAUR
:
1348 winchip_mcheck_init(c
);
1356 static void __mcheck_cpu_init_vendor(struct cpuinfo_x86
*c
)
1358 switch (c
->x86_vendor
) {
1359 case X86_VENDOR_INTEL
:
1360 mce_intel_feature_init(c
);
1362 case X86_VENDOR_AMD
:
1363 mce_amd_feature_init(c
);
1370 static void __mcheck_cpu_init_timer(void)
1372 struct timer_list
*t
= &__get_cpu_var(mce_timer
);
1373 int *n
= &__get_cpu_var(mce_next_interval
);
1375 setup_timer(t
, mce_start_timer
, smp_processor_id());
1380 *n
= check_interval
* HZ
;
1383 t
->expires
= round_jiffies(jiffies
+ *n
);
1384 add_timer_on(t
, smp_processor_id());
1387 /* Handle unconfigured int18 (should never happen) */
1388 static void unexpected_machine_check(struct pt_regs
*regs
, long error_code
)
1390 printk(KERN_ERR
"CPU#%d: Unexpected int18 (Machine Check).\n",
1391 smp_processor_id());
1394 /* Call the installed machine check handler for this CPU setup. */
1395 void (*machine_check_vector
)(struct pt_regs
*, long error_code
) =
1396 unexpected_machine_check
;
1399 * Called for each booted CPU to set up machine checks.
1400 * Must be called with preempt off:
1402 void __cpuinit
mcheck_cpu_init(struct cpuinfo_x86
*c
)
1407 if (__mcheck_cpu_ancient_init(c
))
1410 if (!mce_available(c
))
1413 if (__mcheck_cpu_cap_init() < 0 || __mcheck_cpu_apply_quirks(c
) < 0) {
1418 machine_check_vector
= do_machine_check
;
1420 __mcheck_cpu_init_generic();
1421 __mcheck_cpu_init_vendor(c
);
1422 __mcheck_cpu_init_timer();
1423 INIT_WORK(&__get_cpu_var(mce_work
), mce_process_work
);
1424 init_irq_work(&__get_cpu_var(mce_irq_work
), &mce_irq_work_cb
);
1428 * mce_chrdev: Character device /dev/mcelog to read and clear the MCE log.
1431 static DEFINE_SPINLOCK(mce_chrdev_state_lock
);
1432 static int mce_chrdev_open_count
; /* #times opened */
1433 static int mce_chrdev_open_exclu
; /* already open exclusive? */
1435 static int mce_chrdev_open(struct inode
*inode
, struct file
*file
)
1437 spin_lock(&mce_chrdev_state_lock
);
1439 if (mce_chrdev_open_exclu
||
1440 (mce_chrdev_open_count
&& (file
->f_flags
& O_EXCL
))) {
1441 spin_unlock(&mce_chrdev_state_lock
);
1446 if (file
->f_flags
& O_EXCL
)
1447 mce_chrdev_open_exclu
= 1;
1448 mce_chrdev_open_count
++;
1450 spin_unlock(&mce_chrdev_state_lock
);
1452 return nonseekable_open(inode
, file
);
1455 static int mce_chrdev_release(struct inode
*inode
, struct file
*file
)
1457 spin_lock(&mce_chrdev_state_lock
);
1459 mce_chrdev_open_count
--;
1460 mce_chrdev_open_exclu
= 0;
1462 spin_unlock(&mce_chrdev_state_lock
);
1467 static void collect_tscs(void *data
)
1469 unsigned long *cpu_tsc
= (unsigned long *)data
;
1471 rdtscll(cpu_tsc
[smp_processor_id()]);
1474 static int mce_apei_read_done
;
1476 /* Collect MCE record of previous boot in persistent storage via APEI ERST. */
1477 static int __mce_read_apei(char __user
**ubuf
, size_t usize
)
1483 if (usize
< sizeof(struct mce
))
1486 rc
= apei_read_mce(&m
, &record_id
);
1487 /* Error or no more MCE record */
1489 mce_apei_read_done
= 1;
1493 if (copy_to_user(*ubuf
, &m
, sizeof(struct mce
)))
1496 * In fact, we should have cleared the record after that has
1497 * been flushed to the disk or sent to network in
1498 * /sbin/mcelog, but we have no interface to support that now,
1499 * so just clear it to avoid duplication.
1501 rc
= apei_clear_mce(record_id
);
1503 mce_apei_read_done
= 1;
1506 *ubuf
+= sizeof(struct mce
);
1511 static ssize_t
mce_chrdev_read(struct file
*filp
, char __user
*ubuf
,
1512 size_t usize
, loff_t
*off
)
1514 char __user
*buf
= ubuf
;
1515 unsigned long *cpu_tsc
;
1516 unsigned prev
, next
;
1519 cpu_tsc
= kmalloc(nr_cpu_ids
* sizeof(long), GFP_KERNEL
);
1523 mutex_lock(&mce_chrdev_read_mutex
);
1525 if (!mce_apei_read_done
) {
1526 err
= __mce_read_apei(&buf
, usize
);
1527 if (err
|| buf
!= ubuf
)
1531 next
= rcu_dereference_check_mce(mcelog
.next
);
1533 /* Only supports full reads right now */
1535 if (*off
!= 0 || usize
< MCE_LOG_LEN
*sizeof(struct mce
))
1541 for (i
= prev
; i
< next
; i
++) {
1542 unsigned long start
= jiffies
;
1543 struct mce
*m
= &mcelog
.entry
[i
];
1545 while (!m
->finished
) {
1546 if (time_after_eq(jiffies
, start
+ 2)) {
1547 memset(m
, 0, sizeof(*m
));
1553 err
|= copy_to_user(buf
, m
, sizeof(*m
));
1559 memset(mcelog
.entry
+ prev
, 0,
1560 (next
- prev
) * sizeof(struct mce
));
1562 next
= cmpxchg(&mcelog
.next
, prev
, 0);
1563 } while (next
!= prev
);
1565 synchronize_sched();
1568 * Collect entries that were still getting written before the
1571 on_each_cpu(collect_tscs
, cpu_tsc
, 1);
1573 for (i
= next
; i
< MCE_LOG_LEN
; i
++) {
1574 struct mce
*m
= &mcelog
.entry
[i
];
1576 if (m
->finished
&& m
->tsc
< cpu_tsc
[m
->cpu
]) {
1577 err
|= copy_to_user(buf
, m
, sizeof(*m
));
1580 memset(m
, 0, sizeof(*m
));
1588 mutex_unlock(&mce_chrdev_read_mutex
);
1591 return err
? err
: buf
- ubuf
;
1594 static unsigned int mce_chrdev_poll(struct file
*file
, poll_table
*wait
)
1596 poll_wait(file
, &mce_chrdev_wait
, wait
);
1597 if (rcu_access_index(mcelog
.next
))
1598 return POLLIN
| POLLRDNORM
;
1599 if (!mce_apei_read_done
&& apei_check_mce())
1600 return POLLIN
| POLLRDNORM
;
1604 static long mce_chrdev_ioctl(struct file
*f
, unsigned int cmd
,
1607 int __user
*p
= (int __user
*)arg
;
1609 if (!capable(CAP_SYS_ADMIN
))
1613 case MCE_GET_RECORD_LEN
:
1614 return put_user(sizeof(struct mce
), p
);
1615 case MCE_GET_LOG_LEN
:
1616 return put_user(MCE_LOG_LEN
, p
);
1617 case MCE_GETCLEAR_FLAGS
: {
1621 flags
= mcelog
.flags
;
1622 } while (cmpxchg(&mcelog
.flags
, flags
, 0) != flags
);
1624 return put_user(flags
, p
);
1631 /* Modified in mce-inject.c, so not static or const */
1632 struct file_operations mce_chrdev_ops
= {
1633 .open
= mce_chrdev_open
,
1634 .release
= mce_chrdev_release
,
1635 .read
= mce_chrdev_read
,
1636 .poll
= mce_chrdev_poll
,
1637 .unlocked_ioctl
= mce_chrdev_ioctl
,
1638 .llseek
= no_llseek
,
1640 EXPORT_SYMBOL_GPL(mce_chrdev_ops
);
1642 static struct miscdevice mce_chrdev_device
= {
1649 * mce=off Disables machine check
1650 * mce=no_cmci Disables CMCI
1651 * mce=dont_log_ce Clears corrected events silently, no log created for CEs.
1652 * mce=ignore_ce Disables polling and CMCI, corrected events are not cleared.
1653 * mce=TOLERANCELEVEL[,monarchtimeout] (number, see above)
1654 * monarchtimeout is how long to wait for other CPUs on machine
1655 * check, or 0 to not wait
1656 * mce=bootlog Log MCEs from before booting. Disabled by default on AMD.
1657 * mce=nobootlog Don't log MCEs from before booting.
1659 static int __init
mcheck_enable(char *str
)
1667 if (!strcmp(str
, "off"))
1669 else if (!strcmp(str
, "no_cmci"))
1670 mce_cmci_disabled
= 1;
1671 else if (!strcmp(str
, "dont_log_ce"))
1672 mce_dont_log_ce
= 1;
1673 else if (!strcmp(str
, "ignore_ce"))
1675 else if (!strcmp(str
, "bootlog") || !strcmp(str
, "nobootlog"))
1676 mce_bootlog
= (str
[0] == 'b');
1677 else if (isdigit(str
[0])) {
1678 get_option(&str
, &tolerant
);
1681 get_option(&str
, &monarch_timeout
);
1684 printk(KERN_INFO
"mce argument %s ignored. Please use /sys\n",
1690 __setup("mce", mcheck_enable
);
1692 int __init
mcheck_init(void)
1694 mcheck_intel_therm_init();
1704 * Disable machine checks on suspend and shutdown. We can't really handle
1707 static int mce_disable_error_reporting(void)
1711 for (i
= 0; i
< banks
; i
++) {
1712 struct mce_bank
*b
= &mce_banks
[i
];
1715 wrmsrl(MSR_IA32_MCx_CTL(i
), 0);
1720 static int mce_suspend(void)
1722 return mce_disable_error_reporting();
1725 static void mce_shutdown(void)
1727 mce_disable_error_reporting();
1731 * On resume clear all MCE state. Don't want to see leftovers from the BIOS.
1732 * Only one CPU is active at this time, the others get re-added later using
1735 static void mce_resume(void)
1737 __mcheck_cpu_init_generic();
1738 __mcheck_cpu_init_vendor(__this_cpu_ptr(&cpu_info
));
1741 static struct syscore_ops mce_syscore_ops
= {
1742 .suspend
= mce_suspend
,
1743 .shutdown
= mce_shutdown
,
1744 .resume
= mce_resume
,
1747 static void mce_cpu_restart(void *data
)
1749 del_timer_sync(&__get_cpu_var(mce_timer
));
1750 if (!mce_available(__this_cpu_ptr(&cpu_info
)))
1752 __mcheck_cpu_init_generic();
1753 __mcheck_cpu_init_timer();
1756 /* Reinit MCEs after user configuration changes */
1757 static void mce_restart(void)
1759 on_each_cpu(mce_cpu_restart
, NULL
, 1);
1762 /* Toggle features for corrected errors */
1763 static void mce_disable_ce(void *all
)
1765 if (!mce_available(__this_cpu_ptr(&cpu_info
)))
1768 del_timer_sync(&__get_cpu_var(mce_timer
));
1772 static void mce_enable_ce(void *all
)
1774 if (!mce_available(__this_cpu_ptr(&cpu_info
)))
1779 __mcheck_cpu_init_timer();
1782 static struct sysdev_class mce_sysclass
= {
1783 .name
= "machinecheck",
1786 DEFINE_PER_CPU(struct sys_device
, mce_dev
);
1789 void (*threshold_cpu_callback
)(unsigned long action
, unsigned int cpu
);
1791 static inline struct mce_bank
*attr_to_bank(struct sysdev_attribute
*attr
)
1793 return container_of(attr
, struct mce_bank
, attr
);
1796 static ssize_t
show_bank(struct sys_device
*s
, struct sysdev_attribute
*attr
,
1799 return sprintf(buf
, "%llx\n", attr_to_bank(attr
)->ctl
);
1802 static ssize_t
set_bank(struct sys_device
*s
, struct sysdev_attribute
*attr
,
1803 const char *buf
, size_t size
)
1807 if (strict_strtoull(buf
, 0, &new) < 0)
1810 attr_to_bank(attr
)->ctl
= new;
1817 show_trigger(struct sys_device
*s
, struct sysdev_attribute
*attr
, char *buf
)
1819 strcpy(buf
, mce_helper
);
1821 return strlen(mce_helper
) + 1;
1824 static ssize_t
set_trigger(struct sys_device
*s
, struct sysdev_attribute
*attr
,
1825 const char *buf
, size_t siz
)
1829 strncpy(mce_helper
, buf
, sizeof(mce_helper
));
1830 mce_helper
[sizeof(mce_helper
)-1] = 0;
1831 p
= strchr(mce_helper
, '\n');
1836 return strlen(mce_helper
) + !!p
;
1839 static ssize_t
set_ignore_ce(struct sys_device
*s
,
1840 struct sysdev_attribute
*attr
,
1841 const char *buf
, size_t size
)
1845 if (strict_strtoull(buf
, 0, &new) < 0)
1848 if (mce_ignore_ce
^ !!new) {
1850 /* disable ce features */
1851 on_each_cpu(mce_disable_ce
, (void *)1, 1);
1854 /* enable ce features */
1856 on_each_cpu(mce_enable_ce
, (void *)1, 1);
1862 static ssize_t
set_cmci_disabled(struct sys_device
*s
,
1863 struct sysdev_attribute
*attr
,
1864 const char *buf
, size_t size
)
1868 if (strict_strtoull(buf
, 0, &new) < 0)
1871 if (mce_cmci_disabled
^ !!new) {
1874 on_each_cpu(mce_disable_ce
, NULL
, 1);
1875 mce_cmci_disabled
= 1;
1878 mce_cmci_disabled
= 0;
1879 on_each_cpu(mce_enable_ce
, NULL
, 1);
1885 static ssize_t
store_int_with_restart(struct sys_device
*s
,
1886 struct sysdev_attribute
*attr
,
1887 const char *buf
, size_t size
)
1889 ssize_t ret
= sysdev_store_int(s
, attr
, buf
, size
);
1894 static SYSDEV_ATTR(trigger
, 0644, show_trigger
, set_trigger
);
1895 static SYSDEV_INT_ATTR(tolerant
, 0644, tolerant
);
1896 static SYSDEV_INT_ATTR(monarch_timeout
, 0644, monarch_timeout
);
1897 static SYSDEV_INT_ATTR(dont_log_ce
, 0644, mce_dont_log_ce
);
1899 static struct sysdev_ext_attribute attr_check_interval
= {
1900 _SYSDEV_ATTR(check_interval
, 0644, sysdev_show_int
,
1901 store_int_with_restart
),
1905 static struct sysdev_ext_attribute attr_ignore_ce
= {
1906 _SYSDEV_ATTR(ignore_ce
, 0644, sysdev_show_int
, set_ignore_ce
),
1910 static struct sysdev_ext_attribute attr_cmci_disabled
= {
1911 _SYSDEV_ATTR(cmci_disabled
, 0644, sysdev_show_int
, set_cmci_disabled
),
1915 static struct sysdev_attribute
*mce_attrs
[] = {
1916 &attr_tolerant
.attr
,
1917 &attr_check_interval
.attr
,
1919 &attr_monarch_timeout
.attr
,
1920 &attr_dont_log_ce
.attr
,
1921 &attr_ignore_ce
.attr
,
1922 &attr_cmci_disabled
.attr
,
1926 static cpumask_var_t mce_dev_initialized
;
1928 /* Per cpu sysdev init. All of the cpus still share the same ctrl bank: */
1929 static __cpuinit
int mce_create_device(unsigned int cpu
)
1931 struct sys_device
*sysdev
= &per_cpu(mce_dev
, cpu
);
1935 if (!mce_available(&boot_cpu_data
))
1938 memset(&sysdev
->kobj
, 0, sizeof(struct kobject
));
1940 sysdev
->cls
= &mce_sysclass
;
1942 err
= sysdev_register(sysdev
);
1946 for (i
= 0; mce_attrs
[i
]; i
++) {
1947 err
= sysdev_create_file(sysdev
, mce_attrs
[i
]);
1951 for (j
= 0; j
< banks
; j
++) {
1952 err
= sysdev_create_file(sysdev
, &mce_banks
[j
].attr
);
1956 cpumask_set_cpu(cpu
, mce_dev_initialized
);
1961 sysdev_remove_file(sysdev
, &mce_banks
[j
].attr
);
1964 sysdev_remove_file(sysdev
, mce_attrs
[i
]);
1966 sysdev_unregister(sysdev
);
1971 static __cpuinit
void mce_remove_device(unsigned int cpu
)
1973 struct sys_device
*sysdev
= &per_cpu(mce_dev
, cpu
);
1976 if (!cpumask_test_cpu(cpu
, mce_dev_initialized
))
1979 for (i
= 0; mce_attrs
[i
]; i
++)
1980 sysdev_remove_file(sysdev
, mce_attrs
[i
]);
1982 for (i
= 0; i
< banks
; i
++)
1983 sysdev_remove_file(sysdev
, &mce_banks
[i
].attr
);
1985 sysdev_unregister(sysdev
);
1986 cpumask_clear_cpu(cpu
, mce_dev_initialized
);
1989 /* Make sure there are no machine checks on offlined CPUs. */
1990 static void __cpuinit
mce_disable_cpu(void *h
)
1992 unsigned long action
= *(unsigned long *)h
;
1995 if (!mce_available(__this_cpu_ptr(&cpu_info
)))
1998 if (!(action
& CPU_TASKS_FROZEN
))
2000 for (i
= 0; i
< banks
; i
++) {
2001 struct mce_bank
*b
= &mce_banks
[i
];
2004 wrmsrl(MSR_IA32_MCx_CTL(i
), 0);
2008 static void __cpuinit
mce_reenable_cpu(void *h
)
2010 unsigned long action
= *(unsigned long *)h
;
2013 if (!mce_available(__this_cpu_ptr(&cpu_info
)))
2016 if (!(action
& CPU_TASKS_FROZEN
))
2018 for (i
= 0; i
< banks
; i
++) {
2019 struct mce_bank
*b
= &mce_banks
[i
];
2022 wrmsrl(MSR_IA32_MCx_CTL(i
), b
->ctl
);
2026 /* Get notified when a cpu comes on/off. Be hotplug friendly. */
2027 static int __cpuinit
2028 mce_cpu_callback(struct notifier_block
*nfb
, unsigned long action
, void *hcpu
)
2030 unsigned int cpu
= (unsigned long)hcpu
;
2031 struct timer_list
*t
= &per_cpu(mce_timer
, cpu
);
2035 case CPU_ONLINE_FROZEN
:
2036 mce_create_device(cpu
);
2037 if (threshold_cpu_callback
)
2038 threshold_cpu_callback(action
, cpu
);
2041 case CPU_DEAD_FROZEN
:
2042 if (threshold_cpu_callback
)
2043 threshold_cpu_callback(action
, cpu
);
2044 mce_remove_device(cpu
);
2046 case CPU_DOWN_PREPARE
:
2047 case CPU_DOWN_PREPARE_FROZEN
:
2049 smp_call_function_single(cpu
, mce_disable_cpu
, &action
, 1);
2051 case CPU_DOWN_FAILED
:
2052 case CPU_DOWN_FAILED_FROZEN
:
2053 if (!mce_ignore_ce
&& check_interval
) {
2054 t
->expires
= round_jiffies(jiffies
+
2055 __get_cpu_var(mce_next_interval
));
2056 add_timer_on(t
, cpu
);
2058 smp_call_function_single(cpu
, mce_reenable_cpu
, &action
, 1);
2061 /* intentionally ignoring frozen here */
2062 cmci_rediscover(cpu
);
2068 static struct notifier_block mce_cpu_notifier __cpuinitdata
= {
2069 .notifier_call
= mce_cpu_callback
,
2072 static __init
void mce_init_banks(void)
2076 for (i
= 0; i
< banks
; i
++) {
2077 struct mce_bank
*b
= &mce_banks
[i
];
2078 struct sysdev_attribute
*a
= &b
->attr
;
2080 sysfs_attr_init(&a
->attr
);
2081 a
->attr
.name
= b
->attrname
;
2082 snprintf(b
->attrname
, ATTR_LEN
, "bank%d", i
);
2084 a
->attr
.mode
= 0644;
2085 a
->show
= show_bank
;
2086 a
->store
= set_bank
;
2090 static __init
int mcheck_init_device(void)
2095 if (!mce_available(&boot_cpu_data
))
2098 zalloc_cpumask_var(&mce_dev_initialized
, GFP_KERNEL
);
2102 err
= sysdev_class_register(&mce_sysclass
);
2106 for_each_online_cpu(i
) {
2107 err
= mce_create_device(i
);
2112 register_syscore_ops(&mce_syscore_ops
);
2113 register_hotcpu_notifier(&mce_cpu_notifier
);
2115 /* register character device /dev/mcelog */
2116 misc_register(&mce_chrdev_device
);
2120 device_initcall(mcheck_init_device
);
2123 * Old style boot options parsing. Only for compatibility.
2125 static int __init
mcheck_disable(char *str
)
2130 __setup("nomce", mcheck_disable
);
2132 #ifdef CONFIG_DEBUG_FS
2133 struct dentry
*mce_get_debugfs_dir(void)
2135 static struct dentry
*dmce
;
2138 dmce
= debugfs_create_dir("mce", NULL
);
2143 static void mce_reset(void)
2146 atomic_set(&mce_fake_paniced
, 0);
2147 atomic_set(&mce_executing
, 0);
2148 atomic_set(&mce_callin
, 0);
2149 atomic_set(&global_nwo
, 0);
2152 static int fake_panic_get(void *data
, u64
*val
)
2158 static int fake_panic_set(void *data
, u64 val
)
2165 DEFINE_SIMPLE_ATTRIBUTE(fake_panic_fops
, fake_panic_get
,
2166 fake_panic_set
, "%llu\n");
2168 static int __init
mcheck_debugfs_init(void)
2170 struct dentry
*dmce
, *ffake_panic
;
2172 dmce
= mce_get_debugfs_dir();
2175 ffake_panic
= debugfs_create_file("fake_panic", 0444, dmce
, NULL
,
2182 late_initcall(mcheck_debugfs_init
);