drivers/pci/hotplug/pciehp_hpc.c

   1 /*
   2  * PCI Express PCI Hot Plug Driver
   3  *
   4  * Copyright (C) 1995,2001 Compaq Computer Corporation
   5  * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
   6  * Copyright (C) 2001 IBM Corp.
   7  * Copyright (C) 2003-2004 Intel Corporation
   8  *
   9  * All rights reserved.
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; either version 2 of the License, or (at
  14  * your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful, but
  17  * WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
  19  * NON INFRINGEMENT.  See the GNU General Public License for more
  20  * details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with this program; if not, write to the Free Software
  24  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  25  *
  26  * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com>
  27  *
  28  */
  29
  30 #include <linux/kernel.h>
  31 #include <linux/module.h>
  32 #include <linux/types.h>
  33 #include <linux/signal.h>
  34 #include <linux/jiffies.h>
  35 #include <linux/timer.h>
  36 #include <linux/pci.h>
  37 #include <linux/interrupt.h>
  38 #include <linux/time.h>
  39
  40 #include "../pci.h"
  41 #include "pciehp.h"
  42
  43 static atomic_t pciehp_num_controllers = ATOMIC_INIT(0);
  44
  45 struct ctrl_reg {
  46         u8 cap_id;
  47         u8 nxt_ptr;
  48         u16 cap_reg;
  49         u32 dev_cap;
  50         u16 dev_ctrl;
  51         u16 dev_status;
  52         u32 lnk_cap;
  53         u16 lnk_ctrl;
  54         u16 lnk_status;
  55         u32 slot_cap;
  56         u16 slot_ctrl;
  57         u16 slot_status;
  58         u16 root_ctrl;
  59         u16 rsvp;
  60         u32 root_status;
  61 } __attribute__ ((packed));
  62
  63 /* offsets to the controller registers based on the above structure layout */
  64 enum ctrl_offsets {
  65         PCIECAPID       =       offsetof(struct ctrl_reg, cap_id),
  66         NXTCAPPTR       =       offsetof(struct ctrl_reg, nxt_ptr),
  67         CAPREG          =       offsetof(struct ctrl_reg, cap_reg),
  68         DEVCAP          =       offsetof(struct ctrl_reg, dev_cap),
  69         DEVCTRL         =       offsetof(struct ctrl_reg, dev_ctrl),
  70         DEVSTATUS       =       offsetof(struct ctrl_reg, dev_status),
  71         LNKCAP          =       offsetof(struct ctrl_reg, lnk_cap),
  72         LNKCTRL         =       offsetof(struct ctrl_reg, lnk_ctrl),
  73         LNKSTATUS       =       offsetof(struct ctrl_reg, lnk_status),
  74         SLOTCAP         =       offsetof(struct ctrl_reg, slot_cap),
  75         SLOTCTRL        =       offsetof(struct ctrl_reg, slot_ctrl),
  76         SLOTSTATUS      =       offsetof(struct ctrl_reg, slot_status),
  77         ROOTCTRL        =       offsetof(struct ctrl_reg, root_ctrl),
  78         ROOTSTATUS      =       offsetof(struct ctrl_reg, root_status),
  79 };
  80
  81 static inline int pciehp_readw(struct controller *ctrl, int reg, u16 *value)
  82 {
  83         struct pci_dev *dev = ctrl->pci_dev;
  84         return pci_read_config_word(dev, ctrl->cap_base + reg, value);
  85 }
  86
  87 static inline int pciehp_readl(struct controller *ctrl, int reg, u32 *value)
  88 {
  89         struct pci_dev *dev = ctrl->pci_dev;
  90         return pci_read_config_dword(dev, ctrl->cap_base + reg, value);
  91 }
  92
  93 static inline int pciehp_writew(struct controller *ctrl, int reg, u16 value)
  94 {
  95         struct pci_dev *dev = ctrl->pci_dev;
  96         return pci_write_config_word(dev, ctrl->cap_base + reg, value);
  97 }
  98
  99 static inline int pciehp_writel(struct controller *ctrl, int reg, u32 value)
 100 {
 101         struct pci_dev *dev = ctrl->pci_dev;
 102         return pci_write_config_dword(dev, ctrl->cap_base + reg, value);
 103 }
 104
 105 /* Field definitions in PCI Express Capabilities Register */
 106 #define CAP_VER                 0x000F
 107 #define DEV_PORT_TYPE           0x00F0
 108 #define SLOT_IMPL               0x0100
 109 #define MSG_NUM                 0x3E00
 110
 111 /* Device or Port Type */
 112 #define NAT_ENDPT               0x00
 113 #define LEG_ENDPT               0x01
 114 #define ROOT_PORT               0x04
 115 #define UP_STREAM               0x05
 116 #define DN_STREAM               0x06
 117 #define PCIE_PCI_BRDG           0x07
 118 #define PCI_PCIE_BRDG           0x10
 119
 120 /* Field definitions in Device Capabilities Register */
 121 #define DATTN_BUTTN_PRSN        0x1000
 122 #define DATTN_LED_PRSN          0x2000
 123 #define DPWR_LED_PRSN           0x4000
 124
 125 /* Field definitions in Link Capabilities Register */
 126 #define MAX_LNK_SPEED           0x000F
 127 #define MAX_LNK_WIDTH           0x03F0
 128 #define LINK_ACTIVE_REPORTING   0x00100000
 129
 130 /* Link Width Encoding */
 131 #define LNK_X1          0x01
 132 #define LNK_X2          0x02
 133 #define LNK_X4          0x04
 134 #define LNK_X8          0x08
 135 #define LNK_X12         0x0C
 136 #define LNK_X16         0x10
 137 #define LNK_X32         0x20
 138
 139 /*Field definitions of Link Status Register */
 140 #define LNK_SPEED       0x000F
 141 #define NEG_LINK_WD     0x03F0
 142 #define LNK_TRN_ERR     0x0400
 143 #define LNK_TRN         0x0800
 144 #define SLOT_CLK_CONF   0x1000
 145 #define LINK_ACTIVE     0x2000
 146
 147 /* Field definitions in Slot Capabilities Register */
 148 #define ATTN_BUTTN_PRSN 0x00000001
 149 #define PWR_CTRL_PRSN   0x00000002
 150 #define MRL_SENS_PRSN   0x00000004
 151 #define ATTN_LED_PRSN   0x00000008
 152 #define PWR_LED_PRSN    0x00000010
 153 #define HP_SUPR_RM_SUP  0x00000020
 154 #define HP_CAP          0x00000040
 155 #define SLOT_PWR_VALUE  0x000003F8
 156 #define SLOT_PWR_LIMIT  0x00000C00
 157 #define PSN             0xFFF80000      /* PSN: Physical Slot Number */
 158
 159 /* Field definitions in Slot Control Register */
 160 #define ATTN_BUTTN_ENABLE               0x0001
 161 #define PWR_FAULT_DETECT_ENABLE         0x0002
 162 #define MRL_DETECT_ENABLE               0x0004
 163 #define PRSN_DETECT_ENABLE              0x0008
 164 #define CMD_CMPL_INTR_ENABLE            0x0010
 165 #define HP_INTR_ENABLE                  0x0020
 166 #define ATTN_LED_CTRL                   0x00C0
 167 #define PWR_LED_CTRL                    0x0300
 168 #define PWR_CTRL                        0x0400
 169 #define EMI_CTRL                        0x0800
 170
 171 /* Attention indicator and Power indicator states */
 172 #define LED_ON          0x01
 173 #define LED_BLINK       0x10
 174 #define LED_OFF         0x11
 175
 176 /* Power Control Command */
 177 #define POWER_ON        0
 178 #define POWER_OFF       0x0400
 179
 180 /* EMI Status defines */
 181 #define EMI_DISENGAGED  0
 182 #define EMI_ENGAGED     1
 183
 184 /* Field definitions in Slot Status Register */
 185 #define ATTN_BUTTN_PRESSED      0x0001
 186 #define PWR_FAULT_DETECTED      0x0002
 187 #define MRL_SENS_CHANGED        0x0004
 188 #define PRSN_DETECT_CHANGED     0x0008
 189 #define CMD_COMPLETED           0x0010
 190 #define MRL_STATE               0x0020
 191 #define PRSN_STATE              0x0040
 192 #define EMI_STATE               0x0080
 193 #define EMI_STATUS_BIT          7
 194
 195 static irqreturn_t pcie_isr(int irq, void *dev_id);
 196 static void start_int_poll_timer(struct controller *ctrl, int sec);
 197
 198 /* This is the interrupt polling timeout function. */
 199 static void int_poll_timeout(unsigned long data)
 200 {
 201         struct controller *ctrl = (struct controller *)data;
 202
 203         /* Poll for interrupt events.  regs == NULL => polling */
 204         pcie_isr(0, ctrl);
 205
 206         init_timer(&ctrl->poll_timer);
 207         if (!pciehp_poll_time)
 208                 pciehp_poll_time = 2; /* default polling interval is 2 sec */
 209
 210         start_int_poll_timer(ctrl, pciehp_poll_time);
 211 }
 212
 213 /* This function starts the interrupt polling timer. */
 214 static void start_int_poll_timer(struct controller *ctrl, int sec)
 215 {
 216         /* Clamp to sane value */
 217         if ((sec <= 0) || (sec > 60))
 218                 sec = 2;
 219
 220         ctrl->poll_timer.function = &int_poll_timeout;
 221         ctrl->poll_timer.data = (unsigned long)ctrl;
 222         ctrl->poll_timer.expires = jiffies + sec * HZ;
 223         add_timer(&ctrl->poll_timer);
 224 }
 225
 226 static inline int pciehp_request_irq(struct controller *ctrl)
 227 {
 228         int retval, irq = ctrl->pcie->irq;
 229
 230         /* Install interrupt polling timer. Start with 10 sec delay */
 231         if (pciehp_poll_mode) {
 232                 init_timer(&ctrl->poll_timer);
 233                 start_int_poll_timer(ctrl, 10);
 234                 return 0;
 235         }
 236
 237         /* Installs the interrupt handler */
 238         retval = request_irq(irq, pcie_isr, IRQF_SHARED, MY_NAME, ctrl);
 239         if (retval)
 240                 ctrl_err(ctrl, "Cannot get irq %d for the hotplug controller\n",
 241                          irq);
 242         return retval;
 243 }
 244
 245 static inline void pciehp_free_irq(struct controller *ctrl)
 246 {
 247         if (pciehp_poll_mode)
 248                 del_timer_sync(&ctrl->poll_timer);
 249         else
 250                 free_irq(ctrl->pcie->irq, ctrl);
 251 }
 252
 253 static int pcie_poll_cmd(struct controller *ctrl)
 254 {
 255         u16 slot_status;
 256         int timeout = 1000;
 257
 258         if (!pciehp_readw(ctrl, SLOTSTATUS, &slot_status)) {
 259                 if (slot_status & CMD_COMPLETED) {
 260                         pciehp_writew(ctrl, SLOTSTATUS, CMD_COMPLETED);
 261                         return 1;
 262                 }
 263         }
 264         while (timeout > 0) {
 265                 msleep(10);
 266                 timeout -= 10;
 267                 if (!pciehp_readw(ctrl, SLOTSTATUS, &slot_status)) {
 268                         if (slot_status & CMD_COMPLETED) {
 269                                 pciehp_writew(ctrl, SLOTSTATUS, CMD_COMPLETED);
 270                                 return 1;
 271                         }
 272                 }
 273         }
 274         return 0;       /* timeout */
 275 }
 276
 277 static void pcie_wait_cmd(struct controller *ctrl, int poll)
 278 {
 279         unsigned int msecs = pciehp_poll_mode ? 2500 : 1000;
 280         unsigned long timeout = msecs_to_jiffies(msecs);
 281         int rc;
 282
 283         if (poll)
 284                 rc = pcie_poll_cmd(ctrl);
 285         else
 286                 rc = wait_event_timeout(ctrl->queue, !ctrl->cmd_busy, timeout);
 287         if (!rc)
 288                 ctrl_dbg(ctrl, "Command not completed in 1000 msec\n");
 289 }
 290
 291 /**
 292  * pcie_write_cmd - Issue controller command
 293  * @ctrl: controller to which the command is issued
 294  * @cmd:  command value written to slot control register
 295  * @mask: bitmask of slot control register to be modified
 296  */
 297 static int pcie_write_cmd(struct controller *ctrl, u16 cmd, u16 mask)
 298 {
 299         int retval = 0;
 300         u16 slot_status;
 301         u16 slot_ctrl;
 302
 303         mutex_lock(&ctrl->ctrl_lock);
 304
 305         retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
 306         if (retval) {
 307                 ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n",
 308                          __func__);
 309                 goto out;
 310         }
 311
 312         if (slot_status & CMD_COMPLETED) {
 313                 if (!ctrl->no_cmd_complete) {
 314                         /*
 315                          * After 1 sec and CMD_COMPLETED still not set, just
 316                          * proceed forward to issue the next command according
 317                          * to spec. Just print out the error message.
 318                          */
 319                         ctrl_dbg(ctrl, "CMD_COMPLETED not clear after 1 sec\n");
 320                 } else if (!NO_CMD_CMPL(ctrl)) {
 321                         /*
 322                          * This controller semms to notify of command completed
 323                          * event even though it supports none of power
 324                          * controller, attention led, power led and EMI.
 325                          */
 326                         ctrl_dbg(ctrl, "Unexpected CMD_COMPLETED. Need to "
 327                                  "wait for command completed event.\n");
 328                         ctrl->no_cmd_complete = 0;
 329                 } else {
 330                         ctrl_dbg(ctrl, "Unexpected CMD_COMPLETED. Maybe "
 331                                  "the controller is broken.\n");
 332                 }
 333         }
 334
 335         retval = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl);
 336         if (retval) {
 337                 ctrl_err(ctrl, "%s: Cannot read SLOTCTRL register\n", __func__);
 338                 goto out;
 339         }
 340
 341         slot_ctrl &= ~mask;
 342         slot_ctrl |= (cmd & mask);
 343         ctrl->cmd_busy = 1;
 344         smp_mb();
 345         retval = pciehp_writew(ctrl, SLOTCTRL, slot_ctrl);
 346         if (retval)
 347                 ctrl_err(ctrl, "Cannot write to SLOTCTRL register\n");
 348
 349         /*
 350          * Wait for command completion.
 351          */
 352         if (!retval && !ctrl->no_cmd_complete) {
 353                 int poll = 0;
 354                 /*
 355                  * if hotplug interrupt is not enabled or command
 356                  * completed interrupt is not enabled, we need to poll
 357                  * command completed event.
 358                  */
 359                 if (!(slot_ctrl & HP_INTR_ENABLE) ||
 360                     !(slot_ctrl & CMD_CMPL_INTR_ENABLE))
 361                         poll = 1;
 362                 pcie_wait_cmd(ctrl, poll);
 363         }
 364  out:
 365         mutex_unlock(&ctrl->ctrl_lock);
 366         return retval;
 367 }
 368
 369 static inline int check_link_active(struct controller *ctrl)
 370 {
 371         u16 link_status;
 372
 373         if (pciehp_readw(ctrl, LNKSTATUS, &link_status))
 374                 return 0;
 375         return !!(link_status & LINK_ACTIVE);
 376 }
 377
 378 static void pcie_wait_link_active(struct controller *ctrl)
 379 {
 380         int timeout = 1000;
 381
 382         if (check_link_active(ctrl))
 383                 return;
 384         while (timeout > 0) {
 385                 msleep(10);
 386                 timeout -= 10;
 387                 if (check_link_active(ctrl))
 388                         return;
 389         }
 390         ctrl_dbg(ctrl, "Data Link Layer Link Active not set in 1000 msec\n");
 391 }
 392
 393 static int hpc_check_lnk_status(struct controller *ctrl)
 394 {
 395         u16 lnk_status;
 396         int retval = 0;
 397
 398         /*
 399          * Data Link Layer Link Active Reporting must be capable for
 400          * hot-plug capable downstream port. But old controller might
 401          * not implement it. In this case, we wait for 1000 ms.
 402          */
 403         if (ctrl->link_active_reporting){
 404                 /* Wait for Data Link Layer Link Active bit to be set */
 405                 pcie_wait_link_active(ctrl);
 406                 /*
 407                  * We must wait for 100 ms after the Data Link Layer
 408                  * Link Active bit reads 1b before initiating a
 409                  * configuration access to the hot added device.
 410                  */
 411                 msleep(100);
 412         } else
 413                 msleep(1000);
 414
 415         retval = pciehp_readw(ctrl, LNKSTATUS, &lnk_status);
 416         if (retval) {
 417                 ctrl_err(ctrl, "Cannot read LNKSTATUS register\n");
 418                 return retval;
 419         }
 420
 421         ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status);
 422         if ( (lnk_status & LNK_TRN) || (lnk_status & LNK_TRN_ERR) ||
 423                 !(lnk_status & NEG_LINK_WD)) {
 424                 ctrl_err(ctrl, "Link Training Error occurs \n");
 425                 retval = -1;
 426                 return retval;
 427         }
 428
 429         return retval;
 430 }
 431
 432 static int hpc_get_attention_status(struct slot *slot, u8 *status)
 433 {
 434         struct controller *ctrl = slot->ctrl;
 435         u16 slot_ctrl;
 436         u8 atten_led_state;
 437         int retval = 0;
 438
 439         retval = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl);
 440         if (retval) {
 441                 ctrl_err(ctrl, "%s: Cannot read SLOTCTRL register\n", __func__);
 442                 return retval;
 443         }
 444
 445         ctrl_dbg(ctrl, "%s: SLOTCTRL %x, value read %x\n",
 446                  __func__, ctrl->cap_base + SLOTCTRL, slot_ctrl);
 447
 448         atten_led_state = (slot_ctrl & ATTN_LED_CTRL) >> 6;
 449
 450         switch (atten_led_state) {
 451         case 0:
 452                 *status = 0xFF; /* Reserved */
 453                 break;
 454         case 1:
 455                 *status = 1;    /* On */
 456                 break;
 457         case 2:
 458                 *status = 2;    /* Blink */
 459                 break;
 460         case 3:
 461                 *status = 0;    /* Off */
 462                 break;
 463         default:
 464                 *status = 0xFF;
 465                 break;
 466         }
 467
 468         return 0;
 469 }
 470
 471 static int hpc_get_power_status(struct slot *slot, u8 *status)
 472 {
 473         struct controller *ctrl = slot->ctrl;
 474         u16 slot_ctrl;
 475         u8 pwr_state;
 476         int     retval = 0;
 477
 478         retval = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl);
 479         if (retval) {
 480                 ctrl_err(ctrl, "%s: Cannot read SLOTCTRL register\n", __func__);
 481                 return retval;
 482         }
 483         ctrl_dbg(ctrl, "%s: SLOTCTRL %x value read %x\n",
 484                  __func__, ctrl->cap_base + SLOTCTRL, slot_ctrl);
 485
 486         pwr_state = (slot_ctrl & PWR_CTRL) >> 10;
 487
 488         switch (pwr_state) {
 489         case 0:
 490                 *status = 1;
 491                 break;
 492         case 1:
 493                 *status = 0;
 494                 break;
 495         default:
 496                 *status = 0xFF;
 497                 break;
 498         }
 499
 500         return retval;
 501 }
 502
 503 static int hpc_get_latch_status(struct slot *slot, u8 *status)
 504 {
 505         struct controller *ctrl = slot->ctrl;
 506         u16 slot_status;
 507         int retval = 0;
 508
 509         retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
 510         if (retval) {
 511                 ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n",
 512                          __func__);
 513                 return retval;
 514         }
 515
 516         *status = (((slot_status & MRL_STATE) >> 5) == 0) ? 0 : 1;
 517
 518         return 0;
 519 }
 520
 521 static int hpc_get_adapter_status(struct slot *slot, u8 *status)
 522 {
 523         struct controller *ctrl = slot->ctrl;
 524         u16 slot_status;
 525         u8 card_state;
 526         int retval = 0;
 527
 528         retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
 529         if (retval) {
 530                 ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n",
 531                          __func__);
 532                 return retval;
 533         }
 534         card_state = (u8)((slot_status & PRSN_STATE) >> 6);
 535         *status = (card_state == 1) ? 1 : 0;
 536
 537         return 0;
 538 }
 539
 540 static int hpc_query_power_fault(struct slot *slot)
 541 {
 542         struct controller *ctrl = slot->ctrl;
 543         u16 slot_status;
 544         u8 pwr_fault;
 545         int retval = 0;
 546
 547         retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
 548         if (retval) {
 549                 ctrl_err(ctrl, "Cannot check for power fault\n");
 550                 return retval;
 551         }
 552         pwr_fault = (u8)((slot_status & PWR_FAULT_DETECTED) >> 1);
 553
 554         return pwr_fault;
 555 }
 556
 557 static int hpc_get_emi_status(struct slot *slot, u8 *status)
 558 {
 559         struct controller *ctrl = slot->ctrl;
 560         u16 slot_status;
 561         int retval = 0;
 562
 563         retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
 564         if (retval) {
 565                 ctrl_err(ctrl, "Cannot check EMI status\n");
 566                 return retval;
 567         }
 568         *status = (slot_status & EMI_STATE) >> EMI_STATUS_BIT;
 569
 570         return retval;
 571 }
 572
 573 static int hpc_toggle_emi(struct slot *slot)
 574 {
 575         u16 slot_cmd;
 576         u16 cmd_mask;
 577         int rc;
 578
 579         slot_cmd = EMI_CTRL;
 580         cmd_mask = EMI_CTRL;
 581         rc = pcie_write_cmd(slot->ctrl, slot_cmd, cmd_mask);
 582         slot->last_emi_toggle = get_seconds();
 583
 584         return rc;
 585 }
 586
 587 static int hpc_set_attention_status(struct slot *slot, u8 value)
 588 {
 589         struct controller *ctrl = slot->ctrl;
 590         u16 slot_cmd;
 591         u16 cmd_mask;
 592         int rc;
 593
 594         cmd_mask = ATTN_LED_CTRL;
 595         switch (value) {
 596                 case 0 :        /* turn off */
 597                         slot_cmd = 0x00C0;
 598                         break;
 599                 case 1:         /* turn on */
 600                         slot_cmd = 0x0040;
 601                         break;
 602                 case 2:         /* turn blink */
 603                         slot_cmd = 0x0080;
 604                         break;
 605                 default:
 606                         return -1;
 607         }
 608         rc = pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
 609         ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n",
 610                  __func__, ctrl->cap_base + SLOTCTRL, slot_cmd);
 611
 612         return rc;
 613 }
 614
 615 static void hpc_set_green_led_on(struct slot *slot)
 616 {
 617         struct controller *ctrl = slot->ctrl;
 618         u16 slot_cmd;
 619         u16 cmd_mask;
 620
 621         slot_cmd = 0x0100;
 622         cmd_mask = PWR_LED_CTRL;
 623         pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
 624         ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n",
 625                  __func__, ctrl->cap_base + SLOTCTRL, slot_cmd);
 626 }
 627
 628 static void hpc_set_green_led_off(struct slot *slot)
 629 {
 630         struct controller *ctrl = slot->ctrl;
 631         u16 slot_cmd;
 632         u16 cmd_mask;
 633
 634         slot_cmd = 0x0300;
 635         cmd_mask = PWR_LED_CTRL;
 636         pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
 637         ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n",
 638                  __func__, ctrl->cap_base + SLOTCTRL, slot_cmd);
 639 }
 640
 641 static void hpc_set_green_led_blink(struct slot *slot)
 642 {
 643         struct controller *ctrl = slot->ctrl;
 644         u16 slot_cmd;
 645         u16 cmd_mask;
 646
 647         slot_cmd = 0x0200;
 648         cmd_mask = PWR_LED_CTRL;
 649         pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
 650         ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n",
 651                  __func__, ctrl->cap_base + SLOTCTRL, slot_cmd);
 652 }
 653
 654 static int hpc_power_on_slot(struct slot * slot)
 655 {
 656         struct controller *ctrl = slot->ctrl;
 657         u16 slot_cmd;
 658         u16 cmd_mask;
 659         u16 slot_status;
 660         int retval = 0;
 661
 662         ctrl_dbg(ctrl, "%s: slot->hp_slot %x\n", __func__, slot->hp_slot);
 663
 664         /* Clear sticky power-fault bit from previous power failures */
 665         retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
 666         if (retval) {
 667                 ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n",
 668                          __func__);
 669                 return retval;
 670         }
 671         slot_status &= PWR_FAULT_DETECTED;
 672         if (slot_status) {
 673                 retval = pciehp_writew(ctrl, SLOTSTATUS, slot_status);
 674                 if (retval) {
 675                         ctrl_err(ctrl,
 676                                  "%s: Cannot write to SLOTSTATUS register\n",
 677                                  __func__);
 678                         return retval;
 679                 }
 680         }
 681
 682         slot_cmd = POWER_ON;
 683         cmd_mask = PWR_CTRL;
 684         /* Enable detection that we turned off at slot power-off time */
 685         if (!pciehp_poll_mode) {
 686                 slot_cmd |= (PWR_FAULT_DETECT_ENABLE | MRL_DETECT_ENABLE |
 687                              PRSN_DETECT_ENABLE);
 688                 cmd_mask |= (PWR_FAULT_DETECT_ENABLE | MRL_DETECT_ENABLE |
 689                              PRSN_DETECT_ENABLE);
 690         }
 691
 692         retval = pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
 693
 694         if (retval) {
 695                 ctrl_err(ctrl, "Write %x command failed!\n", slot_cmd);
 696                 return -1;
 697         }
 698         ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n",
 699                  __func__, ctrl->cap_base + SLOTCTRL, slot_cmd);
 700
 701         return retval;
 702 }
 703
 704 static inline int pcie_mask_bad_dllp(struct controller *ctrl)
 705 {
 706         struct pci_dev *dev = ctrl->pci_dev;
 707         int pos;
 708         u32 reg;
 709
 710         pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
 711         if (!pos)
 712                 return 0;
 713         pci_read_config_dword(dev, pos + PCI_ERR_COR_MASK, &reg);
 714         if (reg & PCI_ERR_COR_BAD_DLLP)
 715                 return 0;
 716         reg |= PCI_ERR_COR_BAD_DLLP;
 717         pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, reg);
 718         return 1;
 719 }
 720
 721 static inline void pcie_unmask_bad_dllp(struct controller *ctrl)
 722 {
 723         struct pci_dev *dev = ctrl->pci_dev;
 724         u32 reg;
 725         int pos;
 726
 727         pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
 728         if (!pos)
 729                 return;
 730         pci_read_config_dword(dev, pos + PCI_ERR_COR_MASK, &reg);
 731         if (!(reg & PCI_ERR_COR_BAD_DLLP))
 732                 return;
 733         reg &= ~PCI_ERR_COR_BAD_DLLP;
 734         pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, reg);
 735 }
 736
 737 static int hpc_power_off_slot(struct slot * slot)
 738 {
 739         struct controller *ctrl = slot->ctrl;
 740         u16 slot_cmd;
 741         u16 cmd_mask;
 742         int retval = 0;
 743         int changed;
 744
 745         ctrl_dbg(ctrl, "%s: slot->hp_slot %x\n", __func__, slot->hp_slot);
 746
 747         /*
 748          * Set Bad DLLP Mask bit in Correctable Error Mask
 749          * Register. This is the workaround against Bad DLLP error
 750          * that sometimes happens during turning power off the slot
 751          * which conforms to PCI Express 1.0a spec.
 752          */
 753         changed = pcie_mask_bad_dllp(ctrl);
 754
 755         slot_cmd = POWER_OFF;
 756         cmd_mask = PWR_CTRL;
 757         /*
 758          * If we get MRL or presence detect interrupts now, the isr
 759          * will notice the sticky power-fault bit too and issue power
 760          * indicator change commands. This will lead to an endless loop
 761          * of command completions, since the power-fault bit remains on
 762          * till the slot is powered on again.
 763          */
 764         if (!pciehp_poll_mode) {
 765                 slot_cmd &= ~(PWR_FAULT_DETECT_ENABLE | MRL_DETECT_ENABLE |
 766                               PRSN_DETECT_ENABLE);
 767                 cmd_mask |= (PWR_FAULT_DETECT_ENABLE | MRL_DETECT_ENABLE |
 768                              PRSN_DETECT_ENABLE);
 769         }
 770
 771         retval = pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
 772         if (retval) {
 773                 ctrl_err(ctrl, "Write command failed!\n");
 774                 retval = -1;
 775                 goto out;
 776         }
 777         ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n",
 778                  __func__, ctrl->cap_base + SLOTCTRL, slot_cmd);
 779  out:
 780         if (changed)
 781                 pcie_unmask_bad_dllp(ctrl);
 782
 783         return retval;
 784 }
 785
 786 static irqreturn_t pcie_isr(int irq, void *dev_id)
 787 {
 788         struct controller *ctrl = (struct controller *)dev_id;
 789         u16 detected, intr_loc;
 790         struct slot *p_slot;
 791
 792         /*
 793          * In order to guarantee that all interrupt events are
 794          * serviced, we need to re-inspect Slot Status register after
 795          * clearing what is presumed to be the last pending interrupt.
 796          */
 797         intr_loc = 0;
 798         do {
 799                 if (pciehp_readw(ctrl, SLOTSTATUS, &detected)) {
 800                         ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS\n",
 801                                  __func__);
 802                         return IRQ_NONE;
 803                 }
 804
 805                 detected &= (ATTN_BUTTN_PRESSED | PWR_FAULT_DETECTED |
 806                              MRL_SENS_CHANGED | PRSN_DETECT_CHANGED |
 807                              CMD_COMPLETED);
 808                 intr_loc |= detected;
 809                 if (!intr_loc)
 810                         return IRQ_NONE;
 811                 if (detected && pciehp_writew(ctrl, SLOTSTATUS, detected)) {
 812                         ctrl_err(ctrl, "%s: Cannot write to SLOTSTATUS\n",
 813                                  __func__);
 814                         return IRQ_NONE;
 815                 }
 816         } while (detected);
 817
 818         ctrl_dbg(ctrl, "%s: intr_loc %x\n", __func__, intr_loc);
 819
 820         /* Check Command Complete Interrupt Pending */
 821         if (intr_loc & CMD_COMPLETED) {
 822                 ctrl->cmd_busy = 0;
 823                 smp_mb();
 824                 wake_up(&ctrl->queue);
 825         }
 826
 827         if (!(intr_loc & ~CMD_COMPLETED))
 828                 return IRQ_HANDLED;
 829
 830         p_slot = pciehp_find_slot(ctrl, ctrl->slot_device_offset);
 831
 832         /* Check MRL Sensor Changed */
 833         if (intr_loc & MRL_SENS_CHANGED)
 834                 pciehp_handle_switch_change(p_slot);
 835
 836         /* Check Attention Button Pressed */
 837         if (intr_loc & ATTN_BUTTN_PRESSED)
 838                 pciehp_handle_attention_button(p_slot);
 839
 840         /* Check Presence Detect Changed */
 841         if (intr_loc & PRSN_DETECT_CHANGED)
 842                 pciehp_handle_presence_change(p_slot);
 843
 844         /* Check Power Fault Detected */
 845         if (intr_loc & PWR_FAULT_DETECTED)
 846                 pciehp_handle_power_fault(p_slot);
 847
 848         return IRQ_HANDLED;
 849 }
 850
 851 static int hpc_get_max_lnk_speed(struct slot *slot, enum pci_bus_speed *value)
 852 {
 853         struct controller *ctrl = slot->ctrl;
 854         enum pcie_link_speed lnk_speed;
 855         u32     lnk_cap;
 856         int retval = 0;
 857
 858         retval = pciehp_readl(ctrl, LNKCAP, &lnk_cap);
 859         if (retval) {
 860                 ctrl_err(ctrl, "%s: Cannot read LNKCAP register\n", __func__);
 861                 return retval;
 862         }
 863
 864         switch (lnk_cap & 0x000F) {
 865         case 1:
 866                 lnk_speed = PCIE_2PT5GB;
 867                 break;
 868         default:
 869                 lnk_speed = PCIE_LNK_SPEED_UNKNOWN;
 870                 break;
 871         }
 872
 873         *value = lnk_speed;
 874         ctrl_dbg(ctrl, "Max link speed = %d\n", lnk_speed);
 875
 876         return retval;
 877 }
 878
 879 static int hpc_get_max_lnk_width(struct slot *slot,
 880                                  enum pcie_link_width *value)
 881 {
 882         struct controller *ctrl = slot->ctrl;
 883         enum pcie_link_width lnk_wdth;
 884         u32     lnk_cap;
 885         int retval = 0;
 886
 887         retval = pciehp_readl(ctrl, LNKCAP, &lnk_cap);
 888         if (retval) {
 889                 ctrl_err(ctrl, "%s: Cannot read LNKCAP register\n", __func__);
 890                 return retval;
 891         }
 892
 893         switch ((lnk_cap & 0x03F0) >> 4){
 894         case 0:
 895                 lnk_wdth = PCIE_LNK_WIDTH_RESRV;
 896                 break;
 897         case 1:
 898                 lnk_wdth = PCIE_LNK_X1;
 899                 break;
 900         case 2:
 901                 lnk_wdth = PCIE_LNK_X2;
 902                 break;
 903         case 4:
 904                 lnk_wdth = PCIE_LNK_X4;
 905                 break;
 906         case 8:
 907                 lnk_wdth = PCIE_LNK_X8;
 908                 break;
 909         case 12:
 910                 lnk_wdth = PCIE_LNK_X12;
 911                 break;
 912         case 16:
 913                 lnk_wdth = PCIE_LNK_X16;
 914                 break;
 915         case 32:
 916                 lnk_wdth = PCIE_LNK_X32;
 917                 break;
 918         default:
 919                 lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
 920                 break;
 921         }
 922
 923         *value = lnk_wdth;
 924         ctrl_dbg(ctrl, "Max link width = %d\n", lnk_wdth);
 925
 926         return retval;
 927 }
 928
 929 static int hpc_get_cur_lnk_speed(struct slot *slot, enum pci_bus_speed *value)
 930 {
 931         struct controller *ctrl = slot->ctrl;
 932         enum pcie_link_speed lnk_speed = PCI_SPEED_UNKNOWN;
 933         int retval = 0;
 934         u16 lnk_status;
 935
 936         retval = pciehp_readw(ctrl, LNKSTATUS, &lnk_status);
 937         if (retval) {
 938                 ctrl_err(ctrl, "%s: Cannot read LNKSTATUS register\n",
 939                          __func__);
 940                 return retval;
 941         }
 942
 943         switch (lnk_status & 0x0F) {
 944         case 1:
 945                 lnk_speed = PCIE_2PT5GB;
 946                 break;
 947         default:
 948                 lnk_speed = PCIE_LNK_SPEED_UNKNOWN;
 949                 break;
 950         }
 951
 952         *value = lnk_speed;
 953         ctrl_dbg(ctrl, "Current link speed = %d\n", lnk_speed);
 954
 955         return retval;
 956 }
 957
 958 static int hpc_get_cur_lnk_width(struct slot *slot,
 959                                  enum pcie_link_width *value)
 960 {
 961         struct controller *ctrl = slot->ctrl;
 962         enum pcie_link_width lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
 963         int retval = 0;
 964         u16 lnk_status;
 965
 966         retval = pciehp_readw(ctrl, LNKSTATUS, &lnk_status);
 967         if (retval) {
 968                 ctrl_err(ctrl, "%s: Cannot read LNKSTATUS register\n",
 969                          __func__);
 970                 return retval;
 971         }
 972
 973         switch ((lnk_status & 0x03F0) >> 4){
 974         case 0:
 975                 lnk_wdth = PCIE_LNK_WIDTH_RESRV;
 976                 break;
 977         case 1:
 978                 lnk_wdth = PCIE_LNK_X1;
 979                 break;
 980         case 2:
 981                 lnk_wdth = PCIE_LNK_X2;
 982                 break;
 983         case 4:
 984                 lnk_wdth = PCIE_LNK_X4;
 985                 break;
 986         case 8:
 987                 lnk_wdth = PCIE_LNK_X8;
 988                 break;
 989         case 12:
 990                 lnk_wdth = PCIE_LNK_X12;
 991                 break;
 992         case 16:
 993                 lnk_wdth = PCIE_LNK_X16;
 994                 break;
 995         case 32:
 996                 lnk_wdth = PCIE_LNK_X32;
 997                 break;
 998         default:
 999                 lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
1000                 break;
1001         }
1002
1003         *value = lnk_wdth;
1004         ctrl_dbg(ctrl, "Current link width = %d\n", lnk_wdth);
1005
1006         return retval;
1007 }
1008
1009 static void pcie_release_ctrl(struct controller *ctrl);
1010 static struct hpc_ops pciehp_hpc_ops = {
1011         .power_on_slot                  = hpc_power_on_slot,
1012         .power_off_slot                 = hpc_power_off_slot,
1013         .set_attention_status           = hpc_set_attention_status,
1014         .get_power_status               = hpc_get_power_status,
1015         .get_attention_status           = hpc_get_attention_status,
1016         .get_latch_status               = hpc_get_latch_status,
1017         .get_adapter_status             = hpc_get_adapter_status,
1018         .get_emi_status                 = hpc_get_emi_status,
1019         .toggle_emi                     = hpc_toggle_emi,
1020
1021         .get_max_bus_speed              = hpc_get_max_lnk_speed,
1022         .get_cur_bus_speed              = hpc_get_cur_lnk_speed,
1023         .get_max_lnk_width              = hpc_get_max_lnk_width,
1024         .get_cur_lnk_width              = hpc_get_cur_lnk_width,
1025
1026         .query_power_fault              = hpc_query_power_fault,
1027         .green_led_on                   = hpc_set_green_led_on,
1028         .green_led_off                  = hpc_set_green_led_off,
1029         .green_led_blink                = hpc_set_green_led_blink,
1030
1031         .release_ctlr                   = pcie_release_ctrl,
1032         .check_lnk_status               = hpc_check_lnk_status,
1033 };
1034
1035 int pcie_enable_notification(struct controller *ctrl)
1036 {
1037         u16 cmd, mask;
1038
1039         cmd = PRSN_DETECT_ENABLE;
1040         if (ATTN_BUTTN(ctrl))
1041                 cmd |= ATTN_BUTTN_ENABLE;
1042         if (POWER_CTRL(ctrl))
1043                 cmd |= PWR_FAULT_DETECT_ENABLE;
1044         if (MRL_SENS(ctrl))
1045                 cmd |= MRL_DETECT_ENABLE;
1046         if (!pciehp_poll_mode)
1047                 cmd |= HP_INTR_ENABLE | CMD_CMPL_INTR_ENABLE;
1048
1049         mask = PRSN_DETECT_ENABLE | ATTN_BUTTN_ENABLE | MRL_DETECT_ENABLE |
1050                PWR_FAULT_DETECT_ENABLE | HP_INTR_ENABLE | CMD_CMPL_INTR_ENABLE;
1051
1052         if (pcie_write_cmd(ctrl, cmd, mask)) {
1053                 ctrl_err(ctrl, "Cannot enable software notification\n");
1054                 return -1;
1055         }
1056         return 0;
1057 }
1058
1059 static void pcie_disable_notification(struct controller *ctrl)
1060 {
1061         u16 mask;
1062         mask = PRSN_DETECT_ENABLE | ATTN_BUTTN_ENABLE | MRL_DETECT_ENABLE |
1063                PWR_FAULT_DETECT_ENABLE | HP_INTR_ENABLE | CMD_CMPL_INTR_ENABLE;
1064         if (pcie_write_cmd(ctrl, 0, mask))
1065                 ctrl_warn(ctrl, "Cannot disable software notification\n");
1066 }
1067
1068 static int pcie_init_notification(struct controller *ctrl)
1069 {
1070         if (pciehp_request_irq(ctrl))
1071                 return -1;
1072         if (pcie_enable_notification(ctrl)) {
1073                 pciehp_free_irq(ctrl);
1074                 return -1;
1075         }
1076         return 0;
1077 }
1078
1079 static void pcie_shutdown_notification(struct controller *ctrl)
1080 {
1081         pcie_disable_notification(ctrl);
1082         pciehp_free_irq(ctrl);
1083 }
1084
1085 static int pcie_init_slot(struct controller *ctrl)
1086 {
1087         struct slot *slot;
1088
1089         slot = kzalloc(sizeof(*slot), GFP_KERNEL);
1090         if (!slot)
1091                 return -ENOMEM;
1092
1093         slot->hp_slot = 0;
1094         slot->ctrl = ctrl;
1095         slot->bus = ctrl->pci_dev->subordinate->number;
1096         slot->device = ctrl->slot_device_offset + slot->hp_slot;
1097         slot->hpc_ops = ctrl->hpc_ops;
1098         slot->number = ctrl->first_slot;
1099         mutex_init(&slot->lock);
1100         INIT_DELAYED_WORK(&slot->work, pciehp_queue_pushbutton_work);
1101         list_add(&slot->slot_list, &ctrl->slot_list);
1102         return 0;
1103 }
1104
1105 static void pcie_cleanup_slot(struct controller *ctrl)
1106 {
1107         struct slot *slot;
1108         slot = list_first_entry(&ctrl->slot_list, struct slot, slot_list);
1109         list_del(&slot->slot_list);
1110         cancel_delayed_work(&slot->work);
1111         flush_scheduled_work();
1112         flush_workqueue(pciehp_wq);
1113         kfree(slot);
1114 }
1115
1116 static inline void dbg_ctrl(struct controller *ctrl)
1117 {
1118         int i;
1119         u16 reg16;
1120         struct pci_dev *pdev = ctrl->pci_dev;
1121
1122         if (!pciehp_debug)
1123                 return;
1124
1125         ctrl_info(ctrl, "Hotplug Controller:\n");
1126         ctrl_info(ctrl, "  Seg/Bus/Dev/Func/IRQ : %s IRQ %d\n",
1127                   pci_name(pdev), pdev->irq);
1128         ctrl_info(ctrl, "  Vendor ID            : 0x%04x\n", pdev->vendor);
1129         ctrl_info(ctrl, "  Device ID            : 0x%04x\n", pdev->device);
1130         ctrl_info(ctrl, "  Subsystem ID         : 0x%04x\n",
1131                   pdev->subsystem_device);
1132         ctrl_info(ctrl, "  Subsystem Vendor ID  : 0x%04x\n",
1133                   pdev->subsystem_vendor);
1134         ctrl_info(ctrl, "  PCIe Cap offset      : 0x%02x\n", ctrl->cap_base);
1135         for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
1136                 if (!pci_resource_len(pdev, i))
1137                         continue;
1138                 ctrl_info(ctrl, "  PCI resource [%d]     : 0x%llx@0x%llx\n",
1139                           i, (unsigned long long)pci_resource_len(pdev, i),
1140                           (unsigned long long)pci_resource_start(pdev, i));
1141         }
1142         ctrl_info(ctrl, "Slot Capabilities      : 0x%08x\n", ctrl->slot_cap);
1143         ctrl_info(ctrl, "  Physical Slot Number : %d\n", ctrl->first_slot);
1144         ctrl_info(ctrl, "  Attention Button     : %3s\n",
1145                   ATTN_BUTTN(ctrl) ? "yes" : "no");
1146         ctrl_info(ctrl, "  Power Controller     : %3s\n",
1147                   POWER_CTRL(ctrl) ? "yes" : "no");
1148         ctrl_info(ctrl, "  MRL Sensor           : %3s\n",
1149                   MRL_SENS(ctrl)   ? "yes" : "no");
1150         ctrl_info(ctrl, "  Attention Indicator  : %3s\n",
1151                   ATTN_LED(ctrl)   ? "yes" : "no");
1152         ctrl_info(ctrl, "  Power Indicator      : %3s\n",
1153                   PWR_LED(ctrl)    ? "yes" : "no");
1154         ctrl_info(ctrl, "  Hot-Plug Surprise    : %3s\n",
1155                   HP_SUPR_RM(ctrl) ? "yes" : "no");
1156         ctrl_info(ctrl, "  EMI Present          : %3s\n",
1157                   EMI(ctrl)        ? "yes" : "no");
1158         ctrl_info(ctrl, "  Command Completed    : %3s\n",
1159                   NO_CMD_CMPL(ctrl) ? "no" : "yes");
1160         pciehp_readw(ctrl, SLOTSTATUS, &reg16);
1161         ctrl_info(ctrl, "Slot Status            : 0x%04x\n", reg16);
1162         pciehp_readw(ctrl, SLOTCTRL, &reg16);
1163         ctrl_info(ctrl, "Slot Control           : 0x%04x\n", reg16);
1164 }
1165
1166 struct controller *pcie_init(struct pcie_device *dev)
1167 {
1168         struct controller *ctrl;
1169         u32 slot_cap, link_cap;
1170         struct pci_dev *pdev = dev->port;
1171
1172         ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL);
1173         if (!ctrl) {
1174                 dev_err(&dev->device, "%s: Out of memory\n", __func__);
1175                 goto abort;
1176         }
1177         INIT_LIST_HEAD(&ctrl->slot_list);
1178
1179         ctrl->pcie = dev;
1180         ctrl->pci_dev = pdev;
1181         ctrl->cap_base = pci_find_capability(pdev, PCI_CAP_ID_EXP);
1182         if (!ctrl->cap_base) {
1183                 ctrl_err(ctrl, "Cannot find PCI Express capability\n");
1184                 goto abort_ctrl;
1185         }
1186         if (pciehp_readl(ctrl, SLOTCAP, &slot_cap)) {
1187                 ctrl_err(ctrl, "Cannot read SLOTCAP register\n");
1188                 goto abort_ctrl;
1189         }
1190
1191         ctrl->slot_cap = slot_cap;
1192         ctrl->first_slot = slot_cap >> 19;
1193         ctrl->slot_device_offset = 0;
1194         ctrl->num_slots = 1;
1195         ctrl->hpc_ops = &pciehp_hpc_ops;
1196         mutex_init(&ctrl->crit_sect);
1197         mutex_init(&ctrl->ctrl_lock);
1198         init_waitqueue_head(&ctrl->queue);
1199         dbg_ctrl(ctrl);
1200         /*
1201          * Controller doesn't notify of command completion if the "No
1202          * Command Completed Support" bit is set in Slot Capability
1203          * register or the controller supports none of power
1204          * controller, attention led, power led and EMI.
1205          */
1206         if (NO_CMD_CMPL(ctrl) ||
1207             !(POWER_CTRL(ctrl) | ATTN_LED(ctrl) | PWR_LED(ctrl) | EMI(ctrl)))
1208             ctrl->no_cmd_complete = 1;
1209
1210         /* Check if Data Link Layer Link Active Reporting is implemented */
1211         if (pciehp_readl(ctrl, LNKCAP, &link_cap)) {
1212                 ctrl_err(ctrl, "%s: Cannot read LNKCAP register\n", __func__);
1213                 goto abort_ctrl;
1214         }
1215         if (link_cap & LINK_ACTIVE_REPORTING) {
1216                 ctrl_dbg(ctrl, "Link Active Reporting supported\n");
1217                 ctrl->link_active_reporting = 1;
1218         }
1219
1220         /* Clear all remaining event bits in Slot Status register */
1221         if (pciehp_writew(ctrl, SLOTSTATUS, 0x1f))
1222                 goto abort_ctrl;
1223
1224         /* Disable sotfware notification */
1225         pcie_disable_notification(ctrl);
1226
1227         /*
1228          * If this is the first controller to be initialized,
1229          * initialize the pciehp work queue
1230          */
1231         if (atomic_add_return(1, &pciehp_num_controllers) == 1) {
1232                 pciehp_wq = create_singlethread_workqueue("pciehpd");
1233                 if (!pciehp_wq)
1234                         goto abort_ctrl;
1235         }
1236
1237         ctrl_info(ctrl, "HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n",
1238                   pdev->vendor, pdev->device, pdev->subsystem_vendor,
1239                   pdev->subsystem_device);
1240
1241         if (pcie_init_slot(ctrl))
1242                 goto abort_ctrl;
1243
1244         if (pcie_init_notification(ctrl))
1245                 goto abort_slot;
1246
1247         return ctrl;
1248
1249 abort_slot:
1250         pcie_cleanup_slot(ctrl);
1251 abort_ctrl:
1252         kfree(ctrl);
1253 abort:
1254         return NULL;
1255 }
1256
1257 void pcie_release_ctrl(struct controller *ctrl)
1258 {
1259         pcie_shutdown_notification(ctrl);
1260         pcie_cleanup_slot(ctrl);
1261         /*
1262          * If this is the last controller to be released, destroy the
1263          * pciehp work queue
1264          */
1265         if (atomic_dec_and_test(&pciehp_num_controllers))
1266                 destroy_workqueue(pciehp_wq);
1267         kfree(ctrl);
1268 }