drivers/net/wireless/iwlwifi/iwl-3945-hw.h

   1 /******************************************************************************
   2  *
   3  * This file is provided under a dual BSD/GPLv2 license.  When using or
   4  * redistributing this file, you may do so under either license.
   5  *
   6  * GPL LICENSE SUMMARY
   7  *
   8  * Copyright(c) 2005 - 2007 Intel Corporation. All rights reserved.
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of version 2 of the GNU General Public License as
  12  * published by the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful, but
  15  * WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  17  * General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
  22  * USA
  23  *
  24  * The full GNU General Public License is included in this distribution
  25  * in the file called LICENSE.GPL.
  26  *
  27  * Contact Information:
  28  * James P. Ketrenos <ipw2100-admin@linux.intel.com>
  29  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  30  *
  31  * BSD LICENSE
  32  *
  33  * Copyright(c) 2005 - 2007 Intel Corporation. All rights reserved.
  34  * All rights reserved.
  35  *
  36  * Redistribution and use in source and binary forms, with or without
  37  * modification, are permitted provided that the following conditions
  38  * are met:
  39  *
  40  *  * Redistributions of source code must retain the above copyright
  41  *    notice, this list of conditions and the following disclaimer.
  42  *  * Redistributions in binary form must reproduce the above copyright
  43  *    notice, this list of conditions and the following disclaimer in
  44  *    the documentation and/or other materials provided with the
  45  *    distribution.
  46  *  * Neither the name Intel Corporation nor the names of its
  47  *    contributors may be used to endorse or promote products derived
  48  *    from this software without specific prior written permission.
  49  *
  50  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  51  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  52  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  53  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  54  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  55  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  56  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  57  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  58  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  59  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  60  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  61  *
  62  *****************************************************************************/
  63
  64 #ifndef __iwl_3945_hw__
  65 #define __iwl_3945_hw__
  66
  67 /* uCode queue management definitions */
  68 #define IWL_CMD_QUEUE_NUM       4
  69 #define IWL_CMD_FIFO_NUM        4
  70 #define IWL_BACK_QUEUE_FIRST_ID 7
  71
  72 /* Tx rates */
  73 #define IWL_CCK_RATES 4
  74 #define IWL_OFDM_RATES 8
  75
  76 #define IWL_HT_RATES 0
  77
  78 #define IWL_MAX_RATES  (IWL_CCK_RATES+IWL_OFDM_RATES+IWL_HT_RATES)
  79
  80 /* Time constants */
  81 #define SHORT_SLOT_TIME 9
  82 #define LONG_SLOT_TIME 20
  83
  84 /* RSSI to dBm */
  85 #define IWL_RSSI_OFFSET 95
  86
  87 /*
  88  * This file defines EEPROM related constants, enums, and inline functions.
  89  *
  90  */
  91
  92 #define IWL_EEPROM_ACCESS_TIMEOUT       5000 /* uSec */
  93 #define IWL_EEPROM_ACCESS_DELAY         10   /* uSec */
  94 /* EEPROM field values */
  95 #define ANTENNA_SWITCH_NORMAL     0
  96 #define ANTENNA_SWITCH_INVERSE    1
  97
  98 enum {
  99         EEPROM_CHANNEL_VALID = (1 << 0),        /* usable for this SKU/geo */
 100         EEPROM_CHANNEL_IBSS = (1 << 1), /* usable as an IBSS channel */
 101         /* Bit 2 Reserved */
 102         EEPROM_CHANNEL_ACTIVE = (1 << 3),       /* active scanning allowed */
 103         EEPROM_CHANNEL_RADAR = (1 << 4),        /* radar detection required */
 104         EEPROM_CHANNEL_WIDE = (1 << 5),
 105         EEPROM_CHANNEL_NARROW = (1 << 6),
 106         EEPROM_CHANNEL_DFS = (1 << 7),  /* dynamic freq selection candidate */
 107 };
 108
 109 /* EEPROM field lengths */
 110 #define EEPROM_BOARD_PBA_NUMBER_LENGTH                  11
 111
 112 /* EEPROM field lengths */
 113 #define EEPROM_BOARD_PBA_NUMBER_LENGTH                  11
 114 #define EEPROM_REGULATORY_SKU_ID_LENGTH                 4
 115 #define EEPROM_REGULATORY_BAND1_CHANNELS_LENGTH         14
 116 #define EEPROM_REGULATORY_BAND2_CHANNELS_LENGTH         13
 117 #define EEPROM_REGULATORY_BAND3_CHANNELS_LENGTH         12
 118 #define EEPROM_REGULATORY_BAND4_CHANNELS_LENGTH         11
 119 #define EEPROM_REGULATORY_BAND5_CHANNELS_LENGTH         6
 120
 121 #define EEPROM_REGULATORY_CHANNELS_LENGTH ( \
 122         EEPROM_REGULATORY_BAND1_CHANNELS_LENGTH + \
 123         EEPROM_REGULATORY_BAND2_CHANNELS_LENGTH + \
 124         EEPROM_REGULATORY_BAND3_CHANNELS_LENGTH + \
 125         EEPROM_REGULATORY_BAND4_CHANNELS_LENGTH + \
 126         EEPROM_REGULATORY_BAND5_CHANNELS_LENGTH)
 127
 128 #define EEPROM_REGULATORY_NUMBER_OF_BANDS               5
 129
 130 /* SKU Capabilities */
 131 #define EEPROM_SKU_CAP_SW_RF_KILL_ENABLE                (1 << 0)
 132 #define EEPROM_SKU_CAP_HW_RF_KILL_ENABLE                (1 << 1)
 133 #define EEPROM_SKU_CAP_OP_MODE_MRC                      (1 << 7)
 134
 135 /* *regulatory* channel data from eeprom, one for each channel */
 136 struct iwl_eeprom_channel {
 137         u8 flags;               /* flags copied from EEPROM */
 138         s8 max_power_avg;       /* max power (dBm) on this chnl, limit 31 */
 139 } __attribute__ ((packed));
 140
 141 /*
 142  * Mapping of a Tx power level, at factory calibration temperature,
 143  *   to a radio/DSP gain table index.
 144  * One for each of 5 "sample" power levels in each band.
 145  * v_det is measured at the factory, using the 3945's built-in power amplifier
 146  *   (PA) output voltage detector.  This same detector is used during Tx of
 147  *   long packets in normal operation to provide feedback as to proper output
 148  *   level.
 149  * Data copied from EEPROM.
 150  */
 151 struct iwl_eeprom_txpower_sample {
 152         u8 gain_index;          /* index into power (gain) setup table ... */
 153         s8 power;               /* ... for this pwr level for this chnl group */
 154         u16 v_det;              /* PA output voltage */
 155 } __attribute__ ((packed));
 156
 157 /*
 158  * Mappings of Tx power levels -> nominal radio/DSP gain table indexes.
 159  * One for each channel group (a.k.a. "band") (1 for BG, 4 for A).
 160  * Tx power setup code interpolates between the 5 "sample" power levels
 161  *    to determine the nominal setup for a requested power level.
 162  * Data copied from EEPROM.
 163  * DO NOT ALTER THIS STRUCTURE!!!
 164  */
 165 struct iwl_eeprom_txpower_group {
 166         struct iwl_eeprom_txpower_sample samples[5];    /* 5 power levels */
 167         s32 a, b, c, d, e;      /* coefficients for voltage->power
 168                                  * formula (signed) */
 169         s32 Fa, Fb, Fc, Fd, Fe; /* these modify coeffs based on
 170                                          * frequency (signed) */
 171         s8 saturation_power;    /* highest power possible by h/w in this
 172                                  * band */
 173         u8 group_channel;       /* "representative" channel # in this band */
 174         s16 temperature;        /* h/w temperature at factory calib this band
 175                                  * (signed) */
 176 } __attribute__ ((packed));
 177
 178 /*
 179  * Temperature-based Tx-power compensation data, not band-specific.
 180  * These coefficients are use to modify a/b/c/d/e coeffs based on
 181  *   difference between current temperature and factory calib temperature.
 182  * Data copied from EEPROM.
 183  */
 184 struct iwl_eeprom_temperature_corr {
 185         u32 Ta;
 186         u32 Tb;
 187         u32 Tc;
 188         u32 Td;
 189         u32 Te;
 190 } __attribute__ ((packed));
 191
 192 struct iwl_eeprom {
 193         u8 reserved0[16];
 194 #define EEPROM_DEVICE_ID                    (2*0x08)    /* 2 bytes */
 195         u16 device_id;  /* abs.ofs: 16 */
 196         u8 reserved1[2];
 197 #define EEPROM_PMC                          (2*0x0A)    /* 2 bytes */
 198         u16 pmc;                /* abs.ofs: 20 */
 199         u8 reserved2[20];
 200 #define EEPROM_MAC_ADDRESS                  (2*0x15)    /* 6  bytes */
 201         u8 mac_address[6];      /* abs.ofs: 42 */
 202         u8 reserved3[58];
 203 #define EEPROM_BOARD_REVISION               (2*0x35)    /* 2  bytes */
 204         u16 board_revision;     /* abs.ofs: 106 */
 205         u8 reserved4[11];
 206 #define EEPROM_BOARD_PBA_NUMBER             (2*0x3B+1)  /* 9  bytes */
 207         u8 board_pba_number[9]; /* abs.ofs: 119 */
 208         u8 reserved5[8];
 209 #define EEPROM_VERSION                      (2*0x44)    /* 2  bytes */
 210         u16 version;            /* abs.ofs: 136 */
 211 #define EEPROM_SKU_CAP                      (2*0x45)    /* 1  bytes */
 212         u8 sku_cap;             /* abs.ofs: 138 */
 213 #define EEPROM_LEDS_MODE                    (2*0x45+1)  /* 1  bytes */
 214         u8 leds_mode;           /* abs.ofs: 139 */
 215 #define EEPROM_OEM_MODE                     (2*0x46)    /* 2  bytes */
 216         u16 oem_mode;
 217 #define EEPROM_WOWLAN_MODE                  (2*0x47)    /* 2  bytes */
 218         u16 wowlan_mode;        /* abs.ofs: 142 */
 219 #define EEPROM_LEDS_TIME_INTERVAL           (2*0x48)    /* 2  bytes */
 220         u16 leds_time_interval; /* abs.ofs: 144 */
 221 #define EEPROM_LEDS_OFF_TIME                (2*0x49)    /* 1  bytes */
 222         u8 leds_off_time;       /* abs.ofs: 146 */
 223 #define EEPROM_LEDS_ON_TIME                 (2*0x49+1)  /* 1  bytes */
 224         u8 leds_on_time;        /* abs.ofs: 147 */
 225 #define EEPROM_ALMGOR_M_VERSION             (2*0x4A)    /* 1  bytes */
 226         u8 almgor_m_version;    /* abs.ofs: 148 */
 227 #define EEPROM_ANTENNA_SWITCH_TYPE          (2*0x4A+1)  /* 1  bytes */
 228         u8 antenna_switch_type; /* abs.ofs: 149 */
 229         u8 reserved6[42];
 230 #define EEPROM_REGULATORY_SKU_ID            (2*0x60)    /* 4  bytes */
 231         u8 sku_id[4];           /* abs.ofs: 192 */
 232 #define EEPROM_REGULATORY_BAND_1            (2*0x62)    /* 2  bytes */
 233         u16 band_1_count;       /* abs.ofs: 196 */
 234 #define EEPROM_REGULATORY_BAND_1_CHANNELS   (2*0x63)    /* 28 bytes */
 235         struct iwl_eeprom_channel band_1_channels[14];  /* abs.ofs: 196 */
 236 #define EEPROM_REGULATORY_BAND_2            (2*0x71)    /* 2  bytes */
 237         u16 band_2_count;       /* abs.ofs: 226 */
 238 #define EEPROM_REGULATORY_BAND_2_CHANNELS   (2*0x72)    /* 26 bytes */
 239         struct iwl_eeprom_channel band_2_channels[13];  /* abs.ofs: 228 */
 240 #define EEPROM_REGULATORY_BAND_3            (2*0x7F)    /* 2  bytes */
 241         u16 band_3_count;       /* abs.ofs: 254 */
 242 #define EEPROM_REGULATORY_BAND_3_CHANNELS   (2*0x80)    /* 24 bytes */
 243         struct iwl_eeprom_channel band_3_channels[12];  /* abs.ofs: 256 */
 244 #define EEPROM_REGULATORY_BAND_4            (2*0x8C)    /* 2  bytes */
 245         u16 band_4_count;       /* abs.ofs: 280 */
 246 #define EEPROM_REGULATORY_BAND_4_CHANNELS   (2*0x8D)    /* 22 bytes */
 247         struct iwl_eeprom_channel band_4_channels[11];  /* abs.ofs: 282 */
 248 #define EEPROM_REGULATORY_BAND_5            (2*0x98)    /* 2  bytes */
 249         u16 band_5_count;       /* abs.ofs: 304 */
 250 #define EEPROM_REGULATORY_BAND_5_CHANNELS   (2*0x99)    /* 12 bytes */
 251         struct iwl_eeprom_channel band_5_channels[6];   /* abs.ofs: 306 */
 252
 253         u8 reserved9[194];
 254
 255 #define EEPROM_TXPOWER_CALIB_GROUP0 0x200
 256 #define EEPROM_TXPOWER_CALIB_GROUP1 0x240
 257 #define EEPROM_TXPOWER_CALIB_GROUP2 0x280
 258 #define EEPROM_TXPOWER_CALIB_GROUP3 0x2c0
 259 #define EEPROM_TXPOWER_CALIB_GROUP4 0x300
 260 #define IWL_NUM_TX_CALIB_GROUPS 5
 261         struct iwl_eeprom_txpower_group groups[IWL_NUM_TX_CALIB_GROUPS];
 262 /* abs.ofs: 512 */
 263 #define EEPROM_CALIB_TEMPERATURE_CORRECT 0x340
 264         struct iwl_eeprom_temperature_corr corrections; /* abs.ofs: 832 */
 265         u8 reserved16[172];     /* fill out to full 1024 byte block */
 266 } __attribute__ ((packed));
 267
 268 #define IWL_EEPROM_IMAGE_SIZE 1024
 269
 270
 271 #include "iwl-3945-commands.h"
 272
 273 #define PCI_LINK_CTRL      0x0F0
 274 #define PCI_POWER_SOURCE   0x0C8
 275 #define PCI_REG_WUM8       0x0E8
 276 #define PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT         (0x80000000)
 277
 278 /*=== CSR (control and status registers) ===*/
 279 #define CSR_BASE    (0x000)
 280
 281 #define CSR_SW_VER              (CSR_BASE+0x000)
 282 #define CSR_HW_IF_CONFIG_REG    (CSR_BASE+0x000) /* hardware interface config */
 283 #define CSR_INT_COALESCING      (CSR_BASE+0x004) /* accum ints, 32-usec units */
 284 #define CSR_INT                 (CSR_BASE+0x008) /* host interrupt status/ack */
 285 #define CSR_INT_MASK            (CSR_BASE+0x00c) /* host interrupt enable */
 286 #define CSR_FH_INT_STATUS       (CSR_BASE+0x010) /* busmaster int status/ack*/
 287 #define CSR_GPIO_IN             (CSR_BASE+0x018) /* read external chip pins */
 288 #define CSR_RESET               (CSR_BASE+0x020) /* busmaster enable, NMI, etc*/
 289 #define CSR_GP_CNTRL            (CSR_BASE+0x024)
 290 #define CSR_HW_REV              (CSR_BASE+0x028)
 291 #define CSR_EEPROM_REG          (CSR_BASE+0x02c)
 292 #define CSR_EEPROM_GP           (CSR_BASE+0x030)
 293 #define CSR_GP_UCODE            (CSR_BASE+0x044)
 294 #define CSR_UCODE_DRV_GP1       (CSR_BASE+0x054)
 295 #define CSR_UCODE_DRV_GP1_SET   (CSR_BASE+0x058)
 296 #define CSR_UCODE_DRV_GP1_CLR   (CSR_BASE+0x05c)
 297 #define CSR_UCODE_DRV_GP2       (CSR_BASE+0x060)
 298 #define CSR_LED_REG             (CSR_BASE+0x094)
 299 #define CSR_DRAM_INT_TBL_CTL    (CSR_BASE+0x0A0)
 300 #define CSR_GIO_CHICKEN_BITS    (CSR_BASE+0x100)
 301 #define CSR_ANA_PLL_CFG         (CSR_BASE+0x20c)
 302 #define CSR_HW_REV_WA_REG       (CSR_BASE+0x22C)
 303
 304 /* HW I/F configuration */
 305 #define CSR_HW_IF_CONFIG_REG_BIT_ALMAGOR_MB         (0x00000100)
 306 #define CSR_HW_IF_CONFIG_REG_BIT_ALMAGOR_MM         (0x00000200)
 307 #define CSR_HW_IF_CONFIG_REG_BIT_SKU_MRC            (0x00000400)
 308 #define CSR_HW_IF_CONFIG_REG_BIT_BOARD_TYPE         (0x00000800)
 309 #define CSR_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_A    (0x00000000)
 310 #define CSR_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_B    (0x00001000)
 311 #define CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM     (0x00200000)
 312
 313 /* interrupt flags in INTA, set by uCode or hardware (e.g. dma),
 314  * acknowledged (reset) by host writing "1" to flagged bits. */
 315 #define CSR_INT_BIT_FH_RX        (1<<31) /* Rx DMA, cmd responses, FH_INT[17:16] */
 316 #define CSR_INT_BIT_HW_ERR       (1<<29) /* DMA hardware error FH_INT[31] */
 317 #define CSR_INT_BIT_DNLD         (1<<28) /* uCode Download */
 318 #define CSR_INT_BIT_FH_TX        (1<<27) /* Tx DMA FH_INT[1:0] */
 319 #define CSR_INT_BIT_MAC_CLK_ACTV (1<<26) /* NIC controller's clock toggled on/off */
 320 #define CSR_INT_BIT_SW_ERR       (1<<25) /* uCode error */
 321 #define CSR_INT_BIT_RF_KILL      (1<<7)  /* HW RFKILL switch GP_CNTRL[27] toggled */
 322 #define CSR_INT_BIT_CT_KILL      (1<<6)  /* Critical temp (chip too hot) rfkill */
 323 #define CSR_INT_BIT_SW_RX        (1<<3)  /* Rx, command responses, 3945 */
 324 #define CSR_INT_BIT_WAKEUP       (1<<1)  /* NIC controller waking up (pwr mgmt) */
 325 #define CSR_INT_BIT_ALIVE        (1<<0)  /* uCode interrupts once it initializes */
 326
 327 #define CSR_INI_SET_MASK        (CSR_INT_BIT_FH_RX   | \
 328                                  CSR_INT_BIT_HW_ERR  | \
 329                                  CSR_INT_BIT_FH_TX   | \
 330                                  CSR_INT_BIT_SW_ERR  | \
 331                                  CSR_INT_BIT_RF_KILL | \
 332                                  CSR_INT_BIT_SW_RX   | \
 333                                  CSR_INT_BIT_WAKEUP  | \
 334                                  CSR_INT_BIT_ALIVE)
 335
 336 /* interrupt flags in FH (flow handler) (PCI busmaster DMA) */
 337 #define CSR_FH_INT_BIT_ERR       (1<<31) /* Error */
 338 #define CSR_FH_INT_BIT_HI_PRIOR  (1<<30) /* High priority Rx, bypass coalescing */
 339 #define CSR_FH_INT_BIT_RX_CHNL2  (1<<18) /* Rx channel 2 (3945 only) */
 340 #define CSR_FH_INT_BIT_RX_CHNL1  (1<<17) /* Rx channel 1 */
 341 #define CSR_FH_INT_BIT_RX_CHNL0  (1<<16) /* Rx channel 0 */
 342 #define CSR_FH_INT_BIT_TX_CHNL6  (1<<6)  /* Tx channel 6 (3945 only) */
 343 #define CSR_FH_INT_BIT_TX_CHNL1  (1<<1)  /* Tx channel 1 */
 344 #define CSR_FH_INT_BIT_TX_CHNL0  (1<<0)  /* Tx channel 0 */
 345
 346 #define CSR_FH_INT_RX_MASK      (CSR_FH_INT_BIT_HI_PRIOR | \
 347                                  CSR_FH_INT_BIT_RX_CHNL2 | \
 348                                  CSR_FH_INT_BIT_RX_CHNL1 | \
 349                                  CSR_FH_INT_BIT_RX_CHNL0)
 350
 351 #define CSR_FH_INT_TX_MASK      (CSR_FH_INT_BIT_TX_CHNL6 | \
 352                                  CSR_FH_INT_BIT_TX_CHNL1 | \
 353                                  CSR_FH_INT_BIT_TX_CHNL0)
 354
 355
 356 /* RESET */
 357 #define CSR_RESET_REG_FLAG_NEVO_RESET                (0x00000001)
 358 #define CSR_RESET_REG_FLAG_FORCE_NMI                 (0x00000002)
 359 #define CSR_RESET_REG_FLAG_SW_RESET                  (0x00000080)
 360 #define CSR_RESET_REG_FLAG_MASTER_DISABLED           (0x00000100)
 361 #define CSR_RESET_REG_FLAG_STOP_MASTER               (0x00000200)
 362
 363 /* GP (general purpose) CONTROL */
 364 #define CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY        (0x00000001)
 365 #define CSR_GP_CNTRL_REG_FLAG_INIT_DONE              (0x00000004)
 366 #define CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ         (0x00000008)
 367 #define CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP         (0x00000010)
 368
 369 #define CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN           (0x00000001)
 370
 371 #define CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE         (0x07000000)
 372 #define CSR_GP_CNTRL_REG_FLAG_MAC_POWER_SAVE         (0x04000000)
 373 #define CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW          (0x08000000)
 374
 375
 376 /* EEPROM REG */
 377 #define CSR_EEPROM_REG_READ_VALID_MSK   (0x00000001)
 378 #define CSR_EEPROM_REG_BIT_CMD          (0x00000002)
 379
 380 /* EEPROM GP */
 381 #define CSR_EEPROM_GP_VALID_MSK         (0x00000006)
 382 #define CSR_EEPROM_GP_BAD_SIGNATURE     (0x00000000)
 383 #define CSR_EEPROM_GP_IF_OWNER_MSK      (0x00000180)
 384
 385 /* UCODE DRV GP */
 386 #define CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP             (0x00000001)
 387 #define CSR_UCODE_SW_BIT_RFKILL                     (0x00000002)
 388 #define CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED           (0x00000004)
 389 #define CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT      (0x00000008)
 390
 391 /* GPIO */
 392 #define CSR_GPIO_IN_BIT_AUX_POWER                   (0x00000200)
 393 #define CSR_GPIO_IN_VAL_VAUX_PWR_SRC                (0x00000000)
 394 #define CSR_GPIO_IN_VAL_VMAIN_PWR_SRC           CSR_GPIO_IN_BIT_AUX_POWER
 395
 396 /* GI Chicken Bits */
 397 #define CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX  (0x00800000)
 398 #define CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER  (0x20000000)
 399
 400 /* CSR_ANA_PLL_CFG */
 401 #define CSR_ANA_PLL_CFG_SH              (0x00880300)
 402
 403 #define CSR_LED_REG_TRUN_ON             (0x00000078)
 404 #define CSR_LED_REG_TRUN_OFF            (0x00000038)
 405 #define CSR_LED_BSM_CTRL_MSK            (0xFFFFFFDF)
 406
 407 /* DRAM_INT_TBL_CTRL */
 408 #define CSR_DRAM_INT_TBL_CTRL_EN        (1<<31)
 409 #define CSR_DRAM_INT_TBL_CTRL_WRAP_CHK  (1<<27)
 410
 411 /*=== HBUS (Host-side Bus) ===*/
 412 #define HBUS_BASE       (0x400)
 413
 414 #define HBUS_TARG_MEM_RADDR     (HBUS_BASE+0x00c)
 415 #define HBUS_TARG_MEM_WADDR     (HBUS_BASE+0x010)
 416 #define HBUS_TARG_MEM_WDAT      (HBUS_BASE+0x018)
 417 #define HBUS_TARG_MEM_RDAT      (HBUS_BASE+0x01c)
 418 #define HBUS_TARG_PRPH_WADDR    (HBUS_BASE+0x044)
 419 #define HBUS_TARG_PRPH_RADDR    (HBUS_BASE+0x048)
 420 #define HBUS_TARG_PRPH_WDAT     (HBUS_BASE+0x04c)
 421 #define HBUS_TARG_PRPH_RDAT     (HBUS_BASE+0x050)
 422 #define HBUS_TARG_WRPTR         (HBUS_BASE+0x060)
 423
 424 #define HBUS_TARG_MBX_C         (HBUS_BASE+0x030)
 425
 426
 427 /* SCD (Scheduler) */
 428 #define SCD_BASE                        (CSR_BASE + 0x2E00)
 429
 430 #define SCD_MODE_REG                    (SCD_BASE + 0x000)
 431 #define SCD_ARASTAT_REG                 (SCD_BASE + 0x004)
 432 #define SCD_TXFACT_REG                  (SCD_BASE + 0x010)
 433 #define SCD_TXF4MF_REG                  (SCD_BASE + 0x014)
 434 #define SCD_TXF5MF_REG                  (SCD_BASE + 0x020)
 435 #define SCD_SBYP_MODE_1_REG             (SCD_BASE + 0x02C)
 436 #define SCD_SBYP_MODE_2_REG             (SCD_BASE + 0x030)
 437
 438 /*=== FH (data Flow Handler) ===*/
 439 #define FH_BASE     (0x800)
 440
 441 #define FH_CBCC_TABLE           (FH_BASE+0x140)
 442 #define FH_TFDB_TABLE           (FH_BASE+0x180)
 443 #define FH_RCSR_TABLE           (FH_BASE+0x400)
 444 #define FH_RSSR_TABLE           (FH_BASE+0x4c0)
 445 #define FH_TCSR_TABLE           (FH_BASE+0x500)
 446 #define FH_TSSR_TABLE           (FH_BASE+0x680)
 447
 448 /* TFDB (Transmit Frame Buffer Descriptor) */
 449 #define FH_TFDB(_channel, buf) \
 450         (FH_TFDB_TABLE+((_channel)*2+(buf))*0x28)
 451 #define ALM_FH_TFDB_CHNL_BUF_CTRL_REG(_channel) \
 452         (FH_TFDB_TABLE + 0x50 * _channel)
 453 /* CBCC _channel is [0,2] */
 454 #define FH_CBCC(_channel)           (FH_CBCC_TABLE+(_channel)*0x8)
 455 #define FH_CBCC_CTRL(_channel)      (FH_CBCC(_channel)+0x00)
 456 #define FH_CBCC_BASE(_channel)      (FH_CBCC(_channel)+0x04)
 457
 458 /* RCSR _channel is [0,2] */
 459 #define FH_RCSR(_channel)           (FH_RCSR_TABLE+(_channel)*0x40)
 460 #define FH_RCSR_CONFIG(_channel)    (FH_RCSR(_channel)+0x00)
 461 #define FH_RCSR_RBD_BASE(_channel)  (FH_RCSR(_channel)+0x04)
 462 #define FH_RCSR_WPTR(_channel)      (FH_RCSR(_channel)+0x20)
 463 #define FH_RCSR_RPTR_ADDR(_channel) (FH_RCSR(_channel)+0x24)
 464
 465 #define FH_RSCSR_CHNL0_WPTR        (FH_RCSR_WPTR(0))
 466
 467 /* RSSR */
 468 #define FH_RSSR_CTRL            (FH_RSSR_TABLE+0x000)
 469 #define FH_RSSR_STATUS          (FH_RSSR_TABLE+0x004)
 470 /* TCSR */
 471 #define FH_TCSR(_channel)           (FH_TCSR_TABLE+(_channel)*0x20)
 472 #define FH_TCSR_CONFIG(_channel)    (FH_TCSR(_channel)+0x00)
 473 #define FH_TCSR_CREDIT(_channel)    (FH_TCSR(_channel)+0x04)
 474 #define FH_TCSR_BUFF_STTS(_channel) (FH_TCSR(_channel)+0x08)
 475 /* TSSR */
 476 #define FH_TSSR_CBB_BASE        (FH_TSSR_TABLE+0x000)
 477 #define FH_TSSR_MSG_CONFIG      (FH_TSSR_TABLE+0x008)
 478 #define FH_TSSR_TX_STATUS       (FH_TSSR_TABLE+0x010)
 479 /* 18 - reserved */
 480
 481 /* card static random access memory (SRAM) for processor data and instructs */
 482 #define RTC_INST_LOWER_BOUND                    (0x000000)
 483 #define RTC_DATA_LOWER_BOUND                    (0x800000)
 484
 485
 486 /* DBM */
 487
 488 #define ALM_FH_SRVC_CHNL                            (6)
 489
 490 #define ALM_FH_RCSR_RX_CONFIG_REG_POS_RBDC_SIZE     (20)
 491 #define ALM_FH_RCSR_RX_CONFIG_REG_POS_IRQ_RBTH      (4)
 492
 493 #define ALM_FH_RCSR_RX_CONFIG_REG_BIT_WR_STTS_EN    (0x08000000)
 494
 495 #define ALM_FH_RCSR_RX_CONFIG_REG_VAL_DMA_CHNL_EN_ENABLE        (0x80000000)
 496
 497 #define ALM_FH_RCSR_RX_CONFIG_REG_VAL_RDRBD_EN_ENABLE           (0x20000000)
 498
 499 #define ALM_FH_RCSR_RX_CONFIG_REG_VAL_MAX_FRAG_SIZE_128         (0x01000000)
 500
 501 #define ALM_FH_RCSR_RX_CONFIG_REG_VAL_IRQ_DEST_INT_HOST         (0x00001000)
 502
 503 #define ALM_FH_RCSR_RX_CONFIG_REG_VAL_MSG_MODE_FH               (0x00000000)
 504
 505 #define ALM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF              (0x00000000)
 506 #define ALM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_DRIVER           (0x00000001)
 507
 508 #define ALM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE_VAL    (0x00000000)
 509 #define ALM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL     (0x00000008)
 510
 511 #define ALM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD           (0x00200000)
 512
 513 #define ALM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT            (0x00000000)
 514
 515 #define ALM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE            (0x00000000)
 516 #define ALM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE           (0x80000000)
 517
 518 #define ALM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID          (0x00004000)
 519
 520 #define ALM_FH_TCSR_CHNL_TX_BUF_STS_REG_BIT_TFDB_WPTR           (0x00000001)
 521
 522 #define ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON      (0xFF000000)
 523 #define ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON      (0x00FF0000)
 524
 525 #define ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B    (0x00000400)
 526
 527 #define ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TFD_ON       (0x00000100)
 528 #define ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_CBB_ON       (0x00000080)
 529
 530 #define ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH     (0x00000020)
 531 #define ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH           (0x00000005)
 532
 533 #define ALM_TB_MAX_BYTES_COUNT      (0xFFF0)
 534
 535 #define ALM_FH_TSSR_TX_STATUS_REG_BIT_BUFS_EMPTY(_channel) \
 536         ((1LU << _channel) << 24)
 537 #define ALM_FH_TSSR_TX_STATUS_REG_BIT_NO_PEND_REQ(_channel) \
 538         ((1LU << _channel) << 16)
 539
 540 #define ALM_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(_channel) \
 541         (ALM_FH_TSSR_TX_STATUS_REG_BIT_BUFS_EMPTY(_channel) | \
 542          ALM_FH_TSSR_TX_STATUS_REG_BIT_NO_PEND_REQ(_channel))
 543 #define PCI_CFG_REV_ID_BIT_BASIC_SKU                (0x40)      /* bit 6    */
 544 #define PCI_CFG_REV_ID_BIT_RTP                      (0x80)      /* bit 7    */
 545
 546 #define HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED         (0x00000004)
 547
 548 #define TFD_QUEUE_MIN           0
 549 #define TFD_QUEUE_MAX           6
 550 #define TFD_QUEUE_SIZE_MAX      (256)
 551
 552 /* spectrum and channel data structures */
 553 #define IWL_NUM_SCAN_RATES         (2)
 554
 555 #define IWL_SCAN_FLAG_24GHZ  (1<<0)
 556 #define IWL_SCAN_FLAG_52GHZ  (1<<1)
 557 #define IWL_SCAN_FLAG_ACTIVE (1<<2)
 558 #define IWL_SCAN_FLAG_DIRECT (1<<3)
 559
 560 #define IWL_MAX_CMD_SIZE 1024
 561
 562 #define IWL_DEFAULT_TX_RETRY  15
 563 #define IWL_MAX_TX_RETRY      16
 564
 565 /*********************************************/
 566
 567 #define RFD_SIZE                              4
 568 #define NUM_TFD_CHUNKS                        4
 569
 570 #define RX_QUEUE_SIZE                         256
 571 #define RX_QUEUE_MASK                         255
 572 #define RX_QUEUE_SIZE_LOG                     8
 573
 574 /* QoS  definitions */
 575
 576 #define CW_MIN_OFDM          15
 577 #define CW_MAX_OFDM          1023
 578 #define CW_MIN_CCK           31
 579 #define CW_MAX_CCK           1023
 580
 581 #define QOS_TX0_CW_MIN_OFDM      CW_MIN_OFDM
 582 #define QOS_TX1_CW_MIN_OFDM      CW_MIN_OFDM
 583 #define QOS_TX2_CW_MIN_OFDM      ((CW_MIN_OFDM + 1) / 2 - 1)
 584 #define QOS_TX3_CW_MIN_OFDM      ((CW_MIN_OFDM + 1) / 4 - 1)
 585
 586 #define QOS_TX0_CW_MIN_CCK       CW_MIN_CCK
 587 #define QOS_TX1_CW_MIN_CCK       CW_MIN_CCK
 588 #define QOS_TX2_CW_MIN_CCK       ((CW_MIN_CCK + 1) / 2 - 1)
 589 #define QOS_TX3_CW_MIN_CCK       ((CW_MIN_CCK + 1) / 4 - 1)
 590
 591 #define QOS_TX0_CW_MAX_OFDM      CW_MAX_OFDM
 592 #define QOS_TX1_CW_MAX_OFDM      CW_MAX_OFDM
 593 #define QOS_TX2_CW_MAX_OFDM      CW_MIN_OFDM
 594 #define QOS_TX3_CW_MAX_OFDM      ((CW_MIN_OFDM + 1) / 2 - 1)
 595
 596 #define QOS_TX0_CW_MAX_CCK       CW_MAX_CCK
 597 #define QOS_TX1_CW_MAX_CCK       CW_MAX_CCK
 598 #define QOS_TX2_CW_MAX_CCK       CW_MIN_CCK
 599 #define QOS_TX3_CW_MAX_CCK       ((CW_MIN_CCK + 1) / 2 - 1)
 600
 601 #define QOS_TX0_AIFS            3
 602 #define QOS_TX1_AIFS            7
 603 #define QOS_TX2_AIFS            2
 604 #define QOS_TX3_AIFS            2
 605
 606 #define QOS_TX0_ACM             0
 607 #define QOS_TX1_ACM             0
 608 #define QOS_TX2_ACM             0
 609 #define QOS_TX3_ACM             0
 610
 611 #define QOS_TX0_TXOP_LIMIT_CCK          0
 612 #define QOS_TX1_TXOP_LIMIT_CCK          0
 613 #define QOS_TX2_TXOP_LIMIT_CCK          6016
 614 #define QOS_TX3_TXOP_LIMIT_CCK          3264
 615
 616 #define QOS_TX0_TXOP_LIMIT_OFDM      0
 617 #define QOS_TX1_TXOP_LIMIT_OFDM      0
 618 #define QOS_TX2_TXOP_LIMIT_OFDM      3008
 619 #define QOS_TX3_TXOP_LIMIT_OFDM      1504
 620
 621 #define DEF_TX0_CW_MIN_OFDM      CW_MIN_OFDM
 622 #define DEF_TX1_CW_MIN_OFDM      CW_MIN_OFDM
 623 #define DEF_TX2_CW_MIN_OFDM      CW_MIN_OFDM
 624 #define DEF_TX3_CW_MIN_OFDM      CW_MIN_OFDM
 625
 626 #define DEF_TX0_CW_MIN_CCK       CW_MIN_CCK
 627 #define DEF_TX1_CW_MIN_CCK       CW_MIN_CCK
 628 #define DEF_TX2_CW_MIN_CCK       CW_MIN_CCK
 629 #define DEF_TX3_CW_MIN_CCK       CW_MIN_CCK
 630
 631 #define DEF_TX0_CW_MAX_OFDM      CW_MAX_OFDM
 632 #define DEF_TX1_CW_MAX_OFDM      CW_MAX_OFDM
 633 #define DEF_TX2_CW_MAX_OFDM      CW_MAX_OFDM
 634 #define DEF_TX3_CW_MAX_OFDM      CW_MAX_OFDM
 635
 636 #define DEF_TX0_CW_MAX_CCK       CW_MAX_CCK
 637 #define DEF_TX1_CW_MAX_CCK       CW_MAX_CCK
 638 #define DEF_TX2_CW_MAX_CCK       CW_MAX_CCK
 639 #define DEF_TX3_CW_MAX_CCK       CW_MAX_CCK
 640
 641 #define DEF_TX0_AIFS            (2)
 642 #define DEF_TX1_AIFS            (2)
 643 #define DEF_TX2_AIFS            (2)
 644 #define DEF_TX3_AIFS            (2)
 645
 646 #define DEF_TX0_ACM             0
 647 #define DEF_TX1_ACM             0
 648 #define DEF_TX2_ACM             0
 649 #define DEF_TX3_ACM             0
 650
 651 #define DEF_TX0_TXOP_LIMIT_CCK        0
 652 #define DEF_TX1_TXOP_LIMIT_CCK        0
 653 #define DEF_TX2_TXOP_LIMIT_CCK        0
 654 #define DEF_TX3_TXOP_LIMIT_CCK        0
 655
 656 #define DEF_TX0_TXOP_LIMIT_OFDM       0
 657 #define DEF_TX1_TXOP_LIMIT_OFDM       0
 658 #define DEF_TX2_TXOP_LIMIT_OFDM       0
 659 #define DEF_TX3_TXOP_LIMIT_OFDM       0
 660
 661 #define QOS_QOS_SETS                  3
 662 #define QOS_PARAM_SET_ACTIVE          0
 663 #define QOS_PARAM_SET_DEF_CCK         1
 664 #define QOS_PARAM_SET_DEF_OFDM        2
 665
 666 #define CTRL_QOS_NO_ACK               (0x0020)
 667 #define DCT_FLAG_EXT_QOS_ENABLED      (0x10)
 668
 669 #define U32_PAD(n)              ((4-(n))&0x3)
 670
 671 /*
 672  * Generic queue structure
 673  *
 674  * Contains common data for Rx and Tx queues
 675  */
 676 #define TFD_CTL_COUNT_SET(n)       (n<<24)
 677 #define TFD_CTL_COUNT_GET(ctl)     ((ctl>>24) & 7)
 678 #define TFD_CTL_PAD_SET(n)         (n<<28)
 679 #define TFD_CTL_PAD_GET(ctl)       (ctl>>28)
 680
 681 #define TFD_TX_CMD_SLOTS 256
 682 #define TFD_CMD_SLOTS 32
 683
 684 #define TFD_MAX_PAYLOAD_SIZE (sizeof(struct iwl_cmd) - \
 685                               sizeof(struct iwl_cmd_meta))
 686
 687 /*
 688  * RX related structures and functions
 689  */
 690 #define RX_FREE_BUFFERS 64
 691 #define RX_LOW_WATERMARK 8
 692
 693
 694 #define IWL_RX_BUF_SIZE 3000
 695 /* card static random access memory (SRAM) for processor data and instructs */
 696 #define ALM_RTC_INST_UPPER_BOUND                (0x014000)
 697 #define ALM_RTC_DATA_UPPER_BOUND                (0x808000)
 698
 699 #define ALM_RTC_INST_SIZE (ALM_RTC_INST_UPPER_BOUND - RTC_INST_LOWER_BOUND)
 700 #define ALM_RTC_DATA_SIZE (ALM_RTC_DATA_UPPER_BOUND - RTC_DATA_LOWER_BOUND)
 701
 702 #define IWL_MAX_BSM_SIZE ALM_RTC_INST_SIZE
 703 #define IWL_MAX_INST_SIZE ALM_RTC_INST_SIZE
 704 #define IWL_MAX_DATA_SIZE ALM_RTC_DATA_SIZE
 705 #define IWL_MAX_NUM_QUEUES      8
 706
 707 static inline int iwl_hw_valid_rtc_data_addr(u32 addr)
 708 {
 709         return (addr >= RTC_DATA_LOWER_BOUND) &&
 710                (addr < ALM_RTC_DATA_UPPER_BOUND);
 711 }
 712
 713 /* Base physical address of iwl_shared is provided to FH_TSSR_CBB_BASE
 714  * and &iwl_shared.rx_read_ptr[0] is provided to FH_RCSR_RPTR_ADDR(0) */
 715 struct iwl_shared {
 716         __le32 tx_base_ptr[8];
 717         __le32 rx_read_ptr[3];
 718 } __attribute__ ((packed));
 719
 720 struct iwl_tfd_frame_data {
 721         __le32 addr;
 722         __le32 len;
 723 } __attribute__ ((packed));
 724
 725 struct iwl_tfd_frame {
 726         __le32 control_flags;
 727         struct iwl_tfd_frame_data pa[4];
 728         u8 reserved[28];
 729 } __attribute__ ((packed));
 730
 731 static inline u8 iwl_hw_get_rate(__le16 rate_n_flags)
 732 {
 733         return le16_to_cpu(rate_n_flags) & 0xFF;
 734 }
 735
 736 static inline u16 iwl_hw_get_rate_n_flags(__le16 rate_n_flags)
 737 {
 738         return le16_to_cpu(rate_n_flags);
 739 }
 740
 741 static inline __le16 iwl_hw_set_rate_n_flags(u8 rate, u16 flags)
 742 {
 743         return cpu_to_le16((u16)rate|flags);
 744 }
 745 #endif