2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright (C) 2008 Juergen Beisert
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the
16 * Free Software Foundation
17 * 51 Franklin Street, Fifth Floor
18 * Boston, MA 02110-1301, USA.
21 #include <linux/clk.h>
22 #include <linux/completion.h>
23 #include <linux/delay.h>
24 #include <linux/err.h>
25 #include <linux/gpio.h>
26 #include <linux/init.h>
27 #include <linux/interrupt.h>
29 #include <linux/irq.h>
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/platform_device.h>
33 #include <linux/slab.h>
34 #include <linux/spi/spi.h>
35 #include <linux/spi/spi_bitbang.h>
36 #include <linux/types.h>
40 #define DRIVER_NAME "spi_imx"
42 #define MXC_CSPIRXDATA 0x00
43 #define MXC_CSPITXDATA 0x04
44 #define MXC_CSPICTRL 0x08
45 #define MXC_CSPIINT 0x0c
46 #define MXC_RESET 0x1c
48 #define MX3_CSPISTAT 0x14
49 #define MX3_CSPISTAT_RR (1 << 3)
51 /* generic defines to abstract from the different register layouts */
52 #define MXC_INT_RR (1 << 0) /* Receive data ready interrupt */
53 #define MXC_INT_TE (1 << 1) /* Transmit FIFO empty interrupt */
55 struct spi_imx_config
{
56 unsigned int speed_hz
;
62 enum spi_imx_devtype
{
73 struct spi_imx_devtype_data
{
74 void (*intctrl
)(struct spi_imx_data
*, int);
75 int (*config
)(struct spi_imx_data
*, struct spi_imx_config
*);
76 void (*trigger
)(struct spi_imx_data
*);
77 int (*rx_available
)(struct spi_imx_data
*);
78 void (*reset
)(struct spi_imx_data
*);
79 unsigned int fifosize
;
83 struct spi_bitbang bitbang
;
85 struct completion xfer_done
;
89 unsigned long spi_clk
;
93 void (*tx
)(struct spi_imx_data
*);
94 void (*rx
)(struct spi_imx_data
*);
97 unsigned int txfifo
; /* number of words pushed in tx FIFO */
99 struct spi_imx_devtype_data devtype_data
;
102 #define MXC_SPI_BUF_RX(type) \
103 static void spi_imx_buf_rx_##type(struct spi_imx_data *spi_imx) \
105 unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA); \
107 if (spi_imx->rx_buf) { \
108 *(type *)spi_imx->rx_buf = val; \
109 spi_imx->rx_buf += sizeof(type); \
113 #define MXC_SPI_BUF_TX(type) \
114 static void spi_imx_buf_tx_##type(struct spi_imx_data *spi_imx) \
118 if (spi_imx->tx_buf) { \
119 val = *(type *)spi_imx->tx_buf; \
120 spi_imx->tx_buf += sizeof(type); \
123 spi_imx->count -= sizeof(type); \
125 writel(val, spi_imx->base + MXC_CSPITXDATA); \
135 /* First entry is reserved, second entry is valid only if SDHC_SPIEN is set
136 * (which is currently not the case in this driver)
138 static int mxc_clkdivs
[] = {0, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128, 192,
139 256, 384, 512, 768, 1024};
142 static unsigned int spi_imx_clkdiv_1(unsigned int fin
,
152 for (i
= 2; i
< max
; i
++)
153 if (fspi
* mxc_clkdivs
[i
] >= fin
)
159 /* MX1, MX31, MX35, MX51 CSPI */
160 static unsigned int spi_imx_clkdiv_2(unsigned int fin
,
165 for (i
= 0; i
< 7; i
++) {
166 if (fspi
* div
>= fin
)
174 #define SPI_IMX2_3_CTRL 0x08
175 #define SPI_IMX2_3_CTRL_ENABLE (1 << 0)
176 #define SPI_IMX2_3_CTRL_XCH (1 << 2)
177 #define SPI_IMX2_3_CTRL_MODE(cs) (1 << ((cs) + 4))
178 #define SPI_IMX2_3_CTRL_POSTDIV_OFFSET 8
179 #define SPI_IMX2_3_CTRL_PREDIV_OFFSET 12
180 #define SPI_IMX2_3_CTRL_CS(cs) ((cs) << 18)
181 #define SPI_IMX2_3_CTRL_BL_OFFSET 20
183 #define SPI_IMX2_3_CONFIG 0x0c
184 #define SPI_IMX2_3_CONFIG_SCLKPHA(cs) (1 << ((cs) + 0))
185 #define SPI_IMX2_3_CONFIG_SCLKPOL(cs) (1 << ((cs) + 4))
186 #define SPI_IMX2_3_CONFIG_SBBCTRL(cs) (1 << ((cs) + 8))
187 #define SPI_IMX2_3_CONFIG_SSBPOL(cs) (1 << ((cs) + 12))
189 #define SPI_IMX2_3_INT 0x10
190 #define SPI_IMX2_3_INT_TEEN (1 << 0)
191 #define SPI_IMX2_3_INT_RREN (1 << 3)
193 #define SPI_IMX2_3_STAT 0x18
194 #define SPI_IMX2_3_STAT_RR (1 << 3)
197 static unsigned int spi_imx2_3_clkdiv(unsigned int fin
, unsigned int fspi
)
200 * there are two 4-bit dividers, the pre-divider divides by
201 * $pre, the post-divider by 2^$post
203 unsigned int pre
, post
;
205 if (unlikely(fspi
> fin
))
208 post
= fls(fin
) - fls(fspi
);
209 if (fin
> fspi
<< post
)
212 /* now we have: (fin <= fspi << post) with post being minimal */
214 post
= max(4U, post
) - 4;
215 if (unlikely(post
> 0xf)) {
216 pr_err("%s: cannot set clock freq: %u (base freq: %u)\n",
217 __func__
, fspi
, fin
);
221 pre
= DIV_ROUND_UP(fin
, fspi
<< post
) - 1;
223 pr_debug("%s: fin: %u, fspi: %u, post: %u, pre: %u\n",
224 __func__
, fin
, fspi
, post
, pre
);
225 return (pre
<< SPI_IMX2_3_CTRL_PREDIV_OFFSET
) |
226 (post
<< SPI_IMX2_3_CTRL_POSTDIV_OFFSET
);
229 static void __maybe_unused
spi_imx2_3_intctrl(struct spi_imx_data
*spi_imx
, int enable
)
233 if (enable
& MXC_INT_TE
)
234 val
|= SPI_IMX2_3_INT_TEEN
;
236 if (enable
& MXC_INT_RR
)
237 val
|= SPI_IMX2_3_INT_RREN
;
239 writel(val
, spi_imx
->base
+ SPI_IMX2_3_INT
);
242 static void __maybe_unused
spi_imx2_3_trigger(struct spi_imx_data
*spi_imx
)
246 reg
= readl(spi_imx
->base
+ SPI_IMX2_3_CTRL
);
247 reg
|= SPI_IMX2_3_CTRL_XCH
;
248 writel(reg
, spi_imx
->base
+ SPI_IMX2_3_CTRL
);
251 static int __maybe_unused
spi_imx2_3_config(struct spi_imx_data
*spi_imx
,
252 struct spi_imx_config
*config
)
254 u32 ctrl
= SPI_IMX2_3_CTRL_ENABLE
, cfg
= 0;
256 /* set master mode */
257 ctrl
|= SPI_IMX2_3_CTRL_MODE(config
->cs
);
259 /* set clock speed */
260 ctrl
|= spi_imx2_3_clkdiv(spi_imx
->spi_clk
, config
->speed_hz
);
262 /* set chip select to use */
263 ctrl
|= SPI_IMX2_3_CTRL_CS(config
->cs
);
265 ctrl
|= (config
->bpw
- 1) << SPI_IMX2_3_CTRL_BL_OFFSET
;
267 cfg
|= SPI_IMX2_3_CONFIG_SBBCTRL(config
->cs
);
269 if (config
->mode
& SPI_CPHA
)
270 cfg
|= SPI_IMX2_3_CONFIG_SCLKPHA(config
->cs
);
272 if (config
->mode
& SPI_CPOL
)
273 cfg
|= SPI_IMX2_3_CONFIG_SCLKPOL(config
->cs
);
275 if (config
->mode
& SPI_CS_HIGH
)
276 cfg
|= SPI_IMX2_3_CONFIG_SSBPOL(config
->cs
);
278 writel(ctrl
, spi_imx
->base
+ SPI_IMX2_3_CTRL
);
279 writel(cfg
, spi_imx
->base
+ SPI_IMX2_3_CONFIG
);
284 static int __maybe_unused
spi_imx2_3_rx_available(struct spi_imx_data
*spi_imx
)
286 return readl(spi_imx
->base
+ SPI_IMX2_3_STAT
) & SPI_IMX2_3_STAT_RR
;
289 static void __maybe_unused
spi_imx2_3_reset(struct spi_imx_data
*spi_imx
)
291 /* drain receive buffer */
292 while (spi_imx2_3_rx_available(spi_imx
))
293 readl(spi_imx
->base
+ MXC_CSPIRXDATA
);
296 #define MX31_INTREG_TEEN (1 << 0)
297 #define MX31_INTREG_RREN (1 << 3)
299 #define MX31_CSPICTRL_ENABLE (1 << 0)
300 #define MX31_CSPICTRL_MASTER (1 << 1)
301 #define MX31_CSPICTRL_XCH (1 << 2)
302 #define MX31_CSPICTRL_POL (1 << 4)
303 #define MX31_CSPICTRL_PHA (1 << 5)
304 #define MX31_CSPICTRL_SSCTL (1 << 6)
305 #define MX31_CSPICTRL_SSPOL (1 << 7)
306 #define MX31_CSPICTRL_BC_SHIFT 8
307 #define MX35_CSPICTRL_BL_SHIFT 20
308 #define MX31_CSPICTRL_CS_SHIFT 24
309 #define MX35_CSPICTRL_CS_SHIFT 12
310 #define MX31_CSPICTRL_DR_SHIFT 16
312 #define MX31_CSPISTATUS 0x14
313 #define MX31_STATUS_RR (1 << 3)
315 /* These functions also work for the i.MX35, but be aware that
316 * the i.MX35 has a slightly different register layout for bits
317 * we do not use here.
319 static void __maybe_unused
mx31_intctrl(struct spi_imx_data
*spi_imx
, int enable
)
321 unsigned int val
= 0;
323 if (enable
& MXC_INT_TE
)
324 val
|= MX31_INTREG_TEEN
;
325 if (enable
& MXC_INT_RR
)
326 val
|= MX31_INTREG_RREN
;
328 writel(val
, spi_imx
->base
+ MXC_CSPIINT
);
331 static void __maybe_unused
mx31_trigger(struct spi_imx_data
*spi_imx
)
335 reg
= readl(spi_imx
->base
+ MXC_CSPICTRL
);
336 reg
|= MX31_CSPICTRL_XCH
;
337 writel(reg
, spi_imx
->base
+ MXC_CSPICTRL
);
340 static int __maybe_unused
spi_imx0_4_config(struct spi_imx_data
*spi_imx
,
341 struct spi_imx_config
*config
)
343 unsigned int reg
= MX31_CSPICTRL_ENABLE
| MX31_CSPICTRL_MASTER
;
344 int cs
= spi_imx
->chipselect
[config
->cs
];
346 reg
|= spi_imx_clkdiv_2(spi_imx
->spi_clk
, config
->speed_hz
) <<
347 MX31_CSPICTRL_DR_SHIFT
;
349 reg
|= (config
->bpw
- 1) << MX31_CSPICTRL_BC_SHIFT
;
351 if (config
->mode
& SPI_CPHA
)
352 reg
|= MX31_CSPICTRL_PHA
;
353 if (config
->mode
& SPI_CPOL
)
354 reg
|= MX31_CSPICTRL_POL
;
355 if (config
->mode
& SPI_CS_HIGH
)
356 reg
|= MX31_CSPICTRL_SSPOL
;
358 reg
|= (cs
+ 32) << MX31_CSPICTRL_CS_SHIFT
;
360 writel(reg
, spi_imx
->base
+ MXC_CSPICTRL
);
365 static int __maybe_unused
spi_imx0_7_config(struct spi_imx_data
*spi_imx
,
366 struct spi_imx_config
*config
)
368 unsigned int reg
= MX31_CSPICTRL_ENABLE
| MX31_CSPICTRL_MASTER
;
369 int cs
= spi_imx
->chipselect
[config
->cs
];
371 reg
|= spi_imx_clkdiv_2(spi_imx
->spi_clk
, config
->speed_hz
) <<
372 MX31_CSPICTRL_DR_SHIFT
;
374 reg
|= (config
->bpw
- 1) << MX35_CSPICTRL_BL_SHIFT
;
375 reg
|= MX31_CSPICTRL_SSCTL
;
377 if (config
->mode
& SPI_CPHA
)
378 reg
|= MX31_CSPICTRL_PHA
;
379 if (config
->mode
& SPI_CPOL
)
380 reg
|= MX31_CSPICTRL_POL
;
381 if (config
->mode
& SPI_CS_HIGH
)
382 reg
|= MX31_CSPICTRL_SSPOL
;
384 reg
|= (cs
+ 32) << MX35_CSPICTRL_CS_SHIFT
;
386 writel(reg
, spi_imx
->base
+ MXC_CSPICTRL
);
391 static int __maybe_unused
mx31_rx_available(struct spi_imx_data
*spi_imx
)
393 return readl(spi_imx
->base
+ MX31_CSPISTATUS
) & MX31_STATUS_RR
;
396 static void __maybe_unused
spi_imx0_4_reset(struct spi_imx_data
*spi_imx
)
398 /* drain receive buffer */
399 while (readl(spi_imx
->base
+ MX3_CSPISTAT
) & MX3_CSPISTAT_RR
)
400 readl(spi_imx
->base
+ MXC_CSPIRXDATA
);
403 #define MX27_INTREG_RR (1 << 4)
404 #define MX27_INTREG_TEEN (1 << 9)
405 #define MX27_INTREG_RREN (1 << 13)
407 #define MX27_CSPICTRL_POL (1 << 5)
408 #define MX27_CSPICTRL_PHA (1 << 6)
409 #define MX27_CSPICTRL_SSPOL (1 << 8)
410 #define MX27_CSPICTRL_XCH (1 << 9)
411 #define MX27_CSPICTRL_ENABLE (1 << 10)
412 #define MX27_CSPICTRL_MASTER (1 << 11)
413 #define MX27_CSPICTRL_DR_SHIFT 14
414 #define MX27_CSPICTRL_CS_SHIFT 19
416 static void __maybe_unused
mx27_intctrl(struct spi_imx_data
*spi_imx
, int enable
)
418 unsigned int val
= 0;
420 if (enable
& MXC_INT_TE
)
421 val
|= MX27_INTREG_TEEN
;
422 if (enable
& MXC_INT_RR
)
423 val
|= MX27_INTREG_RREN
;
425 writel(val
, spi_imx
->base
+ MXC_CSPIINT
);
428 static void __maybe_unused
mx27_trigger(struct spi_imx_data
*spi_imx
)
432 reg
= readl(spi_imx
->base
+ MXC_CSPICTRL
);
433 reg
|= MX27_CSPICTRL_XCH
;
434 writel(reg
, spi_imx
->base
+ MXC_CSPICTRL
);
437 static int __maybe_unused
mx27_config(struct spi_imx_data
*spi_imx
,
438 struct spi_imx_config
*config
)
440 unsigned int reg
= MX27_CSPICTRL_ENABLE
| MX27_CSPICTRL_MASTER
;
441 int cs
= spi_imx
->chipselect
[config
->cs
];
443 reg
|= spi_imx_clkdiv_1(spi_imx
->spi_clk
, config
->speed_hz
) <<
444 MX27_CSPICTRL_DR_SHIFT
;
445 reg
|= config
->bpw
- 1;
447 if (config
->mode
& SPI_CPHA
)
448 reg
|= MX27_CSPICTRL_PHA
;
449 if (config
->mode
& SPI_CPOL
)
450 reg
|= MX27_CSPICTRL_POL
;
451 if (config
->mode
& SPI_CS_HIGH
)
452 reg
|= MX27_CSPICTRL_SSPOL
;
454 reg
|= (cs
+ 32) << MX27_CSPICTRL_CS_SHIFT
;
456 writel(reg
, spi_imx
->base
+ MXC_CSPICTRL
);
461 static int __maybe_unused
mx27_rx_available(struct spi_imx_data
*spi_imx
)
463 return readl(spi_imx
->base
+ MXC_CSPIINT
) & MX27_INTREG_RR
;
466 static void __maybe_unused
spi_imx0_0_reset(struct spi_imx_data
*spi_imx
)
468 writel(1, spi_imx
->base
+ MXC_RESET
);
471 #define MX1_INTREG_RR (1 << 3)
472 #define MX1_INTREG_TEEN (1 << 8)
473 #define MX1_INTREG_RREN (1 << 11)
475 #define MX1_CSPICTRL_POL (1 << 4)
476 #define MX1_CSPICTRL_PHA (1 << 5)
477 #define MX1_CSPICTRL_XCH (1 << 8)
478 #define MX1_CSPICTRL_ENABLE (1 << 9)
479 #define MX1_CSPICTRL_MASTER (1 << 10)
480 #define MX1_CSPICTRL_DR_SHIFT 13
482 static void __maybe_unused
mx1_intctrl(struct spi_imx_data
*spi_imx
, int enable
)
484 unsigned int val
= 0;
486 if (enable
& MXC_INT_TE
)
487 val
|= MX1_INTREG_TEEN
;
488 if (enable
& MXC_INT_RR
)
489 val
|= MX1_INTREG_RREN
;
491 writel(val
, spi_imx
->base
+ MXC_CSPIINT
);
494 static void __maybe_unused
mx1_trigger(struct spi_imx_data
*spi_imx
)
498 reg
= readl(spi_imx
->base
+ MXC_CSPICTRL
);
499 reg
|= MX1_CSPICTRL_XCH
;
500 writel(reg
, spi_imx
->base
+ MXC_CSPICTRL
);
503 static int __maybe_unused
mx1_config(struct spi_imx_data
*spi_imx
,
504 struct spi_imx_config
*config
)
506 unsigned int reg
= MX1_CSPICTRL_ENABLE
| MX1_CSPICTRL_MASTER
;
508 reg
|= spi_imx_clkdiv_2(spi_imx
->spi_clk
, config
->speed_hz
) <<
509 MX1_CSPICTRL_DR_SHIFT
;
510 reg
|= config
->bpw
- 1;
512 if (config
->mode
& SPI_CPHA
)
513 reg
|= MX1_CSPICTRL_PHA
;
514 if (config
->mode
& SPI_CPOL
)
515 reg
|= MX1_CSPICTRL_POL
;
517 writel(reg
, spi_imx
->base
+ MXC_CSPICTRL
);
522 static int __maybe_unused
mx1_rx_available(struct spi_imx_data
*spi_imx
)
524 return readl(spi_imx
->base
+ MXC_CSPIINT
) & MX1_INTREG_RR
;
527 static void __maybe_unused
mx1_reset(struct spi_imx_data
*spi_imx
)
529 writel(1, spi_imx
->base
+ MXC_RESET
);
533 * These version numbers are taken from the Freescale driver. Unfortunately it
534 * doesn't support i.MX1, so this entry doesn't match the scheme. :-(
536 static struct spi_imx_devtype_data spi_imx_devtype_data
[] __devinitdata
= {
537 #ifdef CONFIG_SPI_IMX_VER_IMX1
538 [SPI_IMX_VER_IMX1
] = {
539 .intctrl
= mx1_intctrl
,
540 .config
= mx1_config
,
541 .trigger
= mx1_trigger
,
542 .rx_available
= mx1_rx_available
,
547 #ifdef CONFIG_SPI_IMX_VER_0_0
548 [SPI_IMX_VER_0_0
] = {
549 .intctrl
= mx27_intctrl
,
550 .config
= mx27_config
,
551 .trigger
= mx27_trigger
,
552 .rx_available
= mx27_rx_available
,
553 .reset
= spi_imx0_0_reset
,
557 #ifdef CONFIG_SPI_IMX_VER_0_4
558 [SPI_IMX_VER_0_4
] = {
559 .intctrl
= mx31_intctrl
,
560 .config
= spi_imx0_4_config
,
561 .trigger
= mx31_trigger
,
562 .rx_available
= mx31_rx_available
,
563 .reset
= spi_imx0_4_reset
,
567 #ifdef CONFIG_SPI_IMX_VER_0_7
568 [SPI_IMX_VER_0_7
] = {
569 .intctrl
= mx31_intctrl
,
570 .config
= spi_imx0_7_config
,
571 .trigger
= mx31_trigger
,
572 .rx_available
= mx31_rx_available
,
573 .reset
= spi_imx0_4_reset
,
577 #ifdef CONFIG_SPI_IMX_VER_2_3
578 [SPI_IMX_VER_2_3
] = {
579 .intctrl
= spi_imx2_3_intctrl
,
580 .config
= spi_imx2_3_config
,
581 .trigger
= spi_imx2_3_trigger
,
582 .rx_available
= spi_imx2_3_rx_available
,
583 .reset
= spi_imx2_3_reset
,
589 static void spi_imx_chipselect(struct spi_device
*spi
, int is_active
)
591 struct spi_imx_data
*spi_imx
= spi_master_get_devdata(spi
->master
);
592 int gpio
= spi_imx
->chipselect
[spi
->chip_select
];
593 int active
= is_active
!= BITBANG_CS_INACTIVE
;
594 int dev_is_lowactive
= !(spi
->mode
& SPI_CS_HIGH
);
599 gpio_set_value(gpio
, dev_is_lowactive
^ active
);
602 static void spi_imx_push(struct spi_imx_data
*spi_imx
)
604 while (spi_imx
->txfifo
< spi_imx
->devtype_data
.fifosize
) {
607 spi_imx
->tx(spi_imx
);
611 spi_imx
->devtype_data
.trigger(spi_imx
);
614 static irqreturn_t
spi_imx_isr(int irq
, void *dev_id
)
616 struct spi_imx_data
*spi_imx
= dev_id
;
618 while (spi_imx
->devtype_data
.rx_available(spi_imx
)) {
619 spi_imx
->rx(spi_imx
);
623 if (spi_imx
->count
) {
624 spi_imx_push(spi_imx
);
628 if (spi_imx
->txfifo
) {
629 /* No data left to push, but still waiting for rx data,
630 * enable receive data available interrupt.
632 spi_imx
->devtype_data
.intctrl(
633 spi_imx
, MXC_INT_RR
);
637 spi_imx
->devtype_data
.intctrl(spi_imx
, 0);
638 complete(&spi_imx
->xfer_done
);
643 static int spi_imx_setupxfer(struct spi_device
*spi
,
644 struct spi_transfer
*t
)
646 struct spi_imx_data
*spi_imx
= spi_master_get_devdata(spi
->master
);
647 struct spi_imx_config config
;
649 config
.bpw
= t
? t
->bits_per_word
: spi
->bits_per_word
;
650 config
.speed_hz
= t
? t
->speed_hz
: spi
->max_speed_hz
;
651 config
.mode
= spi
->mode
;
652 config
.cs
= spi
->chip_select
;
654 if (!config
.speed_hz
)
655 config
.speed_hz
= spi
->max_speed_hz
;
657 config
.bpw
= spi
->bits_per_word
;
658 if (!config
.speed_hz
)
659 config
.speed_hz
= spi
->max_speed_hz
;
661 /* Initialize the functions for transfer */
662 if (config
.bpw
<= 8) {
663 spi_imx
->rx
= spi_imx_buf_rx_u8
;
664 spi_imx
->tx
= spi_imx_buf_tx_u8
;
665 } else if (config
.bpw
<= 16) {
666 spi_imx
->rx
= spi_imx_buf_rx_u16
;
667 spi_imx
->tx
= spi_imx_buf_tx_u16
;
668 } else if (config
.bpw
<= 32) {
669 spi_imx
->rx
= spi_imx_buf_rx_u32
;
670 spi_imx
->tx
= spi_imx_buf_tx_u32
;
674 spi_imx
->devtype_data
.config(spi_imx
, &config
);
679 static int spi_imx_transfer(struct spi_device
*spi
,
680 struct spi_transfer
*transfer
)
682 struct spi_imx_data
*spi_imx
= spi_master_get_devdata(spi
->master
);
684 spi_imx
->tx_buf
= transfer
->tx_buf
;
685 spi_imx
->rx_buf
= transfer
->rx_buf
;
686 spi_imx
->count
= transfer
->len
;
689 init_completion(&spi_imx
->xfer_done
);
691 spi_imx_push(spi_imx
);
693 spi_imx
->devtype_data
.intctrl(spi_imx
, MXC_INT_TE
);
695 wait_for_completion(&spi_imx
->xfer_done
);
697 return transfer
->len
;
700 static int spi_imx_setup(struct spi_device
*spi
)
702 struct spi_imx_data
*spi_imx
= spi_master_get_devdata(spi
->master
);
703 int gpio
= spi_imx
->chipselect
[spi
->chip_select
];
705 dev_dbg(&spi
->dev
, "%s: mode %d, %u bpw, %d hz\n", __func__
,
706 spi
->mode
, spi
->bits_per_word
, spi
->max_speed_hz
);
709 gpio_direction_output(gpio
, spi
->mode
& SPI_CS_HIGH
? 0 : 1);
711 spi_imx_chipselect(spi
, BITBANG_CS_INACTIVE
);
716 static void spi_imx_cleanup(struct spi_device
*spi
)
720 static struct platform_device_id spi_imx_devtype
[] = {
723 .driver_data
= SPI_IMX_VER_IMX1
,
725 .name
= "imx21-cspi",
726 .driver_data
= SPI_IMX_VER_0_0
,
728 .name
= "imx25-cspi",
729 .driver_data
= SPI_IMX_VER_0_7
,
731 .name
= "imx27-cspi",
732 .driver_data
= SPI_IMX_VER_0_0
,
734 .name
= "imx31-cspi",
735 .driver_data
= SPI_IMX_VER_0_4
,
737 .name
= "imx35-cspi",
738 .driver_data
= SPI_IMX_VER_0_7
,
740 .name
= "imx51-cspi",
741 .driver_data
= SPI_IMX_VER_0_7
,
743 .name
= "imx51-ecspi",
744 .driver_data
= SPI_IMX_VER_2_3
,
746 .name
= "imx53-cspi",
747 .driver_data
= SPI_IMX_VER_0_7
,
749 .name
= "imx53-ecspi",
750 .driver_data
= SPI_IMX_VER_2_3
,
756 static int __devinit
spi_imx_probe(struct platform_device
*pdev
)
758 struct spi_imx_master
*mxc_platform_info
;
759 struct spi_master
*master
;
760 struct spi_imx_data
*spi_imx
;
761 struct resource
*res
;
764 mxc_platform_info
= dev_get_platdata(&pdev
->dev
);
765 if (!mxc_platform_info
) {
766 dev_err(&pdev
->dev
, "can't get the platform data\n");
770 master
= spi_alloc_master(&pdev
->dev
, sizeof(struct spi_imx_data
));
774 platform_set_drvdata(pdev
, master
);
776 master
->bus_num
= pdev
->id
;
777 master
->num_chipselect
= mxc_platform_info
->num_chipselect
;
779 spi_imx
= spi_master_get_devdata(master
);
780 spi_imx
->bitbang
.master
= spi_master_get(master
);
781 spi_imx
->chipselect
= mxc_platform_info
->chipselect
;
783 for (i
= 0; i
< master
->num_chipselect
; i
++) {
784 if (spi_imx
->chipselect
[i
] < 0)
786 ret
= gpio_request(spi_imx
->chipselect
[i
], DRIVER_NAME
);
790 if (spi_imx
->chipselect
[i
] >= 0)
791 gpio_free(spi_imx
->chipselect
[i
]);
793 dev_err(&pdev
->dev
, "can't get cs gpios\n");
798 spi_imx
->bitbang
.chipselect
= spi_imx_chipselect
;
799 spi_imx
->bitbang
.setup_transfer
= spi_imx_setupxfer
;
800 spi_imx
->bitbang
.txrx_bufs
= spi_imx_transfer
;
801 spi_imx
->bitbang
.master
->setup
= spi_imx_setup
;
802 spi_imx
->bitbang
.master
->cleanup
= spi_imx_cleanup
;
803 spi_imx
->bitbang
.master
->mode_bits
= SPI_CPOL
| SPI_CPHA
| SPI_CS_HIGH
;
805 init_completion(&spi_imx
->xfer_done
);
807 spi_imx
->devtype_data
=
808 spi_imx_devtype_data
[pdev
->id_entry
->driver_data
];
810 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
812 dev_err(&pdev
->dev
, "can't get platform resource\n");
817 if (!request_mem_region(res
->start
, resource_size(res
), pdev
->name
)) {
818 dev_err(&pdev
->dev
, "request_mem_region failed\n");
823 spi_imx
->base
= ioremap(res
->start
, resource_size(res
));
824 if (!spi_imx
->base
) {
826 goto out_release_mem
;
829 spi_imx
->irq
= platform_get_irq(pdev
, 0);
830 if (spi_imx
->irq
< 0) {
835 ret
= request_irq(spi_imx
->irq
, spi_imx_isr
, 0, DRIVER_NAME
, spi_imx
);
837 dev_err(&pdev
->dev
, "can't get irq%d: %d\n", spi_imx
->irq
, ret
);
841 spi_imx
->clk
= clk_get(&pdev
->dev
, NULL
);
842 if (IS_ERR(spi_imx
->clk
)) {
843 dev_err(&pdev
->dev
, "unable to get clock\n");
844 ret
= PTR_ERR(spi_imx
->clk
);
848 clk_enable(spi_imx
->clk
);
849 spi_imx
->spi_clk
= clk_get_rate(spi_imx
->clk
);
851 spi_imx
->devtype_data
.reset(spi_imx
);
853 spi_imx
->devtype_data
.intctrl(spi_imx
, 0);
855 ret
= spi_bitbang_start(&spi_imx
->bitbang
);
857 dev_err(&pdev
->dev
, "bitbang start failed with %d\n", ret
);
861 dev_info(&pdev
->dev
, "probed\n");
866 clk_disable(spi_imx
->clk
);
867 clk_put(spi_imx
->clk
);
869 free_irq(spi_imx
->irq
, spi_imx
);
871 iounmap(spi_imx
->base
);
873 release_mem_region(res
->start
, resource_size(res
));
875 for (i
= 0; i
< master
->num_chipselect
; i
++)
876 if (spi_imx
->chipselect
[i
] >= 0)
877 gpio_free(spi_imx
->chipselect
[i
]);
879 spi_master_put(master
);
881 platform_set_drvdata(pdev
, NULL
);
885 static int __devexit
spi_imx_remove(struct platform_device
*pdev
)
887 struct spi_master
*master
= platform_get_drvdata(pdev
);
888 struct resource
*res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
889 struct spi_imx_data
*spi_imx
= spi_master_get_devdata(master
);
892 spi_bitbang_stop(&spi_imx
->bitbang
);
894 writel(0, spi_imx
->base
+ MXC_CSPICTRL
);
895 clk_disable(spi_imx
->clk
);
896 clk_put(spi_imx
->clk
);
897 free_irq(spi_imx
->irq
, spi_imx
);
898 iounmap(spi_imx
->base
);
900 for (i
= 0; i
< master
->num_chipselect
; i
++)
901 if (spi_imx
->chipselect
[i
] >= 0)
902 gpio_free(spi_imx
->chipselect
[i
]);
904 spi_master_put(master
);
906 release_mem_region(res
->start
, resource_size(res
));
908 platform_set_drvdata(pdev
, NULL
);
913 static struct platform_driver spi_imx_driver
= {
916 .owner
= THIS_MODULE
,
918 .id_table
= spi_imx_devtype
,
919 .probe
= spi_imx_probe
,
920 .remove
= __devexit_p(spi_imx_remove
),
923 static int __init
spi_imx_init(void)
925 return platform_driver_register(&spi_imx_driver
);
928 static void __exit
spi_imx_exit(void)
930 platform_driver_unregister(&spi_imx_driver
);
933 module_init(spi_imx_init
);
934 module_exit(spi_imx_exit
);
936 MODULE_DESCRIPTION("SPI Master Controller driver");
937 MODULE_AUTHOR("Sascha Hauer, Pengutronix");
938 MODULE_LICENSE("GPL");