arch/arm/mach-tegra/irq.c

   1 /*
   2  * Copyright (C) 2011 Google, Inc.
   3  *
   4  * Author:
   5  *      Colin Cross <ccross@android.com>
   6  *
   7  * Copyright (C) 2010, NVIDIA Corporation
   8  *
   9  * This software is licensed under the terms of the GNU General Public
  10  * License version 2, as published by the Free Software Foundation, and
  11  * may be copied, distributed, and modified under those terms.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  */
  19
  20 #include <linux/kernel.h>
  21 #include <linux/delay.h>
  22 #include <linux/init.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/irq.h>
  25 #include <linux/io.h>
  26
  27 #include <asm/hardware/gic.h>
  28
  29 #include <mach/iomap.h>
  30 #include <mach/legacy_irq.h>
  31 #include <mach/suspend.h>
  32
  33 #include "board.h"
  34
  35 #define PMC_CTRL                0x0
  36 #define PMC_CTRL_LATCH_WAKEUPS  (1 << 5)
  37 #define PMC_WAKE_MASK           0xc
  38 #define PMC_WAKE_LEVEL          0x10
  39 #define PMC_WAKE_STATUS         0x14
  40 #define PMC_SW_WAKE_STATUS      0x18
  41 #define PMC_DPD_SAMPLE          0x20
  42
  43 static void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
  44
  45 static u32 tegra_lp0_wake_enb;
  46 static u32 tegra_lp0_wake_level;
  47 static u32 tegra_lp0_wake_level_any;
  48
  49 /* ensures that sufficient time is passed for a register write to
  50  * serialize into the 32KHz domain */
  51 static void pmc_32kwritel(u32 val, unsigned long offs)
  52 {
  53         writel(val, pmc + offs);
  54         udelay(130);
  55 }
  56
  57 int tegra_set_lp1_wake(int irq, int enable)
  58 {
  59         return tegra_legacy_irq_set_wake(irq, enable);
  60 }
  61
  62 void tegra_set_lp0_wake_pads(u32 wake_enb, u32 wake_level, u32 wake_any)
  63 {
  64         u32 temp;
  65         u32 status;
  66         u32 lvl;
  67
  68         wake_level &= wake_enb;
  69         wake_any &= wake_enb;
  70
  71         wake_level |= (tegra_lp0_wake_level & tegra_lp0_wake_enb);
  72         wake_any |= (tegra_lp0_wake_level_any & tegra_lp0_wake_enb);
  73
  74         wake_enb |= tegra_lp0_wake_enb;
  75
  76         pmc_32kwritel(0, PMC_SW_WAKE_STATUS);
  77         temp = readl(pmc + PMC_CTRL);
  78         temp |= PMC_CTRL_LATCH_WAKEUPS;
  79         pmc_32kwritel(temp, PMC_CTRL);
  80         temp &= ~PMC_CTRL_LATCH_WAKEUPS;
  81         pmc_32kwritel(temp, PMC_CTRL);
  82         status = readl(pmc + PMC_SW_WAKE_STATUS);
  83         lvl = readl(pmc + PMC_WAKE_LEVEL);
  84
  85         /* flip the wakeup trigger for any-edge triggered pads
  86          * which are currently asserting as wakeups */
  87         lvl ^= status;
  88         lvl &= wake_any;
  89
  90         wake_level |= lvl;
  91
  92         writel(wake_level, pmc + PMC_WAKE_LEVEL);
  93         /* Enable DPD sample to trigger sampling pads data and direction
  94          * in which pad will be driven during lp0 mode*/
  95         writel(0x1, pmc + PMC_DPD_SAMPLE);
  96
  97         writel(wake_enb, pmc + PMC_WAKE_MASK);
  98 }
  99
 100 static void tegra_mask(struct irq_data *d)
 101 {
 102         if (d->irq >= 32)
 103                 tegra_legacy_mask_irq(d->irq);
 104 }
 105
 106 static void tegra_unmask(struct irq_data *d)
 107 {
 108         if (d->irq >= 32)
 109                 tegra_legacy_unmask_irq(d->irq);
 110 }
 111
 112 static void tegra_ack(struct irq_data *d)
 113 {
 114         if (d->irq >= 32)
 115                 tegra_legacy_force_irq_clr(d->irq);
 116 }
 117
 118 static int tegra_retrigger(struct irq_data *d)
 119 {
 120         if (d->irq < 32)
 121                 return 0;
 122
 123         tegra_legacy_force_irq_set(d->irq);
 124         return 1;
 125 }
 126
 127 void __init tegra_init_irq(void)
 128 {
 129         tegra_init_legacy_irq();
 130
 131         gic_arch_extn.irq_ack = tegra_ack;
 132         gic_arch_extn.irq_mask = tegra_mask;
 133         gic_arch_extn.irq_unmask = tegra_unmask;
 134         gic_arch_extn.irq_retrigger = tegra_retrigger;
 135
 136         gic_init(0, 29, IO_ADDRESS(TEGRA_ARM_INT_DIST_BASE),
 137                  IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x100));
 138 }