2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
32 #include "i915_trace.h"
33 #include "intel_drv.h"
34 #include <linux/slab.h>
35 #include <linux/swap.h>
36 #include <linux/pci.h>
37 #include <linux/intel-gtt.h>
39 static uint32_t i915_gem_get_gtt_alignment(struct drm_gem_object
*obj
);
41 static int i915_gem_object_flush_gpu_write_domain(struct drm_gem_object
*obj
,
43 static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object
*obj
);
44 static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object
*obj
);
45 static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object
*obj
,
47 static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object
*obj
,
50 static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object
*obj
);
51 static int i915_gem_object_wait_rendering(struct drm_gem_object
*obj
,
53 static int i915_gem_object_bind_to_gtt(struct drm_gem_object
*obj
,
55 static void i915_gem_clear_fence_reg(struct drm_gem_object
*obj
);
56 static int i915_gem_phys_pwrite(struct drm_device
*dev
, struct drm_gem_object
*obj
,
57 struct drm_i915_gem_pwrite
*args
,
58 struct drm_file
*file_priv
);
59 static void i915_gem_free_object_tail(struct drm_gem_object
*obj
);
61 static LIST_HEAD(shrink_list
);
62 static DEFINE_SPINLOCK(shrink_list_lock
);
65 i915_gem_object_is_inactive(struct drm_i915_gem_object
*obj_priv
)
67 return obj_priv
->gtt_space
&&
69 obj_priv
->pin_count
== 0;
72 int i915_gem_do_init(struct drm_device
*dev
, unsigned long start
,
75 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
78 (start
& (PAGE_SIZE
- 1)) != 0 ||
79 (end
& (PAGE_SIZE
- 1)) != 0) {
83 drm_mm_init(&dev_priv
->mm
.gtt_space
, start
,
86 dev
->gtt_total
= (uint32_t) (end
- start
);
92 i915_gem_init_ioctl(struct drm_device
*dev
, void *data
,
93 struct drm_file
*file_priv
)
95 struct drm_i915_gem_init
*args
= data
;
98 mutex_lock(&dev
->struct_mutex
);
99 ret
= i915_gem_do_init(dev
, args
->gtt_start
, args
->gtt_end
);
100 mutex_unlock(&dev
->struct_mutex
);
106 i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
107 struct drm_file
*file_priv
)
109 struct drm_i915_gem_get_aperture
*args
= data
;
111 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
114 args
->aper_size
= dev
->gtt_total
;
115 args
->aper_available_size
= (args
->aper_size
-
116 atomic_read(&dev
->pin_memory
));
123 * Creates a new mm object and returns a handle to it.
126 i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
127 struct drm_file
*file_priv
)
129 struct drm_i915_gem_create
*args
= data
;
130 struct drm_gem_object
*obj
;
134 args
->size
= roundup(args
->size
, PAGE_SIZE
);
136 /* Allocate the new object */
137 obj
= i915_gem_alloc_object(dev
, args
->size
);
141 ret
= drm_gem_handle_create(file_priv
, obj
, &handle
);
143 drm_gem_object_unreference_unlocked(obj
);
147 /* Sink the floating reference from kref_init(handlecount) */
148 drm_gem_object_handle_unreference_unlocked(obj
);
150 args
->handle
= handle
;
155 fast_shmem_read(struct page
**pages
,
156 loff_t page_base
, int page_offset
,
163 vaddr
= kmap_atomic(pages
[page_base
>> PAGE_SHIFT
], KM_USER0
);
166 unwritten
= __copy_to_user_inatomic(data
, vaddr
+ page_offset
, length
);
167 kunmap_atomic(vaddr
, KM_USER0
);
175 static int i915_gem_object_needs_bit17_swizzle(struct drm_gem_object
*obj
)
177 drm_i915_private_t
*dev_priv
= obj
->dev
->dev_private
;
178 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
180 return dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_9_10_17
&&
181 obj_priv
->tiling_mode
!= I915_TILING_NONE
;
185 slow_shmem_copy(struct page
*dst_page
,
187 struct page
*src_page
,
191 char *dst_vaddr
, *src_vaddr
;
193 dst_vaddr
= kmap(dst_page
);
194 src_vaddr
= kmap(src_page
);
196 memcpy(dst_vaddr
+ dst_offset
, src_vaddr
+ src_offset
, length
);
203 slow_shmem_bit17_copy(struct page
*gpu_page
,
205 struct page
*cpu_page
,
210 char *gpu_vaddr
, *cpu_vaddr
;
212 /* Use the unswizzled path if this page isn't affected. */
213 if ((page_to_phys(gpu_page
) & (1 << 17)) == 0) {
215 return slow_shmem_copy(cpu_page
, cpu_offset
,
216 gpu_page
, gpu_offset
, length
);
218 return slow_shmem_copy(gpu_page
, gpu_offset
,
219 cpu_page
, cpu_offset
, length
);
222 gpu_vaddr
= kmap(gpu_page
);
223 cpu_vaddr
= kmap(cpu_page
);
225 /* Copy the data, XORing A6 with A17 (1). The user already knows he's
226 * XORing with the other bits (A9 for Y, A9 and A10 for X)
229 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
230 int this_length
= min(cacheline_end
- gpu_offset
, length
);
231 int swizzled_gpu_offset
= gpu_offset
^ 64;
234 memcpy(cpu_vaddr
+ cpu_offset
,
235 gpu_vaddr
+ swizzled_gpu_offset
,
238 memcpy(gpu_vaddr
+ swizzled_gpu_offset
,
239 cpu_vaddr
+ cpu_offset
,
242 cpu_offset
+= this_length
;
243 gpu_offset
+= this_length
;
244 length
-= this_length
;
252 * This is the fast shmem pread path, which attempts to copy_from_user directly
253 * from the backing pages of the object to the user's address space. On a
254 * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow().
257 i915_gem_shmem_pread_fast(struct drm_device
*dev
, struct drm_gem_object
*obj
,
258 struct drm_i915_gem_pread
*args
,
259 struct drm_file
*file_priv
)
261 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
263 loff_t offset
, page_base
;
264 char __user
*user_data
;
265 int page_offset
, page_length
;
268 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
271 mutex_lock(&dev
->struct_mutex
);
273 ret
= i915_gem_object_get_pages(obj
, 0);
277 ret
= i915_gem_object_set_cpu_read_domain_range(obj
, args
->offset
,
282 obj_priv
= to_intel_bo(obj
);
283 offset
= args
->offset
;
286 /* Operation in this page
288 * page_base = page offset within aperture
289 * page_offset = offset within page
290 * page_length = bytes to copy for this page
292 page_base
= (offset
& ~(PAGE_SIZE
-1));
293 page_offset
= offset
& (PAGE_SIZE
-1);
294 page_length
= remain
;
295 if ((page_offset
+ remain
) > PAGE_SIZE
)
296 page_length
= PAGE_SIZE
- page_offset
;
298 ret
= fast_shmem_read(obj_priv
->pages
,
299 page_base
, page_offset
,
300 user_data
, page_length
);
304 remain
-= page_length
;
305 user_data
+= page_length
;
306 offset
+= page_length
;
310 i915_gem_object_put_pages(obj
);
312 mutex_unlock(&dev
->struct_mutex
);
318 i915_gem_object_get_pages_or_evict(struct drm_gem_object
*obj
)
322 ret
= i915_gem_object_get_pages(obj
, __GFP_NORETRY
| __GFP_NOWARN
);
324 /* If we've insufficient memory to map in the pages, attempt
325 * to make some space by throwing out some old buffers.
327 if (ret
== -ENOMEM
) {
328 struct drm_device
*dev
= obj
->dev
;
330 ret
= i915_gem_evict_something(dev
, obj
->size
,
331 i915_gem_get_gtt_alignment(obj
));
335 ret
= i915_gem_object_get_pages(obj
, 0);
342 * This is the fallback shmem pread path, which allocates temporary storage
343 * in kernel space to copy_to_user into outside of the struct_mutex, so we
344 * can copy out of the object's backing pages while holding the struct mutex
345 * and not take page faults.
348 i915_gem_shmem_pread_slow(struct drm_device
*dev
, struct drm_gem_object
*obj
,
349 struct drm_i915_gem_pread
*args
,
350 struct drm_file
*file_priv
)
352 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
353 struct mm_struct
*mm
= current
->mm
;
354 struct page
**user_pages
;
356 loff_t offset
, pinned_pages
, i
;
357 loff_t first_data_page
, last_data_page
, num_pages
;
358 int shmem_page_index
, shmem_page_offset
;
359 int data_page_index
, data_page_offset
;
362 uint64_t data_ptr
= args
->data_ptr
;
363 int do_bit17_swizzling
;
367 /* Pin the user pages containing the data. We can't fault while
368 * holding the struct mutex, yet we want to hold it while
369 * dereferencing the user data.
371 first_data_page
= data_ptr
/ PAGE_SIZE
;
372 last_data_page
= (data_ptr
+ args
->size
- 1) / PAGE_SIZE
;
373 num_pages
= last_data_page
- first_data_page
+ 1;
375 user_pages
= drm_calloc_large(num_pages
, sizeof(struct page
*));
376 if (user_pages
== NULL
)
379 down_read(&mm
->mmap_sem
);
380 pinned_pages
= get_user_pages(current
, mm
, (uintptr_t)args
->data_ptr
,
381 num_pages
, 1, 0, user_pages
, NULL
);
382 up_read(&mm
->mmap_sem
);
383 if (pinned_pages
< num_pages
) {
385 goto fail_put_user_pages
;
388 do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
390 mutex_lock(&dev
->struct_mutex
);
392 ret
= i915_gem_object_get_pages_or_evict(obj
);
396 ret
= i915_gem_object_set_cpu_read_domain_range(obj
, args
->offset
,
401 obj_priv
= to_intel_bo(obj
);
402 offset
= args
->offset
;
405 /* Operation in this page
407 * shmem_page_index = page number within shmem file
408 * shmem_page_offset = offset within page in shmem file
409 * data_page_index = page number in get_user_pages return
410 * data_page_offset = offset with data_page_index page.
411 * page_length = bytes to copy for this page
413 shmem_page_index
= offset
/ PAGE_SIZE
;
414 shmem_page_offset
= offset
& ~PAGE_MASK
;
415 data_page_index
= data_ptr
/ PAGE_SIZE
- first_data_page
;
416 data_page_offset
= data_ptr
& ~PAGE_MASK
;
418 page_length
= remain
;
419 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
420 page_length
= PAGE_SIZE
- shmem_page_offset
;
421 if ((data_page_offset
+ page_length
) > PAGE_SIZE
)
422 page_length
= PAGE_SIZE
- data_page_offset
;
424 if (do_bit17_swizzling
) {
425 slow_shmem_bit17_copy(obj_priv
->pages
[shmem_page_index
],
427 user_pages
[data_page_index
],
432 slow_shmem_copy(user_pages
[data_page_index
],
434 obj_priv
->pages
[shmem_page_index
],
439 remain
-= page_length
;
440 data_ptr
+= page_length
;
441 offset
+= page_length
;
445 i915_gem_object_put_pages(obj
);
447 mutex_unlock(&dev
->struct_mutex
);
449 for (i
= 0; i
< pinned_pages
; i
++) {
450 SetPageDirty(user_pages
[i
]);
451 page_cache_release(user_pages
[i
]);
453 drm_free_large(user_pages
);
459 * Reads data from the object referenced by handle.
461 * On error, the contents of *data are undefined.
464 i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
465 struct drm_file
*file_priv
)
467 struct drm_i915_gem_pread
*args
= data
;
468 struct drm_gem_object
*obj
;
469 struct drm_i915_gem_object
*obj_priv
;
472 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
475 obj_priv
= to_intel_bo(obj
);
477 /* Bounds check source.
479 * XXX: This could use review for overflow issues...
481 if (args
->offset
> obj
->size
|| args
->size
> obj
->size
||
482 args
->offset
+ args
->size
> obj
->size
) {
483 drm_gem_object_unreference_unlocked(obj
);
487 if (i915_gem_object_needs_bit17_swizzle(obj
)) {
488 ret
= i915_gem_shmem_pread_slow(dev
, obj
, args
, file_priv
);
490 ret
= i915_gem_shmem_pread_fast(dev
, obj
, args
, file_priv
);
492 ret
= i915_gem_shmem_pread_slow(dev
, obj
, args
,
496 drm_gem_object_unreference_unlocked(obj
);
501 /* This is the fast write path which cannot handle
502 * page faults in the source data
506 fast_user_write(struct io_mapping
*mapping
,
507 loff_t page_base
, int page_offset
,
508 char __user
*user_data
,
512 unsigned long unwritten
;
514 vaddr_atomic
= io_mapping_map_atomic_wc(mapping
, page_base
, KM_USER0
);
515 unwritten
= __copy_from_user_inatomic_nocache(vaddr_atomic
+ page_offset
,
517 io_mapping_unmap_atomic(vaddr_atomic
, KM_USER0
);
523 /* Here's the write path which can sleep for
528 slow_kernel_write(struct io_mapping
*mapping
,
529 loff_t gtt_base
, int gtt_offset
,
530 struct page
*user_page
, int user_offset
,
533 char __iomem
*dst_vaddr
;
536 dst_vaddr
= io_mapping_map_wc(mapping
, gtt_base
);
537 src_vaddr
= kmap(user_page
);
539 memcpy_toio(dst_vaddr
+ gtt_offset
,
540 src_vaddr
+ user_offset
,
544 io_mapping_unmap(dst_vaddr
);
548 fast_shmem_write(struct page
**pages
,
549 loff_t page_base
, int page_offset
,
554 unsigned long unwritten
;
556 vaddr
= kmap_atomic(pages
[page_base
>> PAGE_SHIFT
], KM_USER0
);
559 unwritten
= __copy_from_user_inatomic(vaddr
+ page_offset
, data
, length
);
560 kunmap_atomic(vaddr
, KM_USER0
);
568 * This is the fast pwrite path, where we copy the data directly from the
569 * user into the GTT, uncached.
572 i915_gem_gtt_pwrite_fast(struct drm_device
*dev
, struct drm_gem_object
*obj
,
573 struct drm_i915_gem_pwrite
*args
,
574 struct drm_file
*file_priv
)
576 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
577 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
579 loff_t offset
, page_base
;
580 char __user
*user_data
;
581 int page_offset
, page_length
;
584 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
586 if (!access_ok(VERIFY_READ
, user_data
, remain
))
590 mutex_lock(&dev
->struct_mutex
);
591 ret
= i915_gem_object_pin(obj
, 0);
593 mutex_unlock(&dev
->struct_mutex
);
596 ret
= i915_gem_object_set_to_gtt_domain(obj
, 1);
600 obj_priv
= to_intel_bo(obj
);
601 offset
= obj_priv
->gtt_offset
+ args
->offset
;
604 /* Operation in this page
606 * page_base = page offset within aperture
607 * page_offset = offset within page
608 * page_length = bytes to copy for this page
610 page_base
= (offset
& ~(PAGE_SIZE
-1));
611 page_offset
= offset
& (PAGE_SIZE
-1);
612 page_length
= remain
;
613 if ((page_offset
+ remain
) > PAGE_SIZE
)
614 page_length
= PAGE_SIZE
- page_offset
;
616 ret
= fast_user_write (dev_priv
->mm
.gtt_mapping
, page_base
,
617 page_offset
, user_data
, page_length
);
619 /* If we get a fault while copying data, then (presumably) our
620 * source page isn't available. Return the error and we'll
621 * retry in the slow path.
626 remain
-= page_length
;
627 user_data
+= page_length
;
628 offset
+= page_length
;
632 i915_gem_object_unpin(obj
);
633 mutex_unlock(&dev
->struct_mutex
);
639 * This is the fallback GTT pwrite path, which uses get_user_pages to pin
640 * the memory and maps it using kmap_atomic for copying.
642 * This code resulted in x11perf -rgb10text consuming about 10% more CPU
643 * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit).
646 i915_gem_gtt_pwrite_slow(struct drm_device
*dev
, struct drm_gem_object
*obj
,
647 struct drm_i915_gem_pwrite
*args
,
648 struct drm_file
*file_priv
)
650 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
651 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
653 loff_t gtt_page_base
, offset
;
654 loff_t first_data_page
, last_data_page
, num_pages
;
655 loff_t pinned_pages
, i
;
656 struct page
**user_pages
;
657 struct mm_struct
*mm
= current
->mm
;
658 int gtt_page_offset
, data_page_offset
, data_page_index
, page_length
;
660 uint64_t data_ptr
= args
->data_ptr
;
664 /* Pin the user pages containing the data. We can't fault while
665 * holding the struct mutex, and all of the pwrite implementations
666 * want to hold it while dereferencing the user data.
668 first_data_page
= data_ptr
/ PAGE_SIZE
;
669 last_data_page
= (data_ptr
+ args
->size
- 1) / PAGE_SIZE
;
670 num_pages
= last_data_page
- first_data_page
+ 1;
672 user_pages
= drm_calloc_large(num_pages
, sizeof(struct page
*));
673 if (user_pages
== NULL
)
676 down_read(&mm
->mmap_sem
);
677 pinned_pages
= get_user_pages(current
, mm
, (uintptr_t)args
->data_ptr
,
678 num_pages
, 0, 0, user_pages
, NULL
);
679 up_read(&mm
->mmap_sem
);
680 if (pinned_pages
< num_pages
) {
682 goto out_unpin_pages
;
685 mutex_lock(&dev
->struct_mutex
);
686 ret
= i915_gem_object_pin(obj
, 0);
690 ret
= i915_gem_object_set_to_gtt_domain(obj
, 1);
692 goto out_unpin_object
;
694 obj_priv
= to_intel_bo(obj
);
695 offset
= obj_priv
->gtt_offset
+ args
->offset
;
698 /* Operation in this page
700 * gtt_page_base = page offset within aperture
701 * gtt_page_offset = offset within page in aperture
702 * data_page_index = page number in get_user_pages return
703 * data_page_offset = offset with data_page_index page.
704 * page_length = bytes to copy for this page
706 gtt_page_base
= offset
& PAGE_MASK
;
707 gtt_page_offset
= offset
& ~PAGE_MASK
;
708 data_page_index
= data_ptr
/ PAGE_SIZE
- first_data_page
;
709 data_page_offset
= data_ptr
& ~PAGE_MASK
;
711 page_length
= remain
;
712 if ((gtt_page_offset
+ page_length
) > PAGE_SIZE
)
713 page_length
= PAGE_SIZE
- gtt_page_offset
;
714 if ((data_page_offset
+ page_length
) > PAGE_SIZE
)
715 page_length
= PAGE_SIZE
- data_page_offset
;
717 slow_kernel_write(dev_priv
->mm
.gtt_mapping
,
718 gtt_page_base
, gtt_page_offset
,
719 user_pages
[data_page_index
],
723 remain
-= page_length
;
724 offset
+= page_length
;
725 data_ptr
+= page_length
;
729 i915_gem_object_unpin(obj
);
731 mutex_unlock(&dev
->struct_mutex
);
733 for (i
= 0; i
< pinned_pages
; i
++)
734 page_cache_release(user_pages
[i
]);
735 drm_free_large(user_pages
);
741 * This is the fast shmem pwrite path, which attempts to directly
742 * copy_from_user into the kmapped pages backing the object.
745 i915_gem_shmem_pwrite_fast(struct drm_device
*dev
, struct drm_gem_object
*obj
,
746 struct drm_i915_gem_pwrite
*args
,
747 struct drm_file
*file_priv
)
749 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
751 loff_t offset
, page_base
;
752 char __user
*user_data
;
753 int page_offset
, page_length
;
756 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
759 mutex_lock(&dev
->struct_mutex
);
761 ret
= i915_gem_object_get_pages(obj
, 0);
765 ret
= i915_gem_object_set_to_cpu_domain(obj
, 1);
769 obj_priv
= to_intel_bo(obj
);
770 offset
= args
->offset
;
774 /* Operation in this page
776 * page_base = page offset within aperture
777 * page_offset = offset within page
778 * page_length = bytes to copy for this page
780 page_base
= (offset
& ~(PAGE_SIZE
-1));
781 page_offset
= offset
& (PAGE_SIZE
-1);
782 page_length
= remain
;
783 if ((page_offset
+ remain
) > PAGE_SIZE
)
784 page_length
= PAGE_SIZE
- page_offset
;
786 ret
= fast_shmem_write(obj_priv
->pages
,
787 page_base
, page_offset
,
788 user_data
, page_length
);
792 remain
-= page_length
;
793 user_data
+= page_length
;
794 offset
+= page_length
;
798 i915_gem_object_put_pages(obj
);
800 mutex_unlock(&dev
->struct_mutex
);
806 * This is the fallback shmem pwrite path, which uses get_user_pages to pin
807 * the memory and maps it using kmap_atomic for copying.
809 * This avoids taking mmap_sem for faulting on the user's address while the
810 * struct_mutex is held.
813 i915_gem_shmem_pwrite_slow(struct drm_device
*dev
, struct drm_gem_object
*obj
,
814 struct drm_i915_gem_pwrite
*args
,
815 struct drm_file
*file_priv
)
817 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
818 struct mm_struct
*mm
= current
->mm
;
819 struct page
**user_pages
;
821 loff_t offset
, pinned_pages
, i
;
822 loff_t first_data_page
, last_data_page
, num_pages
;
823 int shmem_page_index
, shmem_page_offset
;
824 int data_page_index
, data_page_offset
;
827 uint64_t data_ptr
= args
->data_ptr
;
828 int do_bit17_swizzling
;
832 /* Pin the user pages containing the data. We can't fault while
833 * holding the struct mutex, and all of the pwrite implementations
834 * want to hold it while dereferencing the user data.
836 first_data_page
= data_ptr
/ PAGE_SIZE
;
837 last_data_page
= (data_ptr
+ args
->size
- 1) / PAGE_SIZE
;
838 num_pages
= last_data_page
- first_data_page
+ 1;
840 user_pages
= drm_calloc_large(num_pages
, sizeof(struct page
*));
841 if (user_pages
== NULL
)
844 down_read(&mm
->mmap_sem
);
845 pinned_pages
= get_user_pages(current
, mm
, (uintptr_t)args
->data_ptr
,
846 num_pages
, 0, 0, user_pages
, NULL
);
847 up_read(&mm
->mmap_sem
);
848 if (pinned_pages
< num_pages
) {
850 goto fail_put_user_pages
;
853 do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
855 mutex_lock(&dev
->struct_mutex
);
857 ret
= i915_gem_object_get_pages_or_evict(obj
);
861 ret
= i915_gem_object_set_to_cpu_domain(obj
, 1);
865 obj_priv
= to_intel_bo(obj
);
866 offset
= args
->offset
;
870 /* Operation in this page
872 * shmem_page_index = page number within shmem file
873 * shmem_page_offset = offset within page in shmem file
874 * data_page_index = page number in get_user_pages return
875 * data_page_offset = offset with data_page_index page.
876 * page_length = bytes to copy for this page
878 shmem_page_index
= offset
/ PAGE_SIZE
;
879 shmem_page_offset
= offset
& ~PAGE_MASK
;
880 data_page_index
= data_ptr
/ PAGE_SIZE
- first_data_page
;
881 data_page_offset
= data_ptr
& ~PAGE_MASK
;
883 page_length
= remain
;
884 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
885 page_length
= PAGE_SIZE
- shmem_page_offset
;
886 if ((data_page_offset
+ page_length
) > PAGE_SIZE
)
887 page_length
= PAGE_SIZE
- data_page_offset
;
889 if (do_bit17_swizzling
) {
890 slow_shmem_bit17_copy(obj_priv
->pages
[shmem_page_index
],
892 user_pages
[data_page_index
],
897 slow_shmem_copy(obj_priv
->pages
[shmem_page_index
],
899 user_pages
[data_page_index
],
904 remain
-= page_length
;
905 data_ptr
+= page_length
;
906 offset
+= page_length
;
910 i915_gem_object_put_pages(obj
);
912 mutex_unlock(&dev
->struct_mutex
);
914 for (i
= 0; i
< pinned_pages
; i
++)
915 page_cache_release(user_pages
[i
]);
916 drm_free_large(user_pages
);
922 * Writes data to the object referenced by handle.
924 * On error, the contents of the buffer that were to be modified are undefined.
927 i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
928 struct drm_file
*file_priv
)
930 struct drm_i915_gem_pwrite
*args
= data
;
931 struct drm_gem_object
*obj
;
932 struct drm_i915_gem_object
*obj_priv
;
935 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
938 obj_priv
= to_intel_bo(obj
);
940 /* Bounds check destination.
942 * XXX: This could use review for overflow issues...
944 if (args
->offset
> obj
->size
|| args
->size
> obj
->size
||
945 args
->offset
+ args
->size
> obj
->size
) {
946 drm_gem_object_unreference_unlocked(obj
);
950 /* We can only do the GTT pwrite on untiled buffers, as otherwise
951 * it would end up going through the fenced access, and we'll get
952 * different detiling behavior between reading and writing.
953 * pread/pwrite currently are reading and writing from the CPU
954 * perspective, requiring manual detiling by the client.
956 if (obj_priv
->phys_obj
)
957 ret
= i915_gem_phys_pwrite(dev
, obj
, args
, file_priv
);
958 else if (obj_priv
->tiling_mode
== I915_TILING_NONE
&&
959 dev
->gtt_total
!= 0 &&
960 obj
->write_domain
!= I915_GEM_DOMAIN_CPU
) {
961 ret
= i915_gem_gtt_pwrite_fast(dev
, obj
, args
, file_priv
);
962 if (ret
== -EFAULT
) {
963 ret
= i915_gem_gtt_pwrite_slow(dev
, obj
, args
,
966 } else if (i915_gem_object_needs_bit17_swizzle(obj
)) {
967 ret
= i915_gem_shmem_pwrite_slow(dev
, obj
, args
, file_priv
);
969 ret
= i915_gem_shmem_pwrite_fast(dev
, obj
, args
, file_priv
);
970 if (ret
== -EFAULT
) {
971 ret
= i915_gem_shmem_pwrite_slow(dev
, obj
, args
,
978 DRM_INFO("pwrite failed %d\n", ret
);
981 drm_gem_object_unreference_unlocked(obj
);
987 * Called when user space prepares to use an object with the CPU, either
988 * through the mmap ioctl's mapping or a GTT mapping.
991 i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
992 struct drm_file
*file_priv
)
994 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
995 struct drm_i915_gem_set_domain
*args
= data
;
996 struct drm_gem_object
*obj
;
997 struct drm_i915_gem_object
*obj_priv
;
998 uint32_t read_domains
= args
->read_domains
;
999 uint32_t write_domain
= args
->write_domain
;
1002 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1005 /* Only handle setting domains to types used by the CPU. */
1006 if (write_domain
& I915_GEM_GPU_DOMAINS
)
1009 if (read_domains
& I915_GEM_GPU_DOMAINS
)
1012 /* Having something in the write domain implies it's in the read
1013 * domain, and only that read domain. Enforce that in the request.
1015 if (write_domain
!= 0 && read_domains
!= write_domain
)
1018 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
1021 obj_priv
= to_intel_bo(obj
);
1023 mutex_lock(&dev
->struct_mutex
);
1025 intel_mark_busy(dev
, obj
);
1028 DRM_INFO("set_domain_ioctl %p(%zd), %08x %08x\n",
1029 obj
, obj
->size
, read_domains
, write_domain
);
1031 if (read_domains
& I915_GEM_DOMAIN_GTT
) {
1032 ret
= i915_gem_object_set_to_gtt_domain(obj
, write_domain
!= 0);
1034 /* Update the LRU on the fence for the CPU access that's
1037 if (obj_priv
->fence_reg
!= I915_FENCE_REG_NONE
) {
1038 struct drm_i915_fence_reg
*reg
=
1039 &dev_priv
->fence_regs
[obj_priv
->fence_reg
];
1040 list_move_tail(®
->lru_list
,
1041 &dev_priv
->mm
.fence_list
);
1044 /* Silently promote "you're not bound, there was nothing to do"
1045 * to success, since the client was just asking us to
1046 * make sure everything was done.
1051 ret
= i915_gem_object_set_to_cpu_domain(obj
, write_domain
!= 0);
1055 /* Maintain LRU order of "inactive" objects */
1056 if (ret
== 0 && i915_gem_object_is_inactive(obj_priv
))
1057 list_move_tail(&obj_priv
->list
, &dev_priv
->mm
.inactive_list
);
1059 drm_gem_object_unreference(obj
);
1060 mutex_unlock(&dev
->struct_mutex
);
1065 * Called when user space has done writes to this buffer
1068 i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
1069 struct drm_file
*file_priv
)
1071 struct drm_i915_gem_sw_finish
*args
= data
;
1072 struct drm_gem_object
*obj
;
1073 struct drm_i915_gem_object
*obj_priv
;
1076 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1079 mutex_lock(&dev
->struct_mutex
);
1080 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
1082 mutex_unlock(&dev
->struct_mutex
);
1087 DRM_INFO("%s: sw_finish %d (%p %zd)\n",
1088 __func__
, args
->handle
, obj
, obj
->size
);
1090 obj_priv
= to_intel_bo(obj
);
1092 /* Pinned buffers may be scanout, so flush the cache */
1093 if (obj_priv
->pin_count
)
1094 i915_gem_object_flush_cpu_write_domain(obj
);
1096 drm_gem_object_unreference(obj
);
1097 mutex_unlock(&dev
->struct_mutex
);
1102 * Maps the contents of an object, returning the address it is mapped
1105 * While the mapping holds a reference on the contents of the object, it doesn't
1106 * imply a ref on the object itself.
1109 i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
1110 struct drm_file
*file_priv
)
1112 struct drm_i915_gem_mmap
*args
= data
;
1113 struct drm_gem_object
*obj
;
1117 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1120 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
1124 offset
= args
->offset
;
1126 down_write(¤t
->mm
->mmap_sem
);
1127 addr
= do_mmap(obj
->filp
, 0, args
->size
,
1128 PROT_READ
| PROT_WRITE
, MAP_SHARED
,
1130 up_write(¤t
->mm
->mmap_sem
);
1131 drm_gem_object_unreference_unlocked(obj
);
1132 if (IS_ERR((void *)addr
))
1135 args
->addr_ptr
= (uint64_t) addr
;
1141 * i915_gem_fault - fault a page into the GTT
1142 * vma: VMA in question
1145 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1146 * from userspace. The fault handler takes care of binding the object to
1147 * the GTT (if needed), allocating and programming a fence register (again,
1148 * only if needed based on whether the old reg is still valid or the object
1149 * is tiled) and inserting a new PTE into the faulting process.
1151 * Note that the faulting process may involve evicting existing objects
1152 * from the GTT and/or fence registers to make room. So performance may
1153 * suffer if the GTT working set is large or there are few fence registers
1156 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
)
1158 struct drm_gem_object
*obj
= vma
->vm_private_data
;
1159 struct drm_device
*dev
= obj
->dev
;
1160 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1161 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1162 pgoff_t page_offset
;
1165 bool write
= !!(vmf
->flags
& FAULT_FLAG_WRITE
);
1167 /* We don't use vmf->pgoff since that has the fake offset */
1168 page_offset
= ((unsigned long)vmf
->virtual_address
- vma
->vm_start
) >>
1171 /* Now bind it into the GTT if needed */
1172 mutex_lock(&dev
->struct_mutex
);
1173 if (!obj_priv
->gtt_space
) {
1174 ret
= i915_gem_object_bind_to_gtt(obj
, 0);
1178 ret
= i915_gem_object_set_to_gtt_domain(obj
, write
);
1183 /* Need a new fence register? */
1184 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
) {
1185 ret
= i915_gem_object_get_fence_reg(obj
, true);
1190 if (i915_gem_object_is_inactive(obj_priv
))
1191 list_move_tail(&obj_priv
->list
, &dev_priv
->mm
.inactive_list
);
1193 pfn
= ((dev
->agp
->base
+ obj_priv
->gtt_offset
) >> PAGE_SHIFT
) +
1196 /* Finally, remap it using the new GTT offset */
1197 ret
= vm_insert_pfn(vma
, (unsigned long)vmf
->virtual_address
, pfn
);
1199 mutex_unlock(&dev
->struct_mutex
);
1204 return VM_FAULT_NOPAGE
;
1207 return VM_FAULT_OOM
;
1209 return VM_FAULT_SIGBUS
;
1214 * i915_gem_create_mmap_offset - create a fake mmap offset for an object
1215 * @obj: obj in question
1217 * GEM memory mapping works by handing back to userspace a fake mmap offset
1218 * it can use in a subsequent mmap(2) call. The DRM core code then looks
1219 * up the object based on the offset and sets up the various memory mapping
1222 * This routine allocates and attaches a fake offset for @obj.
1225 i915_gem_create_mmap_offset(struct drm_gem_object
*obj
)
1227 struct drm_device
*dev
= obj
->dev
;
1228 struct drm_gem_mm
*mm
= dev
->mm_private
;
1229 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1230 struct drm_map_list
*list
;
1231 struct drm_local_map
*map
;
1234 /* Set the object up for mmap'ing */
1235 list
= &obj
->map_list
;
1236 list
->map
= kzalloc(sizeof(struct drm_map_list
), GFP_KERNEL
);
1241 map
->type
= _DRM_GEM
;
1242 map
->size
= obj
->size
;
1245 /* Get a DRM GEM mmap offset allocated... */
1246 list
->file_offset_node
= drm_mm_search_free(&mm
->offset_manager
,
1247 obj
->size
/ PAGE_SIZE
, 0, 0);
1248 if (!list
->file_offset_node
) {
1249 DRM_ERROR("failed to allocate offset for bo %d\n", obj
->name
);
1254 list
->file_offset_node
= drm_mm_get_block(list
->file_offset_node
,
1255 obj
->size
/ PAGE_SIZE
, 0);
1256 if (!list
->file_offset_node
) {
1261 list
->hash
.key
= list
->file_offset_node
->start
;
1262 if (drm_ht_insert_item(&mm
->offset_hash
, &list
->hash
)) {
1263 DRM_ERROR("failed to add to map hash\n");
1268 /* By now we should be all set, any drm_mmap request on the offset
1269 * below will get to our mmap & fault handler */
1270 obj_priv
->mmap_offset
= ((uint64_t) list
->hash
.key
) << PAGE_SHIFT
;
1275 drm_mm_put_block(list
->file_offset_node
);
1283 * i915_gem_release_mmap - remove physical page mappings
1284 * @obj: obj in question
1286 * Preserve the reservation of the mmapping with the DRM core code, but
1287 * relinquish ownership of the pages back to the system.
1289 * It is vital that we remove the page mapping if we have mapped a tiled
1290 * object through the GTT and then lose the fence register due to
1291 * resource pressure. Similarly if the object has been moved out of the
1292 * aperture, than pages mapped into userspace must be revoked. Removing the
1293 * mapping will then trigger a page fault on the next user access, allowing
1294 * fixup by i915_gem_fault().
1297 i915_gem_release_mmap(struct drm_gem_object
*obj
)
1299 struct drm_device
*dev
= obj
->dev
;
1300 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1302 if (dev
->dev_mapping
)
1303 unmap_mapping_range(dev
->dev_mapping
,
1304 obj_priv
->mmap_offset
, obj
->size
, 1);
1308 i915_gem_free_mmap_offset(struct drm_gem_object
*obj
)
1310 struct drm_device
*dev
= obj
->dev
;
1311 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1312 struct drm_gem_mm
*mm
= dev
->mm_private
;
1313 struct drm_map_list
*list
;
1315 list
= &obj
->map_list
;
1316 drm_ht_remove_item(&mm
->offset_hash
, &list
->hash
);
1318 if (list
->file_offset_node
) {
1319 drm_mm_put_block(list
->file_offset_node
);
1320 list
->file_offset_node
= NULL
;
1328 obj_priv
->mmap_offset
= 0;
1332 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1333 * @obj: object to check
1335 * Return the required GTT alignment for an object, taking into account
1336 * potential fence register mapping if needed.
1339 i915_gem_get_gtt_alignment(struct drm_gem_object
*obj
)
1341 struct drm_device
*dev
= obj
->dev
;
1342 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1346 * Minimum alignment is 4k (GTT page size), but might be greater
1347 * if a fence register is needed for the object.
1349 if (INTEL_INFO(dev
)->gen
>= 4 || obj_priv
->tiling_mode
== I915_TILING_NONE
)
1353 * Previous chips need to be aligned to the size of the smallest
1354 * fence register that can contain the object.
1356 if (INTEL_INFO(dev
)->gen
== 3)
1361 for (i
= start
; i
< obj
->size
; i
<<= 1)
1368 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1370 * @data: GTT mapping ioctl data
1371 * @file_priv: GEM object info
1373 * Simply returns the fake offset to userspace so it can mmap it.
1374 * The mmap call will end up in drm_gem_mmap(), which will set things
1375 * up so we can get faults in the handler above.
1377 * The fault handler will take care of binding the object into the GTT
1378 * (since it may have been evicted to make room for something), allocating
1379 * a fence register, and mapping the appropriate aperture address into
1383 i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
1384 struct drm_file
*file_priv
)
1386 struct drm_i915_gem_mmap_gtt
*args
= data
;
1387 struct drm_gem_object
*obj
;
1388 struct drm_i915_gem_object
*obj_priv
;
1391 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1394 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
1398 mutex_lock(&dev
->struct_mutex
);
1400 obj_priv
= to_intel_bo(obj
);
1402 if (obj_priv
->madv
!= I915_MADV_WILLNEED
) {
1403 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1404 drm_gem_object_unreference(obj
);
1405 mutex_unlock(&dev
->struct_mutex
);
1410 if (!obj_priv
->mmap_offset
) {
1411 ret
= i915_gem_create_mmap_offset(obj
);
1413 drm_gem_object_unreference(obj
);
1414 mutex_unlock(&dev
->struct_mutex
);
1419 args
->offset
= obj_priv
->mmap_offset
;
1422 * Pull it into the GTT so that we have a page list (makes the
1423 * initial fault faster and any subsequent flushing possible).
1425 if (!obj_priv
->agp_mem
) {
1426 ret
= i915_gem_object_bind_to_gtt(obj
, 0);
1428 drm_gem_object_unreference(obj
);
1429 mutex_unlock(&dev
->struct_mutex
);
1434 drm_gem_object_unreference(obj
);
1435 mutex_unlock(&dev
->struct_mutex
);
1441 i915_gem_object_put_pages(struct drm_gem_object
*obj
)
1443 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1444 int page_count
= obj
->size
/ PAGE_SIZE
;
1447 BUG_ON(obj_priv
->pages_refcount
== 0);
1448 BUG_ON(obj_priv
->madv
== __I915_MADV_PURGED
);
1450 if (--obj_priv
->pages_refcount
!= 0)
1453 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
)
1454 i915_gem_object_save_bit_17_swizzle(obj
);
1456 if (obj_priv
->madv
== I915_MADV_DONTNEED
)
1457 obj_priv
->dirty
= 0;
1459 for (i
= 0; i
< page_count
; i
++) {
1460 if (obj_priv
->dirty
)
1461 set_page_dirty(obj_priv
->pages
[i
]);
1463 if (obj_priv
->madv
== I915_MADV_WILLNEED
)
1464 mark_page_accessed(obj_priv
->pages
[i
]);
1466 page_cache_release(obj_priv
->pages
[i
]);
1468 obj_priv
->dirty
= 0;
1470 drm_free_large(obj_priv
->pages
);
1471 obj_priv
->pages
= NULL
;
1475 i915_gem_next_request_seqno(struct drm_device
*dev
,
1476 struct intel_ring_buffer
*ring
)
1478 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1480 ring
->outstanding_lazy_request
= true;
1482 return dev_priv
->next_seqno
;
1486 i915_gem_object_move_to_active(struct drm_gem_object
*obj
,
1487 struct intel_ring_buffer
*ring
)
1489 struct drm_device
*dev
= obj
->dev
;
1490 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1491 uint32_t seqno
= i915_gem_next_request_seqno(dev
, ring
);
1493 BUG_ON(ring
== NULL
);
1494 obj_priv
->ring
= ring
;
1496 /* Add a reference if we're newly entering the active list. */
1497 if (!obj_priv
->active
) {
1498 drm_gem_object_reference(obj
);
1499 obj_priv
->active
= 1;
1502 /* Move from whatever list we were on to the tail of execution. */
1503 list_move_tail(&obj_priv
->list
, &ring
->active_list
);
1504 obj_priv
->last_rendering_seqno
= seqno
;
1508 i915_gem_object_move_to_flushing(struct drm_gem_object
*obj
)
1510 struct drm_device
*dev
= obj
->dev
;
1511 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1512 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1514 BUG_ON(!obj_priv
->active
);
1515 list_move_tail(&obj_priv
->list
, &dev_priv
->mm
.flushing_list
);
1516 obj_priv
->last_rendering_seqno
= 0;
1519 /* Immediately discard the backing storage */
1521 i915_gem_object_truncate(struct drm_gem_object
*obj
)
1523 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1524 struct inode
*inode
;
1526 /* Our goal here is to return as much of the memory as
1527 * is possible back to the system as we are called from OOM.
1528 * To do this we must instruct the shmfs to drop all of its
1529 * backing pages, *now*. Here we mirror the actions taken
1530 * when by shmem_delete_inode() to release the backing store.
1532 inode
= obj
->filp
->f_path
.dentry
->d_inode
;
1533 truncate_inode_pages(inode
->i_mapping
, 0);
1534 if (inode
->i_op
->truncate_range
)
1535 inode
->i_op
->truncate_range(inode
, 0, (loff_t
)-1);
1537 obj_priv
->madv
= __I915_MADV_PURGED
;
1541 i915_gem_object_is_purgeable(struct drm_i915_gem_object
*obj_priv
)
1543 return obj_priv
->madv
== I915_MADV_DONTNEED
;
1547 i915_gem_object_move_to_inactive(struct drm_gem_object
*obj
)
1549 struct drm_device
*dev
= obj
->dev
;
1550 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1551 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1553 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
1554 if (obj_priv
->pin_count
!= 0)
1555 list_del_init(&obj_priv
->list
);
1557 list_move_tail(&obj_priv
->list
, &dev_priv
->mm
.inactive_list
);
1559 BUG_ON(!list_empty(&obj_priv
->gpu_write_list
));
1561 obj_priv
->last_rendering_seqno
= 0;
1562 obj_priv
->ring
= NULL
;
1563 if (obj_priv
->active
) {
1564 obj_priv
->active
= 0;
1565 drm_gem_object_unreference(obj
);
1567 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
1571 i915_gem_process_flushing_list(struct drm_device
*dev
,
1572 uint32_t flush_domains
,
1573 struct intel_ring_buffer
*ring
)
1575 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1576 struct drm_i915_gem_object
*obj_priv
, *next
;
1578 list_for_each_entry_safe(obj_priv
, next
,
1579 &dev_priv
->mm
.gpu_write_list
,
1581 struct drm_gem_object
*obj
= &obj_priv
->base
;
1583 if (obj
->write_domain
& flush_domains
&&
1584 obj_priv
->ring
== ring
) {
1585 uint32_t old_write_domain
= obj
->write_domain
;
1587 obj
->write_domain
= 0;
1588 list_del_init(&obj_priv
->gpu_write_list
);
1589 i915_gem_object_move_to_active(obj
, ring
);
1591 /* update the fence lru list */
1592 if (obj_priv
->fence_reg
!= I915_FENCE_REG_NONE
) {
1593 struct drm_i915_fence_reg
*reg
=
1594 &dev_priv
->fence_regs
[obj_priv
->fence_reg
];
1595 list_move_tail(®
->lru_list
,
1596 &dev_priv
->mm
.fence_list
);
1599 trace_i915_gem_object_change_domain(obj
,
1607 i915_add_request(struct drm_device
*dev
,
1608 struct drm_file
*file_priv
,
1609 struct drm_i915_gem_request
*request
,
1610 struct intel_ring_buffer
*ring
)
1612 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1613 struct drm_i915_file_private
*i915_file_priv
= NULL
;
1617 if (file_priv
!= NULL
)
1618 i915_file_priv
= file_priv
->driver_priv
;
1620 if (request
== NULL
) {
1621 request
= kzalloc(sizeof(*request
), GFP_KERNEL
);
1622 if (request
== NULL
)
1626 seqno
= ring
->add_request(dev
, ring
, file_priv
, 0);
1628 request
->seqno
= seqno
;
1629 request
->ring
= ring
;
1630 request
->emitted_jiffies
= jiffies
;
1631 was_empty
= list_empty(&ring
->request_list
);
1632 list_add_tail(&request
->list
, &ring
->request_list
);
1634 if (i915_file_priv
) {
1635 list_add_tail(&request
->client_list
,
1636 &i915_file_priv
->mm
.request_list
);
1638 INIT_LIST_HEAD(&request
->client_list
);
1641 if (!dev_priv
->mm
.suspended
) {
1642 mod_timer(&dev_priv
->hangcheck_timer
,
1643 jiffies
+ msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD
));
1645 queue_delayed_work(dev_priv
->wq
,
1646 &dev_priv
->mm
.retire_work
, HZ
);
1652 * Command execution barrier
1654 * Ensures that all commands in the ring are finished
1655 * before signalling the CPU
1658 i915_retire_commands(struct drm_device
*dev
, struct intel_ring_buffer
*ring
)
1660 uint32_t flush_domains
= 0;
1662 /* The sampler always gets flushed on i965 (sigh) */
1663 if (INTEL_INFO(dev
)->gen
>= 4)
1664 flush_domains
|= I915_GEM_DOMAIN_SAMPLER
;
1666 ring
->flush(dev
, ring
,
1667 I915_GEM_DOMAIN_COMMAND
, flush_domains
);
1671 * Returns true if seq1 is later than seq2.
1674 i915_seqno_passed(uint32_t seq1
, uint32_t seq2
)
1676 return (int32_t)(seq1
- seq2
) >= 0;
1680 i915_get_gem_seqno(struct drm_device
*dev
,
1681 struct intel_ring_buffer
*ring
)
1683 return ring
->get_gem_seqno(dev
, ring
);
1686 void i915_gem_reset_flushing_list(struct drm_device
*dev
)
1688 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1690 while (!list_empty(&dev_priv
->mm
.flushing_list
)) {
1691 struct drm_i915_gem_object
*obj_priv
;
1693 obj_priv
= list_first_entry(&dev_priv
->mm
.flushing_list
,
1694 struct drm_i915_gem_object
,
1697 obj_priv
->base
.write_domain
= 0;
1698 i915_gem_object_move_to_inactive(&obj_priv
->base
);
1703 * This function clears the request list as sequence numbers are passed.
1706 i915_gem_retire_requests_ring(struct drm_device
*dev
,
1707 struct intel_ring_buffer
*ring
)
1709 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1713 if (!ring
->status_page
.page_addr
||
1714 list_empty(&ring
->request_list
))
1717 seqno
= i915_get_gem_seqno(dev
, ring
);
1718 wedged
= atomic_read(&dev_priv
->mm
.wedged
);
1720 while (!list_empty(&ring
->request_list
)) {
1721 struct drm_i915_gem_request
*request
;
1723 request
= list_first_entry(&ring
->request_list
,
1724 struct drm_i915_gem_request
,
1727 if (!wedged
&& !i915_seqno_passed(seqno
, request
->seqno
))
1730 trace_i915_gem_request_retire(dev
, request
->seqno
);
1732 list_del(&request
->list
);
1733 list_del(&request
->client_list
);
1737 /* Move any buffers on the active list that are no longer referenced
1738 * by the ringbuffer to the flushing/inactive lists as appropriate.
1740 while (!list_empty(&ring
->active_list
)) {
1741 struct drm_gem_object
*obj
;
1742 struct drm_i915_gem_object
*obj_priv
;
1744 obj_priv
= list_first_entry(&ring
->active_list
,
1745 struct drm_i915_gem_object
,
1749 !i915_seqno_passed(seqno
, obj_priv
->last_rendering_seqno
))
1752 obj
= &obj_priv
->base
;
1755 DRM_INFO("%s: retire %d moves to inactive list %p\n",
1756 __func__
, request
->seqno
, obj
);
1759 if (obj
->write_domain
!= 0)
1760 i915_gem_object_move_to_flushing(obj
);
1762 i915_gem_object_move_to_inactive(obj
);
1765 if (unlikely (dev_priv
->trace_irq_seqno
&&
1766 i915_seqno_passed(dev_priv
->trace_irq_seqno
, seqno
))) {
1767 ring
->user_irq_put(dev
, ring
);
1768 dev_priv
->trace_irq_seqno
= 0;
1773 i915_gem_retire_requests(struct drm_device
*dev
)
1775 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1777 if (!list_empty(&dev_priv
->mm
.deferred_free_list
)) {
1778 struct drm_i915_gem_object
*obj_priv
, *tmp
;
1780 /* We must be careful that during unbind() we do not
1781 * accidentally infinitely recurse into retire requests.
1783 * retire -> free -> unbind -> wait -> retire_ring
1785 list_for_each_entry_safe(obj_priv
, tmp
,
1786 &dev_priv
->mm
.deferred_free_list
,
1788 i915_gem_free_object_tail(&obj_priv
->base
);
1791 i915_gem_retire_requests_ring(dev
, &dev_priv
->render_ring
);
1793 i915_gem_retire_requests_ring(dev
, &dev_priv
->bsd_ring
);
1797 i915_gem_retire_work_handler(struct work_struct
*work
)
1799 drm_i915_private_t
*dev_priv
;
1800 struct drm_device
*dev
;
1802 dev_priv
= container_of(work
, drm_i915_private_t
,
1803 mm
.retire_work
.work
);
1804 dev
= dev_priv
->dev
;
1806 mutex_lock(&dev
->struct_mutex
);
1807 i915_gem_retire_requests(dev
);
1809 if (!dev_priv
->mm
.suspended
&&
1810 (!list_empty(&dev_priv
->render_ring
.request_list
) ||
1812 !list_empty(&dev_priv
->bsd_ring
.request_list
))))
1813 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, HZ
);
1814 mutex_unlock(&dev
->struct_mutex
);
1818 i915_do_wait_request(struct drm_device
*dev
, uint32_t seqno
,
1819 bool interruptible
, struct intel_ring_buffer
*ring
)
1821 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1827 if (seqno
== dev_priv
->next_seqno
) {
1828 seqno
= i915_add_request(dev
, NULL
, NULL
, ring
);
1833 if (atomic_read(&dev_priv
->mm
.wedged
))
1836 if (!i915_seqno_passed(ring
->get_gem_seqno(dev
, ring
), seqno
)) {
1837 if (HAS_PCH_SPLIT(dev
))
1838 ier
= I915_READ(DEIER
) | I915_READ(GTIER
);
1840 ier
= I915_READ(IER
);
1842 DRM_ERROR("something (likely vbetool) disabled "
1843 "interrupts, re-enabling\n");
1844 i915_driver_irq_preinstall(dev
);
1845 i915_driver_irq_postinstall(dev
);
1848 trace_i915_gem_request_wait_begin(dev
, seqno
);
1850 ring
->waiting_gem_seqno
= seqno
;
1851 ring
->user_irq_get(dev
, ring
);
1853 ret
= wait_event_interruptible(ring
->irq_queue
,
1855 ring
->get_gem_seqno(dev
, ring
), seqno
)
1856 || atomic_read(&dev_priv
->mm
.wedged
));
1858 wait_event(ring
->irq_queue
,
1860 ring
->get_gem_seqno(dev
, ring
), seqno
)
1861 || atomic_read(&dev_priv
->mm
.wedged
));
1863 ring
->user_irq_put(dev
, ring
);
1864 ring
->waiting_gem_seqno
= 0;
1866 trace_i915_gem_request_wait_end(dev
, seqno
);
1868 if (atomic_read(&dev_priv
->mm
.wedged
))
1871 if (ret
&& ret
!= -ERESTARTSYS
)
1872 DRM_ERROR("%s returns %d (awaiting %d at %d, next %d)\n",
1873 __func__
, ret
, seqno
, ring
->get_gem_seqno(dev
, ring
),
1874 dev_priv
->next_seqno
);
1876 /* Directly dispatch request retiring. While we have the work queue
1877 * to handle this, the waiter on a request often wants an associated
1878 * buffer to have made it to the inactive list, and we would need
1879 * a separate wait queue to handle that.
1882 i915_gem_retire_requests_ring(dev
, ring
);
1888 * Waits for a sequence number to be signaled, and cleans up the
1889 * request and object lists appropriately for that event.
1892 i915_wait_request(struct drm_device
*dev
, uint32_t seqno
,
1893 struct intel_ring_buffer
*ring
)
1895 return i915_do_wait_request(dev
, seqno
, 1, ring
);
1899 i915_gem_flush_ring(struct drm_device
*dev
,
1900 struct intel_ring_buffer
*ring
,
1901 uint32_t invalidate_domains
,
1902 uint32_t flush_domains
)
1904 ring
->flush(dev
, ring
, invalidate_domains
, flush_domains
);
1905 i915_gem_process_flushing_list(dev
, flush_domains
, ring
);
1909 i915_gem_flush(struct drm_device
*dev
,
1910 uint32_t invalidate_domains
,
1911 uint32_t flush_domains
,
1912 uint32_t flush_rings
)
1914 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1916 if (flush_domains
& I915_GEM_DOMAIN_CPU
)
1917 drm_agp_chipset_flush(dev
);
1919 if ((flush_domains
| invalidate_domains
) & I915_GEM_GPU_DOMAINS
) {
1920 if (flush_rings
& RING_RENDER
)
1921 i915_gem_flush_ring(dev
,
1922 &dev_priv
->render_ring
,
1923 invalidate_domains
, flush_domains
);
1924 if (flush_rings
& RING_BSD
)
1925 i915_gem_flush_ring(dev
,
1926 &dev_priv
->bsd_ring
,
1927 invalidate_domains
, flush_domains
);
1932 * Ensures that all rendering to the object has completed and the object is
1933 * safe to unbind from the GTT or access from the CPU.
1936 i915_gem_object_wait_rendering(struct drm_gem_object
*obj
,
1939 struct drm_device
*dev
= obj
->dev
;
1940 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1943 /* This function only exists to support waiting for existing rendering,
1944 * not for emitting required flushes.
1946 BUG_ON((obj
->write_domain
& I915_GEM_GPU_DOMAINS
) != 0);
1948 /* If there is rendering queued on the buffer being evicted, wait for
1951 if (obj_priv
->active
) {
1953 DRM_INFO("%s: object %p wait for seqno %08x\n",
1954 __func__
, obj
, obj_priv
->last_rendering_seqno
);
1956 ret
= i915_do_wait_request(dev
,
1957 obj_priv
->last_rendering_seqno
,
1968 * Unbinds an object from the GTT aperture.
1971 i915_gem_object_unbind(struct drm_gem_object
*obj
)
1973 struct drm_device
*dev
= obj
->dev
;
1974 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1978 DRM_INFO("%s:%d %p\n", __func__
, __LINE__
, obj
);
1979 DRM_INFO("gtt_space %p\n", obj_priv
->gtt_space
);
1981 if (obj_priv
->gtt_space
== NULL
)
1984 if (obj_priv
->pin_count
!= 0) {
1985 DRM_ERROR("Attempting to unbind pinned buffer\n");
1989 /* blow away mappings if mapped through GTT */
1990 i915_gem_release_mmap(obj
);
1992 /* Move the object to the CPU domain to ensure that
1993 * any possible CPU writes while it's not in the GTT
1994 * are flushed when we go to remap it. This will
1995 * also ensure that all pending GPU writes are finished
1998 ret
= i915_gem_object_set_to_cpu_domain(obj
, 1);
1999 if (ret
== -ERESTARTSYS
)
2001 /* Continue on if we fail due to EIO, the GPU is hung so we
2002 * should be safe and we need to cleanup or else we might
2003 * cause memory corruption through use-after-free.
2006 /* release the fence reg _after_ flushing */
2007 if (obj_priv
->fence_reg
!= I915_FENCE_REG_NONE
)
2008 i915_gem_clear_fence_reg(obj
);
2010 if (obj_priv
->agp_mem
!= NULL
) {
2011 drm_unbind_agp(obj_priv
->agp_mem
);
2012 drm_free_agp(obj_priv
->agp_mem
, obj
->size
/ PAGE_SIZE
);
2013 obj_priv
->agp_mem
= NULL
;
2016 i915_gem_object_put_pages(obj
);
2017 BUG_ON(obj_priv
->pages_refcount
);
2019 if (obj_priv
->gtt_space
) {
2020 atomic_dec(&dev
->gtt_count
);
2021 atomic_sub(obj
->size
, &dev
->gtt_memory
);
2023 drm_mm_put_block(obj_priv
->gtt_space
);
2024 obj_priv
->gtt_space
= NULL
;
2027 /* Remove ourselves from the LRU list if present. */
2028 if (!list_empty(&obj_priv
->list
))
2029 list_del_init(&obj_priv
->list
);
2031 if (i915_gem_object_is_purgeable(obj_priv
))
2032 i915_gem_object_truncate(obj
);
2034 trace_i915_gem_object_unbind(obj
);
2040 i915_gpu_idle(struct drm_device
*dev
)
2042 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2046 lists_empty
= (list_empty(&dev_priv
->mm
.flushing_list
) &&
2047 list_empty(&dev_priv
->render_ring
.active_list
) &&
2049 list_empty(&dev_priv
->bsd_ring
.active_list
)));
2053 /* Flush everything onto the inactive list. */
2054 i915_gem_flush_ring(dev
,
2055 &dev_priv
->render_ring
,
2056 I915_GEM_GPU_DOMAINS
, I915_GEM_GPU_DOMAINS
);
2058 ret
= i915_wait_request(dev
,
2059 i915_gem_next_request_seqno(dev
, &dev_priv
->render_ring
),
2060 &dev_priv
->render_ring
);
2065 i915_gem_flush_ring(dev
,
2066 &dev_priv
->bsd_ring
,
2067 I915_GEM_GPU_DOMAINS
, I915_GEM_GPU_DOMAINS
);
2069 ret
= i915_wait_request(dev
,
2070 i915_gem_next_request_seqno(dev
, &dev_priv
->bsd_ring
),
2071 &dev_priv
->bsd_ring
);
2080 i915_gem_object_get_pages(struct drm_gem_object
*obj
,
2083 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2085 struct address_space
*mapping
;
2086 struct inode
*inode
;
2089 BUG_ON(obj_priv
->pages_refcount
2090 == DRM_I915_GEM_OBJECT_MAX_PAGES_REFCOUNT
);
2092 if (obj_priv
->pages_refcount
++ != 0)
2095 /* Get the list of pages out of our struct file. They'll be pinned
2096 * at this point until we release them.
2098 page_count
= obj
->size
/ PAGE_SIZE
;
2099 BUG_ON(obj_priv
->pages
!= NULL
);
2100 obj_priv
->pages
= drm_calloc_large(page_count
, sizeof(struct page
*));
2101 if (obj_priv
->pages
== NULL
) {
2102 obj_priv
->pages_refcount
--;
2106 inode
= obj
->filp
->f_path
.dentry
->d_inode
;
2107 mapping
= inode
->i_mapping
;
2108 for (i
= 0; i
< page_count
; i
++) {
2109 page
= read_cache_page_gfp(mapping
, i
,
2117 obj_priv
->pages
[i
] = page
;
2120 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
)
2121 i915_gem_object_do_bit_17_swizzle(obj
);
2127 page_cache_release(obj_priv
->pages
[i
]);
2129 drm_free_large(obj_priv
->pages
);
2130 obj_priv
->pages
= NULL
;
2131 obj_priv
->pages_refcount
--;
2132 return PTR_ERR(page
);
2135 static void sandybridge_write_fence_reg(struct drm_i915_fence_reg
*reg
)
2137 struct drm_gem_object
*obj
= reg
->obj
;
2138 struct drm_device
*dev
= obj
->dev
;
2139 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2140 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2141 int regnum
= obj_priv
->fence_reg
;
2144 val
= (uint64_t)((obj_priv
->gtt_offset
+ obj
->size
- 4096) &
2146 val
|= obj_priv
->gtt_offset
& 0xfffff000;
2147 val
|= (uint64_t)((obj_priv
->stride
/ 128) - 1) <<
2148 SANDYBRIDGE_FENCE_PITCH_SHIFT
;
2150 if (obj_priv
->tiling_mode
== I915_TILING_Y
)
2151 val
|= 1 << I965_FENCE_TILING_Y_SHIFT
;
2152 val
|= I965_FENCE_REG_VALID
;
2154 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0
+ (regnum
* 8), val
);
2157 static void i965_write_fence_reg(struct drm_i915_fence_reg
*reg
)
2159 struct drm_gem_object
*obj
= reg
->obj
;
2160 struct drm_device
*dev
= obj
->dev
;
2161 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2162 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2163 int regnum
= obj_priv
->fence_reg
;
2166 val
= (uint64_t)((obj_priv
->gtt_offset
+ obj
->size
- 4096) &
2168 val
|= obj_priv
->gtt_offset
& 0xfffff000;
2169 val
|= ((obj_priv
->stride
/ 128) - 1) << I965_FENCE_PITCH_SHIFT
;
2170 if (obj_priv
->tiling_mode
== I915_TILING_Y
)
2171 val
|= 1 << I965_FENCE_TILING_Y_SHIFT
;
2172 val
|= I965_FENCE_REG_VALID
;
2174 I915_WRITE64(FENCE_REG_965_0
+ (regnum
* 8), val
);
2177 static void i915_write_fence_reg(struct drm_i915_fence_reg
*reg
)
2179 struct drm_gem_object
*obj
= reg
->obj
;
2180 struct drm_device
*dev
= obj
->dev
;
2181 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2182 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2183 int regnum
= obj_priv
->fence_reg
;
2185 uint32_t fence_reg
, val
;
2188 if ((obj_priv
->gtt_offset
& ~I915_FENCE_START_MASK
) ||
2189 (obj_priv
->gtt_offset
& (obj
->size
- 1))) {
2190 WARN(1, "%s: object 0x%08x not 1M or size (0x%zx) aligned\n",
2191 __func__
, obj_priv
->gtt_offset
, obj
->size
);
2195 if (obj_priv
->tiling_mode
== I915_TILING_Y
&&
2196 HAS_128_BYTE_Y_TILING(dev
))
2201 /* Note: pitch better be a power of two tile widths */
2202 pitch_val
= obj_priv
->stride
/ tile_width
;
2203 pitch_val
= ffs(pitch_val
) - 1;
2205 if (obj_priv
->tiling_mode
== I915_TILING_Y
&&
2206 HAS_128_BYTE_Y_TILING(dev
))
2207 WARN_ON(pitch_val
> I830_FENCE_MAX_PITCH_VAL
);
2209 WARN_ON(pitch_val
> I915_FENCE_MAX_PITCH_VAL
);
2211 val
= obj_priv
->gtt_offset
;
2212 if (obj_priv
->tiling_mode
== I915_TILING_Y
)
2213 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
2214 val
|= I915_FENCE_SIZE_BITS(obj
->size
);
2215 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
2216 val
|= I830_FENCE_REG_VALID
;
2219 fence_reg
= FENCE_REG_830_0
+ (regnum
* 4);
2221 fence_reg
= FENCE_REG_945_8
+ ((regnum
- 8) * 4);
2222 I915_WRITE(fence_reg
, val
);
2225 static void i830_write_fence_reg(struct drm_i915_fence_reg
*reg
)
2227 struct drm_gem_object
*obj
= reg
->obj
;
2228 struct drm_device
*dev
= obj
->dev
;
2229 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2230 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2231 int regnum
= obj_priv
->fence_reg
;
2234 uint32_t fence_size_bits
;
2236 if ((obj_priv
->gtt_offset
& ~I830_FENCE_START_MASK
) ||
2237 (obj_priv
->gtt_offset
& (obj
->size
- 1))) {
2238 WARN(1, "%s: object 0x%08x not 512K or size aligned\n",
2239 __func__
, obj_priv
->gtt_offset
);
2243 pitch_val
= obj_priv
->stride
/ 128;
2244 pitch_val
= ffs(pitch_val
) - 1;
2245 WARN_ON(pitch_val
> I830_FENCE_MAX_PITCH_VAL
);
2247 val
= obj_priv
->gtt_offset
;
2248 if (obj_priv
->tiling_mode
== I915_TILING_Y
)
2249 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
2250 fence_size_bits
= I830_FENCE_SIZE_BITS(obj
->size
);
2251 WARN_ON(fence_size_bits
& ~0x00000f00);
2252 val
|= fence_size_bits
;
2253 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
2254 val
|= I830_FENCE_REG_VALID
;
2256 I915_WRITE(FENCE_REG_830_0
+ (regnum
* 4), val
);
2259 static int i915_find_fence_reg(struct drm_device
*dev
,
2262 struct drm_i915_fence_reg
*reg
= NULL
;
2263 struct drm_i915_gem_object
*obj_priv
= NULL
;
2264 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2265 struct drm_gem_object
*obj
= NULL
;
2268 /* First try to find a free reg */
2270 for (i
= dev_priv
->fence_reg_start
; i
< dev_priv
->num_fence_regs
; i
++) {
2271 reg
= &dev_priv
->fence_regs
[i
];
2275 obj_priv
= to_intel_bo(reg
->obj
);
2276 if (!obj_priv
->pin_count
)
2283 /* None available, try to steal one or wait for a user to finish */
2284 i
= I915_FENCE_REG_NONE
;
2285 list_for_each_entry(reg
, &dev_priv
->mm
.fence_list
,
2288 obj_priv
= to_intel_bo(obj
);
2290 if (obj_priv
->pin_count
)
2294 i
= obj_priv
->fence_reg
;
2298 BUG_ON(i
== I915_FENCE_REG_NONE
);
2300 /* We only have a reference on obj from the active list. put_fence_reg
2301 * might drop that one, causing a use-after-free in it. So hold a
2302 * private reference to obj like the other callers of put_fence_reg
2303 * (set_tiling ioctl) do. */
2304 drm_gem_object_reference(obj
);
2305 ret
= i915_gem_object_put_fence_reg(obj
, interruptible
);
2306 drm_gem_object_unreference(obj
);
2314 * i915_gem_object_get_fence_reg - set up a fence reg for an object
2315 * @obj: object to map through a fence reg
2317 * When mapping objects through the GTT, userspace wants to be able to write
2318 * to them without having to worry about swizzling if the object is tiled.
2320 * This function walks the fence regs looking for a free one for @obj,
2321 * stealing one if it can't find any.
2323 * It then sets up the reg based on the object's properties: address, pitch
2324 * and tiling format.
2327 i915_gem_object_get_fence_reg(struct drm_gem_object
*obj
,
2330 struct drm_device
*dev
= obj
->dev
;
2331 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2332 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2333 struct drm_i915_fence_reg
*reg
= NULL
;
2336 /* Just update our place in the LRU if our fence is getting used. */
2337 if (obj_priv
->fence_reg
!= I915_FENCE_REG_NONE
) {
2338 reg
= &dev_priv
->fence_regs
[obj_priv
->fence_reg
];
2339 list_move_tail(®
->lru_list
, &dev_priv
->mm
.fence_list
);
2343 switch (obj_priv
->tiling_mode
) {
2344 case I915_TILING_NONE
:
2345 WARN(1, "allocating a fence for non-tiled object?\n");
2348 if (!obj_priv
->stride
)
2350 WARN((obj_priv
->stride
& (512 - 1)),
2351 "object 0x%08x is X tiled but has non-512B pitch\n",
2352 obj_priv
->gtt_offset
);
2355 if (!obj_priv
->stride
)
2357 WARN((obj_priv
->stride
& (128 - 1)),
2358 "object 0x%08x is Y tiled but has non-128B pitch\n",
2359 obj_priv
->gtt_offset
);
2363 ret
= i915_find_fence_reg(dev
, interruptible
);
2367 obj_priv
->fence_reg
= ret
;
2368 reg
= &dev_priv
->fence_regs
[obj_priv
->fence_reg
];
2369 list_add_tail(®
->lru_list
, &dev_priv
->mm
.fence_list
);
2373 switch (INTEL_INFO(dev
)->gen
) {
2375 sandybridge_write_fence_reg(reg
);
2379 i965_write_fence_reg(reg
);
2382 i915_write_fence_reg(reg
);
2385 i830_write_fence_reg(reg
);
2389 trace_i915_gem_object_get_fence(obj
, obj_priv
->fence_reg
,
2390 obj_priv
->tiling_mode
);
2396 * i915_gem_clear_fence_reg - clear out fence register info
2397 * @obj: object to clear
2399 * Zeroes out the fence register itself and clears out the associated
2400 * data structures in dev_priv and obj_priv.
2403 i915_gem_clear_fence_reg(struct drm_gem_object
*obj
)
2405 struct drm_device
*dev
= obj
->dev
;
2406 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2407 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2408 struct drm_i915_fence_reg
*reg
=
2409 &dev_priv
->fence_regs
[obj_priv
->fence_reg
];
2412 switch (INTEL_INFO(dev
)->gen
) {
2414 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0
+
2415 (obj_priv
->fence_reg
* 8), 0);
2419 I915_WRITE64(FENCE_REG_965_0
+ (obj_priv
->fence_reg
* 8), 0);
2422 if (obj_priv
->fence_reg
> 8)
2423 fence_reg
= FENCE_REG_945_8
+ (obj_priv
->fence_reg
- 8) * 4;
2426 fence_reg
= FENCE_REG_830_0
+ obj_priv
->fence_reg
* 4;
2428 I915_WRITE(fence_reg
, 0);
2433 obj_priv
->fence_reg
= I915_FENCE_REG_NONE
;
2434 list_del_init(®
->lru_list
);
2438 * i915_gem_object_put_fence_reg - waits on outstanding fenced access
2439 * to the buffer to finish, and then resets the fence register.
2440 * @obj: tiled object holding a fence register.
2441 * @bool: whether the wait upon the fence is interruptible
2443 * Zeroes out the fence register itself and clears out the associated
2444 * data structures in dev_priv and obj_priv.
2447 i915_gem_object_put_fence_reg(struct drm_gem_object
*obj
,
2450 struct drm_device
*dev
= obj
->dev
;
2451 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2453 if (obj_priv
->fence_reg
== I915_FENCE_REG_NONE
)
2456 /* If we've changed tiling, GTT-mappings of the object
2457 * need to re-fault to ensure that the correct fence register
2458 * setup is in place.
2460 i915_gem_release_mmap(obj
);
2462 /* On the i915, GPU access to tiled buffers is via a fence,
2463 * therefore we must wait for any outstanding access to complete
2464 * before clearing the fence.
2466 if (INTEL_INFO(dev
)->gen
< 4) {
2469 ret
= i915_gem_object_flush_gpu_write_domain(obj
, true);
2473 ret
= i915_gem_object_wait_rendering(obj
, interruptible
);
2478 i915_gem_object_flush_gtt_write_domain(obj
);
2479 i915_gem_clear_fence_reg(obj
);
2485 * Finds free space in the GTT aperture and binds the object there.
2488 i915_gem_object_bind_to_gtt(struct drm_gem_object
*obj
, unsigned alignment
)
2490 struct drm_device
*dev
= obj
->dev
;
2491 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2492 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2493 struct drm_mm_node
*free_space
;
2494 gfp_t gfpmask
= __GFP_NORETRY
| __GFP_NOWARN
;
2497 if (obj_priv
->madv
!= I915_MADV_WILLNEED
) {
2498 DRM_ERROR("Attempting to bind a purgeable object\n");
2503 alignment
= i915_gem_get_gtt_alignment(obj
);
2504 if (alignment
& (i915_gem_get_gtt_alignment(obj
) - 1)) {
2505 DRM_ERROR("Invalid object alignment requested %u\n", alignment
);
2509 /* If the object is bigger than the entire aperture, reject it early
2510 * before evicting everything in a vain attempt to find space.
2512 if (obj
->size
> dev
->gtt_total
) {
2513 DRM_ERROR("Attempting to bind an object larger than the aperture\n");
2518 free_space
= drm_mm_search_free(&dev_priv
->mm
.gtt_space
,
2519 obj
->size
, alignment
, 0);
2520 if (free_space
!= NULL
) {
2521 obj_priv
->gtt_space
= drm_mm_get_block(free_space
, obj
->size
,
2523 if (obj_priv
->gtt_space
!= NULL
)
2524 obj_priv
->gtt_offset
= obj_priv
->gtt_space
->start
;
2526 if (obj_priv
->gtt_space
== NULL
) {
2527 /* If the gtt is empty and we're still having trouble
2528 * fitting our object in, we're out of memory.
2531 DRM_INFO("%s: GTT full, evicting something\n", __func__
);
2533 ret
= i915_gem_evict_something(dev
, obj
->size
, alignment
);
2541 DRM_INFO("Binding object of size %zd at 0x%08x\n",
2542 obj
->size
, obj_priv
->gtt_offset
);
2544 ret
= i915_gem_object_get_pages(obj
, gfpmask
);
2546 drm_mm_put_block(obj_priv
->gtt_space
);
2547 obj_priv
->gtt_space
= NULL
;
2549 if (ret
== -ENOMEM
) {
2550 /* first try to clear up some space from the GTT */
2551 ret
= i915_gem_evict_something(dev
, obj
->size
,
2554 /* now try to shrink everyone else */
2569 /* Create an AGP memory structure pointing at our pages, and bind it
2572 obj_priv
->agp_mem
= drm_agp_bind_pages(dev
,
2574 obj
->size
>> PAGE_SHIFT
,
2575 obj_priv
->gtt_offset
,
2576 obj_priv
->agp_type
);
2577 if (obj_priv
->agp_mem
== NULL
) {
2578 i915_gem_object_put_pages(obj
);
2579 drm_mm_put_block(obj_priv
->gtt_space
);
2580 obj_priv
->gtt_space
= NULL
;
2582 ret
= i915_gem_evict_something(dev
, obj
->size
, alignment
);
2588 atomic_inc(&dev
->gtt_count
);
2589 atomic_add(obj
->size
, &dev
->gtt_memory
);
2591 /* keep track of bounds object by adding it to the inactive list */
2592 list_add_tail(&obj_priv
->list
, &dev_priv
->mm
.inactive_list
);
2594 /* Assert that the object is not currently in any GPU domain. As it
2595 * wasn't in the GTT, there shouldn't be any way it could have been in
2598 BUG_ON(obj
->read_domains
& I915_GEM_GPU_DOMAINS
);
2599 BUG_ON(obj
->write_domain
& I915_GEM_GPU_DOMAINS
);
2601 trace_i915_gem_object_bind(obj
, obj_priv
->gtt_offset
);
2607 i915_gem_clflush_object(struct drm_gem_object
*obj
)
2609 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2611 /* If we don't have a page list set up, then we're not pinned
2612 * to GPU, and we can ignore the cache flush because it'll happen
2613 * again at bind time.
2615 if (obj_priv
->pages
== NULL
)
2618 trace_i915_gem_object_clflush(obj
);
2620 drm_clflush_pages(obj_priv
->pages
, obj
->size
/ PAGE_SIZE
);
2623 /** Flushes any GPU write domain for the object if it's dirty. */
2625 i915_gem_object_flush_gpu_write_domain(struct drm_gem_object
*obj
,
2628 struct drm_device
*dev
= obj
->dev
;
2629 uint32_t old_write_domain
;
2631 if ((obj
->write_domain
& I915_GEM_GPU_DOMAINS
) == 0)
2634 /* Queue the GPU write cache flushing we need. */
2635 old_write_domain
= obj
->write_domain
;
2636 i915_gem_flush_ring(dev
,
2637 to_intel_bo(obj
)->ring
,
2638 0, obj
->write_domain
);
2639 BUG_ON(obj
->write_domain
);
2641 trace_i915_gem_object_change_domain(obj
,
2648 return i915_gem_object_wait_rendering(obj
, true);
2651 /** Flushes the GTT write domain for the object if it's dirty. */
2653 i915_gem_object_flush_gtt_write_domain(struct drm_gem_object
*obj
)
2655 uint32_t old_write_domain
;
2657 if (obj
->write_domain
!= I915_GEM_DOMAIN_GTT
)
2660 /* No actual flushing is required for the GTT write domain. Writes
2661 * to it immediately go to main memory as far as we know, so there's
2662 * no chipset flush. It also doesn't land in render cache.
2664 old_write_domain
= obj
->write_domain
;
2665 obj
->write_domain
= 0;
2667 trace_i915_gem_object_change_domain(obj
,
2672 /** Flushes the CPU write domain for the object if it's dirty. */
2674 i915_gem_object_flush_cpu_write_domain(struct drm_gem_object
*obj
)
2676 struct drm_device
*dev
= obj
->dev
;
2677 uint32_t old_write_domain
;
2679 if (obj
->write_domain
!= I915_GEM_DOMAIN_CPU
)
2682 i915_gem_clflush_object(obj
);
2683 drm_agp_chipset_flush(dev
);
2684 old_write_domain
= obj
->write_domain
;
2685 obj
->write_domain
= 0;
2687 trace_i915_gem_object_change_domain(obj
,
2693 * Moves a single object to the GTT read, and possibly write domain.
2695 * This function returns when the move is complete, including waiting on
2699 i915_gem_object_set_to_gtt_domain(struct drm_gem_object
*obj
, int write
)
2701 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2702 uint32_t old_write_domain
, old_read_domains
;
2705 /* Not valid to be called on unbound objects. */
2706 if (obj_priv
->gtt_space
== NULL
)
2709 ret
= i915_gem_object_flush_gpu_write_domain(obj
, false);
2713 i915_gem_object_flush_cpu_write_domain(obj
);
2716 ret
= i915_gem_object_wait_rendering(obj
, true);
2721 old_write_domain
= obj
->write_domain
;
2722 old_read_domains
= obj
->read_domains
;
2724 /* It should now be out of any other write domains, and we can update
2725 * the domain values for our changes.
2727 BUG_ON((obj
->write_domain
& ~I915_GEM_DOMAIN_GTT
) != 0);
2728 obj
->read_domains
|= I915_GEM_DOMAIN_GTT
;
2730 obj
->read_domains
= I915_GEM_DOMAIN_GTT
;
2731 obj
->write_domain
= I915_GEM_DOMAIN_GTT
;
2732 obj_priv
->dirty
= 1;
2735 trace_i915_gem_object_change_domain(obj
,
2743 * Prepare buffer for display plane. Use uninterruptible for possible flush
2744 * wait, as in modesetting process we're not supposed to be interrupted.
2747 i915_gem_object_set_to_display_plane(struct drm_gem_object
*obj
,
2750 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2751 uint32_t old_read_domains
;
2754 /* Not valid to be called on unbound objects. */
2755 if (obj_priv
->gtt_space
== NULL
)
2758 ret
= i915_gem_object_flush_gpu_write_domain(obj
, pipelined
);
2762 i915_gem_object_flush_cpu_write_domain(obj
);
2764 old_read_domains
= obj
->read_domains
;
2765 obj
->read_domains
= I915_GEM_DOMAIN_GTT
;
2767 trace_i915_gem_object_change_domain(obj
,
2775 * Moves a single object to the CPU read, and possibly write domain.
2777 * This function returns when the move is complete, including waiting on
2781 i915_gem_object_set_to_cpu_domain(struct drm_gem_object
*obj
, int write
)
2783 uint32_t old_write_domain
, old_read_domains
;
2786 ret
= i915_gem_object_flush_gpu_write_domain(obj
, false);
2790 i915_gem_object_flush_gtt_write_domain(obj
);
2792 /* If we have a partially-valid cache of the object in the CPU,
2793 * finish invalidating it and free the per-page flags.
2795 i915_gem_object_set_to_full_cpu_read_domain(obj
);
2798 ret
= i915_gem_object_wait_rendering(obj
, true);
2803 old_write_domain
= obj
->write_domain
;
2804 old_read_domains
= obj
->read_domains
;
2806 /* Flush the CPU cache if it's still invalid. */
2807 if ((obj
->read_domains
& I915_GEM_DOMAIN_CPU
) == 0) {
2808 i915_gem_clflush_object(obj
);
2810 obj
->read_domains
|= I915_GEM_DOMAIN_CPU
;
2813 /* It should now be out of any other write domains, and we can update
2814 * the domain values for our changes.
2816 BUG_ON((obj
->write_domain
& ~I915_GEM_DOMAIN_CPU
) != 0);
2818 /* If we're writing through the CPU, then the GPU read domains will
2819 * need to be invalidated at next use.
2822 obj
->read_domains
&= I915_GEM_DOMAIN_CPU
;
2823 obj
->write_domain
= I915_GEM_DOMAIN_CPU
;
2826 trace_i915_gem_object_change_domain(obj
,
2834 * Set the next domain for the specified object. This
2835 * may not actually perform the necessary flushing/invaliding though,
2836 * as that may want to be batched with other set_domain operations
2838 * This is (we hope) the only really tricky part of gem. The goal
2839 * is fairly simple -- track which caches hold bits of the object
2840 * and make sure they remain coherent. A few concrete examples may
2841 * help to explain how it works. For shorthand, we use the notation
2842 * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the
2843 * a pair of read and write domain masks.
2845 * Case 1: the batch buffer
2851 * 5. Unmapped from GTT
2854 * Let's take these a step at a time
2857 * Pages allocated from the kernel may still have
2858 * cache contents, so we set them to (CPU, CPU) always.
2859 * 2. Written by CPU (using pwrite)
2860 * The pwrite function calls set_domain (CPU, CPU) and
2861 * this function does nothing (as nothing changes)
2863 * This function asserts that the object is not
2864 * currently in any GPU-based read or write domains
2866 * i915_gem_execbuffer calls set_domain (COMMAND, 0).
2867 * As write_domain is zero, this function adds in the
2868 * current read domains (CPU+COMMAND, 0).
2869 * flush_domains is set to CPU.
2870 * invalidate_domains is set to COMMAND
2871 * clflush is run to get data out of the CPU caches
2872 * then i915_dev_set_domain calls i915_gem_flush to
2873 * emit an MI_FLUSH and drm_agp_chipset_flush
2874 * 5. Unmapped from GTT
2875 * i915_gem_object_unbind calls set_domain (CPU, CPU)
2876 * flush_domains and invalidate_domains end up both zero
2877 * so no flushing/invalidating happens
2881 * Case 2: The shared render buffer
2885 * 3. Read/written by GPU
2886 * 4. set_domain to (CPU,CPU)
2887 * 5. Read/written by CPU
2888 * 6. Read/written by GPU
2891 * Same as last example, (CPU, CPU)
2893 * Nothing changes (assertions find that it is not in the GPU)
2894 * 3. Read/written by GPU
2895 * execbuffer calls set_domain (RENDER, RENDER)
2896 * flush_domains gets CPU
2897 * invalidate_domains gets GPU
2899 * MI_FLUSH and drm_agp_chipset_flush
2900 * 4. set_domain (CPU, CPU)
2901 * flush_domains gets GPU
2902 * invalidate_domains gets CPU
2903 * wait_rendering (obj) to make sure all drawing is complete.
2904 * This will include an MI_FLUSH to get the data from GPU
2906 * clflush (obj) to invalidate the CPU cache
2907 * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?)
2908 * 5. Read/written by CPU
2909 * cache lines are loaded and dirtied
2910 * 6. Read written by GPU
2911 * Same as last GPU access
2913 * Case 3: The constant buffer
2918 * 4. Updated (written) by CPU again
2927 * flush_domains = CPU
2928 * invalidate_domains = RENDER
2931 * drm_agp_chipset_flush
2932 * 4. Updated (written) by CPU again
2934 * flush_domains = 0 (no previous write domain)
2935 * invalidate_domains = 0 (no new read domains)
2938 * flush_domains = CPU
2939 * invalidate_domains = RENDER
2942 * drm_agp_chipset_flush
2945 i915_gem_object_set_to_gpu_domain(struct drm_gem_object
*obj
)
2947 struct drm_device
*dev
= obj
->dev
;
2948 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2949 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2950 uint32_t invalidate_domains
= 0;
2951 uint32_t flush_domains
= 0;
2952 uint32_t old_read_domains
;
2954 BUG_ON(obj
->pending_read_domains
& I915_GEM_DOMAIN_CPU
);
2955 BUG_ON(obj
->pending_write_domain
== I915_GEM_DOMAIN_CPU
);
2957 intel_mark_busy(dev
, obj
);
2960 DRM_INFO("%s: object %p read %08x -> %08x write %08x -> %08x\n",
2962 obj
->read_domains
, obj
->pending_read_domains
,
2963 obj
->write_domain
, obj
->pending_write_domain
);
2966 * If the object isn't moving to a new write domain,
2967 * let the object stay in multiple read domains
2969 if (obj
->pending_write_domain
== 0)
2970 obj
->pending_read_domains
|= obj
->read_domains
;
2972 obj_priv
->dirty
= 1;
2975 * Flush the current write domain if
2976 * the new read domains don't match. Invalidate
2977 * any read domains which differ from the old
2980 if (obj
->write_domain
&&
2981 obj
->write_domain
!= obj
->pending_read_domains
) {
2982 flush_domains
|= obj
->write_domain
;
2983 invalidate_domains
|=
2984 obj
->pending_read_domains
& ~obj
->write_domain
;
2987 * Invalidate any read caches which may have
2988 * stale data. That is, any new read domains.
2990 invalidate_domains
|= obj
->pending_read_domains
& ~obj
->read_domains
;
2991 if ((flush_domains
| invalidate_domains
) & I915_GEM_DOMAIN_CPU
) {
2993 DRM_INFO("%s: CPU domain flush %08x invalidate %08x\n",
2994 __func__
, flush_domains
, invalidate_domains
);
2996 i915_gem_clflush_object(obj
);
2999 old_read_domains
= obj
->read_domains
;
3001 /* The actual obj->write_domain will be updated with
3002 * pending_write_domain after we emit the accumulated flush for all
3003 * of our domain changes in execbuffers (which clears objects'
3004 * write_domains). So if we have a current write domain that we
3005 * aren't changing, set pending_write_domain to that.
3007 if (flush_domains
== 0 && obj
->pending_write_domain
== 0)
3008 obj
->pending_write_domain
= obj
->write_domain
;
3009 obj
->read_domains
= obj
->pending_read_domains
;
3011 dev
->invalidate_domains
|= invalidate_domains
;
3012 dev
->flush_domains
|= flush_domains
;
3014 dev_priv
->mm
.flush_rings
|= obj_priv
->ring
->id
;
3016 DRM_INFO("%s: read %08x write %08x invalidate %08x flush %08x\n",
3018 obj
->read_domains
, obj
->write_domain
,
3019 dev
->invalidate_domains
, dev
->flush_domains
);
3022 trace_i915_gem_object_change_domain(obj
,
3028 * Moves the object from a partially CPU read to a full one.
3030 * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(),
3031 * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU).
3034 i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object
*obj
)
3036 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
3038 if (!obj_priv
->page_cpu_valid
)
3041 /* If we're partially in the CPU read domain, finish moving it in.
3043 if (obj
->read_domains
& I915_GEM_DOMAIN_CPU
) {
3046 for (i
= 0; i
<= (obj
->size
- 1) / PAGE_SIZE
; i
++) {
3047 if (obj_priv
->page_cpu_valid
[i
])
3049 drm_clflush_pages(obj_priv
->pages
+ i
, 1);
3053 /* Free the page_cpu_valid mappings which are now stale, whether
3054 * or not we've got I915_GEM_DOMAIN_CPU.
3056 kfree(obj_priv
->page_cpu_valid
);
3057 obj_priv
->page_cpu_valid
= NULL
;
3061 * Set the CPU read domain on a range of the object.
3063 * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's
3064 * not entirely valid. The page_cpu_valid member of the object flags which
3065 * pages have been flushed, and will be respected by
3066 * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping
3067 * of the whole object.
3069 * This function returns when the move is complete, including waiting on
3073 i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object
*obj
,
3074 uint64_t offset
, uint64_t size
)
3076 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
3077 uint32_t old_read_domains
;
3080 if (offset
== 0 && size
== obj
->size
)
3081 return i915_gem_object_set_to_cpu_domain(obj
, 0);
3083 ret
= i915_gem_object_flush_gpu_write_domain(obj
, false);
3086 i915_gem_object_flush_gtt_write_domain(obj
);
3088 /* If we're already fully in the CPU read domain, we're done. */
3089 if (obj_priv
->page_cpu_valid
== NULL
&&
3090 (obj
->read_domains
& I915_GEM_DOMAIN_CPU
) != 0)
3093 /* Otherwise, create/clear the per-page CPU read domain flag if we're
3094 * newly adding I915_GEM_DOMAIN_CPU
3096 if (obj_priv
->page_cpu_valid
== NULL
) {
3097 obj_priv
->page_cpu_valid
= kzalloc(obj
->size
/ PAGE_SIZE
,
3099 if (obj_priv
->page_cpu_valid
== NULL
)
3101 } else if ((obj
->read_domains
& I915_GEM_DOMAIN_CPU
) == 0)
3102 memset(obj_priv
->page_cpu_valid
, 0, obj
->size
/ PAGE_SIZE
);
3104 /* Flush the cache on any pages that are still invalid from the CPU's
3107 for (i
= offset
/ PAGE_SIZE
; i
<= (offset
+ size
- 1) / PAGE_SIZE
;
3109 if (obj_priv
->page_cpu_valid
[i
])
3112 drm_clflush_pages(obj_priv
->pages
+ i
, 1);
3114 obj_priv
->page_cpu_valid
[i
] = 1;
3117 /* It should now be out of any other write domains, and we can update
3118 * the domain values for our changes.
3120 BUG_ON((obj
->write_domain
& ~I915_GEM_DOMAIN_CPU
) != 0);
3122 old_read_domains
= obj
->read_domains
;
3123 obj
->read_domains
|= I915_GEM_DOMAIN_CPU
;
3125 trace_i915_gem_object_change_domain(obj
,
3133 * Pin an object to the GTT and evaluate the relocations landing in it.
3136 i915_gem_object_pin_and_relocate(struct drm_gem_object
*obj
,
3137 struct drm_file
*file_priv
,
3138 struct drm_i915_gem_exec_object2
*entry
,
3139 struct drm_i915_gem_relocation_entry
*relocs
)
3141 struct drm_device
*dev
= obj
->dev
;
3142 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3143 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
3145 void __iomem
*reloc_page
;
3148 need_fence
= entry
->flags
& EXEC_OBJECT_NEEDS_FENCE
&&
3149 obj_priv
->tiling_mode
!= I915_TILING_NONE
;
3151 /* Check fence reg constraints and rebind if necessary */
3153 !i915_gem_object_fence_offset_ok(obj
,
3154 obj_priv
->tiling_mode
)) {
3155 ret
= i915_gem_object_unbind(obj
);
3160 /* Choose the GTT offset for our buffer and put it there. */
3161 ret
= i915_gem_object_pin(obj
, (uint32_t) entry
->alignment
);
3166 * Pre-965 chips need a fence register set up in order to
3167 * properly handle blits to/from tiled surfaces.
3170 ret
= i915_gem_object_get_fence_reg(obj
, false);
3172 i915_gem_object_unpin(obj
);
3177 entry
->offset
= obj_priv
->gtt_offset
;
3179 /* Apply the relocations, using the GTT aperture to avoid cache
3180 * flushing requirements.
3182 for (i
= 0; i
< entry
->relocation_count
; i
++) {
3183 struct drm_i915_gem_relocation_entry
*reloc
= &relocs
[i
];
3184 struct drm_gem_object
*target_obj
;
3185 struct drm_i915_gem_object
*target_obj_priv
;
3186 uint32_t reloc_val
, reloc_offset
;
3187 uint32_t __iomem
*reloc_entry
;
3189 target_obj
= drm_gem_object_lookup(obj
->dev
, file_priv
,
3190 reloc
->target_handle
);
3191 if (target_obj
== NULL
) {
3192 i915_gem_object_unpin(obj
);
3195 target_obj_priv
= to_intel_bo(target_obj
);
3198 DRM_INFO("%s: obj %p offset %08x target %d "
3199 "read %08x write %08x gtt %08x "
3200 "presumed %08x delta %08x\n",
3203 (int) reloc
->offset
,
3204 (int) reloc
->target_handle
,
3205 (int) reloc
->read_domains
,
3206 (int) reloc
->write_domain
,
3207 (int) target_obj_priv
->gtt_offset
,
3208 (int) reloc
->presumed_offset
,
3212 /* The target buffer should have appeared before us in the
3213 * exec_object list, so it should have a GTT space bound by now.
3215 if (target_obj_priv
->gtt_space
== NULL
) {
3216 DRM_ERROR("No GTT space found for object %d\n",
3217 reloc
->target_handle
);
3218 drm_gem_object_unreference(target_obj
);
3219 i915_gem_object_unpin(obj
);
3223 /* Validate that the target is in a valid r/w GPU domain */
3224 if (reloc
->write_domain
& (reloc
->write_domain
- 1)) {
3225 DRM_ERROR("reloc with multiple write domains: "
3226 "obj %p target %d offset %d "
3227 "read %08x write %08x",
3228 obj
, reloc
->target_handle
,
3229 (int) reloc
->offset
,
3230 reloc
->read_domains
,
3231 reloc
->write_domain
);
3234 if (reloc
->write_domain
& I915_GEM_DOMAIN_CPU
||
3235 reloc
->read_domains
& I915_GEM_DOMAIN_CPU
) {
3236 DRM_ERROR("reloc with read/write CPU domains: "
3237 "obj %p target %d offset %d "
3238 "read %08x write %08x",
3239 obj
, reloc
->target_handle
,
3240 (int) reloc
->offset
,
3241 reloc
->read_domains
,
3242 reloc
->write_domain
);
3243 drm_gem_object_unreference(target_obj
);
3244 i915_gem_object_unpin(obj
);
3247 if (reloc
->write_domain
&& target_obj
->pending_write_domain
&&
3248 reloc
->write_domain
!= target_obj
->pending_write_domain
) {
3249 DRM_ERROR("Write domain conflict: "
3250 "obj %p target %d offset %d "
3251 "new %08x old %08x\n",
3252 obj
, reloc
->target_handle
,
3253 (int) reloc
->offset
,
3254 reloc
->write_domain
,
3255 target_obj
->pending_write_domain
);
3256 drm_gem_object_unreference(target_obj
);
3257 i915_gem_object_unpin(obj
);
3261 target_obj
->pending_read_domains
|= reloc
->read_domains
;
3262 target_obj
->pending_write_domain
|= reloc
->write_domain
;
3264 /* If the relocation already has the right value in it, no
3265 * more work needs to be done.
3267 if (target_obj_priv
->gtt_offset
== reloc
->presumed_offset
) {
3268 drm_gem_object_unreference(target_obj
);
3272 /* Check that the relocation address is valid... */
3273 if (reloc
->offset
> obj
->size
- 4) {
3274 DRM_ERROR("Relocation beyond object bounds: "
3275 "obj %p target %d offset %d size %d.\n",
3276 obj
, reloc
->target_handle
,
3277 (int) reloc
->offset
, (int) obj
->size
);
3278 drm_gem_object_unreference(target_obj
);
3279 i915_gem_object_unpin(obj
);
3282 if (reloc
->offset
& 3) {
3283 DRM_ERROR("Relocation not 4-byte aligned: "
3284 "obj %p target %d offset %d.\n",
3285 obj
, reloc
->target_handle
,
3286 (int) reloc
->offset
);
3287 drm_gem_object_unreference(target_obj
);
3288 i915_gem_object_unpin(obj
);
3292 /* and points to somewhere within the target object. */
3293 if (reloc
->delta
>= target_obj
->size
) {
3294 DRM_ERROR("Relocation beyond target object bounds: "
3295 "obj %p target %d delta %d size %d.\n",
3296 obj
, reloc
->target_handle
,
3297 (int) reloc
->delta
, (int) target_obj
->size
);
3298 drm_gem_object_unreference(target_obj
);
3299 i915_gem_object_unpin(obj
);
3303 ret
= i915_gem_object_set_to_gtt_domain(obj
, 1);
3305 drm_gem_object_unreference(target_obj
);
3306 i915_gem_object_unpin(obj
);
3310 /* Map the page containing the relocation we're going to
3313 reloc_offset
= obj_priv
->gtt_offset
+ reloc
->offset
;
3314 reloc_page
= io_mapping_map_atomic_wc(dev_priv
->mm
.gtt_mapping
,
3318 reloc_entry
= (uint32_t __iomem
*)(reloc_page
+
3319 (reloc_offset
& (PAGE_SIZE
- 1)));
3320 reloc_val
= target_obj_priv
->gtt_offset
+ reloc
->delta
;
3323 DRM_INFO("Applied relocation: %p@0x%08x %08x -> %08x\n",
3324 obj
, (unsigned int) reloc
->offset
,
3325 readl(reloc_entry
), reloc_val
);
3327 writel(reloc_val
, reloc_entry
);
3328 io_mapping_unmap_atomic(reloc_page
, KM_USER0
);
3330 /* The updated presumed offset for this entry will be
3331 * copied back out to the user.
3333 reloc
->presumed_offset
= target_obj_priv
->gtt_offset
;
3335 drm_gem_object_unreference(target_obj
);
3340 i915_gem_dump_object(obj
, 128, __func__
, ~0);
3345 /* Throttle our rendering by waiting until the ring has completed our requests
3346 * emitted over 20 msec ago.
3348 * Note that if we were to use the current jiffies each time around the loop,
3349 * we wouldn't escape the function with any frames outstanding if the time to
3350 * render a frame was over 20ms.
3352 * This should get us reasonable parallelism between CPU and GPU but also
3353 * relatively low latency when blocking on a particular request to finish.
3356 i915_gem_ring_throttle(struct drm_device
*dev
, struct drm_file
*file_priv
)
3358 struct drm_i915_file_private
*i915_file_priv
= file_priv
->driver_priv
;
3360 unsigned long recent_enough
= jiffies
- msecs_to_jiffies(20);
3362 mutex_lock(&dev
->struct_mutex
);
3363 while (!list_empty(&i915_file_priv
->mm
.request_list
)) {
3364 struct drm_i915_gem_request
*request
;
3366 request
= list_first_entry(&i915_file_priv
->mm
.request_list
,
3367 struct drm_i915_gem_request
,
3370 if (time_after_eq(request
->emitted_jiffies
, recent_enough
))
3373 ret
= i915_wait_request(dev
, request
->seqno
, request
->ring
);
3377 mutex_unlock(&dev
->struct_mutex
);
3383 i915_gem_get_relocs_from_user(struct drm_i915_gem_exec_object2
*exec_list
,
3384 uint32_t buffer_count
,
3385 struct drm_i915_gem_relocation_entry
**relocs
)
3387 uint32_t reloc_count
= 0, reloc_index
= 0, i
;
3391 for (i
= 0; i
< buffer_count
; i
++) {
3392 if (reloc_count
+ exec_list
[i
].relocation_count
< reloc_count
)
3394 reloc_count
+= exec_list
[i
].relocation_count
;
3397 *relocs
= drm_calloc_large(reloc_count
, sizeof(**relocs
));
3398 if (*relocs
== NULL
) {
3399 DRM_ERROR("failed to alloc relocs, count %d\n", reloc_count
);
3403 for (i
= 0; i
< buffer_count
; i
++) {
3404 struct drm_i915_gem_relocation_entry __user
*user_relocs
;
3406 user_relocs
= (void __user
*)(uintptr_t)exec_list
[i
].relocs_ptr
;
3408 ret
= copy_from_user(&(*relocs
)[reloc_index
],
3410 exec_list
[i
].relocation_count
*
3413 drm_free_large(*relocs
);
3418 reloc_index
+= exec_list
[i
].relocation_count
;
3425 i915_gem_put_relocs_to_user(struct drm_i915_gem_exec_object2
*exec_list
,
3426 uint32_t buffer_count
,
3427 struct drm_i915_gem_relocation_entry
*relocs
)
3429 uint32_t reloc_count
= 0, i
;
3435 for (i
= 0; i
< buffer_count
; i
++) {
3436 struct drm_i915_gem_relocation_entry __user
*user_relocs
;
3439 user_relocs
= (void __user
*)(uintptr_t)exec_list
[i
].relocs_ptr
;
3441 unwritten
= copy_to_user(user_relocs
,
3442 &relocs
[reloc_count
],
3443 exec_list
[i
].relocation_count
*
3451 reloc_count
+= exec_list
[i
].relocation_count
;
3455 drm_free_large(relocs
);
3461 i915_gem_check_execbuffer (struct drm_i915_gem_execbuffer2
*exec
,
3462 uint64_t exec_offset
)
3464 uint32_t exec_start
, exec_len
;
3466 exec_start
= (uint32_t) exec_offset
+ exec
->batch_start_offset
;
3467 exec_len
= (uint32_t) exec
->batch_len
;
3469 if ((exec_start
| exec_len
) & 0x7)
3479 i915_gem_wait_for_pending_flip(struct drm_device
*dev
,
3480 struct drm_gem_object
**object_list
,
3483 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3484 struct drm_i915_gem_object
*obj_priv
;
3489 prepare_to_wait(&dev_priv
->pending_flip_queue
,
3490 &wait
, TASK_INTERRUPTIBLE
);
3491 for (i
= 0; i
< count
; i
++) {
3492 obj_priv
= to_intel_bo(object_list
[i
]);
3493 if (atomic_read(&obj_priv
->pending_flip
) > 0)
3499 if (!signal_pending(current
)) {
3500 mutex_unlock(&dev
->struct_mutex
);
3502 mutex_lock(&dev
->struct_mutex
);
3508 finish_wait(&dev_priv
->pending_flip_queue
, &wait
);
3514 i915_gem_do_execbuffer(struct drm_device
*dev
, void *data
,
3515 struct drm_file
*file_priv
,
3516 struct drm_i915_gem_execbuffer2
*args
,
3517 struct drm_i915_gem_exec_object2
*exec_list
)
3519 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3520 struct drm_gem_object
**object_list
= NULL
;
3521 struct drm_gem_object
*batch_obj
;
3522 struct drm_i915_gem_object
*obj_priv
;
3523 struct drm_clip_rect
*cliprects
= NULL
;
3524 struct drm_i915_gem_relocation_entry
*relocs
= NULL
;
3525 struct drm_i915_gem_request
*request
= NULL
;
3526 int ret
= 0, ret2
, i
, pinned
= 0;
3527 uint64_t exec_offset
;
3528 uint32_t seqno
, reloc_index
;
3529 int pin_tries
, flips
;
3531 struct intel_ring_buffer
*ring
= NULL
;
3534 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3535 (int) args
->buffers_ptr
, args
->buffer_count
, args
->batch_len
);
3537 if (args
->flags
& I915_EXEC_BSD
) {
3538 if (!HAS_BSD(dev
)) {
3539 DRM_ERROR("execbuf with wrong flag\n");
3542 ring
= &dev_priv
->bsd_ring
;
3544 ring
= &dev_priv
->render_ring
;
3547 if (args
->buffer_count
< 1) {
3548 DRM_ERROR("execbuf with %d buffers\n", args
->buffer_count
);
3551 object_list
= drm_malloc_ab(sizeof(*object_list
), args
->buffer_count
);
3552 if (object_list
== NULL
) {
3553 DRM_ERROR("Failed to allocate object list for %d buffers\n",
3554 args
->buffer_count
);
3559 if (args
->num_cliprects
!= 0) {
3560 cliprects
= kcalloc(args
->num_cliprects
, sizeof(*cliprects
),
3562 if (cliprects
== NULL
) {
3567 ret
= copy_from_user(cliprects
,
3568 (struct drm_clip_rect __user
*)
3569 (uintptr_t) args
->cliprects_ptr
,
3570 sizeof(*cliprects
) * args
->num_cliprects
);
3572 DRM_ERROR("copy %d cliprects failed: %d\n",
3573 args
->num_cliprects
, ret
);
3579 request
= kzalloc(sizeof(*request
), GFP_KERNEL
);
3580 if (request
== NULL
) {
3585 ret
= i915_gem_get_relocs_from_user(exec_list
, args
->buffer_count
,
3590 mutex_lock(&dev
->struct_mutex
);
3592 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
3594 if (atomic_read(&dev_priv
->mm
.wedged
)) {
3595 mutex_unlock(&dev
->struct_mutex
);
3600 if (dev_priv
->mm
.suspended
) {
3601 mutex_unlock(&dev
->struct_mutex
);
3606 /* Look up object handles */
3608 for (i
= 0; i
< args
->buffer_count
; i
++) {
3609 object_list
[i
] = drm_gem_object_lookup(dev
, file_priv
,
3610 exec_list
[i
].handle
);
3611 if (object_list
[i
] == NULL
) {
3612 DRM_ERROR("Invalid object handle %d at index %d\n",
3613 exec_list
[i
].handle
, i
);
3614 /* prevent error path from reading uninitialized data */
3615 args
->buffer_count
= i
+ 1;
3620 obj_priv
= to_intel_bo(object_list
[i
]);
3621 if (obj_priv
->in_execbuffer
) {
3622 DRM_ERROR("Object %p appears more than once in object list\n",
3624 /* prevent error path from reading uninitialized data */
3625 args
->buffer_count
= i
+ 1;
3629 obj_priv
->in_execbuffer
= true;
3630 flips
+= atomic_read(&obj_priv
->pending_flip
);
3634 ret
= i915_gem_wait_for_pending_flip(dev
, object_list
,
3635 args
->buffer_count
);
3640 /* Pin and relocate */
3641 for (pin_tries
= 0; ; pin_tries
++) {
3645 for (i
= 0; i
< args
->buffer_count
; i
++) {
3646 object_list
[i
]->pending_read_domains
= 0;
3647 object_list
[i
]->pending_write_domain
= 0;
3648 ret
= i915_gem_object_pin_and_relocate(object_list
[i
],
3651 &relocs
[reloc_index
]);
3655 reloc_index
+= exec_list
[i
].relocation_count
;
3661 /* error other than GTT full, or we've already tried again */
3662 if (ret
!= -ENOSPC
|| pin_tries
>= 1) {
3663 if (ret
!= -ERESTARTSYS
) {
3664 unsigned long long total_size
= 0;
3666 for (i
= 0; i
< args
->buffer_count
; i
++) {
3667 obj_priv
= to_intel_bo(object_list
[i
]);
3669 total_size
+= object_list
[i
]->size
;
3671 exec_list
[i
].flags
& EXEC_OBJECT_NEEDS_FENCE
&&
3672 obj_priv
->tiling_mode
!= I915_TILING_NONE
;
3674 DRM_ERROR("Failed to pin buffer %d of %d, total %llu bytes, %d fences: %d\n",
3675 pinned
+1, args
->buffer_count
,
3676 total_size
, num_fences
,
3678 DRM_ERROR("%d objects [%d pinned], "
3679 "%d object bytes [%d pinned], "
3680 "%d/%d gtt bytes\n",
3681 atomic_read(&dev
->object_count
),
3682 atomic_read(&dev
->pin_count
),
3683 atomic_read(&dev
->object_memory
),
3684 atomic_read(&dev
->pin_memory
),
3685 atomic_read(&dev
->gtt_memory
),
3691 /* unpin all of our buffers */
3692 for (i
= 0; i
< pinned
; i
++)
3693 i915_gem_object_unpin(object_list
[i
]);
3696 /* evict everyone we can from the aperture */
3697 ret
= i915_gem_evict_everything(dev
);
3698 if (ret
&& ret
!= -ENOSPC
)
3702 /* Set the pending read domains for the batch buffer to COMMAND */
3703 batch_obj
= object_list
[args
->buffer_count
-1];
3704 if (batch_obj
->pending_write_domain
) {
3705 DRM_ERROR("Attempting to use self-modifying batch buffer\n");
3709 batch_obj
->pending_read_domains
|= I915_GEM_DOMAIN_COMMAND
;
3711 /* Sanity check the batch buffer, prior to moving objects */
3712 exec_offset
= exec_list
[args
->buffer_count
- 1].offset
;
3713 ret
= i915_gem_check_execbuffer (args
, exec_offset
);
3715 DRM_ERROR("execbuf with invalid offset/length\n");
3719 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
3721 /* Zero the global flush/invalidate flags. These
3722 * will be modified as new domains are computed
3725 dev
->invalidate_domains
= 0;
3726 dev
->flush_domains
= 0;
3727 dev_priv
->mm
.flush_rings
= 0;
3729 for (i
= 0; i
< args
->buffer_count
; i
++) {
3730 struct drm_gem_object
*obj
= object_list
[i
];
3732 /* Compute new gpu domains and update invalidate/flush */
3733 i915_gem_object_set_to_gpu_domain(obj
);
3736 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
3738 if (dev
->invalidate_domains
| dev
->flush_domains
) {
3740 DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n",
3742 dev
->invalidate_domains
,
3743 dev
->flush_domains
);
3746 dev
->invalidate_domains
,
3748 dev_priv
->mm
.flush_rings
);
3751 if (dev_priv
->render_ring
.outstanding_lazy_request
) {
3752 (void)i915_add_request(dev
, file_priv
, NULL
, &dev_priv
->render_ring
);
3753 dev_priv
->render_ring
.outstanding_lazy_request
= false;
3755 if (dev_priv
->bsd_ring
.outstanding_lazy_request
) {
3756 (void)i915_add_request(dev
, file_priv
, NULL
, &dev_priv
->bsd_ring
);
3757 dev_priv
->bsd_ring
.outstanding_lazy_request
= false;
3760 for (i
= 0; i
< args
->buffer_count
; i
++) {
3761 struct drm_gem_object
*obj
= object_list
[i
];
3762 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
3763 uint32_t old_write_domain
= obj
->write_domain
;
3765 obj
->write_domain
= obj
->pending_write_domain
;
3766 if (obj
->write_domain
)
3767 list_move_tail(&obj_priv
->gpu_write_list
,
3768 &dev_priv
->mm
.gpu_write_list
);
3770 list_del_init(&obj_priv
->gpu_write_list
);
3772 trace_i915_gem_object_change_domain(obj
,
3777 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
3780 for (i
= 0; i
< args
->buffer_count
; i
++) {
3781 i915_gem_object_check_coherency(object_list
[i
],
3782 exec_list
[i
].handle
);
3787 i915_gem_dump_object(batch_obj
,
3793 /* Exec the batchbuffer */
3794 ret
= ring
->dispatch_gem_execbuffer(dev
, ring
, args
,
3795 cliprects
, exec_offset
);
3797 DRM_ERROR("dispatch failed %d\n", ret
);
3802 * Ensure that the commands in the batch buffer are
3803 * finished before the interrupt fires
3805 i915_retire_commands(dev
, ring
);
3807 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
3809 for (i
= 0; i
< args
->buffer_count
; i
++) {
3810 struct drm_gem_object
*obj
= object_list
[i
];
3811 obj_priv
= to_intel_bo(obj
);
3813 i915_gem_object_move_to_active(obj
, ring
);
3815 DRM_INFO("%s: move to exec list %p\n", __func__
, obj
);
3820 * Get a seqno representing the execution of the current buffer,
3821 * which we can wait on. We would like to mitigate these interrupts,
3822 * likely by only creating seqnos occasionally (so that we have
3823 * *some* interrupts representing completion of buffers that we can
3824 * wait on when trying to clear up gtt space).
3826 seqno
= i915_add_request(dev
, file_priv
, request
, ring
);
3830 i915_dump_lru(dev
, __func__
);
3833 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
3836 for (i
= 0; i
< pinned
; i
++)
3837 i915_gem_object_unpin(object_list
[i
]);
3839 for (i
= 0; i
< args
->buffer_count
; i
++) {
3840 if (object_list
[i
]) {
3841 obj_priv
= to_intel_bo(object_list
[i
]);
3842 obj_priv
->in_execbuffer
= false;
3844 drm_gem_object_unreference(object_list
[i
]);
3847 mutex_unlock(&dev
->struct_mutex
);
3850 /* Copy the updated relocations out regardless of current error
3851 * state. Failure to update the relocs would mean that the next
3852 * time userland calls execbuf, it would do so with presumed offset
3853 * state that didn't match the actual object state.
3855 ret2
= i915_gem_put_relocs_to_user(exec_list
, args
->buffer_count
,
3858 DRM_ERROR("Failed to copy relocations back out: %d\n", ret2
);
3864 drm_free_large(object_list
);
3872 * Legacy execbuffer just creates an exec2 list from the original exec object
3873 * list array and passes it to the real function.
3876 i915_gem_execbuffer(struct drm_device
*dev
, void *data
,
3877 struct drm_file
*file_priv
)
3879 struct drm_i915_gem_execbuffer
*args
= data
;
3880 struct drm_i915_gem_execbuffer2 exec2
;
3881 struct drm_i915_gem_exec_object
*exec_list
= NULL
;
3882 struct drm_i915_gem_exec_object2
*exec2_list
= NULL
;
3886 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3887 (int) args
->buffers_ptr
, args
->buffer_count
, args
->batch_len
);
3890 if (args
->buffer_count
< 1) {
3891 DRM_ERROR("execbuf with %d buffers\n", args
->buffer_count
);
3895 /* Copy in the exec list from userland */
3896 exec_list
= drm_malloc_ab(sizeof(*exec_list
), args
->buffer_count
);
3897 exec2_list
= drm_malloc_ab(sizeof(*exec2_list
), args
->buffer_count
);
3898 if (exec_list
== NULL
|| exec2_list
== NULL
) {
3899 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
3900 args
->buffer_count
);
3901 drm_free_large(exec_list
);
3902 drm_free_large(exec2_list
);
3905 ret
= copy_from_user(exec_list
,
3906 (struct drm_i915_relocation_entry __user
*)
3907 (uintptr_t) args
->buffers_ptr
,
3908 sizeof(*exec_list
) * args
->buffer_count
);
3910 DRM_ERROR("copy %d exec entries failed %d\n",
3911 args
->buffer_count
, ret
);
3912 drm_free_large(exec_list
);
3913 drm_free_large(exec2_list
);
3917 for (i
= 0; i
< args
->buffer_count
; i
++) {
3918 exec2_list
[i
].handle
= exec_list
[i
].handle
;
3919 exec2_list
[i
].relocation_count
= exec_list
[i
].relocation_count
;
3920 exec2_list
[i
].relocs_ptr
= exec_list
[i
].relocs_ptr
;
3921 exec2_list
[i
].alignment
= exec_list
[i
].alignment
;
3922 exec2_list
[i
].offset
= exec_list
[i
].offset
;
3923 if (INTEL_INFO(dev
)->gen
< 4)
3924 exec2_list
[i
].flags
= EXEC_OBJECT_NEEDS_FENCE
;
3926 exec2_list
[i
].flags
= 0;
3929 exec2
.buffers_ptr
= args
->buffers_ptr
;
3930 exec2
.buffer_count
= args
->buffer_count
;
3931 exec2
.batch_start_offset
= args
->batch_start_offset
;
3932 exec2
.batch_len
= args
->batch_len
;
3933 exec2
.DR1
= args
->DR1
;
3934 exec2
.DR4
= args
->DR4
;
3935 exec2
.num_cliprects
= args
->num_cliprects
;
3936 exec2
.cliprects_ptr
= args
->cliprects_ptr
;
3937 exec2
.flags
= I915_EXEC_RENDER
;
3939 ret
= i915_gem_do_execbuffer(dev
, data
, file_priv
, &exec2
, exec2_list
);
3941 /* Copy the new buffer offsets back to the user's exec list. */
3942 for (i
= 0; i
< args
->buffer_count
; i
++)
3943 exec_list
[i
].offset
= exec2_list
[i
].offset
;
3944 /* ... and back out to userspace */
3945 ret
= copy_to_user((struct drm_i915_relocation_entry __user
*)
3946 (uintptr_t) args
->buffers_ptr
,
3948 sizeof(*exec_list
) * args
->buffer_count
);
3951 DRM_ERROR("failed to copy %d exec entries "
3952 "back to user (%d)\n",
3953 args
->buffer_count
, ret
);
3957 drm_free_large(exec_list
);
3958 drm_free_large(exec2_list
);
3963 i915_gem_execbuffer2(struct drm_device
*dev
, void *data
,
3964 struct drm_file
*file_priv
)
3966 struct drm_i915_gem_execbuffer2
*args
= data
;
3967 struct drm_i915_gem_exec_object2
*exec2_list
= NULL
;
3971 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3972 (int) args
->buffers_ptr
, args
->buffer_count
, args
->batch_len
);
3975 if (args
->buffer_count
< 1) {
3976 DRM_ERROR("execbuf2 with %d buffers\n", args
->buffer_count
);
3980 exec2_list
= drm_malloc_ab(sizeof(*exec2_list
), args
->buffer_count
);
3981 if (exec2_list
== NULL
) {
3982 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
3983 args
->buffer_count
);
3986 ret
= copy_from_user(exec2_list
,
3987 (struct drm_i915_relocation_entry __user
*)
3988 (uintptr_t) args
->buffers_ptr
,
3989 sizeof(*exec2_list
) * args
->buffer_count
);
3991 DRM_ERROR("copy %d exec entries failed %d\n",
3992 args
->buffer_count
, ret
);
3993 drm_free_large(exec2_list
);
3997 ret
= i915_gem_do_execbuffer(dev
, data
, file_priv
, args
, exec2_list
);
3999 /* Copy the new buffer offsets back to the user's exec list. */
4000 ret
= copy_to_user((struct drm_i915_relocation_entry __user
*)
4001 (uintptr_t) args
->buffers_ptr
,
4003 sizeof(*exec2_list
) * args
->buffer_count
);
4006 DRM_ERROR("failed to copy %d exec entries "
4007 "back to user (%d)\n",
4008 args
->buffer_count
, ret
);
4012 drm_free_large(exec2_list
);
4017 i915_gem_object_pin(struct drm_gem_object
*obj
, uint32_t alignment
)
4019 struct drm_device
*dev
= obj
->dev
;
4020 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
4023 BUG_ON(obj_priv
->pin_count
== DRM_I915_GEM_OBJECT_MAX_PIN_COUNT
);
4025 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
4027 if (obj_priv
->gtt_space
!= NULL
) {
4029 alignment
= i915_gem_get_gtt_alignment(obj
);
4030 if (obj_priv
->gtt_offset
& (alignment
- 1)) {
4031 WARN(obj_priv
->pin_count
,
4032 "bo is already pinned with incorrect alignment:"
4033 " offset=%x, req.alignment=%x\n",
4034 obj_priv
->gtt_offset
, alignment
);
4035 ret
= i915_gem_object_unbind(obj
);
4041 if (obj_priv
->gtt_space
== NULL
) {
4042 ret
= i915_gem_object_bind_to_gtt(obj
, alignment
);
4047 obj_priv
->pin_count
++;
4049 /* If the object is not active and not pending a flush,
4050 * remove it from the inactive list
4052 if (obj_priv
->pin_count
== 1) {
4053 atomic_inc(&dev
->pin_count
);
4054 atomic_add(obj
->size
, &dev
->pin_memory
);
4055 if (!obj_priv
->active
&&
4056 (obj
->write_domain
& I915_GEM_GPU_DOMAINS
) == 0)
4057 list_del_init(&obj_priv
->list
);
4059 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
4065 i915_gem_object_unpin(struct drm_gem_object
*obj
)
4067 struct drm_device
*dev
= obj
->dev
;
4068 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4069 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
4071 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
4072 obj_priv
->pin_count
--;
4073 BUG_ON(obj_priv
->pin_count
< 0);
4074 BUG_ON(obj_priv
->gtt_space
== NULL
);
4076 /* If the object is no longer pinned, and is
4077 * neither active nor being flushed, then stick it on
4080 if (obj_priv
->pin_count
== 0) {
4081 if (!obj_priv
->active
&&
4082 (obj
->write_domain
& I915_GEM_GPU_DOMAINS
) == 0)
4083 list_move_tail(&obj_priv
->list
,
4084 &dev_priv
->mm
.inactive_list
);
4085 atomic_dec(&dev
->pin_count
);
4086 atomic_sub(obj
->size
, &dev
->pin_memory
);
4088 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
4092 i915_gem_pin_ioctl(struct drm_device
*dev
, void *data
,
4093 struct drm_file
*file_priv
)
4095 struct drm_i915_gem_pin
*args
= data
;
4096 struct drm_gem_object
*obj
;
4097 struct drm_i915_gem_object
*obj_priv
;
4100 mutex_lock(&dev
->struct_mutex
);
4102 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
4104 DRM_ERROR("Bad handle in i915_gem_pin_ioctl(): %d\n",
4106 mutex_unlock(&dev
->struct_mutex
);
4109 obj_priv
= to_intel_bo(obj
);
4111 if (obj_priv
->madv
!= I915_MADV_WILLNEED
) {
4112 DRM_ERROR("Attempting to pin a purgeable buffer\n");
4113 drm_gem_object_unreference(obj
);
4114 mutex_unlock(&dev
->struct_mutex
);
4118 if (obj_priv
->pin_filp
!= NULL
&& obj_priv
->pin_filp
!= file_priv
) {
4119 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
4121 drm_gem_object_unreference(obj
);
4122 mutex_unlock(&dev
->struct_mutex
);
4126 obj_priv
->user_pin_count
++;
4127 obj_priv
->pin_filp
= file_priv
;
4128 if (obj_priv
->user_pin_count
== 1) {
4129 ret
= i915_gem_object_pin(obj
, args
->alignment
);
4131 drm_gem_object_unreference(obj
);
4132 mutex_unlock(&dev
->struct_mutex
);
4137 /* XXX - flush the CPU caches for pinned objects
4138 * as the X server doesn't manage domains yet
4140 i915_gem_object_flush_cpu_write_domain(obj
);
4141 args
->offset
= obj_priv
->gtt_offset
;
4142 drm_gem_object_unreference(obj
);
4143 mutex_unlock(&dev
->struct_mutex
);
4149 i915_gem_unpin_ioctl(struct drm_device
*dev
, void *data
,
4150 struct drm_file
*file_priv
)
4152 struct drm_i915_gem_pin
*args
= data
;
4153 struct drm_gem_object
*obj
;
4154 struct drm_i915_gem_object
*obj_priv
;
4156 mutex_lock(&dev
->struct_mutex
);
4158 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
4160 DRM_ERROR("Bad handle in i915_gem_unpin_ioctl(): %d\n",
4162 mutex_unlock(&dev
->struct_mutex
);
4166 obj_priv
= to_intel_bo(obj
);
4167 if (obj_priv
->pin_filp
!= file_priv
) {
4168 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
4170 drm_gem_object_unreference(obj
);
4171 mutex_unlock(&dev
->struct_mutex
);
4174 obj_priv
->user_pin_count
--;
4175 if (obj_priv
->user_pin_count
== 0) {
4176 obj_priv
->pin_filp
= NULL
;
4177 i915_gem_object_unpin(obj
);
4180 drm_gem_object_unreference(obj
);
4181 mutex_unlock(&dev
->struct_mutex
);
4186 i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
4187 struct drm_file
*file_priv
)
4189 struct drm_i915_gem_busy
*args
= data
;
4190 struct drm_gem_object
*obj
;
4191 struct drm_i915_gem_object
*obj_priv
;
4193 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
4195 DRM_ERROR("Bad handle in i915_gem_busy_ioctl(): %d\n",
4200 mutex_lock(&dev
->struct_mutex
);
4202 /* Count all active objects as busy, even if they are currently not used
4203 * by the gpu. Users of this interface expect objects to eventually
4204 * become non-busy without any further actions, therefore emit any
4205 * necessary flushes here.
4207 obj_priv
= to_intel_bo(obj
);
4208 args
->busy
= obj_priv
->active
;
4210 /* Unconditionally flush objects, even when the gpu still uses this
4211 * object. Userspace calling this function indicates that it wants to
4212 * use this buffer rather sooner than later, so issuing the required
4213 * flush earlier is beneficial.
4215 if (obj
->write_domain
& I915_GEM_GPU_DOMAINS
) {
4216 i915_gem_flush_ring(dev
,
4218 0, obj
->write_domain
);
4219 (void)i915_add_request(dev
, file_priv
, NULL
, obj_priv
->ring
);
4222 /* Update the active list for the hardware's current position.
4223 * Otherwise this only updates on a delayed timer or when irqs
4224 * are actually unmasked, and our working set ends up being
4225 * larger than required.
4227 i915_gem_retire_requests_ring(dev
, obj_priv
->ring
);
4229 args
->busy
= obj_priv
->active
;
4232 drm_gem_object_unreference(obj
);
4233 mutex_unlock(&dev
->struct_mutex
);
4238 i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
4239 struct drm_file
*file_priv
)
4241 return i915_gem_ring_throttle(dev
, file_priv
);
4245 i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
4246 struct drm_file
*file_priv
)
4248 struct drm_i915_gem_madvise
*args
= data
;
4249 struct drm_gem_object
*obj
;
4250 struct drm_i915_gem_object
*obj_priv
;
4252 switch (args
->madv
) {
4253 case I915_MADV_DONTNEED
:
4254 case I915_MADV_WILLNEED
:
4260 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
4262 DRM_ERROR("Bad handle in i915_gem_madvise_ioctl(): %d\n",
4267 mutex_lock(&dev
->struct_mutex
);
4268 obj_priv
= to_intel_bo(obj
);
4270 if (obj_priv
->pin_count
) {
4271 drm_gem_object_unreference(obj
);
4272 mutex_unlock(&dev
->struct_mutex
);
4274 DRM_ERROR("Attempted i915_gem_madvise_ioctl() on a pinned object\n");
4278 if (obj_priv
->madv
!= __I915_MADV_PURGED
)
4279 obj_priv
->madv
= args
->madv
;
4281 /* if the object is no longer bound, discard its backing storage */
4282 if (i915_gem_object_is_purgeable(obj_priv
) &&
4283 obj_priv
->gtt_space
== NULL
)
4284 i915_gem_object_truncate(obj
);
4286 args
->retained
= obj_priv
->madv
!= __I915_MADV_PURGED
;
4288 drm_gem_object_unreference(obj
);
4289 mutex_unlock(&dev
->struct_mutex
);
4294 struct drm_gem_object
* i915_gem_alloc_object(struct drm_device
*dev
,
4297 struct drm_i915_gem_object
*obj
;
4299 obj
= kzalloc(sizeof(*obj
), GFP_KERNEL
);
4303 if (drm_gem_object_init(dev
, &obj
->base
, size
) != 0) {
4308 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
4309 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
4311 obj
->agp_type
= AGP_USER_MEMORY
;
4312 obj
->base
.driver_private
= NULL
;
4313 obj
->fence_reg
= I915_FENCE_REG_NONE
;
4314 INIT_LIST_HEAD(&obj
->list
);
4315 INIT_LIST_HEAD(&obj
->gpu_write_list
);
4316 obj
->madv
= I915_MADV_WILLNEED
;
4318 trace_i915_gem_object_create(&obj
->base
);
4323 int i915_gem_init_object(struct drm_gem_object
*obj
)
4330 static void i915_gem_free_object_tail(struct drm_gem_object
*obj
)
4332 struct drm_device
*dev
= obj
->dev
;
4333 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4334 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
4337 ret
= i915_gem_object_unbind(obj
);
4338 if (ret
== -ERESTARTSYS
) {
4339 list_move(&obj_priv
->list
,
4340 &dev_priv
->mm
.deferred_free_list
);
4344 if (obj_priv
->mmap_offset
)
4345 i915_gem_free_mmap_offset(obj
);
4347 drm_gem_object_release(obj
);
4349 kfree(obj_priv
->page_cpu_valid
);
4350 kfree(obj_priv
->bit_17
);
4354 void i915_gem_free_object(struct drm_gem_object
*obj
)
4356 struct drm_device
*dev
= obj
->dev
;
4357 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
4359 trace_i915_gem_object_destroy(obj
);
4361 while (obj_priv
->pin_count
> 0)
4362 i915_gem_object_unpin(obj
);
4364 if (obj_priv
->phys_obj
)
4365 i915_gem_detach_phys_object(dev
, obj
);
4367 i915_gem_free_object_tail(obj
);
4371 i915_gem_idle(struct drm_device
*dev
)
4373 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4376 mutex_lock(&dev
->struct_mutex
);
4378 if (dev_priv
->mm
.suspended
||
4379 (dev_priv
->render_ring
.gem_object
== NULL
) ||
4381 dev_priv
->bsd_ring
.gem_object
== NULL
)) {
4382 mutex_unlock(&dev
->struct_mutex
);
4386 ret
= i915_gpu_idle(dev
);
4388 mutex_unlock(&dev
->struct_mutex
);
4392 /* Under UMS, be paranoid and evict. */
4393 if (!drm_core_check_feature(dev
, DRIVER_MODESET
)) {
4394 ret
= i915_gem_evict_inactive(dev
);
4396 mutex_unlock(&dev
->struct_mutex
);
4401 /* Hack! Don't let anybody do execbuf while we don't control the chip.
4402 * We need to replace this with a semaphore, or something.
4403 * And not confound mm.suspended!
4405 dev_priv
->mm
.suspended
= 1;
4406 del_timer_sync(&dev_priv
->hangcheck_timer
);
4408 i915_kernel_lost_context(dev
);
4409 i915_gem_cleanup_ringbuffer(dev
);
4411 mutex_unlock(&dev
->struct_mutex
);
4413 /* Cancel the retire work handler, which should be idle now. */
4414 cancel_delayed_work_sync(&dev_priv
->mm
.retire_work
);
4420 * 965+ support PIPE_CONTROL commands, which provide finer grained control
4421 * over cache flushing.
4424 i915_gem_init_pipe_control(struct drm_device
*dev
)
4426 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4427 struct drm_gem_object
*obj
;
4428 struct drm_i915_gem_object
*obj_priv
;
4431 obj
= i915_gem_alloc_object(dev
, 4096);
4433 DRM_ERROR("Failed to allocate seqno page\n");
4437 obj_priv
= to_intel_bo(obj
);
4438 obj_priv
->agp_type
= AGP_USER_CACHED_MEMORY
;
4440 ret
= i915_gem_object_pin(obj
, 4096);
4444 dev_priv
->seqno_gfx_addr
= obj_priv
->gtt_offset
;
4445 dev_priv
->seqno_page
= kmap(obj_priv
->pages
[0]);
4446 if (dev_priv
->seqno_page
== NULL
)
4449 dev_priv
->seqno_obj
= obj
;
4450 memset(dev_priv
->seqno_page
, 0, PAGE_SIZE
);
4455 i915_gem_object_unpin(obj
);
4457 drm_gem_object_unreference(obj
);
4464 i915_gem_cleanup_pipe_control(struct drm_device
*dev
)
4466 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4467 struct drm_gem_object
*obj
;
4468 struct drm_i915_gem_object
*obj_priv
;
4470 obj
= dev_priv
->seqno_obj
;
4471 obj_priv
= to_intel_bo(obj
);
4472 kunmap(obj_priv
->pages
[0]);
4473 i915_gem_object_unpin(obj
);
4474 drm_gem_object_unreference(obj
);
4475 dev_priv
->seqno_obj
= NULL
;
4477 dev_priv
->seqno_page
= NULL
;
4481 i915_gem_init_ringbuffer(struct drm_device
*dev
)
4483 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4486 dev_priv
->render_ring
= render_ring
;
4488 if (!I915_NEED_GFX_HWS(dev
)) {
4489 dev_priv
->render_ring
.status_page
.page_addr
4490 = dev_priv
->status_page_dmah
->vaddr
;
4491 memset(dev_priv
->render_ring
.status_page
.page_addr
,
4495 if (HAS_PIPE_CONTROL(dev
)) {
4496 ret
= i915_gem_init_pipe_control(dev
);
4501 ret
= intel_init_ring_buffer(dev
, &dev_priv
->render_ring
);
4503 goto cleanup_pipe_control
;
4506 dev_priv
->bsd_ring
= bsd_ring
;
4507 ret
= intel_init_ring_buffer(dev
, &dev_priv
->bsd_ring
);
4509 goto cleanup_render_ring
;
4512 dev_priv
->next_seqno
= 1;
4516 cleanup_render_ring
:
4517 intel_cleanup_ring_buffer(dev
, &dev_priv
->render_ring
);
4518 cleanup_pipe_control
:
4519 if (HAS_PIPE_CONTROL(dev
))
4520 i915_gem_cleanup_pipe_control(dev
);
4525 i915_gem_cleanup_ringbuffer(struct drm_device
*dev
)
4527 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4529 intel_cleanup_ring_buffer(dev
, &dev_priv
->render_ring
);
4531 intel_cleanup_ring_buffer(dev
, &dev_priv
->bsd_ring
);
4532 if (HAS_PIPE_CONTROL(dev
))
4533 i915_gem_cleanup_pipe_control(dev
);
4537 i915_gem_entervt_ioctl(struct drm_device
*dev
, void *data
,
4538 struct drm_file
*file_priv
)
4540 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4543 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4546 if (atomic_read(&dev_priv
->mm
.wedged
)) {
4547 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4548 atomic_set(&dev_priv
->mm
.wedged
, 0);
4551 mutex_lock(&dev
->struct_mutex
);
4552 dev_priv
->mm
.suspended
= 0;
4554 ret
= i915_gem_init_ringbuffer(dev
);
4556 mutex_unlock(&dev
->struct_mutex
);
4560 BUG_ON(!list_empty(&dev_priv
->render_ring
.active_list
));
4561 BUG_ON(HAS_BSD(dev
) && !list_empty(&dev_priv
->bsd_ring
.active_list
));
4562 BUG_ON(!list_empty(&dev_priv
->mm
.flushing_list
));
4563 BUG_ON(!list_empty(&dev_priv
->mm
.inactive_list
));
4564 BUG_ON(!list_empty(&dev_priv
->render_ring
.request_list
));
4565 BUG_ON(HAS_BSD(dev
) && !list_empty(&dev_priv
->bsd_ring
.request_list
));
4566 mutex_unlock(&dev
->struct_mutex
);
4568 ret
= drm_irq_install(dev
);
4570 goto cleanup_ringbuffer
;
4575 mutex_lock(&dev
->struct_mutex
);
4576 i915_gem_cleanup_ringbuffer(dev
);
4577 dev_priv
->mm
.suspended
= 1;
4578 mutex_unlock(&dev
->struct_mutex
);
4584 i915_gem_leavevt_ioctl(struct drm_device
*dev
, void *data
,
4585 struct drm_file
*file_priv
)
4587 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4590 drm_irq_uninstall(dev
);
4591 return i915_gem_idle(dev
);
4595 i915_gem_lastclose(struct drm_device
*dev
)
4599 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4602 ret
= i915_gem_idle(dev
);
4604 DRM_ERROR("failed to idle hardware: %d\n", ret
);
4608 i915_gem_load(struct drm_device
*dev
)
4611 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4613 INIT_LIST_HEAD(&dev_priv
->mm
.flushing_list
);
4614 INIT_LIST_HEAD(&dev_priv
->mm
.gpu_write_list
);
4615 INIT_LIST_HEAD(&dev_priv
->mm
.inactive_list
);
4616 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
4617 INIT_LIST_HEAD(&dev_priv
->mm
.deferred_free_list
);
4618 INIT_LIST_HEAD(&dev_priv
->render_ring
.active_list
);
4619 INIT_LIST_HEAD(&dev_priv
->render_ring
.request_list
);
4621 INIT_LIST_HEAD(&dev_priv
->bsd_ring
.active_list
);
4622 INIT_LIST_HEAD(&dev_priv
->bsd_ring
.request_list
);
4624 for (i
= 0; i
< 16; i
++)
4625 INIT_LIST_HEAD(&dev_priv
->fence_regs
[i
].lru_list
);
4626 INIT_DELAYED_WORK(&dev_priv
->mm
.retire_work
,
4627 i915_gem_retire_work_handler
);
4628 spin_lock(&shrink_list_lock
);
4629 list_add(&dev_priv
->mm
.shrink_list
, &shrink_list
);
4630 spin_unlock(&shrink_list_lock
);
4632 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4634 u32 tmp
= I915_READ(MI_ARB_STATE
);
4635 if (!(tmp
& MI_ARB_C3_LP_WRITE_ENABLE
)) {
4636 /* arb state is a masked write, so set bit + bit in mask */
4637 tmp
= MI_ARB_C3_LP_WRITE_ENABLE
| (MI_ARB_C3_LP_WRITE_ENABLE
<< MI_ARB_MASK_SHIFT
);
4638 I915_WRITE(MI_ARB_STATE
, tmp
);
4642 /* Old X drivers will take 0-2 for front, back, depth buffers */
4643 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
4644 dev_priv
->fence_reg_start
= 3;
4646 if (INTEL_INFO(dev
)->gen
>= 4 || IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
4647 dev_priv
->num_fence_regs
= 16;
4649 dev_priv
->num_fence_regs
= 8;
4651 /* Initialize fence registers to zero */
4652 switch (INTEL_INFO(dev
)->gen
) {
4654 for (i
= 0; i
< 16; i
++)
4655 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0
+ (i
* 8), 0);
4659 for (i
= 0; i
< 16; i
++)
4660 I915_WRITE64(FENCE_REG_965_0
+ (i
* 8), 0);
4663 if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
4664 for (i
= 0; i
< 8; i
++)
4665 I915_WRITE(FENCE_REG_945_8
+ (i
* 4), 0);
4667 for (i
= 0; i
< 8; i
++)
4668 I915_WRITE(FENCE_REG_830_0
+ (i
* 4), 0);
4671 i915_gem_detect_bit_6_swizzle(dev
);
4672 init_waitqueue_head(&dev_priv
->pending_flip_queue
);
4676 * Create a physically contiguous memory object for this object
4677 * e.g. for cursor + overlay regs
4679 static int i915_gem_init_phys_object(struct drm_device
*dev
,
4680 int id
, int size
, int align
)
4682 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4683 struct drm_i915_gem_phys_object
*phys_obj
;
4686 if (dev_priv
->mm
.phys_objs
[id
- 1] || !size
)
4689 phys_obj
= kzalloc(sizeof(struct drm_i915_gem_phys_object
), GFP_KERNEL
);
4695 phys_obj
->handle
= drm_pci_alloc(dev
, size
, align
);
4696 if (!phys_obj
->handle
) {
4701 set_memory_wc((unsigned long)phys_obj
->handle
->vaddr
, phys_obj
->handle
->size
/ PAGE_SIZE
);
4704 dev_priv
->mm
.phys_objs
[id
- 1] = phys_obj
;
4712 static void i915_gem_free_phys_object(struct drm_device
*dev
, int id
)
4714 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4715 struct drm_i915_gem_phys_object
*phys_obj
;
4717 if (!dev_priv
->mm
.phys_objs
[id
- 1])
4720 phys_obj
= dev_priv
->mm
.phys_objs
[id
- 1];
4721 if (phys_obj
->cur_obj
) {
4722 i915_gem_detach_phys_object(dev
, phys_obj
->cur_obj
);
4726 set_memory_wb((unsigned long)phys_obj
->handle
->vaddr
, phys_obj
->handle
->size
/ PAGE_SIZE
);
4728 drm_pci_free(dev
, phys_obj
->handle
);
4730 dev_priv
->mm
.phys_objs
[id
- 1] = NULL
;
4733 void i915_gem_free_all_phys_object(struct drm_device
*dev
)
4737 for (i
= I915_GEM_PHYS_CURSOR_0
; i
<= I915_MAX_PHYS_OBJECT
; i
++)
4738 i915_gem_free_phys_object(dev
, i
);
4741 void i915_gem_detach_phys_object(struct drm_device
*dev
,
4742 struct drm_gem_object
*obj
)
4744 struct drm_i915_gem_object
*obj_priv
;
4749 obj_priv
= to_intel_bo(obj
);
4750 if (!obj_priv
->phys_obj
)
4753 ret
= i915_gem_object_get_pages(obj
, 0);
4757 page_count
= obj
->size
/ PAGE_SIZE
;
4759 for (i
= 0; i
< page_count
; i
++) {
4760 char *dst
= kmap_atomic(obj_priv
->pages
[i
], KM_USER0
);
4761 char *src
= obj_priv
->phys_obj
->handle
->vaddr
+ (i
* PAGE_SIZE
);
4763 memcpy(dst
, src
, PAGE_SIZE
);
4764 kunmap_atomic(dst
, KM_USER0
);
4766 drm_clflush_pages(obj_priv
->pages
, page_count
);
4767 drm_agp_chipset_flush(dev
);
4769 i915_gem_object_put_pages(obj
);
4771 obj_priv
->phys_obj
->cur_obj
= NULL
;
4772 obj_priv
->phys_obj
= NULL
;
4776 i915_gem_attach_phys_object(struct drm_device
*dev
,
4777 struct drm_gem_object
*obj
,
4781 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4782 struct drm_i915_gem_object
*obj_priv
;
4787 if (id
> I915_MAX_PHYS_OBJECT
)
4790 obj_priv
= to_intel_bo(obj
);
4792 if (obj_priv
->phys_obj
) {
4793 if (obj_priv
->phys_obj
->id
== id
)
4795 i915_gem_detach_phys_object(dev
, obj
);
4798 /* create a new object */
4799 if (!dev_priv
->mm
.phys_objs
[id
- 1]) {
4800 ret
= i915_gem_init_phys_object(dev
, id
,
4803 DRM_ERROR("failed to init phys object %d size: %zu\n", id
, obj
->size
);
4808 /* bind to the object */
4809 obj_priv
->phys_obj
= dev_priv
->mm
.phys_objs
[id
- 1];
4810 obj_priv
->phys_obj
->cur_obj
= obj
;
4812 ret
= i915_gem_object_get_pages(obj
, 0);
4814 DRM_ERROR("failed to get page list\n");
4818 page_count
= obj
->size
/ PAGE_SIZE
;
4820 for (i
= 0; i
< page_count
; i
++) {
4821 char *src
= kmap_atomic(obj_priv
->pages
[i
], KM_USER0
);
4822 char *dst
= obj_priv
->phys_obj
->handle
->vaddr
+ (i
* PAGE_SIZE
);
4824 memcpy(dst
, src
, PAGE_SIZE
);
4825 kunmap_atomic(src
, KM_USER0
);
4828 i915_gem_object_put_pages(obj
);
4836 i915_gem_phys_pwrite(struct drm_device
*dev
, struct drm_gem_object
*obj
,
4837 struct drm_i915_gem_pwrite
*args
,
4838 struct drm_file
*file_priv
)
4840 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
4843 char __user
*user_data
;
4845 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
4846 obj_addr
= obj_priv
->phys_obj
->handle
->vaddr
+ args
->offset
;
4848 DRM_DEBUG_DRIVER("obj_addr %p, %lld\n", obj_addr
, args
->size
);
4849 ret
= copy_from_user(obj_addr
, user_data
, args
->size
);
4853 drm_agp_chipset_flush(dev
);
4857 void i915_gem_release(struct drm_device
* dev
, struct drm_file
*file_priv
)
4859 struct drm_i915_file_private
*i915_file_priv
= file_priv
->driver_priv
;
4861 /* Clean up our request list when the client is going away, so that
4862 * later retire_requests won't dereference our soon-to-be-gone
4865 mutex_lock(&dev
->struct_mutex
);
4866 while (!list_empty(&i915_file_priv
->mm
.request_list
))
4867 list_del_init(i915_file_priv
->mm
.request_list
.next
);
4868 mutex_unlock(&dev
->struct_mutex
);
4872 i915_gpu_is_active(struct drm_device
*dev
)
4874 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4877 lists_empty
= list_empty(&dev_priv
->mm
.flushing_list
) &&
4878 list_empty(&dev_priv
->render_ring
.active_list
);
4880 lists_empty
&= list_empty(&dev_priv
->bsd_ring
.active_list
);
4882 return !lists_empty
;
4886 i915_gem_shrink(struct shrinker
*shrink
, int nr_to_scan
, gfp_t gfp_mask
)
4888 drm_i915_private_t
*dev_priv
, *next_dev
;
4889 struct drm_i915_gem_object
*obj_priv
, *next_obj
;
4891 int would_deadlock
= 1;
4893 /* "fast-path" to count number of available objects */
4894 if (nr_to_scan
== 0) {
4895 spin_lock(&shrink_list_lock
);
4896 list_for_each_entry(dev_priv
, &shrink_list
, mm
.shrink_list
) {
4897 struct drm_device
*dev
= dev_priv
->dev
;
4899 if (mutex_trylock(&dev
->struct_mutex
)) {
4900 list_for_each_entry(obj_priv
,
4901 &dev_priv
->mm
.inactive_list
,
4904 mutex_unlock(&dev
->struct_mutex
);
4907 spin_unlock(&shrink_list_lock
);
4909 return (cnt
/ 100) * sysctl_vfs_cache_pressure
;
4912 spin_lock(&shrink_list_lock
);
4915 /* first scan for clean buffers */
4916 list_for_each_entry_safe(dev_priv
, next_dev
,
4917 &shrink_list
, mm
.shrink_list
) {
4918 struct drm_device
*dev
= dev_priv
->dev
;
4920 if (! mutex_trylock(&dev
->struct_mutex
))
4923 spin_unlock(&shrink_list_lock
);
4924 i915_gem_retire_requests(dev
);
4926 list_for_each_entry_safe(obj_priv
, next_obj
,
4927 &dev_priv
->mm
.inactive_list
,
4929 if (i915_gem_object_is_purgeable(obj_priv
)) {
4930 i915_gem_object_unbind(&obj_priv
->base
);
4931 if (--nr_to_scan
<= 0)
4936 spin_lock(&shrink_list_lock
);
4937 mutex_unlock(&dev
->struct_mutex
);
4941 if (nr_to_scan
<= 0)
4945 /* second pass, evict/count anything still on the inactive list */
4946 list_for_each_entry_safe(dev_priv
, next_dev
,
4947 &shrink_list
, mm
.shrink_list
) {
4948 struct drm_device
*dev
= dev_priv
->dev
;
4950 if (! mutex_trylock(&dev
->struct_mutex
))
4953 spin_unlock(&shrink_list_lock
);
4955 list_for_each_entry_safe(obj_priv
, next_obj
,
4956 &dev_priv
->mm
.inactive_list
,
4958 if (nr_to_scan
> 0) {
4959 i915_gem_object_unbind(&obj_priv
->base
);
4965 spin_lock(&shrink_list_lock
);
4966 mutex_unlock(&dev
->struct_mutex
);
4975 * We are desperate for pages, so as a last resort, wait
4976 * for the GPU to finish and discard whatever we can.
4977 * This has a dramatic impact to reduce the number of
4978 * OOM-killer events whilst running the GPU aggressively.
4980 list_for_each_entry(dev_priv
, &shrink_list
, mm
.shrink_list
) {
4981 struct drm_device
*dev
= dev_priv
->dev
;
4983 if (!mutex_trylock(&dev
->struct_mutex
))
4986 spin_unlock(&shrink_list_lock
);
4988 if (i915_gpu_is_active(dev
)) {
4993 spin_lock(&shrink_list_lock
);
4994 mutex_unlock(&dev
->struct_mutex
);
5001 spin_unlock(&shrink_list_lock
);
5006 return (cnt
/ 100) * sysctl_vfs_cache_pressure
;
5011 static struct shrinker shrinker
= {
5012 .shrink
= i915_gem_shrink
,
5013 .seeks
= DEFAULT_SEEKS
,
5017 i915_gem_shrinker_init(void)
5019 register_shrinker(&shrinker
);
5023 i915_gem_shrinker_exit(void)
5025 unregister_shrinker(&shrinker
);