include/linux/dw_dmac.h

   1 /*
   2  * Driver for the Synopsys DesignWare DMA Controller (aka DMACA on
   3  * AVR32 systems.)
   4  *
   5  * Copyright (C) 2007 Atmel Corporation
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11 #ifndef DW_DMAC_H
  12 #define DW_DMAC_H
  13
  14 #include <linux/dmaengine.h>
  15
  16 /**
  17  * struct dw_dma_platform_data - Controller configuration parameters
  18  * @nr_channels: Number of channels supported by hardware (max 8)
  19  * @is_private: The device channels should be marked as private and not for
  20  *      by the general purpose DMA channel allocator.
  21  */
  22 struct dw_dma_platform_data {
  23         unsigned int    nr_channels;
  24         bool            is_private;
  25 #define CHAN_ALLOCATION_ASCENDING       0       /* zero to seven */
  26 #define CHAN_ALLOCATION_DESCENDING      1       /* seven to zero */
  27         unsigned char   chan_allocation_order;
  28 #define CHAN_PRIORITY_ASCENDING         0       /* chan0 highest */
  29 #define CHAN_PRIORITY_DESCENDING        1       /* chan7 highest */
  30         unsigned char   chan_priority;
  31 };
  32
  33 /**
  34  * enum dw_dma_slave_width - DMA slave register access width.
  35  * @DMA_SLAVE_WIDTH_8BIT: Do 8-bit slave register accesses
  36  * @DMA_SLAVE_WIDTH_16BIT: Do 16-bit slave register accesses
  37  * @DMA_SLAVE_WIDTH_32BIT: Do 32-bit slave register accesses
  38  */
  39 enum dw_dma_slave_width {
  40         DW_DMA_SLAVE_WIDTH_8BIT,
  41         DW_DMA_SLAVE_WIDTH_16BIT,
  42         DW_DMA_SLAVE_WIDTH_32BIT,
  43 };
  44
  45 /**
  46  * struct dw_dma_slave - Controller-specific information about a slave
  47  *
  48  * @dma_dev: required DMA master device
  49  * @tx_reg: physical address of data register used for
  50  *      memory-to-peripheral transfers
  51  * @rx_reg: physical address of data register used for
  52  *      peripheral-to-memory transfers
  53  * @reg_width: peripheral register width
  54  * @cfg_hi: Platform-specific initializer for the CFG_HI register
  55  * @cfg_lo: Platform-specific initializer for the CFG_LO register
  56  */
  57 struct dw_dma_slave {
  58         struct device           *dma_dev;
  59         dma_addr_t              tx_reg;
  60         dma_addr_t              rx_reg;
  61         enum dw_dma_slave_width reg_width;
  62         u32                     cfg_hi;
  63         u32                     cfg_lo;
  64         int                     src_master;
  65         int                     dst_master;
  66 };
  67
  68 /* Platform-configurable bits in CFG_HI */
  69 #define DWC_CFGH_FCMODE         (1 << 0)
  70 #define DWC_CFGH_FIFO_MODE      (1 << 1)
  71 #define DWC_CFGH_PROTCTL(x)     ((x) << 2)
  72 #define DWC_CFGH_SRC_PER(x)     ((x) << 7)
  73 #define DWC_CFGH_DST_PER(x)     ((x) << 11)
  74
  75 /* Platform-configurable bits in CFG_LO */
  76 #define DWC_CFGL_LOCK_CH_XFER   (0 << 12)       /* scope of LOCK_CH */
  77 #define DWC_CFGL_LOCK_CH_BLOCK  (1 << 12)
  78 #define DWC_CFGL_LOCK_CH_XACT   (2 << 12)
  79 #define DWC_CFGL_LOCK_BUS_XFER  (0 << 14)       /* scope of LOCK_BUS */
  80 #define DWC_CFGL_LOCK_BUS_BLOCK (1 << 14)
  81 #define DWC_CFGL_LOCK_BUS_XACT  (2 << 14)
  82 #define DWC_CFGL_LOCK_CH        (1 << 15)       /* channel lockout */
  83 #define DWC_CFGL_LOCK_BUS       (1 << 16)       /* busmaster lockout */
  84 #define DWC_CFGL_HS_DST_POL     (1 << 18)       /* dst handshake active low */
  85 #define DWC_CFGL_HS_SRC_POL     (1 << 19)       /* src handshake active low */
  86
  87 /* DMA API extensions */
  88 struct dw_cyclic_desc {
  89         struct dw_desc  **desc;
  90         unsigned long   periods;
  91         void            (*period_callback)(void *param);
  92         void            *period_callback_param;
  93 };
  94
  95 struct dw_cyclic_desc *dw_dma_cyclic_prep(struct dma_chan *chan,
  96                 dma_addr_t buf_addr, size_t buf_len, size_t period_len,
  97                 enum dma_data_direction direction);
  98 void dw_dma_cyclic_free(struct dma_chan *chan);
  99 int dw_dma_cyclic_start(struct dma_chan *chan);
 100 void dw_dma_cyclic_stop(struct dma_chan *chan);
 101
 102 dma_addr_t dw_dma_get_src_addr(struct dma_chan *chan);
 103
 104 dma_addr_t dw_dma_get_dst_addr(struct dma_chan *chan);
 105
 106 #endif /* DW_DMAC_H */