PCI: Clean up build for CONFIG_PCI_QUIRKS unset
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / pci / pci.c
blob1f9be53c39ba0c2217728c9ef47b6734311f3843
1 /*
2 * PCI Bus Services, see include/linux/pci.h for further explanation.
4 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
5 * David Mosberger-Tang
7 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
8 */
10 #include <linux/kernel.h>
11 #include <linux/delay.h>
12 #include <linux/init.h>
13 #include <linux/pci.h>
14 #include <linux/pm.h>
15 #include <linux/module.h>
16 #include <linux/spinlock.h>
17 #include <linux/string.h>
18 #include <linux/log2.h>
19 #include <linux/pci-aspm.h>
20 #include <linux/pm_wakeup.h>
21 #include <linux/interrupt.h>
22 #include <linux/device.h>
23 #include <asm/setup.h>
24 #include "pci.h"
26 const char *pci_power_names[] = {
27 "error", "D0", "D1", "D2", "D3hot", "D3cold", "unknown",
29 EXPORT_SYMBOL_GPL(pci_power_names);
31 int isa_dma_bridge_buggy;
32 EXPORT_SYMBOL(isa_dma_bridge_buggy);
34 int pci_pci_problems;
35 EXPORT_SYMBOL(pci_pci_problems);
37 unsigned int pci_pm_d3_delay;
39 static void pci_dev_d3_sleep(struct pci_dev *dev)
41 unsigned int delay = dev->d3_delay;
43 if (delay < pci_pm_d3_delay)
44 delay = pci_pm_d3_delay;
46 msleep(delay);
49 #ifdef CONFIG_PCI_DOMAINS
50 int pci_domains_supported = 1;
51 #endif
53 #define DEFAULT_CARDBUS_IO_SIZE (256)
54 #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024)
55 /* pci=cbmemsize=nnM,cbiosize=nn can override this */
56 unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE;
57 unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE;
59 #define DEFAULT_HOTPLUG_IO_SIZE (256)
60 #define DEFAULT_HOTPLUG_MEM_SIZE (2*1024*1024)
61 /* pci=hpmemsize=nnM,hpiosize=nn can override this */
62 unsigned long pci_hotplug_io_size = DEFAULT_HOTPLUG_IO_SIZE;
63 unsigned long pci_hotplug_mem_size = DEFAULT_HOTPLUG_MEM_SIZE;
66 * The default CLS is used if arch didn't set CLS explicitly and not
67 * all pci devices agree on the same value. Arch can override either
68 * the dfl or actual value as it sees fit. Don't forget this is
69 * measured in 32-bit words, not bytes.
71 u8 pci_dfl_cache_line_size __devinitdata = L1_CACHE_BYTES >> 2;
72 u8 pci_cache_line_size;
74 /**
75 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
76 * @bus: pointer to PCI bus structure to search
78 * Given a PCI bus, returns the highest PCI bus number present in the set
79 * including the given PCI bus and its list of child PCI buses.
81 unsigned char pci_bus_max_busnr(struct pci_bus* bus)
83 struct list_head *tmp;
84 unsigned char max, n;
86 max = bus->subordinate;
87 list_for_each(tmp, &bus->children) {
88 n = pci_bus_max_busnr(pci_bus_b(tmp));
89 if(n > max)
90 max = n;
92 return max;
94 EXPORT_SYMBOL_GPL(pci_bus_max_busnr);
96 #ifdef CONFIG_HAS_IOMEM
97 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar)
100 * Make sure the BAR is actually a memory resource, not an IO resource
102 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
103 WARN_ON(1);
104 return NULL;
106 return ioremap_nocache(pci_resource_start(pdev, bar),
107 pci_resource_len(pdev, bar));
109 EXPORT_SYMBOL_GPL(pci_ioremap_bar);
110 #endif
112 #if 0
114 * pci_max_busnr - returns maximum PCI bus number
116 * Returns the highest PCI bus number present in the system global list of
117 * PCI buses.
119 unsigned char __devinit
120 pci_max_busnr(void)
122 struct pci_bus *bus = NULL;
123 unsigned char max, n;
125 max = 0;
126 while ((bus = pci_find_next_bus(bus)) != NULL) {
127 n = pci_bus_max_busnr(bus);
128 if(n > max)
129 max = n;
131 return max;
134 #endif /* 0 */
136 #define PCI_FIND_CAP_TTL 48
138 static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn,
139 u8 pos, int cap, int *ttl)
141 u8 id;
143 while ((*ttl)--) {
144 pci_bus_read_config_byte(bus, devfn, pos, &pos);
145 if (pos < 0x40)
146 break;
147 pos &= ~3;
148 pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_ID,
149 &id);
150 if (id == 0xff)
151 break;
152 if (id == cap)
153 return pos;
154 pos += PCI_CAP_LIST_NEXT;
156 return 0;
159 static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn,
160 u8 pos, int cap)
162 int ttl = PCI_FIND_CAP_TTL;
164 return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl);
167 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap)
169 return __pci_find_next_cap(dev->bus, dev->devfn,
170 pos + PCI_CAP_LIST_NEXT, cap);
172 EXPORT_SYMBOL_GPL(pci_find_next_capability);
174 static int __pci_bus_find_cap_start(struct pci_bus *bus,
175 unsigned int devfn, u8 hdr_type)
177 u16 status;
179 pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status);
180 if (!(status & PCI_STATUS_CAP_LIST))
181 return 0;
183 switch (hdr_type) {
184 case PCI_HEADER_TYPE_NORMAL:
185 case PCI_HEADER_TYPE_BRIDGE:
186 return PCI_CAPABILITY_LIST;
187 case PCI_HEADER_TYPE_CARDBUS:
188 return PCI_CB_CAPABILITY_LIST;
189 default:
190 return 0;
193 return 0;
197 * pci_find_capability - query for devices' capabilities
198 * @dev: PCI device to query
199 * @cap: capability code
201 * Tell if a device supports a given PCI capability.
202 * Returns the address of the requested capability structure within the
203 * device's PCI configuration space or 0 in case the device does not
204 * support it. Possible values for @cap:
206 * %PCI_CAP_ID_PM Power Management
207 * %PCI_CAP_ID_AGP Accelerated Graphics Port
208 * %PCI_CAP_ID_VPD Vital Product Data
209 * %PCI_CAP_ID_SLOTID Slot Identification
210 * %PCI_CAP_ID_MSI Message Signalled Interrupts
211 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
212 * %PCI_CAP_ID_PCIX PCI-X
213 * %PCI_CAP_ID_EXP PCI Express
215 int pci_find_capability(struct pci_dev *dev, int cap)
217 int pos;
219 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
220 if (pos)
221 pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap);
223 return pos;
227 * pci_bus_find_capability - query for devices' capabilities
228 * @bus: the PCI bus to query
229 * @devfn: PCI device to query
230 * @cap: capability code
232 * Like pci_find_capability() but works for pci devices that do not have a
233 * pci_dev structure set up yet.
235 * Returns the address of the requested capability structure within the
236 * device's PCI configuration space or 0 in case the device does not
237 * support it.
239 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap)
241 int pos;
242 u8 hdr_type;
244 pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type);
246 pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f);
247 if (pos)
248 pos = __pci_find_next_cap(bus, devfn, pos, cap);
250 return pos;
254 * pci_find_ext_capability - Find an extended capability
255 * @dev: PCI device to query
256 * @cap: capability code
258 * Returns the address of the requested extended capability structure
259 * within the device's PCI configuration space or 0 if the device does
260 * not support it. Possible values for @cap:
262 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
263 * %PCI_EXT_CAP_ID_VC Virtual Channel
264 * %PCI_EXT_CAP_ID_DSN Device Serial Number
265 * %PCI_EXT_CAP_ID_PWR Power Budgeting
267 int pci_find_ext_capability(struct pci_dev *dev, int cap)
269 u32 header;
270 int ttl;
271 int pos = PCI_CFG_SPACE_SIZE;
273 /* minimum 8 bytes per capability */
274 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
276 if (dev->cfg_size <= PCI_CFG_SPACE_SIZE)
277 return 0;
279 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
280 return 0;
283 * If we have no capabilities, this is indicated by cap ID,
284 * cap version and next pointer all being 0.
286 if (header == 0)
287 return 0;
289 while (ttl-- > 0) {
290 if (PCI_EXT_CAP_ID(header) == cap)
291 return pos;
293 pos = PCI_EXT_CAP_NEXT(header);
294 if (pos < PCI_CFG_SPACE_SIZE)
295 break;
297 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
298 break;
301 return 0;
303 EXPORT_SYMBOL_GPL(pci_find_ext_capability);
305 static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap)
307 int rc, ttl = PCI_FIND_CAP_TTL;
308 u8 cap, mask;
310 if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST)
311 mask = HT_3BIT_CAP_MASK;
312 else
313 mask = HT_5BIT_CAP_MASK;
315 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos,
316 PCI_CAP_ID_HT, &ttl);
317 while (pos) {
318 rc = pci_read_config_byte(dev, pos + 3, &cap);
319 if (rc != PCIBIOS_SUCCESSFUL)
320 return 0;
322 if ((cap & mask) == ht_cap)
323 return pos;
325 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn,
326 pos + PCI_CAP_LIST_NEXT,
327 PCI_CAP_ID_HT, &ttl);
330 return 0;
333 * pci_find_next_ht_capability - query a device's Hypertransport capabilities
334 * @dev: PCI device to query
335 * @pos: Position from which to continue searching
336 * @ht_cap: Hypertransport capability code
338 * To be used in conjunction with pci_find_ht_capability() to search for
339 * all capabilities matching @ht_cap. @pos should always be a value returned
340 * from pci_find_ht_capability().
342 * NB. To be 100% safe against broken PCI devices, the caller should take
343 * steps to avoid an infinite loop.
345 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap)
347 return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap);
349 EXPORT_SYMBOL_GPL(pci_find_next_ht_capability);
352 * pci_find_ht_capability - query a device's Hypertransport capabilities
353 * @dev: PCI device to query
354 * @ht_cap: Hypertransport capability code
356 * Tell if a device supports a given Hypertransport capability.
357 * Returns an address within the device's PCI configuration space
358 * or 0 in case the device does not support the request capability.
359 * The address points to the PCI capability, of type PCI_CAP_ID_HT,
360 * which has a Hypertransport capability matching @ht_cap.
362 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap)
364 int pos;
366 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
367 if (pos)
368 pos = __pci_find_next_ht_cap(dev, pos, ht_cap);
370 return pos;
372 EXPORT_SYMBOL_GPL(pci_find_ht_capability);
375 * pci_find_parent_resource - return resource region of parent bus of given region
376 * @dev: PCI device structure contains resources to be searched
377 * @res: child resource record for which parent is sought
379 * For given resource region of given device, return the resource
380 * region of parent bus the given region is contained in or where
381 * it should be allocated from.
383 struct resource *
384 pci_find_parent_resource(const struct pci_dev *dev, struct resource *res)
386 const struct pci_bus *bus = dev->bus;
387 int i;
388 struct resource *best = NULL;
390 for(i = 0; i < PCI_BUS_NUM_RESOURCES; i++) {
391 struct resource *r = bus->resource[i];
392 if (!r)
393 continue;
394 if (res->start && !(res->start >= r->start && res->end <= r->end))
395 continue; /* Not contained */
396 if ((res->flags ^ r->flags) & (IORESOURCE_IO | IORESOURCE_MEM))
397 continue; /* Wrong type */
398 if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH))
399 return r; /* Exact match */
400 /* We can't insert a non-prefetch resource inside a prefetchable parent .. */
401 if (r->flags & IORESOURCE_PREFETCH)
402 continue;
403 /* .. but we can put a prefetchable resource inside a non-prefetchable one */
404 if (!best)
405 best = r;
407 return best;
411 * pci_restore_bars - restore a devices BAR values (e.g. after wake-up)
412 * @dev: PCI device to have its BARs restored
414 * Restore the BAR values for a given device, so as to make it
415 * accessible by its driver.
417 static void
418 pci_restore_bars(struct pci_dev *dev)
420 int i;
422 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++)
423 pci_update_resource(dev, i);
426 static struct pci_platform_pm_ops *pci_platform_pm;
428 int pci_set_platform_pm(struct pci_platform_pm_ops *ops)
430 if (!ops->is_manageable || !ops->set_state || !ops->choose_state
431 || !ops->sleep_wake || !ops->can_wakeup)
432 return -EINVAL;
433 pci_platform_pm = ops;
434 return 0;
437 static inline bool platform_pci_power_manageable(struct pci_dev *dev)
439 return pci_platform_pm ? pci_platform_pm->is_manageable(dev) : false;
442 static inline int platform_pci_set_power_state(struct pci_dev *dev,
443 pci_power_t t)
445 return pci_platform_pm ? pci_platform_pm->set_state(dev, t) : -ENOSYS;
448 static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev)
450 return pci_platform_pm ?
451 pci_platform_pm->choose_state(dev) : PCI_POWER_ERROR;
454 static inline bool platform_pci_can_wakeup(struct pci_dev *dev)
456 return pci_platform_pm ? pci_platform_pm->can_wakeup(dev) : false;
459 static inline int platform_pci_sleep_wake(struct pci_dev *dev, bool enable)
461 return pci_platform_pm ?
462 pci_platform_pm->sleep_wake(dev, enable) : -ENODEV;
466 * pci_raw_set_power_state - Use PCI PM registers to set the power state of
467 * given PCI device
468 * @dev: PCI device to handle.
469 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
471 * RETURN VALUE:
472 * -EINVAL if the requested state is invalid.
473 * -EIO if device does not support PCI PM or its PM capabilities register has a
474 * wrong version, or device doesn't support the requested state.
475 * 0 if device already is in the requested state.
476 * 0 if device's power state has been successfully changed.
478 static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state)
480 u16 pmcsr;
481 bool need_restore = false;
483 /* Check if we're already there */
484 if (dev->current_state == state)
485 return 0;
487 if (!dev->pm_cap)
488 return -EIO;
490 if (state < PCI_D0 || state > PCI_D3hot)
491 return -EINVAL;
493 /* Validate current state:
494 * Can enter D0 from any state, but if we can only go deeper
495 * to sleep if we're already in a low power state
497 if (state != PCI_D0 && dev->current_state <= PCI_D3cold
498 && dev->current_state > state) {
499 dev_err(&dev->dev, "invalid power transition "
500 "(from state %d to %d)\n", dev->current_state, state);
501 return -EINVAL;
504 /* check if this device supports the desired state */
505 if ((state == PCI_D1 && !dev->d1_support)
506 || (state == PCI_D2 && !dev->d2_support))
507 return -EIO;
509 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
511 /* If we're (effectively) in D3, force entire word to 0.
512 * This doesn't affect PME_Status, disables PME_En, and
513 * sets PowerState to 0.
515 switch (dev->current_state) {
516 case PCI_D0:
517 case PCI_D1:
518 case PCI_D2:
519 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
520 pmcsr |= state;
521 break;
522 case PCI_D3hot:
523 case PCI_D3cold:
524 case PCI_UNKNOWN: /* Boot-up */
525 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot
526 && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET))
527 need_restore = true;
528 /* Fall-through: force to D0 */
529 default:
530 pmcsr = 0;
531 break;
534 /* enter specified state */
535 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
537 /* Mandatory power management transition delays */
538 /* see PCI PM 1.1 5.6.1 table 18 */
539 if (state == PCI_D3hot || dev->current_state == PCI_D3hot)
540 pci_dev_d3_sleep(dev);
541 else if (state == PCI_D2 || dev->current_state == PCI_D2)
542 udelay(PCI_PM_D2_DELAY);
544 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
545 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
546 if (dev->current_state != state && printk_ratelimit())
547 dev_info(&dev->dev, "Refused to change power state, "
548 "currently in D%d\n", dev->current_state);
550 /* According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
551 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
552 * from D3hot to D0 _may_ perform an internal reset, thereby
553 * going to "D0 Uninitialized" rather than "D0 Initialized".
554 * For example, at least some versions of the 3c905B and the
555 * 3c556B exhibit this behaviour.
557 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
558 * devices in a D3hot state at boot. Consequently, we need to
559 * restore at least the BARs so that the device will be
560 * accessible to its driver.
562 if (need_restore)
563 pci_restore_bars(dev);
565 if (dev->bus->self)
566 pcie_aspm_pm_state_change(dev->bus->self);
568 return 0;
572 * pci_update_current_state - Read PCI power state of given device from its
573 * PCI PM registers and cache it
574 * @dev: PCI device to handle.
575 * @state: State to cache in case the device doesn't have the PM capability
577 void pci_update_current_state(struct pci_dev *dev, pci_power_t state)
579 if (dev->pm_cap) {
580 u16 pmcsr;
582 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
583 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
584 } else {
585 dev->current_state = state;
590 * pci_platform_power_transition - Use platform to change device power state
591 * @dev: PCI device to handle.
592 * @state: State to put the device into.
594 static int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state)
596 int error;
598 if (platform_pci_power_manageable(dev)) {
599 error = platform_pci_set_power_state(dev, state);
600 if (!error)
601 pci_update_current_state(dev, state);
602 } else {
603 error = -ENODEV;
604 /* Fall back to PCI_D0 if native PM is not supported */
605 if (!dev->pm_cap)
606 dev->current_state = PCI_D0;
609 return error;
613 * __pci_start_power_transition - Start power transition of a PCI device
614 * @dev: PCI device to handle.
615 * @state: State to put the device into.
617 static void __pci_start_power_transition(struct pci_dev *dev, pci_power_t state)
619 if (state == PCI_D0)
620 pci_platform_power_transition(dev, PCI_D0);
624 * __pci_complete_power_transition - Complete power transition of a PCI device
625 * @dev: PCI device to handle.
626 * @state: State to put the device into.
628 * This function should not be called directly by device drivers.
630 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state)
632 return state > PCI_D0 ?
633 pci_platform_power_transition(dev, state) : -EINVAL;
635 EXPORT_SYMBOL_GPL(__pci_complete_power_transition);
638 * pci_set_power_state - Set the power state of a PCI device
639 * @dev: PCI device to handle.
640 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
642 * Transition a device to a new power state, using the platform firmware and/or
643 * the device's PCI PM registers.
645 * RETURN VALUE:
646 * -EINVAL if the requested state is invalid.
647 * -EIO if device does not support PCI PM or its PM capabilities register has a
648 * wrong version, or device doesn't support the requested state.
649 * 0 if device already is in the requested state.
650 * 0 if device's power state has been successfully changed.
652 int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
654 int error;
656 /* bound the state we're entering */
657 if (state > PCI_D3hot)
658 state = PCI_D3hot;
659 else if (state < PCI_D0)
660 state = PCI_D0;
661 else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev))
663 * If the device or the parent bridge do not support PCI PM,
664 * ignore the request if we're doing anything other than putting
665 * it into D0 (which would only happen on boot).
667 return 0;
669 /* Check if we're already there */
670 if (dev->current_state == state)
671 return 0;
673 __pci_start_power_transition(dev, state);
675 /* This device is quirked not to be put into D3, so
676 don't put it in D3 */
677 if (state == PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3))
678 return 0;
680 error = pci_raw_set_power_state(dev, state);
682 if (!__pci_complete_power_transition(dev, state))
683 error = 0;
685 return error;
689 * pci_choose_state - Choose the power state of a PCI device
690 * @dev: PCI device to be suspended
691 * @state: target sleep state for the whole system. This is the value
692 * that is passed to suspend() function.
694 * Returns PCI power state suitable for given device and given system
695 * message.
698 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state)
700 pci_power_t ret;
702 if (!pci_find_capability(dev, PCI_CAP_ID_PM))
703 return PCI_D0;
705 ret = platform_pci_choose_state(dev);
706 if (ret != PCI_POWER_ERROR)
707 return ret;
709 switch (state.event) {
710 case PM_EVENT_ON:
711 return PCI_D0;
712 case PM_EVENT_FREEZE:
713 case PM_EVENT_PRETHAW:
714 /* REVISIT both freeze and pre-thaw "should" use D0 */
715 case PM_EVENT_SUSPEND:
716 case PM_EVENT_HIBERNATE:
717 return PCI_D3hot;
718 default:
719 dev_info(&dev->dev, "unrecognized suspend event %d\n",
720 state.event);
721 BUG();
723 return PCI_D0;
726 EXPORT_SYMBOL(pci_choose_state);
728 #define PCI_EXP_SAVE_REGS 7
730 #define pcie_cap_has_devctl(type, flags) 1
731 #define pcie_cap_has_lnkctl(type, flags) \
732 ((flags & PCI_EXP_FLAGS_VERS) > 1 || \
733 (type == PCI_EXP_TYPE_ROOT_PORT || \
734 type == PCI_EXP_TYPE_ENDPOINT || \
735 type == PCI_EXP_TYPE_LEG_END))
736 #define pcie_cap_has_sltctl(type, flags) \
737 ((flags & PCI_EXP_FLAGS_VERS) > 1 || \
738 ((type == PCI_EXP_TYPE_ROOT_PORT) || \
739 (type == PCI_EXP_TYPE_DOWNSTREAM && \
740 (flags & PCI_EXP_FLAGS_SLOT))))
741 #define pcie_cap_has_rtctl(type, flags) \
742 ((flags & PCI_EXP_FLAGS_VERS) > 1 || \
743 (type == PCI_EXP_TYPE_ROOT_PORT || \
744 type == PCI_EXP_TYPE_RC_EC))
745 #define pcie_cap_has_devctl2(type, flags) \
746 ((flags & PCI_EXP_FLAGS_VERS) > 1)
747 #define pcie_cap_has_lnkctl2(type, flags) \
748 ((flags & PCI_EXP_FLAGS_VERS) > 1)
749 #define pcie_cap_has_sltctl2(type, flags) \
750 ((flags & PCI_EXP_FLAGS_VERS) > 1)
752 static int pci_save_pcie_state(struct pci_dev *dev)
754 int pos, i = 0;
755 struct pci_cap_saved_state *save_state;
756 u16 *cap;
757 u16 flags;
759 pos = pci_pcie_cap(dev);
760 if (!pos)
761 return 0;
763 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
764 if (!save_state) {
765 dev_err(&dev->dev, "buffer not found in %s\n", __func__);
766 return -ENOMEM;
768 cap = (u16 *)&save_state->data[0];
770 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, &flags);
772 if (pcie_cap_has_devctl(dev->pcie_type, flags))
773 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &cap[i++]);
774 if (pcie_cap_has_lnkctl(dev->pcie_type, flags))
775 pci_read_config_word(dev, pos + PCI_EXP_LNKCTL, &cap[i++]);
776 if (pcie_cap_has_sltctl(dev->pcie_type, flags))
777 pci_read_config_word(dev, pos + PCI_EXP_SLTCTL, &cap[i++]);
778 if (pcie_cap_has_rtctl(dev->pcie_type, flags))
779 pci_read_config_word(dev, pos + PCI_EXP_RTCTL, &cap[i++]);
780 if (pcie_cap_has_devctl2(dev->pcie_type, flags))
781 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &cap[i++]);
782 if (pcie_cap_has_lnkctl2(dev->pcie_type, flags))
783 pci_read_config_word(dev, pos + PCI_EXP_LNKCTL2, &cap[i++]);
784 if (pcie_cap_has_sltctl2(dev->pcie_type, flags))
785 pci_read_config_word(dev, pos + PCI_EXP_SLTCTL2, &cap[i++]);
787 return 0;
790 static void pci_restore_pcie_state(struct pci_dev *dev)
792 int i = 0, pos;
793 struct pci_cap_saved_state *save_state;
794 u16 *cap;
795 u16 flags;
797 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
798 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
799 if (!save_state || pos <= 0)
800 return;
801 cap = (u16 *)&save_state->data[0];
803 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, &flags);
805 if (pcie_cap_has_devctl(dev->pcie_type, flags))
806 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, cap[i++]);
807 if (pcie_cap_has_lnkctl(dev->pcie_type, flags))
808 pci_write_config_word(dev, pos + PCI_EXP_LNKCTL, cap[i++]);
809 if (pcie_cap_has_sltctl(dev->pcie_type, flags))
810 pci_write_config_word(dev, pos + PCI_EXP_SLTCTL, cap[i++]);
811 if (pcie_cap_has_rtctl(dev->pcie_type, flags))
812 pci_write_config_word(dev, pos + PCI_EXP_RTCTL, cap[i++]);
813 if (pcie_cap_has_devctl2(dev->pcie_type, flags))
814 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, cap[i++]);
815 if (pcie_cap_has_lnkctl2(dev->pcie_type, flags))
816 pci_write_config_word(dev, pos + PCI_EXP_LNKCTL2, cap[i++]);
817 if (pcie_cap_has_sltctl2(dev->pcie_type, flags))
818 pci_write_config_word(dev, pos + PCI_EXP_SLTCTL2, cap[i++]);
822 static int pci_save_pcix_state(struct pci_dev *dev)
824 int pos;
825 struct pci_cap_saved_state *save_state;
827 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
828 if (pos <= 0)
829 return 0;
831 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
832 if (!save_state) {
833 dev_err(&dev->dev, "buffer not found in %s\n", __func__);
834 return -ENOMEM;
837 pci_read_config_word(dev, pos + PCI_X_CMD, (u16 *)save_state->data);
839 return 0;
842 static void pci_restore_pcix_state(struct pci_dev *dev)
844 int i = 0, pos;
845 struct pci_cap_saved_state *save_state;
846 u16 *cap;
848 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
849 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
850 if (!save_state || pos <= 0)
851 return;
852 cap = (u16 *)&save_state->data[0];
854 pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]);
859 * pci_save_state - save the PCI configuration space of a device before suspending
860 * @dev: - PCI device that we're dealing with
863 pci_save_state(struct pci_dev *dev)
865 int i;
866 /* XXX: 100% dword access ok here? */
867 for (i = 0; i < 16; i++)
868 pci_read_config_dword(dev, i * 4, &dev->saved_config_space[i]);
869 dev->state_saved = true;
870 if ((i = pci_save_pcie_state(dev)) != 0)
871 return i;
872 if ((i = pci_save_pcix_state(dev)) != 0)
873 return i;
874 return 0;
877 /**
878 * pci_restore_state - Restore the saved state of a PCI device
879 * @dev: - PCI device that we're dealing with
881 int
882 pci_restore_state(struct pci_dev *dev)
884 int i;
885 u32 val;
887 if (!dev->state_saved)
888 return 0;
890 /* PCI Express register must be restored first */
891 pci_restore_pcie_state(dev);
894 * The Base Address register should be programmed before the command
895 * register(s)
897 for (i = 15; i >= 0; i--) {
898 pci_read_config_dword(dev, i * 4, &val);
899 if (val != dev->saved_config_space[i]) {
900 dev_printk(KERN_DEBUG, &dev->dev, "restoring config "
901 "space at offset %#x (was %#x, writing %#x)\n",
902 i, val, (int)dev->saved_config_space[i]);
903 pci_write_config_dword(dev,i * 4,
904 dev->saved_config_space[i]);
907 pci_restore_pcix_state(dev);
908 pci_restore_msi_state(dev);
909 pci_restore_iov_state(dev);
911 dev->state_saved = false;
913 return 0;
916 static int do_pci_enable_device(struct pci_dev *dev, int bars)
918 int err;
920 err = pci_set_power_state(dev, PCI_D0);
921 if (err < 0 && err != -EIO)
922 return err;
923 err = pcibios_enable_device(dev, bars);
924 if (err < 0)
925 return err;
926 pci_fixup_device(pci_fixup_enable, dev);
928 return 0;
932 * pci_reenable_device - Resume abandoned device
933 * @dev: PCI device to be resumed
935 * Note this function is a backend of pci_default_resume and is not supposed
936 * to be called by normal code, write proper resume handler and use it instead.
938 int pci_reenable_device(struct pci_dev *dev)
940 if (pci_is_enabled(dev))
941 return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1);
942 return 0;
945 static int __pci_enable_device_flags(struct pci_dev *dev,
946 resource_size_t flags)
948 int err;
949 int i, bars = 0;
951 if (atomic_add_return(1, &dev->enable_cnt) > 1)
952 return 0; /* already enabled */
954 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
955 if (dev->resource[i].flags & flags)
956 bars |= (1 << i);
958 err = do_pci_enable_device(dev, bars);
959 if (err < 0)
960 atomic_dec(&dev->enable_cnt);
961 return err;
965 * pci_enable_device_io - Initialize a device for use with IO space
966 * @dev: PCI device to be initialized
968 * Initialize device before it's used by a driver. Ask low-level code
969 * to enable I/O resources. Wake up the device if it was suspended.
970 * Beware, this function can fail.
972 int pci_enable_device_io(struct pci_dev *dev)
974 return __pci_enable_device_flags(dev, IORESOURCE_IO);
978 * pci_enable_device_mem - Initialize a device for use with Memory space
979 * @dev: PCI device to be initialized
981 * Initialize device before it's used by a driver. Ask low-level code
982 * to enable Memory resources. Wake up the device if it was suspended.
983 * Beware, this function can fail.
985 int pci_enable_device_mem(struct pci_dev *dev)
987 return __pci_enable_device_flags(dev, IORESOURCE_MEM);
991 * pci_enable_device - Initialize device before it's used by a driver.
992 * @dev: PCI device to be initialized
994 * Initialize device before it's used by a driver. Ask low-level code
995 * to enable I/O and memory. Wake up the device if it was suspended.
996 * Beware, this function can fail.
998 * Note we don't actually enable the device many times if we call
999 * this function repeatedly (we just increment the count).
1001 int pci_enable_device(struct pci_dev *dev)
1003 return __pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO);
1007 * Managed PCI resources. This manages device on/off, intx/msi/msix
1008 * on/off and BAR regions. pci_dev itself records msi/msix status, so
1009 * there's no need to track it separately. pci_devres is initialized
1010 * when a device is enabled using managed PCI device enable interface.
1012 struct pci_devres {
1013 unsigned int enabled:1;
1014 unsigned int pinned:1;
1015 unsigned int orig_intx:1;
1016 unsigned int restore_intx:1;
1017 u32 region_mask;
1020 static void pcim_release(struct device *gendev, void *res)
1022 struct pci_dev *dev = container_of(gendev, struct pci_dev, dev);
1023 struct pci_devres *this = res;
1024 int i;
1026 if (dev->msi_enabled)
1027 pci_disable_msi(dev);
1028 if (dev->msix_enabled)
1029 pci_disable_msix(dev);
1031 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
1032 if (this->region_mask & (1 << i))
1033 pci_release_region(dev, i);
1035 if (this->restore_intx)
1036 pci_intx(dev, this->orig_intx);
1038 if (this->enabled && !this->pinned)
1039 pci_disable_device(dev);
1042 static struct pci_devres * get_pci_dr(struct pci_dev *pdev)
1044 struct pci_devres *dr, *new_dr;
1046 dr = devres_find(&pdev->dev, pcim_release, NULL, NULL);
1047 if (dr)
1048 return dr;
1050 new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL);
1051 if (!new_dr)
1052 return NULL;
1053 return devres_get(&pdev->dev, new_dr, NULL, NULL);
1056 static struct pci_devres * find_pci_dr(struct pci_dev *pdev)
1058 if (pci_is_managed(pdev))
1059 return devres_find(&pdev->dev, pcim_release, NULL, NULL);
1060 return NULL;
1064 * pcim_enable_device - Managed pci_enable_device()
1065 * @pdev: PCI device to be initialized
1067 * Managed pci_enable_device().
1069 int pcim_enable_device(struct pci_dev *pdev)
1071 struct pci_devres *dr;
1072 int rc;
1074 dr = get_pci_dr(pdev);
1075 if (unlikely(!dr))
1076 return -ENOMEM;
1077 if (dr->enabled)
1078 return 0;
1080 rc = pci_enable_device(pdev);
1081 if (!rc) {
1082 pdev->is_managed = 1;
1083 dr->enabled = 1;
1085 return rc;
1089 * pcim_pin_device - Pin managed PCI device
1090 * @pdev: PCI device to pin
1092 * Pin managed PCI device @pdev. Pinned device won't be disabled on
1093 * driver detach. @pdev must have been enabled with
1094 * pcim_enable_device().
1096 void pcim_pin_device(struct pci_dev *pdev)
1098 struct pci_devres *dr;
1100 dr = find_pci_dr(pdev);
1101 WARN_ON(!dr || !dr->enabled);
1102 if (dr)
1103 dr->pinned = 1;
1107 * pcibios_disable_device - disable arch specific PCI resources for device dev
1108 * @dev: the PCI device to disable
1110 * Disables architecture specific PCI resources for the device. This
1111 * is the default implementation. Architecture implementations can
1112 * override this.
1114 void __attribute__ ((weak)) pcibios_disable_device (struct pci_dev *dev) {}
1116 static void do_pci_disable_device(struct pci_dev *dev)
1118 u16 pci_command;
1120 pci_read_config_word(dev, PCI_COMMAND, &pci_command);
1121 if (pci_command & PCI_COMMAND_MASTER) {
1122 pci_command &= ~PCI_COMMAND_MASTER;
1123 pci_write_config_word(dev, PCI_COMMAND, pci_command);
1126 pcibios_disable_device(dev);
1130 * pci_disable_enabled_device - Disable device without updating enable_cnt
1131 * @dev: PCI device to disable
1133 * NOTE: This function is a backend of PCI power management routines and is
1134 * not supposed to be called drivers.
1136 void pci_disable_enabled_device(struct pci_dev *dev)
1138 if (pci_is_enabled(dev))
1139 do_pci_disable_device(dev);
1143 * pci_disable_device - Disable PCI device after use
1144 * @dev: PCI device to be disabled
1146 * Signal to the system that the PCI device is not in use by the system
1147 * anymore. This only involves disabling PCI bus-mastering, if active.
1149 * Note we don't actually disable the device until all callers of
1150 * pci_device_enable() have called pci_device_disable().
1152 void
1153 pci_disable_device(struct pci_dev *dev)
1155 struct pci_devres *dr;
1157 dr = find_pci_dr(dev);
1158 if (dr)
1159 dr->enabled = 0;
1161 if (atomic_sub_return(1, &dev->enable_cnt) != 0)
1162 return;
1164 do_pci_disable_device(dev);
1166 dev->is_busmaster = 0;
1170 * pcibios_set_pcie_reset_state - set reset state for device dev
1171 * @dev: the PCIe device reset
1172 * @state: Reset state to enter into
1175 * Sets the PCIe reset state for the device. This is the default
1176 * implementation. Architecture implementations can override this.
1178 int __attribute__ ((weak)) pcibios_set_pcie_reset_state(struct pci_dev *dev,
1179 enum pcie_reset_state state)
1181 return -EINVAL;
1185 * pci_set_pcie_reset_state - set reset state for device dev
1186 * @dev: the PCIe device reset
1187 * @state: Reset state to enter into
1190 * Sets the PCI reset state for the device.
1192 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state)
1194 return pcibios_set_pcie_reset_state(dev, state);
1198 * pci_pme_capable - check the capability of PCI device to generate PME#
1199 * @dev: PCI device to handle.
1200 * @state: PCI state from which device will issue PME#.
1202 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state)
1204 if (!dev->pm_cap)
1205 return false;
1207 return !!(dev->pme_support & (1 << state));
1211 * pci_pme_active - enable or disable PCI device's PME# function
1212 * @dev: PCI device to handle.
1213 * @enable: 'true' to enable PME# generation; 'false' to disable it.
1215 * The caller must verify that the device is capable of generating PME# before
1216 * calling this function with @enable equal to 'true'.
1218 void pci_pme_active(struct pci_dev *dev, bool enable)
1220 u16 pmcsr;
1222 if (!dev->pm_cap)
1223 return;
1225 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1226 /* Clear PME_Status by writing 1 to it and enable PME# */
1227 pmcsr |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE;
1228 if (!enable)
1229 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
1231 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
1233 dev_printk(KERN_DEBUG, &dev->dev, "PME# %s\n",
1234 enable ? "enabled" : "disabled");
1238 * pci_enable_wake - enable PCI device as wakeup event source
1239 * @dev: PCI device affected
1240 * @state: PCI state from which device will issue wakeup events
1241 * @enable: True to enable event generation; false to disable
1243 * This enables the device as a wakeup event source, or disables it.
1244 * When such events involves platform-specific hooks, those hooks are
1245 * called automatically by this routine.
1247 * Devices with legacy power management (no standard PCI PM capabilities)
1248 * always require such platform hooks.
1250 * RETURN VALUE:
1251 * 0 is returned on success
1252 * -EINVAL is returned if device is not supposed to wake up the system
1253 * Error code depending on the platform is returned if both the platform and
1254 * the native mechanism fail to enable the generation of wake-up events
1256 int pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable)
1258 int ret = 0;
1260 if (enable && !device_may_wakeup(&dev->dev))
1261 return -EINVAL;
1263 /* Don't do the same thing twice in a row for one device. */
1264 if (!!enable == !!dev->wakeup_prepared)
1265 return 0;
1268 * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don
1269 * Anderson we should be doing PME# wake enable followed by ACPI wake
1270 * enable. To disable wake-up we call the platform first, for symmetry.
1273 if (enable) {
1274 int error;
1276 if (pci_pme_capable(dev, state))
1277 pci_pme_active(dev, true);
1278 else
1279 ret = 1;
1280 error = platform_pci_sleep_wake(dev, true);
1281 if (ret)
1282 ret = error;
1283 if (!ret)
1284 dev->wakeup_prepared = true;
1285 } else {
1286 platform_pci_sleep_wake(dev, false);
1287 pci_pme_active(dev, false);
1288 dev->wakeup_prepared = false;
1291 return ret;
1295 * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold
1296 * @dev: PCI device to prepare
1297 * @enable: True to enable wake-up event generation; false to disable
1299 * Many drivers want the device to wake up the system from D3_hot or D3_cold
1300 * and this function allows them to set that up cleanly - pci_enable_wake()
1301 * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI
1302 * ordering constraints.
1304 * This function only returns error code if the device is not capable of
1305 * generating PME# from both D3_hot and D3_cold, and the platform is unable to
1306 * enable wake-up power for it.
1308 int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1310 return pci_pme_capable(dev, PCI_D3cold) ?
1311 pci_enable_wake(dev, PCI_D3cold, enable) :
1312 pci_enable_wake(dev, PCI_D3hot, enable);
1316 * pci_target_state - find an appropriate low power state for a given PCI dev
1317 * @dev: PCI device
1319 * Use underlying platform code to find a supported low power state for @dev.
1320 * If the platform can't manage @dev, return the deepest state from which it
1321 * can generate wake events, based on any available PME info.
1323 pci_power_t pci_target_state(struct pci_dev *dev)
1325 pci_power_t target_state = PCI_D3hot;
1327 if (platform_pci_power_manageable(dev)) {
1329 * Call the platform to choose the target state of the device
1330 * and enable wake-up from this state if supported.
1332 pci_power_t state = platform_pci_choose_state(dev);
1334 switch (state) {
1335 case PCI_POWER_ERROR:
1336 case PCI_UNKNOWN:
1337 break;
1338 case PCI_D1:
1339 case PCI_D2:
1340 if (pci_no_d1d2(dev))
1341 break;
1342 default:
1343 target_state = state;
1345 } else if (!dev->pm_cap) {
1346 target_state = PCI_D0;
1347 } else if (device_may_wakeup(&dev->dev)) {
1349 * Find the deepest state from which the device can generate
1350 * wake-up events, make it the target state and enable device
1351 * to generate PME#.
1353 if (dev->pme_support) {
1354 while (target_state
1355 && !(dev->pme_support & (1 << target_state)))
1356 target_state--;
1360 return target_state;
1364 * pci_prepare_to_sleep - prepare PCI device for system-wide transition into a sleep state
1365 * @dev: Device to handle.
1367 * Choose the power state appropriate for the device depending on whether
1368 * it can wake up the system and/or is power manageable by the platform
1369 * (PCI_D3hot is the default) and put the device into that state.
1371 int pci_prepare_to_sleep(struct pci_dev *dev)
1373 pci_power_t target_state = pci_target_state(dev);
1374 int error;
1376 if (target_state == PCI_POWER_ERROR)
1377 return -EIO;
1379 pci_enable_wake(dev, target_state, device_may_wakeup(&dev->dev));
1381 error = pci_set_power_state(dev, target_state);
1383 if (error)
1384 pci_enable_wake(dev, target_state, false);
1386 return error;
1390 * pci_back_from_sleep - turn PCI device on during system-wide transition into working state
1391 * @dev: Device to handle.
1393 * Disable device's sytem wake-up capability and put it into D0.
1395 int pci_back_from_sleep(struct pci_dev *dev)
1397 pci_enable_wake(dev, PCI_D0, false);
1398 return pci_set_power_state(dev, PCI_D0);
1402 * pci_pm_init - Initialize PM functions of given PCI device
1403 * @dev: PCI device to handle.
1405 void pci_pm_init(struct pci_dev *dev)
1407 int pm;
1408 u16 pmc;
1410 dev->wakeup_prepared = false;
1411 dev->pm_cap = 0;
1413 /* find PCI PM capability in list */
1414 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
1415 if (!pm)
1416 return;
1417 /* Check device's ability to generate PME# */
1418 pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc);
1420 if ((pmc & PCI_PM_CAP_VER_MASK) > 3) {
1421 dev_err(&dev->dev, "unsupported PM cap regs version (%u)\n",
1422 pmc & PCI_PM_CAP_VER_MASK);
1423 return;
1426 dev->pm_cap = pm;
1427 dev->d3_delay = PCI_PM_D3_WAIT;
1429 dev->d1_support = false;
1430 dev->d2_support = false;
1431 if (!pci_no_d1d2(dev)) {
1432 if (pmc & PCI_PM_CAP_D1)
1433 dev->d1_support = true;
1434 if (pmc & PCI_PM_CAP_D2)
1435 dev->d2_support = true;
1437 if (dev->d1_support || dev->d2_support)
1438 dev_printk(KERN_DEBUG, &dev->dev, "supports%s%s\n",
1439 dev->d1_support ? " D1" : "",
1440 dev->d2_support ? " D2" : "");
1443 pmc &= PCI_PM_CAP_PME_MASK;
1444 if (pmc) {
1445 dev_printk(KERN_DEBUG, &dev->dev,
1446 "PME# supported from%s%s%s%s%s\n",
1447 (pmc & PCI_PM_CAP_PME_D0) ? " D0" : "",
1448 (pmc & PCI_PM_CAP_PME_D1) ? " D1" : "",
1449 (pmc & PCI_PM_CAP_PME_D2) ? " D2" : "",
1450 (pmc & PCI_PM_CAP_PME_D3) ? " D3hot" : "",
1451 (pmc & PCI_PM_CAP_PME_D3cold) ? " D3cold" : "");
1452 dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT;
1454 * Make device's PM flags reflect the wake-up capability, but
1455 * let the user space enable it to wake up the system as needed.
1457 device_set_wakeup_capable(&dev->dev, true);
1458 device_set_wakeup_enable(&dev->dev, false);
1459 /* Disable the PME# generation functionality */
1460 pci_pme_active(dev, false);
1461 } else {
1462 dev->pme_support = 0;
1467 * platform_pci_wakeup_init - init platform wakeup if present
1468 * @dev: PCI device
1470 * Some devices don't have PCI PM caps but can still generate wakeup
1471 * events through platform methods (like ACPI events). If @dev supports
1472 * platform wakeup events, set the device flag to indicate as much. This
1473 * may be redundant if the device also supports PCI PM caps, but double
1474 * initialization should be safe in that case.
1476 void platform_pci_wakeup_init(struct pci_dev *dev)
1478 if (!platform_pci_can_wakeup(dev))
1479 return;
1481 device_set_wakeup_capable(&dev->dev, true);
1482 device_set_wakeup_enable(&dev->dev, false);
1483 platform_pci_sleep_wake(dev, false);
1487 * pci_add_save_buffer - allocate buffer for saving given capability registers
1488 * @dev: the PCI device
1489 * @cap: the capability to allocate the buffer for
1490 * @size: requested size of the buffer
1492 static int pci_add_cap_save_buffer(
1493 struct pci_dev *dev, char cap, unsigned int size)
1495 int pos;
1496 struct pci_cap_saved_state *save_state;
1498 pos = pci_find_capability(dev, cap);
1499 if (pos <= 0)
1500 return 0;
1502 save_state = kzalloc(sizeof(*save_state) + size, GFP_KERNEL);
1503 if (!save_state)
1504 return -ENOMEM;
1506 save_state->cap_nr = cap;
1507 pci_add_saved_cap(dev, save_state);
1509 return 0;
1513 * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities
1514 * @dev: the PCI device
1516 void pci_allocate_cap_save_buffers(struct pci_dev *dev)
1518 int error;
1520 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_EXP,
1521 PCI_EXP_SAVE_REGS * sizeof(u16));
1522 if (error)
1523 dev_err(&dev->dev,
1524 "unable to preallocate PCI Express save buffer\n");
1526 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_PCIX, sizeof(u16));
1527 if (error)
1528 dev_err(&dev->dev,
1529 "unable to preallocate PCI-X save buffer\n");
1533 * pci_enable_ari - enable ARI forwarding if hardware support it
1534 * @dev: the PCI device
1536 void pci_enable_ari(struct pci_dev *dev)
1538 int pos;
1539 u32 cap;
1540 u16 ctrl;
1541 struct pci_dev *bridge;
1543 if (!pci_is_pcie(dev) || dev->devfn)
1544 return;
1546 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI);
1547 if (!pos)
1548 return;
1550 bridge = dev->bus->self;
1551 if (!bridge || !pci_is_pcie(bridge))
1552 return;
1554 pos = pci_pcie_cap(bridge);
1555 if (!pos)
1556 return;
1558 pci_read_config_dword(bridge, pos + PCI_EXP_DEVCAP2, &cap);
1559 if (!(cap & PCI_EXP_DEVCAP2_ARI))
1560 return;
1562 pci_read_config_word(bridge, pos + PCI_EXP_DEVCTL2, &ctrl);
1563 ctrl |= PCI_EXP_DEVCTL2_ARI;
1564 pci_write_config_word(bridge, pos + PCI_EXP_DEVCTL2, ctrl);
1566 bridge->ari_enabled = 1;
1569 static int pci_acs_enable;
1572 * pci_request_acs - ask for ACS to be enabled if supported
1574 void pci_request_acs(void)
1576 pci_acs_enable = 1;
1580 * pci_enable_acs - enable ACS if hardware support it
1581 * @dev: the PCI device
1583 void pci_enable_acs(struct pci_dev *dev)
1585 int pos;
1586 u16 cap;
1587 u16 ctrl;
1589 if (!pci_acs_enable)
1590 return;
1592 if (!pci_is_pcie(dev))
1593 return;
1595 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
1596 if (!pos)
1597 return;
1599 pci_read_config_word(dev, pos + PCI_ACS_CAP, &cap);
1600 pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl);
1602 /* Source Validation */
1603 ctrl |= (cap & PCI_ACS_SV);
1605 /* P2P Request Redirect */
1606 ctrl |= (cap & PCI_ACS_RR);
1608 /* P2P Completion Redirect */
1609 ctrl |= (cap & PCI_ACS_CR);
1611 /* Upstream Forwarding */
1612 ctrl |= (cap & PCI_ACS_UF);
1614 pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl);
1618 * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge
1619 * @dev: the PCI device
1620 * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTD, 4=INTD)
1622 * Perform INTx swizzling for a device behind one level of bridge. This is
1623 * required by section 9.1 of the PCI-to-PCI bridge specification for devices
1624 * behind bridges on add-in cards. For devices with ARI enabled, the slot
1625 * number is always 0 (see the Implementation Note in section 2.2.8.1 of
1626 * the PCI Express Base Specification, Revision 2.1)
1628 u8 pci_swizzle_interrupt_pin(struct pci_dev *dev, u8 pin)
1630 int slot;
1632 if (pci_ari_enabled(dev->bus))
1633 slot = 0;
1634 else
1635 slot = PCI_SLOT(dev->devfn);
1637 return (((pin - 1) + slot) % 4) + 1;
1641 pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge)
1643 u8 pin;
1645 pin = dev->pin;
1646 if (!pin)
1647 return -1;
1649 while (!pci_is_root_bus(dev->bus)) {
1650 pin = pci_swizzle_interrupt_pin(dev, pin);
1651 dev = dev->bus->self;
1653 *bridge = dev;
1654 return pin;
1658 * pci_common_swizzle - swizzle INTx all the way to root bridge
1659 * @dev: the PCI device
1660 * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD)
1662 * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI
1663 * bridges all the way up to a PCI root bus.
1665 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp)
1667 u8 pin = *pinp;
1669 while (!pci_is_root_bus(dev->bus)) {
1670 pin = pci_swizzle_interrupt_pin(dev, pin);
1671 dev = dev->bus->self;
1673 *pinp = pin;
1674 return PCI_SLOT(dev->devfn);
1678 * pci_release_region - Release a PCI bar
1679 * @pdev: PCI device whose resources were previously reserved by pci_request_region
1680 * @bar: BAR to release
1682 * Releases the PCI I/O and memory resources previously reserved by a
1683 * successful call to pci_request_region. Call this function only
1684 * after all use of the PCI regions has ceased.
1686 void pci_release_region(struct pci_dev *pdev, int bar)
1688 struct pci_devres *dr;
1690 if (pci_resource_len(pdev, bar) == 0)
1691 return;
1692 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO)
1693 release_region(pci_resource_start(pdev, bar),
1694 pci_resource_len(pdev, bar));
1695 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM)
1696 release_mem_region(pci_resource_start(pdev, bar),
1697 pci_resource_len(pdev, bar));
1699 dr = find_pci_dr(pdev);
1700 if (dr)
1701 dr->region_mask &= ~(1 << bar);
1705 * __pci_request_region - Reserved PCI I/O and memory resource
1706 * @pdev: PCI device whose resources are to be reserved
1707 * @bar: BAR to be reserved
1708 * @res_name: Name to be associated with resource.
1709 * @exclusive: whether the region access is exclusive or not
1711 * Mark the PCI region associated with PCI device @pdev BR @bar as
1712 * being reserved by owner @res_name. Do not access any
1713 * address inside the PCI regions unless this call returns
1714 * successfully.
1716 * If @exclusive is set, then the region is marked so that userspace
1717 * is explicitly not allowed to map the resource via /dev/mem or
1718 * sysfs MMIO access.
1720 * Returns 0 on success, or %EBUSY on error. A warning
1721 * message is also printed on failure.
1723 static int __pci_request_region(struct pci_dev *pdev, int bar, const char *res_name,
1724 int exclusive)
1726 struct pci_devres *dr;
1728 if (pci_resource_len(pdev, bar) == 0)
1729 return 0;
1731 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) {
1732 if (!request_region(pci_resource_start(pdev, bar),
1733 pci_resource_len(pdev, bar), res_name))
1734 goto err_out;
1736 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
1737 if (!__request_mem_region(pci_resource_start(pdev, bar),
1738 pci_resource_len(pdev, bar), res_name,
1739 exclusive))
1740 goto err_out;
1743 dr = find_pci_dr(pdev);
1744 if (dr)
1745 dr->region_mask |= 1 << bar;
1747 return 0;
1749 err_out:
1750 dev_warn(&pdev->dev, "BAR %d: can't reserve %pR\n", bar,
1751 &pdev->resource[bar]);
1752 return -EBUSY;
1756 * pci_request_region - Reserve PCI I/O and memory resource
1757 * @pdev: PCI device whose resources are to be reserved
1758 * @bar: BAR to be reserved
1759 * @res_name: Name to be associated with resource
1761 * Mark the PCI region associated with PCI device @pdev BAR @bar as
1762 * being reserved by owner @res_name. Do not access any
1763 * address inside the PCI regions unless this call returns
1764 * successfully.
1766 * Returns 0 on success, or %EBUSY on error. A warning
1767 * message is also printed on failure.
1769 int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name)
1771 return __pci_request_region(pdev, bar, res_name, 0);
1775 * pci_request_region_exclusive - Reserved PCI I/O and memory resource
1776 * @pdev: PCI device whose resources are to be reserved
1777 * @bar: BAR to be reserved
1778 * @res_name: Name to be associated with resource.
1780 * Mark the PCI region associated with PCI device @pdev BR @bar as
1781 * being reserved by owner @res_name. Do not access any
1782 * address inside the PCI regions unless this call returns
1783 * successfully.
1785 * Returns 0 on success, or %EBUSY on error. A warning
1786 * message is also printed on failure.
1788 * The key difference that _exclusive makes it that userspace is
1789 * explicitly not allowed to map the resource via /dev/mem or
1790 * sysfs.
1792 int pci_request_region_exclusive(struct pci_dev *pdev, int bar, const char *res_name)
1794 return __pci_request_region(pdev, bar, res_name, IORESOURCE_EXCLUSIVE);
1797 * pci_release_selected_regions - Release selected PCI I/O and memory resources
1798 * @pdev: PCI device whose resources were previously reserved
1799 * @bars: Bitmask of BARs to be released
1801 * Release selected PCI I/O and memory resources previously reserved.
1802 * Call this function only after all use of the PCI regions has ceased.
1804 void pci_release_selected_regions(struct pci_dev *pdev, int bars)
1806 int i;
1808 for (i = 0; i < 6; i++)
1809 if (bars & (1 << i))
1810 pci_release_region(pdev, i);
1813 int __pci_request_selected_regions(struct pci_dev *pdev, int bars,
1814 const char *res_name, int excl)
1816 int i;
1818 for (i = 0; i < 6; i++)
1819 if (bars & (1 << i))
1820 if (__pci_request_region(pdev, i, res_name, excl))
1821 goto err_out;
1822 return 0;
1824 err_out:
1825 while(--i >= 0)
1826 if (bars & (1 << i))
1827 pci_release_region(pdev, i);
1829 return -EBUSY;
1834 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
1835 * @pdev: PCI device whose resources are to be reserved
1836 * @bars: Bitmask of BARs to be requested
1837 * @res_name: Name to be associated with resource
1839 int pci_request_selected_regions(struct pci_dev *pdev, int bars,
1840 const char *res_name)
1842 return __pci_request_selected_regions(pdev, bars, res_name, 0);
1845 int pci_request_selected_regions_exclusive(struct pci_dev *pdev,
1846 int bars, const char *res_name)
1848 return __pci_request_selected_regions(pdev, bars, res_name,
1849 IORESOURCE_EXCLUSIVE);
1853 * pci_release_regions - Release reserved PCI I/O and memory resources
1854 * @pdev: PCI device whose resources were previously reserved by pci_request_regions
1856 * Releases all PCI I/O and memory resources previously reserved by a
1857 * successful call to pci_request_regions. Call this function only
1858 * after all use of the PCI regions has ceased.
1861 void pci_release_regions(struct pci_dev *pdev)
1863 pci_release_selected_regions(pdev, (1 << 6) - 1);
1867 * pci_request_regions - Reserved PCI I/O and memory resources
1868 * @pdev: PCI device whose resources are to be reserved
1869 * @res_name: Name to be associated with resource.
1871 * Mark all PCI regions associated with PCI device @pdev as
1872 * being reserved by owner @res_name. Do not access any
1873 * address inside the PCI regions unless this call returns
1874 * successfully.
1876 * Returns 0 on success, or %EBUSY on error. A warning
1877 * message is also printed on failure.
1879 int pci_request_regions(struct pci_dev *pdev, const char *res_name)
1881 return pci_request_selected_regions(pdev, ((1 << 6) - 1), res_name);
1885 * pci_request_regions_exclusive - Reserved PCI I/O and memory resources
1886 * @pdev: PCI device whose resources are to be reserved
1887 * @res_name: Name to be associated with resource.
1889 * Mark all PCI regions associated with PCI device @pdev as
1890 * being reserved by owner @res_name. Do not access any
1891 * address inside the PCI regions unless this call returns
1892 * successfully.
1894 * pci_request_regions_exclusive() will mark the region so that
1895 * /dev/mem and the sysfs MMIO access will not be allowed.
1897 * Returns 0 on success, or %EBUSY on error. A warning
1898 * message is also printed on failure.
1900 int pci_request_regions_exclusive(struct pci_dev *pdev, const char *res_name)
1902 return pci_request_selected_regions_exclusive(pdev,
1903 ((1 << 6) - 1), res_name);
1906 static void __pci_set_master(struct pci_dev *dev, bool enable)
1908 u16 old_cmd, cmd;
1910 pci_read_config_word(dev, PCI_COMMAND, &old_cmd);
1911 if (enable)
1912 cmd = old_cmd | PCI_COMMAND_MASTER;
1913 else
1914 cmd = old_cmd & ~PCI_COMMAND_MASTER;
1915 if (cmd != old_cmd) {
1916 dev_dbg(&dev->dev, "%s bus mastering\n",
1917 enable ? "enabling" : "disabling");
1918 pci_write_config_word(dev, PCI_COMMAND, cmd);
1920 dev->is_busmaster = enable;
1924 * pci_set_master - enables bus-mastering for device dev
1925 * @dev: the PCI device to enable
1927 * Enables bus-mastering on the device and calls pcibios_set_master()
1928 * to do the needed arch specific settings.
1930 void pci_set_master(struct pci_dev *dev)
1932 __pci_set_master(dev, true);
1933 pcibios_set_master(dev);
1937 * pci_clear_master - disables bus-mastering for device dev
1938 * @dev: the PCI device to disable
1940 void pci_clear_master(struct pci_dev *dev)
1942 __pci_set_master(dev, false);
1946 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
1947 * @dev: the PCI device for which MWI is to be enabled
1949 * Helper function for pci_set_mwi.
1950 * Originally copied from drivers/net/acenic.c.
1951 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
1953 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
1955 int pci_set_cacheline_size(struct pci_dev *dev)
1957 u8 cacheline_size;
1959 if (!pci_cache_line_size)
1960 return -EINVAL;
1962 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
1963 equal to or multiple of the right value. */
1964 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
1965 if (cacheline_size >= pci_cache_line_size &&
1966 (cacheline_size % pci_cache_line_size) == 0)
1967 return 0;
1969 /* Write the correct value. */
1970 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size);
1971 /* Read it back. */
1972 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
1973 if (cacheline_size == pci_cache_line_size)
1974 return 0;
1976 dev_printk(KERN_DEBUG, &dev->dev, "cache line size of %d is not "
1977 "supported\n", pci_cache_line_size << 2);
1979 return -EINVAL;
1981 EXPORT_SYMBOL_GPL(pci_set_cacheline_size);
1983 #ifdef PCI_DISABLE_MWI
1984 int pci_set_mwi(struct pci_dev *dev)
1986 return 0;
1989 int pci_try_set_mwi(struct pci_dev *dev)
1991 return 0;
1994 void pci_clear_mwi(struct pci_dev *dev)
1998 #else
2001 * pci_set_mwi - enables memory-write-invalidate PCI transaction
2002 * @dev: the PCI device for which MWI is enabled
2004 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
2006 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2009 pci_set_mwi(struct pci_dev *dev)
2011 int rc;
2012 u16 cmd;
2014 rc = pci_set_cacheline_size(dev);
2015 if (rc)
2016 return rc;
2018 pci_read_config_word(dev, PCI_COMMAND, &cmd);
2019 if (! (cmd & PCI_COMMAND_INVALIDATE)) {
2020 dev_dbg(&dev->dev, "enabling Mem-Wr-Inval\n");
2021 cmd |= PCI_COMMAND_INVALIDATE;
2022 pci_write_config_word(dev, PCI_COMMAND, cmd);
2025 return 0;
2029 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
2030 * @dev: the PCI device for which MWI is enabled
2032 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
2033 * Callers are not required to check the return value.
2035 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2037 int pci_try_set_mwi(struct pci_dev *dev)
2039 int rc = pci_set_mwi(dev);
2040 return rc;
2044 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
2045 * @dev: the PCI device to disable
2047 * Disables PCI Memory-Write-Invalidate transaction on the device
2049 void
2050 pci_clear_mwi(struct pci_dev *dev)
2052 u16 cmd;
2054 pci_read_config_word(dev, PCI_COMMAND, &cmd);
2055 if (cmd & PCI_COMMAND_INVALIDATE) {
2056 cmd &= ~PCI_COMMAND_INVALIDATE;
2057 pci_write_config_word(dev, PCI_COMMAND, cmd);
2060 #endif /* ! PCI_DISABLE_MWI */
2063 * pci_intx - enables/disables PCI INTx for device dev
2064 * @pdev: the PCI device to operate on
2065 * @enable: boolean: whether to enable or disable PCI INTx
2067 * Enables/disables PCI INTx for device dev
2069 void
2070 pci_intx(struct pci_dev *pdev, int enable)
2072 u16 pci_command, new;
2074 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
2076 if (enable) {
2077 new = pci_command & ~PCI_COMMAND_INTX_DISABLE;
2078 } else {
2079 new = pci_command | PCI_COMMAND_INTX_DISABLE;
2082 if (new != pci_command) {
2083 struct pci_devres *dr;
2085 pci_write_config_word(pdev, PCI_COMMAND, new);
2087 dr = find_pci_dr(pdev);
2088 if (dr && !dr->restore_intx) {
2089 dr->restore_intx = 1;
2090 dr->orig_intx = !enable;
2096 * pci_msi_off - disables any msi or msix capabilities
2097 * @dev: the PCI device to operate on
2099 * If you want to use msi see pci_enable_msi and friends.
2100 * This is a lower level primitive that allows us to disable
2101 * msi operation at the device level.
2103 void pci_msi_off(struct pci_dev *dev)
2105 int pos;
2106 u16 control;
2108 pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
2109 if (pos) {
2110 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control);
2111 control &= ~PCI_MSI_FLAGS_ENABLE;
2112 pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control);
2114 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
2115 if (pos) {
2116 pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control);
2117 control &= ~PCI_MSIX_FLAGS_ENABLE;
2118 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
2122 #ifndef HAVE_ARCH_PCI_SET_DMA_MASK
2124 * These can be overridden by arch-specific implementations
2127 pci_set_dma_mask(struct pci_dev *dev, u64 mask)
2129 if (!pci_dma_supported(dev, mask))
2130 return -EIO;
2132 dev->dma_mask = mask;
2133 dev_dbg(&dev->dev, "using %dbit DMA mask\n", fls64(mask));
2135 return 0;
2139 pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask)
2141 if (!pci_dma_supported(dev, mask))
2142 return -EIO;
2144 dev->dev.coherent_dma_mask = mask;
2145 dev_dbg(&dev->dev, "using %dbit consistent DMA mask\n", fls64(mask));
2147 return 0;
2149 #endif
2151 #ifndef HAVE_ARCH_PCI_SET_DMA_MAX_SEGMENT_SIZE
2152 int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size)
2154 return dma_set_max_seg_size(&dev->dev, size);
2156 EXPORT_SYMBOL(pci_set_dma_max_seg_size);
2157 #endif
2159 #ifndef HAVE_ARCH_PCI_SET_DMA_SEGMENT_BOUNDARY
2160 int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask)
2162 return dma_set_seg_boundary(&dev->dev, mask);
2164 EXPORT_SYMBOL(pci_set_dma_seg_boundary);
2165 #endif
2167 static int pcie_flr(struct pci_dev *dev, int probe)
2169 int i;
2170 int pos;
2171 u32 cap;
2172 u16 status, control;
2174 pos = pci_pcie_cap(dev);
2175 if (!pos)
2176 return -ENOTTY;
2178 pci_read_config_dword(dev, pos + PCI_EXP_DEVCAP, &cap);
2179 if (!(cap & PCI_EXP_DEVCAP_FLR))
2180 return -ENOTTY;
2182 if (probe)
2183 return 0;
2185 /* Wait for Transaction Pending bit clean */
2186 for (i = 0; i < 4; i++) {
2187 if (i)
2188 msleep((1 << (i - 1)) * 100);
2190 pci_read_config_word(dev, pos + PCI_EXP_DEVSTA, &status);
2191 if (!(status & PCI_EXP_DEVSTA_TRPND))
2192 goto clear;
2195 dev_err(&dev->dev, "transaction is not cleared; "
2196 "proceeding with reset anyway\n");
2198 clear:
2199 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &control);
2200 control |= PCI_EXP_DEVCTL_BCR_FLR;
2201 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, control);
2203 msleep(100);
2205 return 0;
2208 static int pci_af_flr(struct pci_dev *dev, int probe)
2210 int i;
2211 int pos;
2212 u8 cap;
2213 u8 status;
2215 pos = pci_find_capability(dev, PCI_CAP_ID_AF);
2216 if (!pos)
2217 return -ENOTTY;
2219 pci_read_config_byte(dev, pos + PCI_AF_CAP, &cap);
2220 if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR))
2221 return -ENOTTY;
2223 if (probe)
2224 return 0;
2226 /* Wait for Transaction Pending bit clean */
2227 for (i = 0; i < 4; i++) {
2228 if (i)
2229 msleep((1 << (i - 1)) * 100);
2231 pci_read_config_byte(dev, pos + PCI_AF_STATUS, &status);
2232 if (!(status & PCI_AF_STATUS_TP))
2233 goto clear;
2236 dev_err(&dev->dev, "transaction is not cleared; "
2237 "proceeding with reset anyway\n");
2239 clear:
2240 pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR);
2241 msleep(100);
2243 return 0;
2246 static int pci_pm_reset(struct pci_dev *dev, int probe)
2248 u16 csr;
2250 if (!dev->pm_cap)
2251 return -ENOTTY;
2253 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &csr);
2254 if (csr & PCI_PM_CTRL_NO_SOFT_RESET)
2255 return -ENOTTY;
2257 if (probe)
2258 return 0;
2260 if (dev->current_state != PCI_D0)
2261 return -EINVAL;
2263 csr &= ~PCI_PM_CTRL_STATE_MASK;
2264 csr |= PCI_D3hot;
2265 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
2266 pci_dev_d3_sleep(dev);
2268 csr &= ~PCI_PM_CTRL_STATE_MASK;
2269 csr |= PCI_D0;
2270 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
2271 pci_dev_d3_sleep(dev);
2273 return 0;
2276 static int pci_parent_bus_reset(struct pci_dev *dev, int probe)
2278 u16 ctrl;
2279 struct pci_dev *pdev;
2281 if (pci_is_root_bus(dev->bus) || dev->subordinate || !dev->bus->self)
2282 return -ENOTTY;
2284 list_for_each_entry(pdev, &dev->bus->devices, bus_list)
2285 if (pdev != dev)
2286 return -ENOTTY;
2288 if (probe)
2289 return 0;
2291 pci_read_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, &ctrl);
2292 ctrl |= PCI_BRIDGE_CTL_BUS_RESET;
2293 pci_write_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, ctrl);
2294 msleep(100);
2296 ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
2297 pci_write_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, ctrl);
2298 msleep(100);
2300 return 0;
2303 static int pci_dev_reset(struct pci_dev *dev, int probe)
2305 int rc;
2307 might_sleep();
2309 if (!probe) {
2310 pci_block_user_cfg_access(dev);
2311 /* block PM suspend, driver probe, etc. */
2312 down(&dev->dev.sem);
2315 rc = pci_dev_specific_reset(dev, probe);
2316 if (rc != -ENOTTY)
2317 goto done;
2319 rc = pcie_flr(dev, probe);
2320 if (rc != -ENOTTY)
2321 goto done;
2323 rc = pci_af_flr(dev, probe);
2324 if (rc != -ENOTTY)
2325 goto done;
2327 rc = pci_pm_reset(dev, probe);
2328 if (rc != -ENOTTY)
2329 goto done;
2331 rc = pci_parent_bus_reset(dev, probe);
2332 done:
2333 if (!probe) {
2334 up(&dev->dev.sem);
2335 pci_unblock_user_cfg_access(dev);
2338 return rc;
2342 * __pci_reset_function - reset a PCI device function
2343 * @dev: PCI device to reset
2345 * Some devices allow an individual function to be reset without affecting
2346 * other functions in the same device. The PCI device must be responsive
2347 * to PCI config space in order to use this function.
2349 * The device function is presumed to be unused when this function is called.
2350 * Resetting the device will make the contents of PCI configuration space
2351 * random, so any caller of this must be prepared to reinitialise the
2352 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
2353 * etc.
2355 * Returns 0 if the device function was successfully reset or negative if the
2356 * device doesn't support resetting a single function.
2358 int __pci_reset_function(struct pci_dev *dev)
2360 return pci_dev_reset(dev, 0);
2362 EXPORT_SYMBOL_GPL(__pci_reset_function);
2365 * pci_probe_reset_function - check whether the device can be safely reset
2366 * @dev: PCI device to reset
2368 * Some devices allow an individual function to be reset without affecting
2369 * other functions in the same device. The PCI device must be responsive
2370 * to PCI config space in order to use this function.
2372 * Returns 0 if the device function can be reset or negative if the
2373 * device doesn't support resetting a single function.
2375 int pci_probe_reset_function(struct pci_dev *dev)
2377 return pci_dev_reset(dev, 1);
2381 * pci_reset_function - quiesce and reset a PCI device function
2382 * @dev: PCI device to reset
2384 * Some devices allow an individual function to be reset without affecting
2385 * other functions in the same device. The PCI device must be responsive
2386 * to PCI config space in order to use this function.
2388 * This function does not just reset the PCI portion of a device, but
2389 * clears all the state associated with the device. This function differs
2390 * from __pci_reset_function in that it saves and restores device state
2391 * over the reset.
2393 * Returns 0 if the device function was successfully reset or negative if the
2394 * device doesn't support resetting a single function.
2396 int pci_reset_function(struct pci_dev *dev)
2398 int rc;
2400 rc = pci_dev_reset(dev, 1);
2401 if (rc)
2402 return rc;
2404 pci_save_state(dev);
2407 * both INTx and MSI are disabled after the Interrupt Disable bit
2408 * is set and the Bus Master bit is cleared.
2410 pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE);
2412 rc = pci_dev_reset(dev, 0);
2414 pci_restore_state(dev);
2416 return rc;
2418 EXPORT_SYMBOL_GPL(pci_reset_function);
2421 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
2422 * @dev: PCI device to query
2424 * Returns mmrbc: maximum designed memory read count in bytes
2425 * or appropriate error value.
2427 int pcix_get_max_mmrbc(struct pci_dev *dev)
2429 int err, cap;
2430 u32 stat;
2432 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
2433 if (!cap)
2434 return -EINVAL;
2436 err = pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat);
2437 if (err)
2438 return -EINVAL;
2440 return (stat & PCI_X_STATUS_MAX_READ) >> 12;
2442 EXPORT_SYMBOL(pcix_get_max_mmrbc);
2445 * pcix_get_mmrbc - get PCI-X maximum memory read byte count
2446 * @dev: PCI device to query
2448 * Returns mmrbc: maximum memory read count in bytes
2449 * or appropriate error value.
2451 int pcix_get_mmrbc(struct pci_dev *dev)
2453 int ret, cap;
2454 u32 cmd;
2456 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
2457 if (!cap)
2458 return -EINVAL;
2460 ret = pci_read_config_dword(dev, cap + PCI_X_CMD, &cmd);
2461 if (!ret)
2462 ret = 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2);
2464 return ret;
2466 EXPORT_SYMBOL(pcix_get_mmrbc);
2469 * pcix_set_mmrbc - set PCI-X maximum memory read byte count
2470 * @dev: PCI device to query
2471 * @mmrbc: maximum memory read count in bytes
2472 * valid values are 512, 1024, 2048, 4096
2474 * If possible sets maximum memory read byte count, some bridges have erratas
2475 * that prevent this.
2477 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc)
2479 int cap, err = -EINVAL;
2480 u32 stat, cmd, v, o;
2482 if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc))
2483 goto out;
2485 v = ffs(mmrbc) - 10;
2487 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
2488 if (!cap)
2489 goto out;
2491 err = pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat);
2492 if (err)
2493 goto out;
2495 if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21)
2496 return -E2BIG;
2498 err = pci_read_config_dword(dev, cap + PCI_X_CMD, &cmd);
2499 if (err)
2500 goto out;
2502 o = (cmd & PCI_X_CMD_MAX_READ) >> 2;
2503 if (o != v) {
2504 if (v > o && dev->bus &&
2505 (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC))
2506 return -EIO;
2508 cmd &= ~PCI_X_CMD_MAX_READ;
2509 cmd |= v << 2;
2510 err = pci_write_config_dword(dev, cap + PCI_X_CMD, cmd);
2512 out:
2513 return err;
2515 EXPORT_SYMBOL(pcix_set_mmrbc);
2518 * pcie_get_readrq - get PCI Express read request size
2519 * @dev: PCI device to query
2521 * Returns maximum memory read request in bytes
2522 * or appropriate error value.
2524 int pcie_get_readrq(struct pci_dev *dev)
2526 int ret, cap;
2527 u16 ctl;
2529 cap = pci_pcie_cap(dev);
2530 if (!cap)
2531 return -EINVAL;
2533 ret = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
2534 if (!ret)
2535 ret = 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12);
2537 return ret;
2539 EXPORT_SYMBOL(pcie_get_readrq);
2542 * pcie_set_readrq - set PCI Express maximum memory read request
2543 * @dev: PCI device to query
2544 * @rq: maximum memory read count in bytes
2545 * valid values are 128, 256, 512, 1024, 2048, 4096
2547 * If possible sets maximum read byte count
2549 int pcie_set_readrq(struct pci_dev *dev, int rq)
2551 int cap, err = -EINVAL;
2552 u16 ctl, v;
2554 if (rq < 128 || rq > 4096 || !is_power_of_2(rq))
2555 goto out;
2557 v = (ffs(rq) - 8) << 12;
2559 cap = pci_pcie_cap(dev);
2560 if (!cap)
2561 goto out;
2563 err = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
2564 if (err)
2565 goto out;
2567 if ((ctl & PCI_EXP_DEVCTL_READRQ) != v) {
2568 ctl &= ~PCI_EXP_DEVCTL_READRQ;
2569 ctl |= v;
2570 err = pci_write_config_dword(dev, cap + PCI_EXP_DEVCTL, ctl);
2573 out:
2574 return err;
2576 EXPORT_SYMBOL(pcie_set_readrq);
2579 * pci_select_bars - Make BAR mask from the type of resource
2580 * @dev: the PCI device for which BAR mask is made
2581 * @flags: resource type mask to be selected
2583 * This helper routine makes bar mask from the type of resource.
2585 int pci_select_bars(struct pci_dev *dev, unsigned long flags)
2587 int i, bars = 0;
2588 for (i = 0; i < PCI_NUM_RESOURCES; i++)
2589 if (pci_resource_flags(dev, i) & flags)
2590 bars |= (1 << i);
2591 return bars;
2595 * pci_resource_bar - get position of the BAR associated with a resource
2596 * @dev: the PCI device
2597 * @resno: the resource number
2598 * @type: the BAR type to be filled in
2600 * Returns BAR position in config space, or 0 if the BAR is invalid.
2602 int pci_resource_bar(struct pci_dev *dev, int resno, enum pci_bar_type *type)
2604 int reg;
2606 if (resno < PCI_ROM_RESOURCE) {
2607 *type = pci_bar_unknown;
2608 return PCI_BASE_ADDRESS_0 + 4 * resno;
2609 } else if (resno == PCI_ROM_RESOURCE) {
2610 *type = pci_bar_mem32;
2611 return dev->rom_base_reg;
2612 } else if (resno < PCI_BRIDGE_RESOURCES) {
2613 /* device specific resource */
2614 reg = pci_iov_resource_bar(dev, resno, type);
2615 if (reg)
2616 return reg;
2619 dev_err(&dev->dev, "BAR %d: invalid resource\n", resno);
2620 return 0;
2624 * pci_set_vga_state - set VGA decode state on device and parents if requested
2625 * @dev: the PCI device
2626 * @decode: true = enable decoding, false = disable decoding
2627 * @command_bits: PCI_COMMAND_IO and/or PCI_COMMAND_MEMORY
2628 * @change_bridge: traverse ancestors and change bridges
2630 int pci_set_vga_state(struct pci_dev *dev, bool decode,
2631 unsigned int command_bits, bool change_bridge)
2633 struct pci_bus *bus;
2634 struct pci_dev *bridge;
2635 u16 cmd;
2637 WARN_ON(command_bits & ~(PCI_COMMAND_IO|PCI_COMMAND_MEMORY));
2639 pci_read_config_word(dev, PCI_COMMAND, &cmd);
2640 if (decode == true)
2641 cmd |= command_bits;
2642 else
2643 cmd &= ~command_bits;
2644 pci_write_config_word(dev, PCI_COMMAND, cmd);
2646 if (change_bridge == false)
2647 return 0;
2649 bus = dev->bus;
2650 while (bus) {
2651 bridge = bus->self;
2652 if (bridge) {
2653 pci_read_config_word(bridge, PCI_BRIDGE_CONTROL,
2654 &cmd);
2655 if (decode == true)
2656 cmd |= PCI_BRIDGE_CTL_VGA;
2657 else
2658 cmd &= ~PCI_BRIDGE_CTL_VGA;
2659 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL,
2660 cmd);
2662 bus = bus->parent;
2664 return 0;
2667 #define RESOURCE_ALIGNMENT_PARAM_SIZE COMMAND_LINE_SIZE
2668 static char resource_alignment_param[RESOURCE_ALIGNMENT_PARAM_SIZE] = {0};
2669 static DEFINE_SPINLOCK(resource_alignment_lock);
2672 * pci_specified_resource_alignment - get resource alignment specified by user.
2673 * @dev: the PCI device to get
2675 * RETURNS: Resource alignment if it is specified.
2676 * Zero if it is not specified.
2678 resource_size_t pci_specified_resource_alignment(struct pci_dev *dev)
2680 int seg, bus, slot, func, align_order, count;
2681 resource_size_t align = 0;
2682 char *p;
2684 spin_lock(&resource_alignment_lock);
2685 p = resource_alignment_param;
2686 while (*p) {
2687 count = 0;
2688 if (sscanf(p, "%d%n", &align_order, &count) == 1 &&
2689 p[count] == '@') {
2690 p += count + 1;
2691 } else {
2692 align_order = -1;
2694 if (sscanf(p, "%x:%x:%x.%x%n",
2695 &seg, &bus, &slot, &func, &count) != 4) {
2696 seg = 0;
2697 if (sscanf(p, "%x:%x.%x%n",
2698 &bus, &slot, &func, &count) != 3) {
2699 /* Invalid format */
2700 printk(KERN_ERR "PCI: Can't parse resource_alignment parameter: %s\n",
2702 break;
2705 p += count;
2706 if (seg == pci_domain_nr(dev->bus) &&
2707 bus == dev->bus->number &&
2708 slot == PCI_SLOT(dev->devfn) &&
2709 func == PCI_FUNC(dev->devfn)) {
2710 if (align_order == -1) {
2711 align = PAGE_SIZE;
2712 } else {
2713 align = 1 << align_order;
2715 /* Found */
2716 break;
2718 if (*p != ';' && *p != ',') {
2719 /* End of param or invalid format */
2720 break;
2722 p++;
2724 spin_unlock(&resource_alignment_lock);
2725 return align;
2729 * pci_is_reassigndev - check if specified PCI is target device to reassign
2730 * @dev: the PCI device to check
2732 * RETURNS: non-zero for PCI device is a target device to reassign,
2733 * or zero is not.
2735 int pci_is_reassigndev(struct pci_dev *dev)
2737 return (pci_specified_resource_alignment(dev) != 0);
2740 ssize_t pci_set_resource_alignment_param(const char *buf, size_t count)
2742 if (count > RESOURCE_ALIGNMENT_PARAM_SIZE - 1)
2743 count = RESOURCE_ALIGNMENT_PARAM_SIZE - 1;
2744 spin_lock(&resource_alignment_lock);
2745 strncpy(resource_alignment_param, buf, count);
2746 resource_alignment_param[count] = '\0';
2747 spin_unlock(&resource_alignment_lock);
2748 return count;
2751 ssize_t pci_get_resource_alignment_param(char *buf, size_t size)
2753 size_t count;
2754 spin_lock(&resource_alignment_lock);
2755 count = snprintf(buf, size, "%s", resource_alignment_param);
2756 spin_unlock(&resource_alignment_lock);
2757 return count;
2760 static ssize_t pci_resource_alignment_show(struct bus_type *bus, char *buf)
2762 return pci_get_resource_alignment_param(buf, PAGE_SIZE);
2765 static ssize_t pci_resource_alignment_store(struct bus_type *bus,
2766 const char *buf, size_t count)
2768 return pci_set_resource_alignment_param(buf, count);
2771 BUS_ATTR(resource_alignment, 0644, pci_resource_alignment_show,
2772 pci_resource_alignment_store);
2774 static int __init pci_resource_alignment_sysfs_init(void)
2776 return bus_create_file(&pci_bus_type,
2777 &bus_attr_resource_alignment);
2780 late_initcall(pci_resource_alignment_sysfs_init);
2782 static void __devinit pci_no_domains(void)
2784 #ifdef CONFIG_PCI_DOMAINS
2785 pci_domains_supported = 0;
2786 #endif
2790 * pci_ext_cfg_enabled - can we access extended PCI config space?
2791 * @dev: The PCI device of the root bridge.
2793 * Returns 1 if we can access PCI extended config space (offsets
2794 * greater than 0xff). This is the default implementation. Architecture
2795 * implementations can override this.
2797 int __attribute__ ((weak)) pci_ext_cfg_avail(struct pci_dev *dev)
2799 return 1;
2802 void __weak pci_fixup_cardbus(struct pci_bus *bus)
2805 EXPORT_SYMBOL(pci_fixup_cardbus);
2807 static int __init pci_setup(char *str)
2809 while (str) {
2810 char *k = strchr(str, ',');
2811 if (k)
2812 *k++ = 0;
2813 if (*str && (str = pcibios_setup(str)) && *str) {
2814 if (!strcmp(str, "nomsi")) {
2815 pci_no_msi();
2816 } else if (!strcmp(str, "noaer")) {
2817 pci_no_aer();
2818 } else if (!strcmp(str, "nodomains")) {
2819 pci_no_domains();
2820 } else if (!strncmp(str, "cbiosize=", 9)) {
2821 pci_cardbus_io_size = memparse(str + 9, &str);
2822 } else if (!strncmp(str, "cbmemsize=", 10)) {
2823 pci_cardbus_mem_size = memparse(str + 10, &str);
2824 } else if (!strncmp(str, "resource_alignment=", 19)) {
2825 pci_set_resource_alignment_param(str + 19,
2826 strlen(str + 19));
2827 } else if (!strncmp(str, "ecrc=", 5)) {
2828 pcie_ecrc_get_policy(str + 5);
2829 } else if (!strncmp(str, "hpiosize=", 9)) {
2830 pci_hotplug_io_size = memparse(str + 9, &str);
2831 } else if (!strncmp(str, "hpmemsize=", 10)) {
2832 pci_hotplug_mem_size = memparse(str + 10, &str);
2833 } else {
2834 printk(KERN_ERR "PCI: Unknown option `%s'\n",
2835 str);
2838 str = k;
2840 return 0;
2842 early_param("pci", pci_setup);
2844 EXPORT_SYMBOL(pci_reenable_device);
2845 EXPORT_SYMBOL(pci_enable_device_io);
2846 EXPORT_SYMBOL(pci_enable_device_mem);
2847 EXPORT_SYMBOL(pci_enable_device);
2848 EXPORT_SYMBOL(pcim_enable_device);
2849 EXPORT_SYMBOL(pcim_pin_device);
2850 EXPORT_SYMBOL(pci_disable_device);
2851 EXPORT_SYMBOL(pci_find_capability);
2852 EXPORT_SYMBOL(pci_bus_find_capability);
2853 EXPORT_SYMBOL(pci_release_regions);
2854 EXPORT_SYMBOL(pci_request_regions);
2855 EXPORT_SYMBOL(pci_request_regions_exclusive);
2856 EXPORT_SYMBOL(pci_release_region);
2857 EXPORT_SYMBOL(pci_request_region);
2858 EXPORT_SYMBOL(pci_request_region_exclusive);
2859 EXPORT_SYMBOL(pci_release_selected_regions);
2860 EXPORT_SYMBOL(pci_request_selected_regions);
2861 EXPORT_SYMBOL(pci_request_selected_regions_exclusive);
2862 EXPORT_SYMBOL(pci_set_master);
2863 EXPORT_SYMBOL(pci_clear_master);
2864 EXPORT_SYMBOL(pci_set_mwi);
2865 EXPORT_SYMBOL(pci_try_set_mwi);
2866 EXPORT_SYMBOL(pci_clear_mwi);
2867 EXPORT_SYMBOL_GPL(pci_intx);
2868 EXPORT_SYMBOL(pci_set_dma_mask);
2869 EXPORT_SYMBOL(pci_set_consistent_dma_mask);
2870 EXPORT_SYMBOL(pci_assign_resource);
2871 EXPORT_SYMBOL(pci_find_parent_resource);
2872 EXPORT_SYMBOL(pci_select_bars);
2874 EXPORT_SYMBOL(pci_set_power_state);
2875 EXPORT_SYMBOL(pci_save_state);
2876 EXPORT_SYMBOL(pci_restore_state);
2877 EXPORT_SYMBOL(pci_pme_capable);
2878 EXPORT_SYMBOL(pci_pme_active);
2879 EXPORT_SYMBOL(pci_enable_wake);
2880 EXPORT_SYMBOL(pci_wake_from_d3);
2881 EXPORT_SYMBOL(pci_target_state);
2882 EXPORT_SYMBOL(pci_prepare_to_sleep);
2883 EXPORT_SYMBOL(pci_back_from_sleep);
2884 EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state);