drivers/ide/pci/ns87415.c

   1 /*
   2  * Copyright (C) 1997-1998      Mark Lord <mlord@pobox.com>
   3  * Copyright (C) 1998           Eddie C. Dost <ecd@skynet.be>
   4  * Copyright (C) 1999-2000      Andre Hedrick <andre@linux-ide.org>
   5  * Copyright (C) 2004           Grant Grundler <grundler at parisc-linux.org>
   6  *
   7  * Inspired by an earlier effort from David S. Miller <davem@redhat.com>
   8  */
   9
  10 #include <linux/module.h>
  11 #include <linux/types.h>
  12 #include <linux/kernel.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/hdreg.h>
  15 #include <linux/pci.h>
  16 #include <linux/delay.h>
  17 #include <linux/ide.h>
  18 #include <linux/init.h>
  19
  20 #include <asm/io.h>
  21
  22 #ifdef CONFIG_SUPERIO
  23 /* SUPERIO 87560 is a PoS chip that NatSem denies exists.
  24  * Unfortunately, it's built-in on all Astro-based PA-RISC workstations
  25  * which use the integrated NS87514 cell for CD-ROM support.
  26  * i.e we have to support for CD-ROM installs.
  27  * See drivers/parisc/superio.c for more gory details.
  28  */
  29 #include <asm/superio.h>
  30
  31 static unsigned long superio_ide_status[2];
  32 static unsigned long superio_ide_select[2];
  33 static unsigned long superio_ide_dma_status[2];
  34
  35 #define SUPERIO_IDE_MAX_RETRIES 25
  36
  37 /* Because of a defect in Super I/O, all reads of the PCI DMA status
  38  * registers, IDE status register and the IDE select register need to be
  39  * retried
  40  */
  41 static u8 superio_ide_inb (unsigned long port)
  42 {
  43         if (port == superio_ide_status[0] ||
  44             port == superio_ide_status[1] ||
  45             port == superio_ide_select[0] ||
  46             port == superio_ide_select[1] ||
  47             port == superio_ide_dma_status[0] ||
  48             port == superio_ide_dma_status[1]) {
  49                 u8 tmp;
  50                 int retries = SUPERIO_IDE_MAX_RETRIES;
  51
  52                 /* printk(" [ reading port 0x%x with retry ] ", port); */
  53
  54                 do {
  55                         tmp = inb(port);
  56                         if (tmp == 0)
  57                                 udelay(50);
  58                 } while (tmp == 0 && retries-- > 0);
  59
  60                 return tmp;
  61         }
  62
  63         return inb(port);
  64 }
  65
  66 static u8 superio_read_status(ide_hwif_t *hwif)
  67 {
  68         return superio_ide_inb(hwif->io_ports.status_addr);
  69 }
  70
  71 static u8 superio_read_sff_dma_status(ide_hwif_t *hwif)
  72 {
  73         return superio_ide_inb(hwif->dma_base + ATA_DMA_STATUS);
  74 }
  75
  76 static void superio_tf_read(ide_drive_t *drive, ide_task_t *task)
  77 {
  78         struct ide_io_ports *io_ports = &drive->hwif->io_ports;
  79         struct ide_taskfile *tf = &task->tf;
  80
  81         if (task->tf_flags & IDE_TFLAG_IN_DATA) {
  82                 u16 data = inw(io_ports->data_addr);
  83
  84                 tf->data = data & 0xff;
  85                 tf->hob_data = (data >> 8) & 0xff;
  86         }
  87
  88         /* be sure we're looking at the low order bits */
  89         outb(ATA_DEVCTL_OBS & ~0x80, io_ports->ctl_addr);
  90
  91         if (task->tf_flags & IDE_TFLAG_IN_FEATURE)
  92                 tf->feature = inb(io_ports->feature_addr);
  93         if (task->tf_flags & IDE_TFLAG_IN_NSECT)
  94                 tf->nsect  = inb(io_ports->nsect_addr);
  95         if (task->tf_flags & IDE_TFLAG_IN_LBAL)
  96                 tf->lbal   = inb(io_ports->lbal_addr);
  97         if (task->tf_flags & IDE_TFLAG_IN_LBAM)
  98                 tf->lbam   = inb(io_ports->lbam_addr);
  99         if (task->tf_flags & IDE_TFLAG_IN_LBAH)
 100                 tf->lbah   = inb(io_ports->lbah_addr);
 101         if (task->tf_flags & IDE_TFLAG_IN_DEVICE)
 102                 tf->device = superio_ide_inb(io_ports->device_addr);
 103
 104         if (task->tf_flags & IDE_TFLAG_LBA48) {
 105                 outb(ATA_DEVCTL_OBS | 0x80, io_ports->ctl_addr);
 106
 107                 if (task->tf_flags & IDE_TFLAG_IN_HOB_FEATURE)
 108                         tf->hob_feature = inb(io_ports->feature_addr);
 109                 if (task->tf_flags & IDE_TFLAG_IN_HOB_NSECT)
 110                         tf->hob_nsect   = inb(io_ports->nsect_addr);
 111                 if (task->tf_flags & IDE_TFLAG_IN_HOB_LBAL)
 112                         tf->hob_lbal    = inb(io_ports->lbal_addr);
 113                 if (task->tf_flags & IDE_TFLAG_IN_HOB_LBAM)
 114                         tf->hob_lbam    = inb(io_ports->lbam_addr);
 115                 if (task->tf_flags & IDE_TFLAG_IN_HOB_LBAH)
 116                         tf->hob_lbah    = inb(io_ports->lbah_addr);
 117         }
 118 }
 119
 120 static void __devinit superio_ide_init_iops (struct hwif_s *hwif)
 121 {
 122         struct pci_dev *pdev = to_pci_dev(hwif->dev);
 123         u32 base, dmabase;
 124         u8 port = hwif->channel, tmp;
 125
 126         base = pci_resource_start(pdev, port * 2) & ~3;
 127         dmabase = pci_resource_start(pdev, 4) & ~3;
 128
 129         superio_ide_status[port] = base + 7;
 130         superio_ide_select[port] = base + 6;
 131         superio_ide_dma_status[port] = dmabase + (!port ? 2 : 0xa);
 132
 133         /* Clear error/interrupt, enable dma */
 134         tmp = superio_ide_inb(superio_ide_dma_status[port]);
 135         outb(tmp | 0x66, superio_ide_dma_status[port]);
 136
 137         hwif->read_status         = superio_read_status;
 138         hwif->read_sff_dma_status = superio_read_sff_dma_status;
 139
 140         hwif->tf_read = superio_tf_read;
 141
 142         /* We need to override inb to workaround a SuperIO errata */
 143         hwif->INB = superio_ide_inb;
 144 }
 145
 146 static void __devinit init_iops_ns87415(ide_hwif_t *hwif)
 147 {
 148         struct pci_dev *dev = to_pci_dev(hwif->dev);
 149
 150         if (PCI_SLOT(dev->devfn) == 0xE)
 151                 /* Built-in - assume it's under superio. */
 152                 superio_ide_init_iops(hwif);
 153 }
 154 #endif
 155
 156 static unsigned int ns87415_count = 0, ns87415_control[MAX_HWIFS] = { 0 };
 157
 158 /*
 159  * This routine either enables/disables (according to drive->present)
 160  * the IRQ associated with the port (HWIF(drive)),
 161  * and selects either PIO or DMA handshaking for the next I/O operation.
 162  */
 163 static void ns87415_prepare_drive (ide_drive_t *drive, unsigned int use_dma)
 164 {
 165         ide_hwif_t *hwif = HWIF(drive);
 166         struct pci_dev *dev = to_pci_dev(hwif->dev);
 167         unsigned int bit, other, new, *old = (unsigned int *) hwif->select_data;
 168         unsigned long flags;
 169
 170         local_irq_save(flags);
 171         new = *old;
 172
 173         /* Adjust IRQ enable bit */
 174         bit = 1 << (8 + hwif->channel);
 175         new = drive->present ? (new & ~bit) : (new | bit);
 176
 177         /* Select PIO or DMA, DMA may only be selected for one drive/channel. */
 178         bit   = 1 << (20 + drive->select.b.unit       + (hwif->channel << 1));
 179         other = 1 << (20 + (1 - drive->select.b.unit) + (hwif->channel << 1));
 180         new = use_dma ? ((new & ~other) | bit) : (new & ~bit);
 181
 182         if (new != *old) {
 183                 unsigned char stat;
 184
 185                 /*
 186                  * Don't change DMA engine settings while Write Buffers
 187                  * are busy.
 188                  */
 189                 (void) pci_read_config_byte(dev, 0x43, &stat);
 190                 while (stat & 0x03) {
 191                         udelay(1);
 192                         (void) pci_read_config_byte(dev, 0x43, &stat);
 193                 }
 194
 195                 *old = new;
 196                 (void) pci_write_config_dword(dev, 0x40, new);
 197
 198                 /*
 199                  * And let things settle...
 200                  */
 201                 udelay(10);
 202         }
 203
 204         local_irq_restore(flags);
 205 }
 206
 207 static void ns87415_selectproc (ide_drive_t *drive)
 208 {
 209         ns87415_prepare_drive (drive, drive->using_dma);
 210 }
 211
 212 static int ns87415_dma_end(ide_drive_t *drive)
 213 {
 214         ide_hwif_t      *hwif = HWIF(drive);
 215         u8 dma_stat = 0, dma_cmd = 0;
 216
 217         drive->waiting_for_dma = 0;
 218         dma_stat = hwif->read_sff_dma_status(hwif);
 219         /* get DMA command mode */
 220         dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD);
 221         /* stop DMA */
 222         outb(dma_cmd & ~1, hwif->dma_base + ATA_DMA_CMD);
 223         /* from ERRATA: clear the INTR & ERROR bits */
 224         dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD);
 225         outb(dma_cmd | 6, hwif->dma_base + ATA_DMA_CMD);
 226         /* and free any DMA resources */
 227         ide_destroy_dmatable(drive);
 228         /* verify good DMA status */
 229         return (dma_stat & 7) != 4;
 230 }
 231
 232 static int ns87415_dma_setup(ide_drive_t *drive)
 233 {
 234         /* select DMA xfer */
 235         ns87415_prepare_drive(drive, 1);
 236         if (!ide_dma_setup(drive))
 237                 return 0;
 238         /* DMA failed: select PIO xfer */
 239         ns87415_prepare_drive(drive, 0);
 240         return 1;
 241 }
 242
 243 static void __devinit init_hwif_ns87415 (ide_hwif_t *hwif)
 244 {
 245         struct pci_dev *dev = to_pci_dev(hwif->dev);
 246         unsigned int ctrl, using_inta;
 247         u8 progif;
 248 #ifdef __sparc_v9__
 249         int timeout;
 250         u8 stat;
 251 #endif
 252
 253         /*
 254          * We cannot probe for IRQ: both ports share common IRQ on INTA.
 255          * Also, leave IRQ masked during drive probing, to prevent infinite
 256          * interrupts from a potentially floating INTA..
 257          *
 258          * IRQs get unmasked in selectproc when drive is first used.
 259          */
 260         (void) pci_read_config_dword(dev, 0x40, &ctrl);
 261         (void) pci_read_config_byte(dev, 0x09, &progif);
 262         /* is irq in "native" mode? */
 263         using_inta = progif & (1 << (hwif->channel << 1));
 264         if (!using_inta)
 265                 using_inta = ctrl & (1 << (4 + hwif->channel));
 266         if (hwif->mate) {
 267                 hwif->select_data = hwif->mate->select_data;
 268         } else {
 269                 hwif->select_data = (unsigned long)
 270                                         &ns87415_control[ns87415_count++];
 271                 ctrl |= (1 << 8) | (1 << 9);    /* mask both IRQs */
 272                 if (using_inta)
 273                         ctrl &= ~(1 << 6);      /* unmask INTA */
 274                 *((unsigned int *)hwif->select_data) = ctrl;
 275                 (void) pci_write_config_dword(dev, 0x40, ctrl);
 276
 277                 /*
 278                  * Set prefetch size to 512 bytes for both ports,
 279                  * but don't turn on/off prefetching here.
 280                  */
 281                 pci_write_config_byte(dev, 0x55, 0xee);
 282
 283 #ifdef __sparc_v9__
 284                 /*
 285                  * XXX: Reset the device, if we don't it will not respond to
 286                  *      SELECT_DRIVE() properly during first ide_probe_port().
 287                  */
 288                 timeout = 10000;
 289                 outb(12, hwif->io_ports.ctl_addr);
 290                 udelay(10);
 291                 outb(8, hwif->io_ports.ctl_addr);
 292                 do {
 293                         udelay(50);
 294                         stat = hwif->read_status(hwif);
 295                         if (stat == 0xff)
 296                                 break;
 297                 } while ((stat & BUSY_STAT) && --timeout);
 298 #endif
 299         }
 300
 301         if (!using_inta)
 302                 hwif->irq = __ide_default_irq(hwif->io_ports.data_addr);
 303         else if (!hwif->irq && hwif->mate && hwif->mate->irq)
 304                 hwif->irq = hwif->mate->irq;    /* share IRQ with mate */
 305
 306         if (!hwif->dma_base)
 307                 return;
 308
 309         outb(0x60, hwif->dma_base + ATA_DMA_STATUS);
 310 }
 311
 312 static const struct ide_port_ops ns87415_port_ops = {
 313         .selectproc             = ns87415_selectproc,
 314 };
 315
 316 static const struct ide_dma_ops ns87415_dma_ops = {
 317         .dma_host_set           = ide_dma_host_set,
 318         .dma_setup              = ns87415_dma_setup,
 319         .dma_exec_cmd           = ide_dma_exec_cmd,
 320         .dma_start              = ide_dma_start,
 321         .dma_end                = ns87415_dma_end,
 322         .dma_test_irq           = ide_dma_test_irq,
 323         .dma_lost_irq           = ide_dma_lost_irq,
 324         .dma_timeout            = ide_dma_timeout,
 325 };
 326
 327 static const struct ide_port_info ns87415_chipset __devinitdata = {
 328         .name           = "NS87415",
 329 #ifdef CONFIG_SUPERIO
 330         .init_iops      = init_iops_ns87415,
 331 #endif
 332         .init_hwif      = init_hwif_ns87415,
 333         .port_ops       = &ns87415_port_ops,
 334         .dma_ops        = &ns87415_dma_ops,
 335         .host_flags     = IDE_HFLAG_TRUST_BIOS_FOR_DMA |
 336                           IDE_HFLAG_NO_ATAPI_DMA,
 337 };
 338
 339 static int __devinit ns87415_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 340 {
 341         return ide_setup_pci_device(dev, &ns87415_chipset);
 342 }
 343
 344 static const struct pci_device_id ns87415_pci_tbl[] = {
 345         { PCI_VDEVICE(NS, PCI_DEVICE_ID_NS_87415), 0 },
 346         { 0, },
 347 };
 348 MODULE_DEVICE_TABLE(pci, ns87415_pci_tbl);
 349
 350 static struct pci_driver driver = {
 351         .name           = "NS87415_IDE",
 352         .id_table       = ns87415_pci_tbl,
 353         .probe          = ns87415_init_one,
 354 };
 355
 356 static int __init ns87415_ide_init(void)
 357 {
 358         return ide_pci_register_driver(&driver);
 359 }
 360
 361 module_init(ns87415_ide_init);
 362
 363 MODULE_AUTHOR("Mark Lord, Eddie Dost, Andre Hedrick");
 364 MODULE_DESCRIPTION("PCI driver module for NS87415 IDE");
 365 MODULE_LICENSE("GPL");