arch/arm/mach-s5p64x0/irq-eint.c

   1 /* arch/arm/mach-s5p64x0/irq-eint.c
   2  *
   3  * Copyright (c) 2011 Samsung Electronics Co., Ltd
   4  *              http://www.samsung.com/
   5  *
   6  * Based on linux/arch/arm/mach-s3c64xx/irq-eint.c
   7  *
   8  * S5P64X0 - Interrupt handling for External Interrupts.
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13  */
  14
  15 #include <linux/kernel.h>
  16 #include <linux/gpio.h>
  17 #include <linux/irq.h>
  18 #include <linux/io.h>
  19
  20 #include <plat/cpu.h>
  21 #include <plat/regs-irqtype.h>
  22 #include <plat/gpio-cfg.h>
  23 #include <plat/pm.h>
  24
  25 #include <mach/regs-gpio.h>
  26 #include <mach/regs-clock.h>
  27
  28 #define eint_offset(irq)        ((irq) - IRQ_EINT(0))
  29
  30 static int s5p64x0_irq_eint_set_type(struct irq_data *data, unsigned int type)
  31 {
  32         int offs = eint_offset(data->irq);
  33         int shift;
  34         u32 ctrl, mask;
  35         u32 newvalue = 0;
  36
  37         if (offs > 15)
  38                 return -EINVAL;
  39
  40         switch (type) {
  41         case IRQ_TYPE_NONE:
  42                 printk(KERN_WARNING "No edge setting!\n");
  43                 break;
  44         case IRQ_TYPE_EDGE_RISING:
  45                 newvalue = S3C2410_EXTINT_RISEEDGE;
  46                 break;
  47         case IRQ_TYPE_EDGE_FALLING:
  48                 newvalue = S3C2410_EXTINT_FALLEDGE;
  49                 break;
  50         case IRQ_TYPE_EDGE_BOTH:
  51                 newvalue = S3C2410_EXTINT_BOTHEDGE;
  52                 break;
  53         case IRQ_TYPE_LEVEL_LOW:
  54                 newvalue = S3C2410_EXTINT_LOWLEV;
  55                 break;
  56         case IRQ_TYPE_LEVEL_HIGH:
  57                 newvalue = S3C2410_EXTINT_HILEV;
  58                 break;
  59         default:
  60                 printk(KERN_ERR "No such irq type %d", type);
  61                 return -EINVAL;
  62         }
  63
  64         shift = (offs / 2) * 4;
  65         mask = 0x7 << shift;
  66
  67         ctrl = __raw_readl(S5P64X0_EINT0CON0) & ~mask;
  68         ctrl |= newvalue << shift;
  69         __raw_writel(ctrl, S5P64X0_EINT0CON0);
  70
  71         /* Configure the GPIO pin for 6450 or 6440 based on CPU ID */
  72         if (soc_is_s5p6450())
  73                 s3c_gpio_cfgpin(S5P6450_GPN(offs), S3C_GPIO_SFN(2));
  74         else
  75                 s3c_gpio_cfgpin(S5P6440_GPN(offs), S3C_GPIO_SFN(2));
  76
  77         return 0;
  78 }
  79
  80 /*
  81  * s5p64x0_irq_demux_eint
  82  *
  83  * This function demuxes the IRQ from the group0 external interrupts,
  84  * from IRQ_EINT(0) to IRQ_EINT(15). It is designed to be inlined into
  85  * the specific handlers s5p64x0_irq_demux_eintX_Y.
  86  */
  87 static inline void s5p64x0_irq_demux_eint(unsigned int start, unsigned int end)
  88 {
  89         u32 status = __raw_readl(S5P64X0_EINT0PEND);
  90         u32 mask = __raw_readl(S5P64X0_EINT0MASK);
  91         unsigned int irq;
  92
  93         status &= ~mask;
  94         status >>= start;
  95         status &= (1 << (end - start + 1)) - 1;
  96
  97         for (irq = IRQ_EINT(start); irq <= IRQ_EINT(end); irq++) {
  98                 if (status & 1)
  99                         generic_handle_irq(irq);
 100                 status >>= 1;
 101         }
 102 }
 103
 104 static void s5p64x0_irq_demux_eint0_3(unsigned int irq, struct irq_desc *desc)
 105 {
 106         s5p64x0_irq_demux_eint(0, 3);
 107 }
 108
 109 static void s5p64x0_irq_demux_eint4_11(unsigned int irq, struct irq_desc *desc)
 110 {
 111         s5p64x0_irq_demux_eint(4, 11);
 112 }
 113
 114 static void s5p64x0_irq_demux_eint12_15(unsigned int irq,
 115                                         struct irq_desc *desc)
 116 {
 117         s5p64x0_irq_demux_eint(12, 15);
 118 }
 119
 120 static int s5p64x0_alloc_gc(void)
 121 {
 122         struct irq_chip_generic *gc;
 123         struct irq_chip_type *ct;
 124
 125         gc = irq_alloc_generic_chip("s5p64x0-eint", 1, S5P_IRQ_EINT_BASE,
 126                                     S5P_VA_GPIO, handle_level_irq);
 127         if (!gc) {
 128                 printk(KERN_ERR "%s: irq_alloc_generic_chip for group 0"
 129                         "external interrupts failed\n", __func__);
 130                 return -EINVAL;
 131         }
 132
 133         ct = gc->chip_types;
 134         ct->chip.irq_ack = irq_gc_ack_set_bit;
 135         ct->chip.irq_mask = irq_gc_mask_set_bit;
 136         ct->chip.irq_unmask = irq_gc_mask_clr_bit;
 137         ct->chip.irq_set_type = s5p64x0_irq_eint_set_type;
 138         ct->chip.irq_set_wake = s3c_irqext_wake;
 139         ct->regs.ack = EINT0PEND_OFFSET;
 140         ct->regs.mask = EINT0MASK_OFFSET;
 141         irq_setup_generic_chip(gc, IRQ_MSK(16), IRQ_GC_INIT_MASK_CACHE,
 142                                IRQ_NOREQUEST | IRQ_NOPROBE, 0);
 143         return 0;
 144 }
 145
 146 static int __init s5p64x0_init_irq_eint(void)
 147 {
 148         int ret = s5p64x0_alloc_gc();
 149         irq_set_chained_handler(IRQ_EINT0_3, s5p64x0_irq_demux_eint0_3);
 150         irq_set_chained_handler(IRQ_EINT4_11, s5p64x0_irq_demux_eint4_11);
 151         irq_set_chained_handler(IRQ_EINT12_15, s5p64x0_irq_demux_eint12_15);
 152
 153         return ret;
 154 }
 155 arch_initcall(s5p64x0_init_irq_eint);