arch/arm/mach-exynos/dma.c

   1 /* linux/arch/arm/mach-exynos4/dma.c
   2  *
   3  * Copyright (c) 2011 Samsung Electronics Co., Ltd.
   4  *              http://www.samsung.com
   5  *
   6  * Copyright (C) 2010 Samsung Electronics Co. Ltd.
   7  *      Jaswinder Singh <jassi.brar@samsung.com>
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; either version 2 of the License, or
  12  * (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  22  */
  23
  24 #include <linux/dma-mapping.h>
  25 #include <linux/amba/bus.h>
  26 #include <linux/amba/pl330.h>
  27
  28 #include <asm/irq.h>
  29 #include <plat/devs.h>
  30 #include <plat/irqs.h>
  31
  32 #include <mach/map.h>
  33 #include <mach/irqs.h>
  34 #include <mach/dma.h>
  35
  36 static u64 dma_dmamask = DMA_BIT_MASK(32);
  37
  38 struct dma_pl330_peri pdma0_peri[28] = {
  39         {
  40                 .peri_id = (u8)DMACH_PCM0_RX,
  41                 .rqtype = DEVTOMEM,
  42         }, {
  43                 .peri_id = (u8)DMACH_PCM0_TX,
  44                 .rqtype = MEMTODEV,
  45         }, {
  46                 .peri_id = (u8)DMACH_PCM2_RX,
  47                 .rqtype = DEVTOMEM,
  48         }, {
  49                 .peri_id = (u8)DMACH_PCM2_TX,
  50                 .rqtype = MEMTODEV,
  51         }, {
  52                 .peri_id = (u8)DMACH_MSM_REQ0,
  53         }, {
  54                 .peri_id = (u8)DMACH_MSM_REQ2,
  55         }, {
  56                 .peri_id = (u8)DMACH_SPI0_RX,
  57                 .rqtype = DEVTOMEM,
  58         }, {
  59                 .peri_id = (u8)DMACH_SPI0_TX,
  60                 .rqtype = MEMTODEV,
  61         }, {
  62                 .peri_id = (u8)DMACH_SPI2_RX,
  63                 .rqtype = DEVTOMEM,
  64         }, {
  65                 .peri_id = (u8)DMACH_SPI2_TX,
  66                 .rqtype = MEMTODEV,
  67         }, {
  68                 .peri_id = (u8)DMACH_I2S0S_TX,
  69                 .rqtype = MEMTODEV,
  70         }, {
  71                 .peri_id = (u8)DMACH_I2S0_RX,
  72                 .rqtype = DEVTOMEM,
  73         }, {
  74                 .peri_id = (u8)DMACH_I2S0_TX,
  75                 .rqtype = MEMTODEV,
  76         }, {
  77                 .peri_id = (u8)DMACH_UART0_RX,
  78                 .rqtype = DEVTOMEM,
  79         }, {
  80                 .peri_id = (u8)DMACH_UART0_TX,
  81                 .rqtype = MEMTODEV,
  82         }, {
  83                 .peri_id = (u8)DMACH_UART2_RX,
  84                 .rqtype = DEVTOMEM,
  85         }, {
  86                 .peri_id = (u8)DMACH_UART2_TX,
  87                 .rqtype = MEMTODEV,
  88         }, {
  89                 .peri_id = (u8)DMACH_UART4_RX,
  90                 .rqtype = DEVTOMEM,
  91         }, {
  92                 .peri_id = (u8)DMACH_UART4_TX,
  93                 .rqtype = MEMTODEV,
  94         }, {
  95                 .peri_id = (u8)DMACH_SLIMBUS0_RX,
  96                 .rqtype = DEVTOMEM,
  97         }, {
  98                 .peri_id = (u8)DMACH_SLIMBUS0_TX,
  99                 .rqtype = MEMTODEV,
 100         }, {
 101                 .peri_id = (u8)DMACH_SLIMBUS2_RX,
 102                 .rqtype = DEVTOMEM,
 103         }, {
 104                 .peri_id = (u8)DMACH_SLIMBUS2_TX,
 105                 .rqtype = MEMTODEV,
 106         }, {
 107                 .peri_id = (u8)DMACH_SLIMBUS4_RX,
 108                 .rqtype = DEVTOMEM,
 109         }, {
 110                 .peri_id = (u8)DMACH_SLIMBUS4_TX,
 111                 .rqtype = MEMTODEV,
 112         }, {
 113                 .peri_id = (u8)DMACH_AC97_MICIN,
 114                 .rqtype = DEVTOMEM,
 115         }, {
 116                 .peri_id = (u8)DMACH_AC97_PCMIN,
 117                 .rqtype = DEVTOMEM,
 118         }, {
 119                 .peri_id = (u8)DMACH_AC97_PCMOUT,
 120                 .rqtype = MEMTODEV,
 121         },
 122 };
 123
 124 struct dma_pl330_platdata exynos4_pdma0_pdata = {
 125         .nr_valid_peri = ARRAY_SIZE(pdma0_peri),
 126         .peri = pdma0_peri,
 127 };
 128
 129 struct amba_device exynos4_device_pdma0 = {
 130         .dev = {
 131                 .init_name = "dma-pl330.0",
 132                 .dma_mask = &dma_dmamask,
 133                 .coherent_dma_mask = DMA_BIT_MASK(32),
 134                 .platform_data = &exynos4_pdma0_pdata,
 135         },
 136         .res = {
 137                 .start = EXYNOS4_PA_PDMA0,
 138                 .end = EXYNOS4_PA_PDMA0 + SZ_4K,
 139                 .flags = IORESOURCE_MEM,
 140         },
 141         .irq = {IRQ_PDMA0, NO_IRQ},
 142         .periphid = 0x00041330,
 143 };
 144
 145 struct dma_pl330_peri pdma1_peri[25] = {
 146         {
 147                 .peri_id = (u8)DMACH_PCM0_RX,
 148                 .rqtype = DEVTOMEM,
 149         }, {
 150                 .peri_id = (u8)DMACH_PCM0_TX,
 151                 .rqtype = MEMTODEV,
 152         }, {
 153                 .peri_id = (u8)DMACH_PCM1_RX,
 154                 .rqtype = DEVTOMEM,
 155         }, {
 156                 .peri_id = (u8)DMACH_PCM1_TX,
 157                 .rqtype = MEMTODEV,
 158         }, {
 159                 .peri_id = (u8)DMACH_MSM_REQ1,
 160         }, {
 161                 .peri_id = (u8)DMACH_MSM_REQ3,
 162         }, {
 163                 .peri_id = (u8)DMACH_SPI1_RX,
 164                 .rqtype = DEVTOMEM,
 165         }, {
 166                 .peri_id = (u8)DMACH_SPI1_TX,
 167                 .rqtype = MEMTODEV,
 168         }, {
 169                 .peri_id = (u8)DMACH_I2S0S_TX,
 170                 .rqtype = MEMTODEV,
 171         }, {
 172                 .peri_id = (u8)DMACH_I2S0_RX,
 173                 .rqtype = DEVTOMEM,
 174         }, {
 175                 .peri_id = (u8)DMACH_I2S0_TX,
 176                 .rqtype = MEMTODEV,
 177         }, {
 178                 .peri_id = (u8)DMACH_I2S1_RX,
 179                 .rqtype = DEVTOMEM,
 180         }, {
 181                 .peri_id = (u8)DMACH_I2S1_TX,
 182                 .rqtype = MEMTODEV,
 183         }, {
 184                 .peri_id = (u8)DMACH_UART0_RX,
 185                 .rqtype = DEVTOMEM,
 186         }, {
 187                 .peri_id = (u8)DMACH_UART0_TX,
 188                 .rqtype = MEMTODEV,
 189         }, {
 190                 .peri_id = (u8)DMACH_UART1_RX,
 191                 .rqtype = DEVTOMEM,
 192         }, {
 193                 .peri_id = (u8)DMACH_UART1_TX,
 194                 .rqtype = MEMTODEV,
 195         }, {
 196                 .peri_id = (u8)DMACH_UART3_RX,
 197                 .rqtype = DEVTOMEM,
 198         }, {
 199                 .peri_id = (u8)DMACH_UART3_TX,
 200                 .rqtype = MEMTODEV,
 201         }, {
 202                 .peri_id = (u8)DMACH_SLIMBUS1_RX,
 203                 .rqtype = DEVTOMEM,
 204         }, {
 205                 .peri_id = (u8)DMACH_SLIMBUS1_TX,
 206                 .rqtype = MEMTODEV,
 207         }, {
 208                 .peri_id = (u8)DMACH_SLIMBUS3_RX,
 209                 .rqtype = DEVTOMEM,
 210         }, {
 211                 .peri_id = (u8)DMACH_SLIMBUS3_TX,
 212                 .rqtype = MEMTODEV,
 213         }, {
 214                 .peri_id = (u8)DMACH_SLIMBUS5_RX,
 215                 .rqtype = DEVTOMEM,
 216         }, {
 217                 .peri_id = (u8)DMACH_SLIMBUS5_TX,
 218                 .rqtype = MEMTODEV,
 219         },
 220 };
 221
 222 struct dma_pl330_platdata exynos4_pdma1_pdata = {
 223         .nr_valid_peri = ARRAY_SIZE(pdma1_peri),
 224         .peri = pdma1_peri,
 225 };
 226
 227 struct amba_device exynos4_device_pdma1 = {
 228         .dev = {
 229                 .init_name = "dma-pl330.1",
 230                 .dma_mask = &dma_dmamask,
 231                 .coherent_dma_mask = DMA_BIT_MASK(32),
 232                 .platform_data = &exynos4_pdma1_pdata,
 233         },
 234         .res = {
 235                 .start = EXYNOS4_PA_PDMA1,
 236                 .end = EXYNOS4_PA_PDMA1 + SZ_4K,
 237                 .flags = IORESOURCE_MEM,
 238         },
 239         .irq = {IRQ_PDMA1, NO_IRQ},
 240         .periphid = 0x00041330,
 241 };
 242
 243 static int __init exynos4_dma_init(void)
 244 {
 245         amba_device_register(&exynos4_device_pdma0, &iomem_resource);
 246         amba_device_register(&exynos4_device_pdma1, &iomem_resource);
 247
 248         return 0;
 249 }
 250 arch_initcall(exynos4_dma_init);