drm: Fix authentication kernel crash
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / arch / arm / kernel / bios32.c
blobb530e9116a0c76283a1d5839868241abec382a1b
1 /*
2 * linux/arch/arm/kernel/bios32.c
4 * PCI bios-type initialisation for PCI machines
6 * Bits taken from various places.
7 */
8 #include <linux/export.h>
9 #include <linux/kernel.h>
10 #include <linux/pci.h>
11 #include <linux/slab.h>
12 #include <linux/init.h>
13 #include <linux/io.h>
15 #include <asm/mach-types.h>
16 #include <asm/mach/pci.h>
18 static int debug_pci;
19 static int use_firmware;
22 * We can't use pci_find_device() here since we are
23 * called from interrupt context.
25 static void pcibios_bus_report_status(struct pci_bus *bus, u_int status_mask, int warn)
27 struct pci_dev *dev;
29 list_for_each_entry(dev, &bus->devices, bus_list) {
30 u16 status;
33 * ignore host bridge - we handle
34 * that separately
36 if (dev->bus->number == 0 && dev->devfn == 0)
37 continue;
39 pci_read_config_word(dev, PCI_STATUS, &status);
40 if (status == 0xffff)
41 continue;
43 if ((status & status_mask) == 0)
44 continue;
46 /* clear the status errors */
47 pci_write_config_word(dev, PCI_STATUS, status & status_mask);
49 if (warn)
50 printk("(%s: %04X) ", pci_name(dev), status);
53 list_for_each_entry(dev, &bus->devices, bus_list)
54 if (dev->subordinate)
55 pcibios_bus_report_status(dev->subordinate, status_mask, warn);
58 void pcibios_report_status(u_int status_mask, int warn)
60 struct list_head *l;
62 list_for_each(l, &pci_root_buses) {
63 struct pci_bus *bus = pci_bus_b(l);
65 pcibios_bus_report_status(bus, status_mask, warn);
70 * We don't use this to fix the device, but initialisation of it.
71 * It's not the correct use for this, but it works.
72 * Note that the arbiter/ISA bridge appears to be buggy, specifically in
73 * the following area:
74 * 1. park on CPU
75 * 2. ISA bridge ping-pong
76 * 3. ISA bridge master handling of target RETRY
78 * Bug 3 is responsible for the sound DMA grinding to a halt. We now
79 * live with bug 2.
81 static void __devinit pci_fixup_83c553(struct pci_dev *dev)
84 * Set memory region to start at address 0, and enable IO
86 pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_SPACE_MEMORY);
87 pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_IO);
89 dev->resource[0].end -= dev->resource[0].start;
90 dev->resource[0].start = 0;
93 * All memory requests from ISA to be channelled to PCI
95 pci_write_config_byte(dev, 0x48, 0xff);
98 * Enable ping-pong on bus master to ISA bridge transactions.
99 * This improves the sound DMA substantially. The fixed
100 * priority arbiter also helps (see below).
102 pci_write_config_byte(dev, 0x42, 0x01);
105 * Enable PCI retry
107 pci_write_config_byte(dev, 0x40, 0x22);
110 * We used to set the arbiter to "park on last master" (bit
111 * 1 set), but unfortunately the CyberPro does not park the
112 * bus. We must therefore park on CPU. Unfortunately, this
113 * may trigger yet another bug in the 553.
115 pci_write_config_byte(dev, 0x83, 0x02);
118 * Make the ISA DMA request lowest priority, and disable
119 * rotating priorities completely.
121 pci_write_config_byte(dev, 0x80, 0x11);
122 pci_write_config_byte(dev, 0x81, 0x00);
125 * Route INTA input to IRQ 11, and set IRQ11 to be level
126 * sensitive.
128 pci_write_config_word(dev, 0x44, 0xb000);
129 outb(0x08, 0x4d1);
131 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_WINBOND, PCI_DEVICE_ID_WINBOND_83C553, pci_fixup_83c553);
133 static void __devinit pci_fixup_unassign(struct pci_dev *dev)
135 dev->resource[0].end -= dev->resource[0].start;
136 dev->resource[0].start = 0;
138 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_WINBOND2, PCI_DEVICE_ID_WINBOND2_89C940F, pci_fixup_unassign);
141 * Prevent the PCI layer from seeing the resources allocated to this device
142 * if it is the host bridge by marking it as such. These resources are of
143 * no consequence to the PCI layer (they are handled elsewhere).
145 static void __devinit pci_fixup_dec21285(struct pci_dev *dev)
147 int i;
149 if (dev->devfn == 0) {
150 dev->class &= 0xff;
151 dev->class |= PCI_CLASS_BRIDGE_HOST << 8;
152 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
153 dev->resource[i].start = 0;
154 dev->resource[i].end = 0;
155 dev->resource[i].flags = 0;
159 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21285, pci_fixup_dec21285);
162 * PCI IDE controllers use non-standard I/O port decoding, respect it.
164 static void __devinit pci_fixup_ide_bases(struct pci_dev *dev)
166 struct resource *r;
167 int i;
169 if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE)
170 return;
172 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
173 r = dev->resource + i;
174 if ((r->start & ~0x80) == 0x374) {
175 r->start |= 2;
176 r->end = r->start;
180 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pci_fixup_ide_bases);
183 * Put the DEC21142 to sleep
185 static void __devinit pci_fixup_dec21142(struct pci_dev *dev)
187 pci_write_config_dword(dev, 0x40, 0x80000000);
189 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21142, pci_fixup_dec21142);
192 * The CY82C693 needs some rather major fixups to ensure that it does
193 * the right thing. Idea from the Alpha people, with a few additions.
195 * We ensure that the IDE base registers are set to 1f0/3f4 for the
196 * primary bus, and 170/374 for the secondary bus. Also, hide them
197 * from the PCI subsystem view as well so we won't try to perform
198 * our own auto-configuration on them.
200 * In addition, we ensure that the PCI IDE interrupts are routed to
201 * IRQ 14 and IRQ 15 respectively.
203 * The above gets us to a point where the IDE on this device is
204 * functional. However, The CY82C693U _does not work_ in bus
205 * master mode without locking the PCI bus solid.
207 static void __devinit pci_fixup_cy82c693(struct pci_dev *dev)
209 if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE) {
210 u32 base0, base1;
212 if (dev->class & 0x80) { /* primary */
213 base0 = 0x1f0;
214 base1 = 0x3f4;
215 } else { /* secondary */
216 base0 = 0x170;
217 base1 = 0x374;
220 pci_write_config_dword(dev, PCI_BASE_ADDRESS_0,
221 base0 | PCI_BASE_ADDRESS_SPACE_IO);
222 pci_write_config_dword(dev, PCI_BASE_ADDRESS_1,
223 base1 | PCI_BASE_ADDRESS_SPACE_IO);
225 dev->resource[0].start = 0;
226 dev->resource[0].end = 0;
227 dev->resource[0].flags = 0;
229 dev->resource[1].start = 0;
230 dev->resource[1].end = 0;
231 dev->resource[1].flags = 0;
232 } else if (PCI_FUNC(dev->devfn) == 0) {
234 * Setup IDE IRQ routing.
236 pci_write_config_byte(dev, 0x4b, 14);
237 pci_write_config_byte(dev, 0x4c, 15);
240 * Disable FREQACK handshake, enable USB.
242 pci_write_config_byte(dev, 0x4d, 0x41);
245 * Enable PCI retry, and PCI post-write buffer.
247 pci_write_config_byte(dev, 0x44, 0x17);
250 * Enable ISA master and DMA post write buffering.
252 pci_write_config_byte(dev, 0x45, 0x03);
255 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CONTAQ, PCI_DEVICE_ID_CONTAQ_82C693, pci_fixup_cy82c693);
257 static void __init pci_fixup_it8152(struct pci_dev *dev)
259 int i;
260 /* fixup for ITE 8152 devices */
261 /* FIXME: add defines for class 0x68000 and 0x80103 */
262 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_HOST ||
263 dev->class == 0x68000 ||
264 dev->class == 0x80103) {
265 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
266 dev->resource[i].start = 0;
267 dev->resource[i].end = 0;
268 dev->resource[i].flags = 0;
272 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8152, pci_fixup_it8152);
276 void __devinit pcibios_update_irq(struct pci_dev *dev, int irq)
278 if (debug_pci)
279 printk("PCI: Assigning IRQ %02d to %s\n", irq, pci_name(dev));
280 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
284 * If the bus contains any of these devices, then we must not turn on
285 * parity checking of any kind. Currently this is CyberPro 20x0 only.
287 static inline int pdev_bad_for_parity(struct pci_dev *dev)
289 return ((dev->vendor == PCI_VENDOR_ID_INTERG &&
290 (dev->device == PCI_DEVICE_ID_INTERG_2000 ||
291 dev->device == PCI_DEVICE_ID_INTERG_2010)) ||
292 (dev->vendor == PCI_VENDOR_ID_ITE &&
293 dev->device == PCI_DEVICE_ID_ITE_8152));
298 * Adjust the device resources from bus-centric to Linux-centric.
300 static void __devinit
301 pdev_fixup_device_resources(struct pci_sys_data *root, struct pci_dev *dev)
303 resource_size_t offset;
304 int i;
306 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
307 if (dev->resource[i].start == 0)
308 continue;
309 if (dev->resource[i].flags & IORESOURCE_MEM)
310 offset = root->mem_offset;
311 else
312 offset = root->io_offset;
314 dev->resource[i].start += offset;
315 dev->resource[i].end += offset;
319 static void __devinit
320 pbus_assign_bus_resources(struct pci_bus *bus, struct pci_sys_data *root)
322 struct pci_dev *dev = bus->self;
323 int i;
325 if (!dev) {
327 * Assign root bus resources.
329 for (i = 0; i < 3; i++)
330 bus->resource[i] = root->resource[i];
335 * pcibios_fixup_bus - Called after each bus is probed,
336 * but before its children are examined.
338 void pcibios_fixup_bus(struct pci_bus *bus)
340 struct pci_sys_data *root = bus->sysdata;
341 struct pci_dev *dev;
342 u16 features = PCI_COMMAND_SERR | PCI_COMMAND_PARITY | PCI_COMMAND_FAST_BACK;
344 pbus_assign_bus_resources(bus, root);
347 * Walk the devices on this bus, working out what we can
348 * and can't support.
350 list_for_each_entry(dev, &bus->devices, bus_list) {
351 u16 status;
353 pdev_fixup_device_resources(root, dev);
355 pci_read_config_word(dev, PCI_STATUS, &status);
358 * If any device on this bus does not support fast back
359 * to back transfers, then the bus as a whole is not able
360 * to support them. Having fast back to back transfers
361 * on saves us one PCI cycle per transaction.
363 if (!(status & PCI_STATUS_FAST_BACK))
364 features &= ~PCI_COMMAND_FAST_BACK;
366 if (pdev_bad_for_parity(dev))
367 features &= ~(PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
369 switch (dev->class >> 8) {
370 case PCI_CLASS_BRIDGE_PCI:
371 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &status);
372 status |= PCI_BRIDGE_CTL_PARITY|PCI_BRIDGE_CTL_MASTER_ABORT;
373 status &= ~(PCI_BRIDGE_CTL_BUS_RESET|PCI_BRIDGE_CTL_FAST_BACK);
374 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, status);
375 break;
377 case PCI_CLASS_BRIDGE_CARDBUS:
378 pci_read_config_word(dev, PCI_CB_BRIDGE_CONTROL, &status);
379 status |= PCI_CB_BRIDGE_CTL_PARITY|PCI_CB_BRIDGE_CTL_MASTER_ABORT;
380 pci_write_config_word(dev, PCI_CB_BRIDGE_CONTROL, status);
381 break;
386 * Now walk the devices again, this time setting them up.
388 list_for_each_entry(dev, &bus->devices, bus_list) {
389 u16 cmd;
391 pci_read_config_word(dev, PCI_COMMAND, &cmd);
392 cmd |= features;
393 pci_write_config_word(dev, PCI_COMMAND, cmd);
395 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE,
396 L1_CACHE_BYTES >> 2);
400 * Propagate the flags to the PCI bridge.
402 if (bus->self && bus->self->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
403 if (features & PCI_COMMAND_FAST_BACK)
404 bus->bridge_ctl |= PCI_BRIDGE_CTL_FAST_BACK;
405 if (features & PCI_COMMAND_PARITY)
406 bus->bridge_ctl |= PCI_BRIDGE_CTL_PARITY;
410 * Report what we did for this bus
412 printk(KERN_INFO "PCI: bus%d: Fast back to back transfers %sabled\n",
413 bus->number, (features & PCI_COMMAND_FAST_BACK) ? "en" : "dis");
415 #ifdef CONFIG_HOTPLUG
416 EXPORT_SYMBOL(pcibios_fixup_bus);
417 #endif
420 * Convert from Linux-centric to bus-centric addresses for bridge devices.
422 void
423 pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
424 struct resource *res)
426 struct pci_sys_data *root = dev->sysdata;
427 unsigned long offset = 0;
429 if (res->flags & IORESOURCE_IO)
430 offset = root->io_offset;
431 if (res->flags & IORESOURCE_MEM)
432 offset = root->mem_offset;
434 region->start = res->start - offset;
435 region->end = res->end - offset;
437 EXPORT_SYMBOL(pcibios_resource_to_bus);
439 void __devinit
440 pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
441 struct pci_bus_region *region)
443 struct pci_sys_data *root = dev->sysdata;
444 unsigned long offset = 0;
446 if (res->flags & IORESOURCE_IO)
447 offset = root->io_offset;
448 if (res->flags & IORESOURCE_MEM)
449 offset = root->mem_offset;
451 res->start = region->start + offset;
452 res->end = region->end + offset;
454 EXPORT_SYMBOL(pcibios_bus_to_resource);
457 * Swizzle the device pin each time we cross a bridge.
458 * This might update pin and returns the slot number.
460 static u8 __devinit pcibios_swizzle(struct pci_dev *dev, u8 *pin)
462 struct pci_sys_data *sys = dev->sysdata;
463 int slot = 0, oldpin = *pin;
465 if (sys->swizzle)
466 slot = sys->swizzle(dev, pin);
468 if (debug_pci)
469 printk("PCI: %s swizzling pin %d => pin %d slot %d\n",
470 pci_name(dev), oldpin, *pin, slot);
472 return slot;
476 * Map a slot/pin to an IRQ.
478 static int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
480 struct pci_sys_data *sys = dev->sysdata;
481 int irq = -1;
483 if (sys->map_irq)
484 irq = sys->map_irq(dev, slot, pin);
486 if (debug_pci)
487 printk("PCI: %s mapping slot %d pin %d => irq %d\n",
488 pci_name(dev), slot, pin, irq);
490 return irq;
493 static void __init pcibios_init_hw(struct hw_pci *hw)
495 struct pci_sys_data *sys = NULL;
496 int ret;
497 int nr, busnr;
499 for (nr = busnr = 0; nr < hw->nr_controllers; nr++) {
500 sys = kzalloc(sizeof(struct pci_sys_data), GFP_KERNEL);
501 if (!sys)
502 panic("PCI: unable to allocate sys data!");
504 #ifdef CONFIG_PCI_DOMAINS
505 sys->domain = hw->domain;
506 #endif
507 sys->hw = hw;
508 sys->busnr = busnr;
509 sys->swizzle = hw->swizzle;
510 sys->map_irq = hw->map_irq;
511 sys->resource[0] = &ioport_resource;
512 sys->resource[1] = &iomem_resource;
514 ret = hw->setup(nr, sys);
516 if (ret > 0) {
517 sys->bus = hw->scan(nr, sys);
519 if (!sys->bus)
520 panic("PCI: unable to scan bus!");
522 busnr = sys->bus->subordinate + 1;
524 list_add(&sys->node, &hw->buses);
525 } else {
526 kfree(sys);
527 if (ret < 0)
528 break;
533 void __init pci_common_init(struct hw_pci *hw)
535 struct pci_sys_data *sys;
537 INIT_LIST_HEAD(&hw->buses);
539 if (hw->preinit)
540 hw->preinit();
541 pcibios_init_hw(hw);
542 if (hw->postinit)
543 hw->postinit();
545 pci_fixup_irqs(pcibios_swizzle, pcibios_map_irq);
547 list_for_each_entry(sys, &hw->buses, node) {
548 struct pci_bus *bus = sys->bus;
550 if (!use_firmware) {
552 * Size the bridge windows.
554 pci_bus_size_bridges(bus);
557 * Assign resources.
559 pci_bus_assign_resources(bus);
562 * Enable bridges
564 pci_enable_bridges(bus);
568 * Tell drivers about devices found.
570 pci_bus_add_devices(bus);
574 char * __init pcibios_setup(char *str)
576 if (!strcmp(str, "debug")) {
577 debug_pci = 1;
578 return NULL;
579 } else if (!strcmp(str, "firmware")) {
580 use_firmware = 1;
581 return NULL;
583 return str;
587 * From arch/i386/kernel/pci-i386.c:
589 * We need to avoid collisions with `mirrored' VGA ports
590 * and other strange ISA hardware, so we always want the
591 * addresses to be allocated in the 0x000-0x0ff region
592 * modulo 0x400.
594 * Why? Because some silly external IO cards only decode
595 * the low 10 bits of the IO address. The 0x00-0xff region
596 * is reserved for motherboard devices that decode all 16
597 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
598 * but we want to try to avoid allocating at 0x2900-0x2bff
599 * which might be mirrored at 0x0100-0x03ff..
601 resource_size_t pcibios_align_resource(void *data, const struct resource *res,
602 resource_size_t size, resource_size_t align)
604 resource_size_t start = res->start;
606 if (res->flags & IORESOURCE_IO && start & 0x300)
607 start = (start + 0x3ff) & ~0x3ff;
609 start = (start + align - 1) & ~(align - 1);
611 return start;
615 * pcibios_enable_device - Enable I/O and memory.
616 * @dev: PCI device to be enabled
618 int pcibios_enable_device(struct pci_dev *dev, int mask)
620 u16 cmd, old_cmd;
621 int idx;
622 struct resource *r;
624 pci_read_config_word(dev, PCI_COMMAND, &cmd);
625 old_cmd = cmd;
626 for (idx = 0; idx < 6; idx++) {
627 /* Only set up the requested stuff */
628 if (!(mask & (1 << idx)))
629 continue;
631 r = dev->resource + idx;
632 if (!r->start && r->end) {
633 printk(KERN_ERR "PCI: Device %s not available because"
634 " of resource collisions\n", pci_name(dev));
635 return -EINVAL;
637 if (r->flags & IORESOURCE_IO)
638 cmd |= PCI_COMMAND_IO;
639 if (r->flags & IORESOURCE_MEM)
640 cmd |= PCI_COMMAND_MEMORY;
644 * Bridges (eg, cardbus bridges) need to be fully enabled
646 if ((dev->class >> 16) == PCI_BASE_CLASS_BRIDGE)
647 cmd |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
649 if (cmd != old_cmd) {
650 printk("PCI: enabling device %s (%04x -> %04x)\n",
651 pci_name(dev), old_cmd, cmd);
652 pci_write_config_word(dev, PCI_COMMAND, cmd);
654 return 0;
657 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
658 enum pci_mmap_state mmap_state, int write_combine)
660 struct pci_sys_data *root = dev->sysdata;
661 unsigned long phys;
663 if (mmap_state == pci_mmap_io) {
664 return -EINVAL;
665 } else {
666 phys = vma->vm_pgoff + (root->mem_offset >> PAGE_SHIFT);
670 * Mark this as IO
672 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
674 if (remap_pfn_range(vma, vma->vm_start, phys,
675 vma->vm_end - vma->vm_start,
676 vma->vm_page_prot))
677 return -EAGAIN;
679 return 0;