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usb: musb: drop board_set_vbus
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / usb / musb / musb_core.c
blob325d7acafdf9777eed834de44f279c55925de4f5
1 /*
2 * MUSB OTG driver core code
3 *
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
20 * 02110-1301 USA
21 *
22 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
25 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 */
34
35 /*
36 * Inventra (Multipoint) Dual-Role Controller Driver for Linux.
37 *
38 * This consists of a Host Controller Driver (HCD) and a peripheral
39 * controller driver implementing the "Gadget" API; OTG support is
40 * in the works. These are normal Linux-USB controller drivers which
41 * use IRQs and have no dedicated thread.
42 *
43 * This version of the driver has only been used with products from
44 * Texas Instruments. Those products integrate the Inventra logic
45 * with other DMA, IRQ, and bus modules, as well as other logic that
46 * needs to be reflected in this driver.
47 *
48 *
49 * NOTE: the original Mentor code here was pretty much a collection
50 * of mechanisms that don't seem to have been fully integrated/working
51 * for *any* Linux kernel version. This version aims at Linux 2.6.now,
52 * Key open issues include:
53 *
54 * - Lack of host-side transaction scheduling, for all transfer types.
55 * The hardware doesn't do it; instead, software must.
56 *
57 * This is not an issue for OTG devices that don't support external
58 * hubs, but for more "normal" USB hosts it's a user issue that the
59 * "multipoint" support doesn't scale in the expected ways. That
60 * includes DaVinci EVM in a common non-OTG mode.
61 *
62 * * Control and bulk use dedicated endpoints, and there's as
63 * yet no mechanism to either (a) reclaim the hardware when
64 * peripherals are NAKing, which gets complicated with bulk
65 * endpoints, or (b) use more than a single bulk endpoint in
66 * each direction.
67 *
68 * RESULT: one device may be perceived as blocking another one.
69 *
70 * * Interrupt and isochronous will dynamically allocate endpoint
71 * hardware, but (a) there's no record keeping for bandwidth;
72 * (b) in the common case that few endpoints are available, there
73 * is no mechanism to reuse endpoints to talk to multiple devices.
74 *
75 * RESULT: At one extreme, bandwidth can be overcommitted in
76 * some hardware configurations, no faults will be reported.
77 * At the other extreme, the bandwidth capabilities which do
78 * exist tend to be severely undercommitted. You can't yet hook
79 * up both a keyboard and a mouse to an external USB hub.
80 */
81
82 /*
83 * This gets many kinds of configuration information:
84 * - Kconfig for everything user-configurable
85 * - platform_device for addressing, irq, and platform_data
86 * - platform_data is mostly for board-specific informarion
87 * (plus recentrly, SOC or family details)
88 *
89 * Most of the conditional compilation will (someday) vanish.
90 */
91
92 #include <linux/module.h>
93 #include <linux/kernel.h>
94 #include <linux/sched.h>
95 #include <linux/slab.h>
96 #include <linux/init.h>
97 #include <linux/list.h>
98 #include <linux/kobject.h>
99 #include <linux/platform_device.h>
100 #include <linux/io.h>
101
102 #ifdef CONFIG_ARM
103 #include <mach/hardware.h>
104 #include <mach/memory.h>
105 #include <asm/mach-types.h>
106 #endif
107
108 #include "musb_core.h"
109
110
111 #ifdef CONFIG_ARCH_DAVINCI
112 #include "davinci.h"
113 #endif
114
115 #define TA_WAIT_BCON(m) max_t(int, (m)->a_wait_bcon, OTG_TIME_A_WAIT_BCON)
116
117
118 unsigned musb_debug;
119 module_param_named(debug, musb_debug, uint, S_IRUGO | S_IWUSR);
120 MODULE_PARM_DESC(debug, "Debug message level. Default = 0");
121
122 #define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia"
123 #define DRIVER_DESC "Inventra Dual-Role USB Controller Driver"
124
125 #define MUSB_VERSION "6.0"
126
127 #define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION
128
129 #define MUSB_DRIVER_NAME "musb-hdrc"
130 const char musb_driver_name[] = MUSB_DRIVER_NAME;
131
132 MODULE_DESCRIPTION(DRIVER_INFO);
133 MODULE_AUTHOR(DRIVER_AUTHOR);
134 MODULE_LICENSE("GPL");
135 MODULE_ALIAS("platform:" MUSB_DRIVER_NAME);
136
137
138 /*-------------------------------------------------------------------------*/
139
140 static inline struct musb *dev_to_musb(struct device *dev)
141 {
142 #ifdef CONFIG_USB_MUSB_HDRC_HCD
143 /* usbcore insists dev->driver_data is a "struct hcd *" */
144 return hcd_to_musb(dev_get_drvdata(dev));
145 #else
146 return dev_get_drvdata(dev);
147 #endif
148 }
149
150 /*-------------------------------------------------------------------------*/
151
152 #ifndef CONFIG_BLACKFIN
153 static int musb_ulpi_read(struct otg_transceiver *otg, u32 offset)
154 {
155 void __iomem *addr = otg->io_priv;
156 int i = 0;
157 u8 r;
158 u8 power;
159
160 /* Make sure the transceiver is not in low power mode */
161 power = musb_readb(addr, MUSB_POWER);
162 power &= ~MUSB_POWER_SUSPENDM;
163 musb_writeb(addr, MUSB_POWER, power);
164
165 /* REVISIT: musbhdrc_ulpi_an.pdf recommends setting the
166 * ULPICarKitControlDisableUTMI after clearing POWER_SUSPENDM.
167 */
168
169 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset);
170 musb_writeb(addr, MUSB_ULPI_REG_CONTROL,
171 MUSB_ULPI_REG_REQ | MUSB_ULPI_RDN_WR);
172
173 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
174 & MUSB_ULPI_REG_CMPLT)) {
175 i++;
176 if (i == 10000) {
177 DBG(3, "ULPI read timed out\n");
178 return -ETIMEDOUT;
179 }
180
181 }
182 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
183 r &= ~MUSB_ULPI_REG_CMPLT;
184 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
185
186 return musb_readb(addr, MUSB_ULPI_REG_DATA);
187 }
188
189 static int musb_ulpi_write(struct otg_transceiver *otg,
190 u32 offset, u32 data)
191 {
192 void __iomem *addr = otg->io_priv;
193 int i = 0;
194 u8 r = 0;
195 u8 power;
196
197 /* Make sure the transceiver is not in low power mode */
198 power = musb_readb(addr, MUSB_POWER);
199 power &= ~MUSB_POWER_SUSPENDM;
200 musb_writeb(addr, MUSB_POWER, power);
201
202 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset);
203 musb_writeb(addr, MUSB_ULPI_REG_DATA, (u8)data);
204 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, MUSB_ULPI_REG_REQ);
205
206 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
207 & MUSB_ULPI_REG_CMPLT)) {
208 i++;
209 if (i == 10000) {
210 DBG(3, "ULPI write timed out\n");
211 return -ETIMEDOUT;
212 }
213 }
214
215 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
216 r &= ~MUSB_ULPI_REG_CMPLT;
217 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
218
219 return 0;
220 }
221 #else
222 #define musb_ulpi_read NULL
223 #define musb_ulpi_write NULL
224 #endif
225
226 static struct otg_io_access_ops musb_ulpi_access = {
227 .read = musb_ulpi_read,
228 .write = musb_ulpi_write,
229 };
230
231 /*-------------------------------------------------------------------------*/
232
233 #if !defined(CONFIG_USB_MUSB_TUSB6010) && !defined(CONFIG_USB_MUSB_BLACKFIN)
234
235 /*
236 * Load an endpoint's FIFO
237 */
238 void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
239 {
240 void __iomem *fifo = hw_ep->fifo;
241
242 prefetch((u8 *)src);
243
244 DBG(4, "%cX ep%d fifo %p count %d buf %p\n",
245 'T', hw_ep->epnum, fifo, len, src);
246
247 /* we can't assume unaligned reads work */
248 if (likely((0x01 & (unsigned long) src) == 0)) {
249 u16 index = 0;
250
251 /* best case is 32bit-aligned source address */
252 if ((0x02 & (unsigned long) src) == 0) {
253 if (len >= 4) {
254 writesl(fifo, src + index, len >> 2);
255 index += len & ~0x03;
256 }
257 if (len & 0x02) {
258 musb_writew(fifo, 0, *(u16 *)&src[index]);
259 index += 2;
260 }
261 } else {
262 if (len >= 2) {
263 writesw(fifo, src + index, len >> 1);
264 index += len & ~0x01;
265 }
266 }
267 if (len & 0x01)
268 musb_writeb(fifo, 0, src[index]);
269 } else {
270 /* byte aligned */
271 writesb(fifo, src, len);
272 }
273 }
274
275 #if !defined(CONFIG_USB_MUSB_AM35X)
276 /*
277 * Unload an endpoint's FIFO
278 */
279 void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
280 {
281 void __iomem *fifo = hw_ep->fifo;
282
283 DBG(4, "%cX ep%d fifo %p count %d buf %p\n",
284 'R', hw_ep->epnum, fifo, len, dst);
285
286 /* we can't assume unaligned writes work */
287 if (likely((0x01 & (unsigned long) dst) == 0)) {
288 u16 index = 0;
289
290 /* best case is 32bit-aligned destination address */
291 if ((0x02 & (unsigned long) dst) == 0) {
292 if (len >= 4) {
293 readsl(fifo, dst, len >> 2);
294 index = len & ~0x03;
295 }
296 if (len & 0x02) {
297 *(u16 *)&dst[index] = musb_readw(fifo, 0);
298 index += 2;
299 }
300 } else {
301 if (len >= 2) {
302 readsw(fifo, dst, len >> 1);
303 index = len & ~0x01;
304 }
305 }
306 if (len & 0x01)
307 dst[index] = musb_readb(fifo, 0);
308 } else {
309 /* byte aligned */
310 readsb(fifo, dst, len);
311 }
312 }
313 #endif
314
315 #endif /* normal PIO */
316
317
318 /*-------------------------------------------------------------------------*/
319
320 /* for high speed test mode; see USB 2.0 spec 7.1.20 */
321 static const u8 musb_test_packet[53] = {
322 /* implicit SYNC then DATA0 to start */
323
324 /* JKJKJKJK x9 */
325 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
326 /* JJKKJJKK x8 */
327 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
328 /* JJJJKKKK x8 */
329 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee,
330 /* JJJJJJJKKKKKKK x8 */
331 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
332 /* JJJJJJJK x8 */
333 0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd,
334 /* JKKKKKKK x10, JK */
335 0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e
336
337 /* implicit CRC16 then EOP to end */
338 };
339
340 void musb_load_testpacket(struct musb *musb)
341 {
342 void __iomem *regs = musb->endpoints[0].regs;
343
344 musb_ep_select(musb->mregs, 0);
345 musb_write_fifo(musb->control_ep,
346 sizeof(musb_test_packet), musb_test_packet);
347 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_TXPKTRDY);
348 }
349
350 /*-------------------------------------------------------------------------*/
351
352 const char *otg_state_string(struct musb *musb)
353 {
354 switch (musb->xceiv->state) {
355 case OTG_STATE_A_IDLE: return "a_idle";
356 case OTG_STATE_A_WAIT_VRISE: return "a_wait_vrise";
357 case OTG_STATE_A_WAIT_BCON: return "a_wait_bcon";
358 case OTG_STATE_A_HOST: return "a_host";
359 case OTG_STATE_A_SUSPEND: return "a_suspend";
360 case OTG_STATE_A_PERIPHERAL: return "a_peripheral";
361 case OTG_STATE_A_WAIT_VFALL: return "a_wait_vfall";
362 case OTG_STATE_A_VBUS_ERR: return "a_vbus_err";
363 case OTG_STATE_B_IDLE: return "b_idle";
364 case OTG_STATE_B_SRP_INIT: return "b_srp_init";
365 case OTG_STATE_B_PERIPHERAL: return "b_peripheral";
366 case OTG_STATE_B_WAIT_ACON: return "b_wait_acon";
367 case OTG_STATE_B_HOST: return "b_host";
368 default: return "UNDEFINED";
369 }
370 }
371
372 #ifdef CONFIG_USB_MUSB_OTG
373
374 /*
375 * Handles OTG hnp timeouts, such as b_ase0_brst
376 */
377 void musb_otg_timer_func(unsigned long data)
378 {
379 struct musb *musb = (struct musb *)data;
380 unsigned long flags;
381
382 spin_lock_irqsave(&musb->lock, flags);
383 switch (musb->xceiv->state) {
384 case OTG_STATE_B_WAIT_ACON:
385 DBG(1, "HNP: b_wait_acon timeout; back to b_peripheral\n");
386 musb_g_disconnect(musb);
387 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
388 musb->is_active = 0;
389 break;
390 case OTG_STATE_A_SUSPEND:
391 case OTG_STATE_A_WAIT_BCON:
392 DBG(1, "HNP: %s timeout\n", otg_state_string(musb));
393 musb_platform_set_vbus(musb, 0);
394 musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
395 break;
396 default:
397 DBG(1, "HNP: Unhandled mode %s\n", otg_state_string(musb));
398 }
399 musb->ignore_disconnect = 0;
400 spin_unlock_irqrestore(&musb->lock, flags);
401 }
402
403 /*
404 * Stops the HNP transition. Caller must take care of locking.
405 */
406 void musb_hnp_stop(struct musb *musb)
407 {
408 struct usb_hcd *hcd = musb_to_hcd(musb);
409 void __iomem *mbase = musb->mregs;
410 u8 reg;
411
412 DBG(1, "HNP: stop from %s\n", otg_state_string(musb));
413
414 switch (musb->xceiv->state) {
415 case OTG_STATE_A_PERIPHERAL:
416 musb_g_disconnect(musb);
417 DBG(1, "HNP: back to %s\n", otg_state_string(musb));
418 break;
419 case OTG_STATE_B_HOST:
420 DBG(1, "HNP: Disabling HR\n");
421 hcd->self.is_b_host = 0;
422 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
423 MUSB_DEV_MODE(musb);
424 reg = musb_readb(mbase, MUSB_POWER);
425 reg |= MUSB_POWER_SUSPENDM;
426 musb_writeb(mbase, MUSB_POWER, reg);
427 /* REVISIT: Start SESSION_REQUEST here? */
428 break;
429 default:
430 DBG(1, "HNP: Stopping in unknown state %s\n",
431 otg_state_string(musb));
432 }
433
434 /*
435 * When returning to A state after HNP, avoid hub_port_rebounce(),
436 * which cause occasional OPT A "Did not receive reset after connect"
437 * errors.
438 */
439 musb->port1_status &= ~(USB_PORT_STAT_C_CONNECTION << 16);
440 }
441
442 #endif
443
444 /*
445 * Interrupt Service Routine to record USB "global" interrupts.
446 * Since these do not happen often and signify things of
447 * paramount importance, it seems OK to check them individually;
448 * the order of the tests is specified in the manual
449 *
450 * @param musb instance pointer
451 * @param int_usb register contents
452 * @param devctl
453 * @param power
454 */
455
456 static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
457 u8 devctl, u8 power)
458 {
459 irqreturn_t handled = IRQ_NONE;
460
461 DBG(3, "<== Power=%02x, DevCtl=%02x, int_usb=0x%x\n", power, devctl,
462 int_usb);
463
464 /* in host mode, the peripheral may issue remote wakeup.
465 * in peripheral mode, the host may resume the link.
466 * spurious RESUME irqs happen too, paired with SUSPEND.
467 */
468 if (int_usb & MUSB_INTR_RESUME) {
469 handled = IRQ_HANDLED;
470 DBG(3, "RESUME (%s)\n", otg_state_string(musb));
471
472 if (devctl & MUSB_DEVCTL_HM) {
473 #ifdef CONFIG_USB_MUSB_HDRC_HCD
474 void __iomem *mbase = musb->mregs;
475
476 switch (musb->xceiv->state) {
477 case OTG_STATE_A_SUSPEND:
478 /* remote wakeup? later, GetPortStatus
479 * will stop RESUME signaling
480 */
481
482 if (power & MUSB_POWER_SUSPENDM) {
483 /* spurious */
484 musb->int_usb &= ~MUSB_INTR_SUSPEND;
485 DBG(2, "Spurious SUSPENDM\n");
486 break;
487 }
488
489 power &= ~MUSB_POWER_SUSPENDM;
490 musb_writeb(mbase, MUSB_POWER,
491 power | MUSB_POWER_RESUME);
492
493 musb->port1_status |=
494 (USB_PORT_STAT_C_SUSPEND << 16)
495 | MUSB_PORT_STAT_RESUME;
496 musb->rh_timer = jiffies
497 + msecs_to_jiffies(20);
498
499 musb->xceiv->state = OTG_STATE_A_HOST;
500 musb->is_active = 1;
501 usb_hcd_resume_root_hub(musb_to_hcd(musb));
502 break;
503 case OTG_STATE_B_WAIT_ACON:
504 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
505 musb->is_active = 1;
506 MUSB_DEV_MODE(musb);
507 break;
508 default:
509 WARNING("bogus %s RESUME (%s)\n",
510 "host",
511 otg_state_string(musb));
512 }
513 #endif
514 } else {
515 switch (musb->xceiv->state) {
516 #ifdef CONFIG_USB_MUSB_HDRC_HCD
517 case OTG_STATE_A_SUSPEND:
518 /* possibly DISCONNECT is upcoming */
519 musb->xceiv->state = OTG_STATE_A_HOST;
520 usb_hcd_resume_root_hub(musb_to_hcd(musb));
521 break;
522 #endif
523 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
524 case OTG_STATE_B_WAIT_ACON:
525 case OTG_STATE_B_PERIPHERAL:
526 /* disconnect while suspended? we may
527 * not get a disconnect irq...
528 */
529 if ((devctl & MUSB_DEVCTL_VBUS)
530 != (3 << MUSB_DEVCTL_VBUS_SHIFT)
531 ) {
532 musb->int_usb |= MUSB_INTR_DISCONNECT;
533 musb->int_usb &= ~MUSB_INTR_SUSPEND;
534 break;
535 }
536 musb_g_resume(musb);
537 break;
538 case OTG_STATE_B_IDLE:
539 musb->int_usb &= ~MUSB_INTR_SUSPEND;
540 break;
541 #endif
542 default:
543 WARNING("bogus %s RESUME (%s)\n",
544 "peripheral",
545 otg_state_string(musb));
546 }
547 }
548 }
549
550 #ifdef CONFIG_USB_MUSB_HDRC_HCD
551 /* see manual for the order of the tests */
552 if (int_usb & MUSB_INTR_SESSREQ) {
553 void __iomem *mbase = musb->mregs;
554
555 if (devctl & MUSB_DEVCTL_BDEVICE) {
556 DBG(3, "SessReq while on B state\n");
557 return IRQ_HANDLED;
558 }
559
560 DBG(1, "SESSION_REQUEST (%s)\n", otg_state_string(musb));
561
562 /* IRQ arrives from ID pin sense or (later, if VBUS power
563 * is removed) SRP. responses are time critical:
564 * - turn on VBUS (with silicon-specific mechanism)
565 * - go through A_WAIT_VRISE
566 * - ... to A_WAIT_BCON.
567 * a_wait_vrise_tmout triggers VBUS_ERROR transitions
568 */
569 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);
570 musb->ep0_stage = MUSB_EP0_START;
571 musb->xceiv->state = OTG_STATE_A_IDLE;
572 MUSB_HST_MODE(musb);
573 musb_platform_set_vbus(musb, 1);
574
575 handled = IRQ_HANDLED;
576 }
577
578 if (int_usb & MUSB_INTR_VBUSERROR) {
579 int ignore = 0;
580
581 /* During connection as an A-Device, we may see a short
582 * current spikes causing voltage drop, because of cable
583 * and peripheral capacitance combined with vbus draw.
584 * (So: less common with truly self-powered devices, where
585 * vbus doesn't act like a power supply.)
586 *
587 * Such spikes are short; usually less than ~500 usec, max
588 * of ~2 msec. That is, they're not sustained overcurrent
589 * errors, though they're reported using VBUSERROR irqs.
590 *
591 * Workarounds: (a) hardware: use self powered devices.
592 * (b) software: ignore non-repeated VBUS errors.
593 *
594 * REVISIT: do delays from lots of DEBUG_KERNEL checks
595 * make trouble here, keeping VBUS < 4.4V ?
596 */
597 switch (musb->xceiv->state) {
598 case OTG_STATE_A_HOST:
599 /* recovery is dicey once we've gotten past the
600 * initial stages of enumeration, but if VBUS
601 * stayed ok at the other end of the link, and
602 * another reset is due (at least for high speed,
603 * to redo the chirp etc), it might work OK...
604 */
605 case OTG_STATE_A_WAIT_BCON:
606 case OTG_STATE_A_WAIT_VRISE:
607 if (musb->vbuserr_retry) {
608 void __iomem *mbase = musb->mregs;
609
610 musb->vbuserr_retry--;
611 ignore = 1;
612 devctl |= MUSB_DEVCTL_SESSION;
613 musb_writeb(mbase, MUSB_DEVCTL, devctl);
614 } else {
615 musb->port1_status |=
616 USB_PORT_STAT_OVERCURRENT
617 | (USB_PORT_STAT_C_OVERCURRENT << 16);
618 }
619 break;
620 default:
621 break;
622 }
623
624 DBG(1, "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n",
625 otg_state_string(musb),
626 devctl,
627 ({ char *s;
628 switch (devctl & MUSB_DEVCTL_VBUS) {
629 case 0 << MUSB_DEVCTL_VBUS_SHIFT:
630 s = "<SessEnd"; break;
631 case 1 << MUSB_DEVCTL_VBUS_SHIFT:
632 s = "<AValid"; break;
633 case 2 << MUSB_DEVCTL_VBUS_SHIFT:
634 s = "<VBusValid"; break;
635 /* case 3 << MUSB_DEVCTL_VBUS_SHIFT: */
636 default:
637 s = "VALID"; break;
638 }; s; }),
639 VBUSERR_RETRY_COUNT - musb->vbuserr_retry,
640 musb->port1_status);
641
642 /* go through A_WAIT_VFALL then start a new session */
643 if (!ignore)
644 musb_platform_set_vbus(musb, 0);
645 handled = IRQ_HANDLED;
646 }
647
648 #endif
649 if (int_usb & MUSB_INTR_SUSPEND) {
650 DBG(1, "SUSPEND (%s) devctl %02x power %02x\n",
651 otg_state_string(musb), devctl, power);
652 handled = IRQ_HANDLED;
653
654 switch (musb->xceiv->state) {
655 #ifdef CONFIG_USB_MUSB_OTG
656 case OTG_STATE_A_PERIPHERAL:
657 /* We also come here if the cable is removed, since
658 * this silicon doesn't report ID-no-longer-grounded.
659 *
660 * We depend on T(a_wait_bcon) to shut us down, and
661 * hope users don't do anything dicey during this
662 * undesired detour through A_WAIT_BCON.
663 */
664 musb_hnp_stop(musb);
665 usb_hcd_resume_root_hub(musb_to_hcd(musb));
666 musb_root_disconnect(musb);
667 musb_platform_try_idle(musb, jiffies
668 + msecs_to_jiffies(musb->a_wait_bcon
669 ? : OTG_TIME_A_WAIT_BCON));
670
671 break;
672 #endif
673 case OTG_STATE_B_IDLE:
674 if (!musb->is_active)
675 break;
676 case OTG_STATE_B_PERIPHERAL:
677 musb_g_suspend(musb);
678 musb->is_active = is_otg_enabled(musb)
679 && musb->xceiv->gadget->b_hnp_enable;
680 if (musb->is_active) {
681 #ifdef CONFIG_USB_MUSB_OTG
682 musb->xceiv->state = OTG_STATE_B_WAIT_ACON;
683 DBG(1, "HNP: Setting timer for b_ase0_brst\n");
684 mod_timer(&musb->otg_timer, jiffies
685 + msecs_to_jiffies(
686 OTG_TIME_B_ASE0_BRST));
687 #endif
688 }
689 break;
690 case OTG_STATE_A_WAIT_BCON:
691 if (musb->a_wait_bcon != 0)
692 musb_platform_try_idle(musb, jiffies
693 + msecs_to_jiffies(musb->a_wait_bcon));
694 break;
695 case OTG_STATE_A_HOST:
696 musb->xceiv->state = OTG_STATE_A_SUSPEND;
697 musb->is_active = is_otg_enabled(musb)
698 && musb->xceiv->host->b_hnp_enable;
699 break;
700 case OTG_STATE_B_HOST:
701 /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */
702 DBG(1, "REVISIT: SUSPEND as B_HOST\n");
703 break;
704 default:
705 /* "should not happen" */
706 musb->is_active = 0;
707 break;
708 }
709 }
710
711 #ifdef CONFIG_USB_MUSB_HDRC_HCD
712 if (int_usb & MUSB_INTR_CONNECT) {
713 struct usb_hcd *hcd = musb_to_hcd(musb);
714
715 handled = IRQ_HANDLED;
716 musb->is_active = 1;
717 set_bit(HCD_FLAG_SAW_IRQ, &hcd->flags);
718
719 musb->ep0_stage = MUSB_EP0_START;
720
721 #ifdef CONFIG_USB_MUSB_OTG
722 /* flush endpoints when transitioning from Device Mode */
723 if (is_peripheral_active(musb)) {
724 /* REVISIT HNP; just force disconnect */
725 }
726 musb_writew(musb->mregs, MUSB_INTRTXE, musb->epmask);
727 musb_writew(musb->mregs, MUSB_INTRRXE, musb->epmask & 0xfffe);
728 musb_writeb(musb->mregs, MUSB_INTRUSBE, 0xf7);
729 #endif
730 musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED
731 |USB_PORT_STAT_HIGH_SPEED
732 |USB_PORT_STAT_ENABLE
733 );
734 musb->port1_status |= USB_PORT_STAT_CONNECTION
735 |(USB_PORT_STAT_C_CONNECTION << 16);
736
737 /* high vs full speed is just a guess until after reset */
738 if (devctl & MUSB_DEVCTL_LSDEV)
739 musb->port1_status |= USB_PORT_STAT_LOW_SPEED;
740
741 /* indicate new connection to OTG machine */
742 switch (musb->xceiv->state) {
743 case OTG_STATE_B_PERIPHERAL:
744 if (int_usb & MUSB_INTR_SUSPEND) {
745 DBG(1, "HNP: SUSPEND+CONNECT, now b_host\n");
746 int_usb &= ~MUSB_INTR_SUSPEND;
747 goto b_host;
748 } else
749 DBG(1, "CONNECT as b_peripheral???\n");
750 break;
751 case OTG_STATE_B_WAIT_ACON:
752 DBG(1, "HNP: CONNECT, now b_host\n");
753 b_host:
754 musb->xceiv->state = OTG_STATE_B_HOST;
755 hcd->self.is_b_host = 1;
756 musb->ignore_disconnect = 0;
757 del_timer(&musb->otg_timer);
758 break;
759 default:
760 if ((devctl & MUSB_DEVCTL_VBUS)
761 == (3 << MUSB_DEVCTL_VBUS_SHIFT)) {
762 musb->xceiv->state = OTG_STATE_A_HOST;
763 hcd->self.is_b_host = 0;
764 }
765 break;
766 }
767
768 /* poke the root hub */
769 MUSB_HST_MODE(musb);
770 if (hcd->status_urb)
771 usb_hcd_poll_rh_status(hcd);
772 else
773 usb_hcd_resume_root_hub(hcd);
774
775 DBG(1, "CONNECT (%s) devctl %02x\n",
776 otg_state_string(musb), devctl);
777 }
778 #endif /* CONFIG_USB_MUSB_HDRC_HCD */
779
780 if ((int_usb & MUSB_INTR_DISCONNECT) && !musb->ignore_disconnect) {
781 DBG(1, "DISCONNECT (%s) as %s, devctl %02x\n",
782 otg_state_string(musb),
783 MUSB_MODE(musb), devctl);
784 handled = IRQ_HANDLED;
785
786 switch (musb->xceiv->state) {
787 #ifdef CONFIG_USB_MUSB_HDRC_HCD
788 case OTG_STATE_A_HOST:
789 case OTG_STATE_A_SUSPEND:
790 usb_hcd_resume_root_hub(musb_to_hcd(musb));
791 musb_root_disconnect(musb);
792 if (musb->a_wait_bcon != 0 && is_otg_enabled(musb))
793 musb_platform_try_idle(musb, jiffies
794 + msecs_to_jiffies(musb->a_wait_bcon));
795 break;
796 #endif /* HOST */
797 #ifdef CONFIG_USB_MUSB_OTG
798 case OTG_STATE_B_HOST:
799 /* REVISIT this behaves for "real disconnect"
800 * cases; make sure the other transitions from
801 * from B_HOST act right too. The B_HOST code
802 * in hnp_stop() is currently not used...
803 */
804 musb_root_disconnect(musb);
805 musb_to_hcd(musb)->self.is_b_host = 0;
806 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
807 MUSB_DEV_MODE(musb);
808 musb_g_disconnect(musb);
809 break;
810 case OTG_STATE_A_PERIPHERAL:
811 musb_hnp_stop(musb);
812 musb_root_disconnect(musb);
813 /* FALLTHROUGH */
814 case OTG_STATE_B_WAIT_ACON:
815 /* FALLTHROUGH */
816 #endif /* OTG */
817 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
818 case OTG_STATE_B_PERIPHERAL:
819 case OTG_STATE_B_IDLE:
820 musb_g_disconnect(musb);
821 break;
822 #endif /* GADGET */
823 default:
824 WARNING("unhandled DISCONNECT transition (%s)\n",
825 otg_state_string(musb));
826 break;
827 }
828 }
829
830 /* mentor saves a bit: bus reset and babble share the same irq.
831 * only host sees babble; only peripheral sees bus reset.
832 */
833 if (int_usb & MUSB_INTR_RESET) {
834 handled = IRQ_HANDLED;
835 if (is_host_capable() && (devctl & MUSB_DEVCTL_HM) != 0) {
836 /*
837 * Looks like non-HS BABBLE can be ignored, but
838 * HS BABBLE is an error condition. For HS the solution
839 * is to avoid babble in the first place and fix what
840 * caused BABBLE. When HS BABBLE happens we can only
841 * stop the session.
842 */
843 if (devctl & (MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV))
844 DBG(1, "BABBLE devctl: %02x\n", devctl);
845 else {
846 ERR("Stopping host session -- babble\n");
847 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
848 }
849 } else if (is_peripheral_capable()) {
850 DBG(1, "BUS RESET as %s\n", otg_state_string(musb));
851 switch (musb->xceiv->state) {
852 #ifdef CONFIG_USB_OTG
853 case OTG_STATE_A_SUSPEND:
854 /* We need to ignore disconnect on suspend
855 * otherwise tusb 2.0 won't reconnect after a
856 * power cycle, which breaks otg compliance.
857 */
858 musb->ignore_disconnect = 1;
859 musb_g_reset(musb);
860 /* FALLTHROUGH */
861 case OTG_STATE_A_WAIT_BCON: /* OPT TD.4.7-900ms */
862 /* never use invalid T(a_wait_bcon) */
863 DBG(1, "HNP: in %s, %d msec timeout\n",
864 otg_state_string(musb),
865 TA_WAIT_BCON(musb));
866 mod_timer(&musb->otg_timer, jiffies
867 + msecs_to_jiffies(TA_WAIT_BCON(musb)));
868 break;
869 case OTG_STATE_A_PERIPHERAL:
870 musb->ignore_disconnect = 0;
871 del_timer(&musb->otg_timer);
872 musb_g_reset(musb);
873 break;
874 case OTG_STATE_B_WAIT_ACON:
875 DBG(1, "HNP: RESET (%s), to b_peripheral\n",
876 otg_state_string(musb));
877 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
878 musb_g_reset(musb);
879 break;
880 #endif
881 case OTG_STATE_B_IDLE:
882 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
883 /* FALLTHROUGH */
884 case OTG_STATE_B_PERIPHERAL:
885 musb_g_reset(musb);
886 break;
887 default:
888 DBG(1, "Unhandled BUS RESET as %s\n",
889 otg_state_string(musb));
890 }
891 }
892 }
893
894 #if 0
895 /* REVISIT ... this would be for multiplexing periodic endpoints, or
896 * supporting transfer phasing to prevent exceeding ISO bandwidth
897 * limits of a given frame or microframe.
898 *
899 * It's not needed for peripheral side, which dedicates endpoints;
900 * though it _might_ use SOF irqs for other purposes.
901 *
902 * And it's not currently needed for host side, which also dedicates
903 * endpoints, relies on TX/RX interval registers, and isn't claimed
904 * to support ISO transfers yet.
905 */
906 if (int_usb & MUSB_INTR_SOF) {
907 void __iomem *mbase = musb->mregs;
908 struct musb_hw_ep *ep;
909 u8 epnum;
910 u16 frame;
911
912 DBG(6, "START_OF_FRAME\n");
913 handled = IRQ_HANDLED;
914
915 /* start any periodic Tx transfers waiting for current frame */
916 frame = musb_readw(mbase, MUSB_FRAME);
917 ep = musb->endpoints;
918 for (epnum = 1; (epnum < musb->nr_endpoints)
919 && (musb->epmask >= (1 << epnum));
920 epnum++, ep++) {
921 /*
922 * FIXME handle framecounter wraps (12 bits)
923 * eliminate duplicated StartUrb logic
924 */
925 if (ep->dwWaitFrame >= frame) {
926 ep->dwWaitFrame = 0;
927 pr_debug("SOF --> periodic TX%s on %d\n",
928 ep->tx_channel ? " DMA" : "",
929 epnum);
930 if (!ep->tx_channel)
931 musb_h_tx_start(musb, epnum);
932 else
933 cppi_hostdma_start(musb, epnum);
934 }
935 } /* end of for loop */
936 }
937 #endif
938
939 schedule_work(&musb->irq_work);
940
941 return handled;
942 }
943
944 /*-------------------------------------------------------------------------*/
945
946 /*
947 * Program the HDRC to start (enable interrupts, dma, etc.).
948 */
949 void musb_start(struct musb *musb)
950 {
951 void __iomem *regs = musb->mregs;
952 u8 devctl = musb_readb(regs, MUSB_DEVCTL);
953
954 DBG(2, "<== devctl %02x\n", devctl);
955
956 /* Set INT enable registers, enable interrupts */
957 musb_writew(regs, MUSB_INTRTXE, musb->epmask);
958 musb_writew(regs, MUSB_INTRRXE, musb->epmask & 0xfffe);
959 musb_writeb(regs, MUSB_INTRUSBE, 0xf7);
960
961 musb_writeb(regs, MUSB_TESTMODE, 0);
962
963 /* put into basic highspeed mode and start session */
964 musb_writeb(regs, MUSB_POWER, MUSB_POWER_ISOUPDATE
965 | MUSB_POWER_SOFTCONN
966 | MUSB_POWER_HSENAB
967 /* ENSUSPEND wedges tusb */
968 /* | MUSB_POWER_ENSUSPEND */
969 );
970
971 musb->is_active = 0;
972 devctl = musb_readb(regs, MUSB_DEVCTL);
973 devctl &= ~MUSB_DEVCTL_SESSION;
974
975 if (is_otg_enabled(musb)) {
976 /* session started after:
977 * (a) ID-grounded irq, host mode;
978 * (b) vbus present/connect IRQ, peripheral mode;
979 * (c) peripheral initiates, using SRP
980 */
981 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
982 musb->is_active = 1;
983 else
984 devctl |= MUSB_DEVCTL_SESSION;
985
986 } else if (is_host_enabled(musb)) {
987 /* assume ID pin is hard-wired to ground */
988 devctl |= MUSB_DEVCTL_SESSION;
989
990 } else /* peripheral is enabled */ {
991 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
992 musb->is_active = 1;
993 }
994 musb_platform_enable(musb);
995 musb_writeb(regs, MUSB_DEVCTL, devctl);
996 }
997
998
999 static void musb_generic_disable(struct musb *musb)
1000 {
1001 void __iomem *mbase = musb->mregs;
1002 u16 temp;
1003
1004 /* disable interrupts */
1005 musb_writeb(mbase, MUSB_INTRUSBE, 0);
1006 musb_writew(mbase, MUSB_INTRTXE, 0);
1007 musb_writew(mbase, MUSB_INTRRXE, 0);
1008
1009 /* off */
1010 musb_writeb(mbase, MUSB_DEVCTL, 0);
1011
1012 /* flush pending interrupts */
1013 temp = musb_readb(mbase, MUSB_INTRUSB);
1014 temp = musb_readw(mbase, MUSB_INTRTX);
1015 temp = musb_readw(mbase, MUSB_INTRRX);
1016
1017 }
1018
1019 /*
1020 * Make the HDRC stop (disable interrupts, etc.);
1021 * reversible by musb_start
1022 * called on gadget driver unregister
1023 * with controller locked, irqs blocked
1024 * acts as a NOP unless some role activated the hardware
1025 */
1026 void musb_stop(struct musb *musb)
1027 {
1028 /* stop IRQs, timers, ... */
1029 musb_platform_disable(musb);
1030 musb_generic_disable(musb);
1031 DBG(3, "HDRC disabled\n");
1032
1033 /* FIXME
1034 * - mark host and/or peripheral drivers unusable/inactive
1035 * - disable DMA (and enable it in HdrcStart)
1036 * - make sure we can musb_start() after musb_stop(); with
1037 * OTG mode, gadget driver module rmmod/modprobe cycles that
1038 * - ...
1039 */
1040 musb_platform_try_idle(musb, 0);
1041 }
1042
1043 static void musb_shutdown(struct platform_device *pdev)
1044 {
1045 struct musb *musb = dev_to_musb(&pdev->dev);
1046 unsigned long flags;
1047
1048 spin_lock_irqsave(&musb->lock, flags);
1049 musb_platform_disable(musb);
1050 musb_generic_disable(musb);
1051 spin_unlock_irqrestore(&musb->lock, flags);
1052
1053 /* FIXME power down */
1054 }
1055
1056
1057 /*-------------------------------------------------------------------------*/
1058
1059 /*
1060 * The silicon either has hard-wired endpoint configurations, or else
1061 * "dynamic fifo" sizing. The driver has support for both, though at this
1062 * writing only the dynamic sizing is very well tested. Since we switched
1063 * away from compile-time hardware parameters, we can no longer rely on
1064 * dead code elimination to leave only the relevant one in the object file.
1065 *
1066 * We don't currently use dynamic fifo setup capability to do anything
1067 * more than selecting one of a bunch of predefined configurations.
1068 */
1069 #if defined(CONFIG_USB_MUSB_TUSB6010) || defined(CONFIG_USB_MUSB_OMAP2PLUS) \
1070 || defined(CONFIG_USB_MUSB_AM35X)
1071 static ushort __initdata fifo_mode = 4;
1072 #else
1073 static ushort __initdata fifo_mode = 2;
1074 #endif
1075
1076 /* "modprobe ... fifo_mode=1" etc */
1077 module_param(fifo_mode, ushort, 0);
1078 MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration");
1079
1080 /*
1081 * tables defining fifo_mode values. define more if you like.
1082 * for host side, make sure both halves of ep1 are set up.
1083 */
1084
1085 /* mode 0 - fits in 2KB */
1086 static struct musb_fifo_cfg __initdata mode_0_cfg[] = {
1087 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1088 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1089 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, },
1090 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1091 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1092 };
1093
1094 /* mode 1 - fits in 4KB */
1095 static struct musb_fifo_cfg __initdata mode_1_cfg[] = {
1096 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1097 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1098 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1099 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1100 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1101 };
1102
1103 /* mode 2 - fits in 4KB */
1104 static struct musb_fifo_cfg __initdata mode_2_cfg[] = {
1105 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1106 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1107 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1108 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1109 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1110 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1111 };
1112
1113 /* mode 3 - fits in 4KB */
1114 static struct musb_fifo_cfg __initdata mode_3_cfg[] = {
1115 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1116 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1117 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1118 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1119 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1120 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1121 };
1122
1123 /* mode 4 - fits in 16KB */
1124 static struct musb_fifo_cfg __initdata mode_4_cfg[] = {
1125 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1126 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1127 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1128 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1129 { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1130 { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1131 { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1132 { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1133 { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1134 { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1135 { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, },
1136 { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, },
1137 { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, },
1138 { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, },
1139 { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 512, },
1140 { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 512, },
1141 { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 512, },
1142 { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 512, },
1143 { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 256, },
1144 { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 64, },
1145 { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 256, },
1146 { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 64, },
1147 { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 256, },
1148 { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 64, },
1149 { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 4096, },
1150 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1151 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1152 };
1153
1154 /* mode 5 - fits in 8KB */
1155 static struct musb_fifo_cfg __initdata mode_5_cfg[] = {
1156 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1157 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1158 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1159 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1160 { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1161 { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1162 { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1163 { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1164 { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1165 { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1166 { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 32, },
1167 { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 32, },
1168 { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 32, },
1169 { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 32, },
1170 { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 32, },
1171 { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 32, },
1172 { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 32, },
1173 { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 32, },
1174 { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 32, },
1175 { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 32, },
1176 { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 32, },
1177 { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 32, },
1178 { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 32, },
1179 { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 32, },
1180 { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 512, },
1181 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1182 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1183 };
1184
1185 /*
1186 * configure a fifo; for non-shared endpoints, this may be called
1187 * once for a tx fifo and once for an rx fifo.
1188 *
1189 * returns negative errno or offset for next fifo.
1190 */
1191 static int __init
1192 fifo_setup(struct musb *musb, struct musb_hw_ep *hw_ep,
1193 const struct musb_fifo_cfg *cfg, u16 offset)
1194 {
1195 void __iomem *mbase = musb->mregs;
1196 int size = 0;
1197 u16 maxpacket = cfg->maxpacket;
1198 u16 c_off = offset >> 3;
1199 u8 c_size;
1200
1201 /* expect hw_ep has already been zero-initialized */
1202
1203 size = ffs(max(maxpacket, (u16) 8)) - 1;
1204 maxpacket = 1 << size;
1205
1206 c_size = size - 3;
1207 if (cfg->mode == BUF_DOUBLE) {
1208 if ((offset + (maxpacket << 1)) >
1209 (1 << (musb->config->ram_bits + 2)))
1210 return -EMSGSIZE;
1211 c_size |= MUSB_FIFOSZ_DPB;
1212 } else {
1213 if ((offset + maxpacket) > (1 << (musb->config->ram_bits + 2)))
1214 return -EMSGSIZE;
1215 }
1216
1217 /* configure the FIFO */
1218 musb_writeb(mbase, MUSB_INDEX, hw_ep->epnum);
1219
1220 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1221 /* EP0 reserved endpoint for control, bidirectional;
1222 * EP1 reserved for bulk, two unidirection halves.
1223 */
1224 if (hw_ep->epnum == 1)
1225 musb->bulk_ep = hw_ep;
1226 /* REVISIT error check: be sure ep0 can both rx and tx ... */
1227 #endif
1228 switch (cfg->style) {
1229 case FIFO_TX:
1230 musb_write_txfifosz(mbase, c_size);
1231 musb_write_txfifoadd(mbase, c_off);
1232 hw_ep->tx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1233 hw_ep->max_packet_sz_tx = maxpacket;
1234 break;
1235 case FIFO_RX:
1236 musb_write_rxfifosz(mbase, c_size);
1237 musb_write_rxfifoadd(mbase, c_off);
1238 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1239 hw_ep->max_packet_sz_rx = maxpacket;
1240 break;
1241 case FIFO_RXTX:
1242 musb_write_txfifosz(mbase, c_size);
1243 musb_write_txfifoadd(mbase, c_off);
1244 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1245 hw_ep->max_packet_sz_rx = maxpacket;
1246
1247 musb_write_rxfifosz(mbase, c_size);
1248 musb_write_rxfifoadd(mbase, c_off);
1249 hw_ep->tx_double_buffered = hw_ep->rx_double_buffered;
1250 hw_ep->max_packet_sz_tx = maxpacket;
1251
1252 hw_ep->is_shared_fifo = true;
1253 break;
1254 }
1255
1256 /* NOTE rx and tx endpoint irqs aren't managed separately,
1257 * which happens to be ok
1258 */
1259 musb->epmask |= (1 << hw_ep->epnum);
1260
1261 return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0));
1262 }
1263
1264 static struct musb_fifo_cfg __initdata ep0_cfg = {
1265 .style = FIFO_RXTX, .maxpacket = 64,
1266 };
1267
1268 static int __init ep_config_from_table(struct musb *musb)
1269 {
1270 const struct musb_fifo_cfg *cfg;
1271 unsigned i, n;
1272 int offset;
1273 struct musb_hw_ep *hw_ep = musb->endpoints;
1274
1275 if (musb->config->fifo_cfg) {
1276 cfg = musb->config->fifo_cfg;
1277 n = musb->config->fifo_cfg_size;
1278 goto done;
1279 }
1280
1281 switch (fifo_mode) {
1282 default:
1283 fifo_mode = 0;
1284 /* FALLTHROUGH */
1285 case 0:
1286 cfg = mode_0_cfg;
1287 n = ARRAY_SIZE(mode_0_cfg);
1288 break;
1289 case 1:
1290 cfg = mode_1_cfg;
1291 n = ARRAY_SIZE(mode_1_cfg);
1292 break;
1293 case 2:
1294 cfg = mode_2_cfg;
1295 n = ARRAY_SIZE(mode_2_cfg);
1296 break;
1297 case 3:
1298 cfg = mode_3_cfg;
1299 n = ARRAY_SIZE(mode_3_cfg);
1300 break;
1301 case 4:
1302 cfg = mode_4_cfg;
1303 n = ARRAY_SIZE(mode_4_cfg);
1304 break;
1305 case 5:
1306 cfg = mode_5_cfg;
1307 n = ARRAY_SIZE(mode_5_cfg);
1308 break;
1309 }
1310
1311 printk(KERN_DEBUG "%s: setup fifo_mode %d\n",
1312 musb_driver_name, fifo_mode);
1313
1314
1315 done:
1316 offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0);
1317 /* assert(offset > 0) */
1318
1319 /* NOTE: for RTL versions >= 1.400 EPINFO and RAMINFO would
1320 * be better than static musb->config->num_eps and DYN_FIFO_SIZE...
1321 */
1322
1323 for (i = 0; i < n; i++) {
1324 u8 epn = cfg->hw_ep_num;
1325
1326 if (epn >= musb->config->num_eps) {
1327 pr_debug("%s: invalid ep %d\n",
1328 musb_driver_name, epn);
1329 return -EINVAL;
1330 }
1331 offset = fifo_setup(musb, hw_ep + epn, cfg++, offset);
1332 if (offset < 0) {
1333 pr_debug("%s: mem overrun, ep %d\n",
1334 musb_driver_name, epn);
1335 return -EINVAL;
1336 }
1337 epn++;
1338 musb->nr_endpoints = max(epn, musb->nr_endpoints);
1339 }
1340
1341 printk(KERN_DEBUG "%s: %d/%d max ep, %d/%d memory\n",
1342 musb_driver_name,
1343 n + 1, musb->config->num_eps * 2 - 1,
1344 offset, (1 << (musb->config->ram_bits + 2)));
1345
1346 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1347 if (!musb->bulk_ep) {
1348 pr_debug("%s: missing bulk\n", musb_driver_name);
1349 return -EINVAL;
1350 }
1351 #endif
1352
1353 return 0;
1354 }
1355
1356
1357 /*
1358 * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false
1359 * @param musb the controller
1360 */
1361 static int __init ep_config_from_hw(struct musb *musb)
1362 {
1363 u8 epnum = 0;
1364 struct musb_hw_ep *hw_ep;
1365 void *mbase = musb->mregs;
1366 int ret = 0;
1367
1368 DBG(2, "<== static silicon ep config\n");
1369
1370 /* FIXME pick up ep0 maxpacket size */
1371
1372 for (epnum = 1; epnum < musb->config->num_eps; epnum++) {
1373 musb_ep_select(mbase, epnum);
1374 hw_ep = musb->endpoints + epnum;
1375
1376 ret = musb_read_fifosize(musb, hw_ep, epnum);
1377 if (ret < 0)
1378 break;
1379
1380 /* FIXME set up hw_ep->{rx,tx}_double_buffered */
1381
1382 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1383 /* pick an RX/TX endpoint for bulk */
1384 if (hw_ep->max_packet_sz_tx < 512
1385 || hw_ep->max_packet_sz_rx < 512)
1386 continue;
1387
1388 /* REVISIT: this algorithm is lazy, we should at least
1389 * try to pick a double buffered endpoint.
1390 */
1391 if (musb->bulk_ep)
1392 continue;
1393 musb->bulk_ep = hw_ep;
1394 #endif
1395 }
1396
1397 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1398 if (!musb->bulk_ep) {
1399 pr_debug("%s: missing bulk\n", musb_driver_name);
1400 return -EINVAL;
1401 }
1402 #endif
1403
1404 return 0;
1405 }
1406
1407 enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, };
1408
1409 /* Initialize MUSB (M)HDRC part of the USB hardware subsystem;
1410 * configure endpoints, or take their config from silicon
1411 */
1412 static int __init musb_core_init(u16 musb_type, struct musb *musb)
1413 {
1414 u8 reg;
1415 char *type;
1416 char aInfo[90], aRevision[32], aDate[12];
1417 void __iomem *mbase = musb->mregs;
1418 int status = 0;
1419 int i;
1420
1421 /* log core options (read using indexed model) */
1422 reg = musb_read_configdata(mbase);
1423
1424 strcpy(aInfo, (reg & MUSB_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8");
1425 if (reg & MUSB_CONFIGDATA_DYNFIFO) {
1426 strcat(aInfo, ", dyn FIFOs");
1427 musb->dyn_fifo = true;
1428 }
1429 if (reg & MUSB_CONFIGDATA_MPRXE) {
1430 strcat(aInfo, ", bulk combine");
1431 musb->bulk_combine = true;
1432 }
1433 if (reg & MUSB_CONFIGDATA_MPTXE) {
1434 strcat(aInfo, ", bulk split");
1435 musb->bulk_split = true;
1436 }
1437 if (reg & MUSB_CONFIGDATA_HBRXE) {
1438 strcat(aInfo, ", HB-ISO Rx");
1439 musb->hb_iso_rx = true;
1440 }
1441 if (reg & MUSB_CONFIGDATA_HBTXE) {
1442 strcat(aInfo, ", HB-ISO Tx");
1443 musb->hb_iso_tx = true;
1444 }
1445 if (reg & MUSB_CONFIGDATA_SOFTCONE)
1446 strcat(aInfo, ", SoftConn");
1447
1448 printk(KERN_DEBUG "%s: ConfigData=0x%02x (%s)\n",
1449 musb_driver_name, reg, aInfo);
1450
1451 aDate[0] = 0;
1452 if (MUSB_CONTROLLER_MHDRC == musb_type) {
1453 musb->is_multipoint = 1;
1454 type = "M";
1455 } else {
1456 musb->is_multipoint = 0;
1457 type = "";
1458 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1459 #ifndef CONFIG_USB_OTG_BLACKLIST_HUB
1460 printk(KERN_ERR
1461 "%s: kernel must blacklist external hubs\n",
1462 musb_driver_name);
1463 #endif
1464 #endif
1465 }
1466
1467 /* log release info */
1468 musb->hwvers = musb_read_hwvers(mbase);
1469 snprintf(aRevision, 32, "%d.%d%s", MUSB_HWVERS_MAJOR(musb->hwvers),
1470 MUSB_HWVERS_MINOR(musb->hwvers),
1471 (musb->hwvers & MUSB_HWVERS_RC) ? "RC" : "");
1472 printk(KERN_DEBUG "%s: %sHDRC RTL version %s %s\n",
1473 musb_driver_name, type, aRevision, aDate);
1474
1475 /* configure ep0 */
1476 musb_configure_ep0(musb);
1477
1478 /* discover endpoint configuration */
1479 musb->nr_endpoints = 1;
1480 musb->epmask = 1;
1481
1482 if (musb->dyn_fifo)
1483 status = ep_config_from_table(musb);
1484 else
1485 status = ep_config_from_hw(musb);
1486
1487 if (status < 0)
1488 return status;
1489
1490 /* finish init, and print endpoint config */
1491 for (i = 0; i < musb->nr_endpoints; i++) {
1492 struct musb_hw_ep *hw_ep = musb->endpoints + i;
1493
1494 hw_ep->fifo = MUSB_FIFO_OFFSET(i) + mbase;
1495 #ifdef CONFIG_USB_MUSB_TUSB6010
1496 hw_ep->fifo_async = musb->async + 0x400 + MUSB_FIFO_OFFSET(i);
1497 hw_ep->fifo_sync = musb->sync + 0x400 + MUSB_FIFO_OFFSET(i);
1498 hw_ep->fifo_sync_va =
1499 musb->sync_va + 0x400 + MUSB_FIFO_OFFSET(i);
1500
1501 if (i == 0)
1502 hw_ep->conf = mbase - 0x400 + TUSB_EP0_CONF;
1503 else
1504 hw_ep->conf = mbase + 0x400 + (((i - 1) & 0xf) << 2);
1505 #endif
1506
1507 hw_ep->regs = MUSB_EP_OFFSET(i, 0) + mbase;
1508 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1509 hw_ep->target_regs = musb_read_target_reg_base(i, mbase);
1510 hw_ep->rx_reinit = 1;
1511 hw_ep->tx_reinit = 1;
1512 #endif
1513
1514 if (hw_ep->max_packet_sz_tx) {
1515 DBG(1,
1516 "%s: hw_ep %d%s, %smax %d\n",
1517 musb_driver_name, i,
1518 hw_ep->is_shared_fifo ? "shared" : "tx",
1519 hw_ep->tx_double_buffered
1520 ? "doublebuffer, " : "",
1521 hw_ep->max_packet_sz_tx);
1522 }
1523 if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) {
1524 DBG(1,
1525 "%s: hw_ep %d%s, %smax %d\n",
1526 musb_driver_name, i,
1527 "rx",
1528 hw_ep->rx_double_buffered
1529 ? "doublebuffer, " : "",
1530 hw_ep->max_packet_sz_rx);
1531 }
1532 if (!(hw_ep->max_packet_sz_tx || hw_ep->max_packet_sz_rx))
1533 DBG(1, "hw_ep %d not configured\n", i);
1534 }
1535
1536 return 0;
1537 }
1538
1539 /*-------------------------------------------------------------------------*/
1540
1541 #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3430) || \
1542 defined(CONFIG_ARCH_OMAP4)
1543
1544 static irqreturn_t generic_interrupt(int irq, void *__hci)
1545 {
1546 unsigned long flags;
1547 irqreturn_t retval = IRQ_NONE;
1548 struct musb *musb = __hci;
1549
1550 spin_lock_irqsave(&musb->lock, flags);
1551
1552 musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB);
1553 musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX);
1554 musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX);
1555
1556 if (musb->int_usb || musb->int_tx || musb->int_rx)
1557 retval = musb_interrupt(musb);
1558
1559 spin_unlock_irqrestore(&musb->lock, flags);
1560
1561 return retval;
1562 }
1563
1564 #else
1565 #define generic_interrupt NULL
1566 #endif
1567
1568 /*
1569 * handle all the irqs defined by the HDRC core. for now we expect: other
1570 * irq sources (phy, dma, etc) will be handled first, musb->int_* values
1571 * will be assigned, and the irq will already have been acked.
1572 *
1573 * called in irq context with spinlock held, irqs blocked
1574 */
1575 irqreturn_t musb_interrupt(struct musb *musb)
1576 {
1577 irqreturn_t retval = IRQ_NONE;
1578 u8 devctl, power;
1579 int ep_num;
1580 u32 reg;
1581
1582 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1583 power = musb_readb(musb->mregs, MUSB_POWER);
1584
1585 DBG(4, "** IRQ %s usb%04x tx%04x rx%04x\n",
1586 (devctl & MUSB_DEVCTL_HM) ? "host" : "peripheral",
1587 musb->int_usb, musb->int_tx, musb->int_rx);
1588
1589 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
1590 if (is_otg_enabled(musb) || is_peripheral_enabled(musb))
1591 if (!musb->gadget_driver) {
1592 DBG(5, "No gadget driver loaded\n");
1593 return IRQ_HANDLED;
1594 }
1595 #endif
1596
1597 /* the core can interrupt us for multiple reasons; docs have
1598 * a generic interrupt flowchart to follow
1599 */
1600 if (musb->int_usb)
1601 retval |= musb_stage0_irq(musb, musb->int_usb,
1602 devctl, power);
1603
1604 /* "stage 1" is handling endpoint irqs */
1605
1606 /* handle endpoint 0 first */
1607 if (musb->int_tx & 1) {
1608 if (devctl & MUSB_DEVCTL_HM)
1609 retval |= musb_h_ep0_irq(musb);
1610 else
1611 retval |= musb_g_ep0_irq(musb);
1612 }
1613
1614 /* RX on endpoints 1-15 */
1615 reg = musb->int_rx >> 1;
1616 ep_num = 1;
1617 while (reg) {
1618 if (reg & 1) {
1619 /* musb_ep_select(musb->mregs, ep_num); */
1620 /* REVISIT just retval = ep->rx_irq(...) */
1621 retval = IRQ_HANDLED;
1622 if (devctl & MUSB_DEVCTL_HM) {
1623 if (is_host_capable())
1624 musb_host_rx(musb, ep_num);
1625 } else {
1626 if (is_peripheral_capable())
1627 musb_g_rx(musb, ep_num);
1628 }
1629 }
1630
1631 reg >>= 1;
1632 ep_num++;
1633 }
1634
1635 /* TX on endpoints 1-15 */
1636 reg = musb->int_tx >> 1;
1637 ep_num = 1;
1638 while (reg) {
1639 if (reg & 1) {
1640 /* musb_ep_select(musb->mregs, ep_num); */
1641 /* REVISIT just retval |= ep->tx_irq(...) */
1642 retval = IRQ_HANDLED;
1643 if (devctl & MUSB_DEVCTL_HM) {
1644 if (is_host_capable())
1645 musb_host_tx(musb, ep_num);
1646 } else {
1647 if (is_peripheral_capable())
1648 musb_g_tx(musb, ep_num);
1649 }
1650 }
1651 reg >>= 1;
1652 ep_num++;
1653 }
1654
1655 return retval;
1656 }
1657
1658
1659 #ifndef CONFIG_MUSB_PIO_ONLY
1660 static int __initdata use_dma = 1;
1661
1662 /* "modprobe ... use_dma=0" etc */
1663 module_param(use_dma, bool, 0);
1664 MODULE_PARM_DESC(use_dma, "enable/disable use of DMA");
1665
1666 void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit)
1667 {
1668 u8 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1669
1670 /* called with controller lock already held */
1671
1672 if (!epnum) {
1673 #ifndef CONFIG_USB_TUSB_OMAP_DMA
1674 if (!is_cppi_enabled()) {
1675 /* endpoint 0 */
1676 if (devctl & MUSB_DEVCTL_HM)
1677 musb_h_ep0_irq(musb);
1678 else
1679 musb_g_ep0_irq(musb);
1680 }
1681 #endif
1682 } else {
1683 /* endpoints 1..15 */
1684 if (transmit) {
1685 if (devctl & MUSB_DEVCTL_HM) {
1686 if (is_host_capable())
1687 musb_host_tx(musb, epnum);
1688 } else {
1689 if (is_peripheral_capable())
1690 musb_g_tx(musb, epnum);
1691 }
1692 } else {
1693 /* receive */
1694 if (devctl & MUSB_DEVCTL_HM) {
1695 if (is_host_capable())
1696 musb_host_rx(musb, epnum);
1697 } else {
1698 if (is_peripheral_capable())
1699 musb_g_rx(musb, epnum);
1700 }
1701 }
1702 }
1703 }
1704
1705 #else
1706 #define use_dma 0
1707 #endif
1708
1709 /*-------------------------------------------------------------------------*/
1710
1711 #ifdef CONFIG_SYSFS
1712
1713 static ssize_t
1714 musb_mode_show(struct device *dev, struct device_attribute *attr, char *buf)
1715 {
1716 struct musb *musb = dev_to_musb(dev);
1717 unsigned long flags;
1718 int ret = -EINVAL;
1719
1720 spin_lock_irqsave(&musb->lock, flags);
1721 ret = sprintf(buf, "%s\n", otg_state_string(musb));
1722 spin_unlock_irqrestore(&musb->lock, flags);
1723
1724 return ret;
1725 }
1726
1727 static ssize_t
1728 musb_mode_store(struct device *dev, struct device_attribute *attr,
1729 const char *buf, size_t n)
1730 {
1731 struct musb *musb = dev_to_musb(dev);
1732 unsigned long flags;
1733 int status;
1734
1735 spin_lock_irqsave(&musb->lock, flags);
1736 if (sysfs_streq(buf, "host"))
1737 status = musb_platform_set_mode(musb, MUSB_HOST);
1738 else if (sysfs_streq(buf, "peripheral"))
1739 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL);
1740 else if (sysfs_streq(buf, "otg"))
1741 status = musb_platform_set_mode(musb, MUSB_OTG);
1742 else
1743 status = -EINVAL;
1744 spin_unlock_irqrestore(&musb->lock, flags);
1745
1746 return (status == 0) ? n : status;
1747 }
1748 static DEVICE_ATTR(mode, 0644, musb_mode_show, musb_mode_store);
1749
1750 static ssize_t
1751 musb_vbus_store(struct device *dev, struct device_attribute *attr,
1752 const char *buf, size_t n)
1753 {
1754 struct musb *musb = dev_to_musb(dev);
1755 unsigned long flags;
1756 unsigned long val;
1757
1758 if (sscanf(buf, "%lu", &val) < 1) {
1759 dev_err(dev, "Invalid VBUS timeout ms value\n");
1760 return -EINVAL;
1761 }
1762
1763 spin_lock_irqsave(&musb->lock, flags);
1764 /* force T(a_wait_bcon) to be zero/unlimited *OR* valid */
1765 musb->a_wait_bcon = val ? max_t(int, val, OTG_TIME_A_WAIT_BCON) : 0 ;
1766 if (musb->xceiv->state == OTG_STATE_A_WAIT_BCON)
1767 musb->is_active = 0;
1768 musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val));
1769 spin_unlock_irqrestore(&musb->lock, flags);
1770
1771 return n;
1772 }
1773
1774 static ssize_t
1775 musb_vbus_show(struct device *dev, struct device_attribute *attr, char *buf)
1776 {
1777 struct musb *musb = dev_to_musb(dev);
1778 unsigned long flags;
1779 unsigned long val;
1780 int vbus;
1781
1782 spin_lock_irqsave(&musb->lock, flags);
1783 val = musb->a_wait_bcon;
1784 /* FIXME get_vbus_status() is normally #defined as false...
1785 * and is effectively TUSB-specific.
1786 */
1787 vbus = musb_platform_get_vbus_status(musb);
1788 spin_unlock_irqrestore(&musb->lock, flags);
1789
1790 return sprintf(buf, "Vbus %s, timeout %lu msec\n",
1791 vbus ? "on" : "off", val);
1792 }
1793 static DEVICE_ATTR(vbus, 0644, musb_vbus_show, musb_vbus_store);
1794
1795 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
1796
1797 /* Gadget drivers can't know that a host is connected so they might want
1798 * to start SRP, but users can. This allows userspace to trigger SRP.
1799 */
1800 static ssize_t
1801 musb_srp_store(struct device *dev, struct device_attribute *attr,
1802 const char *buf, size_t n)
1803 {
1804 struct musb *musb = dev_to_musb(dev);
1805 unsigned short srp;
1806
1807 if (sscanf(buf, "%hu", &srp) != 1
1808 || (srp != 1)) {
1809 dev_err(dev, "SRP: Value must be 1\n");
1810 return -EINVAL;
1811 }
1812
1813 if (srp == 1)
1814 musb_g_wakeup(musb);
1815
1816 return n;
1817 }
1818 static DEVICE_ATTR(srp, 0644, NULL, musb_srp_store);
1819
1820 #endif /* CONFIG_USB_GADGET_MUSB_HDRC */
1821
1822 static struct attribute *musb_attributes[] = {
1823 &dev_attr_mode.attr,
1824 &dev_attr_vbus.attr,
1825 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
1826 &dev_attr_srp.attr,
1827 #endif
1828 NULL
1829 };
1830
1831 static const struct attribute_group musb_attr_group = {
1832 .attrs = musb_attributes,
1833 };
1834
1835 #endif /* sysfs */
1836
1837 /* Only used to provide driver mode change events */
1838 static void musb_irq_work(struct work_struct *data)
1839 {
1840 struct musb *musb = container_of(data, struct musb, irq_work);
1841 static int old_state;
1842
1843 if (musb->xceiv->state != old_state) {
1844 old_state = musb->xceiv->state;
1845 sysfs_notify(&musb->controller->kobj, NULL, "mode");
1846 }
1847 }
1848
1849 /* --------------------------------------------------------------------------
1850 * Init support
1851 */
1852
1853 static struct musb *__init
1854 allocate_instance(struct device *dev,
1855 struct musb_hdrc_config *config, void __iomem *mbase)
1856 {
1857 struct musb *musb;
1858 struct musb_hw_ep *ep;
1859 int epnum;
1860 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1861 struct usb_hcd *hcd;
1862
1863 hcd = usb_create_hcd(&musb_hc_driver, dev, dev_name(dev));
1864 if (!hcd)
1865 return NULL;
1866 /* usbcore sets dev->driver_data to hcd, and sometimes uses that... */
1867
1868 musb = hcd_to_musb(hcd);
1869 INIT_LIST_HEAD(&musb->control);
1870 INIT_LIST_HEAD(&musb->in_bulk);
1871 INIT_LIST_HEAD(&musb->out_bulk);
1872
1873 hcd->uses_new_polling = 1;
1874
1875 musb->vbuserr_retry = VBUSERR_RETRY_COUNT;
1876 musb->a_wait_bcon = OTG_TIME_A_WAIT_BCON;
1877 #else
1878 musb = kzalloc(sizeof *musb, GFP_KERNEL);
1879 if (!musb)
1880 return NULL;
1881 dev_set_drvdata(dev, musb);
1882
1883 #endif
1884
1885 musb->mregs = mbase;
1886 musb->ctrl_base = mbase;
1887 musb->nIrq = -ENODEV;
1888 musb->config = config;
1889 BUG_ON(musb->config->num_eps > MUSB_C_NUM_EPS);
1890 for (epnum = 0, ep = musb->endpoints;
1891 epnum < musb->config->num_eps;
1892 epnum++, ep++) {
1893 ep->musb = musb;
1894 ep->epnum = epnum;
1895 }
1896
1897 musb->controller = dev;
1898
1899 return musb;
1900 }
1901
1902 static void musb_free(struct musb *musb)
1903 {
1904 /* this has multiple entry modes. it handles fault cleanup after
1905 * probe(), where things may be partially set up, as well as rmmod
1906 * cleanup after everything's been de-activated.
1907 */
1908
1909 #ifdef CONFIG_SYSFS
1910 sysfs_remove_group(&musb->controller->kobj, &musb_attr_group);
1911 #endif
1912
1913 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
1914 musb_gadget_cleanup(musb);
1915 #endif
1916
1917 if (musb->nIrq >= 0) {
1918 if (musb->irq_wake)
1919 disable_irq_wake(musb->nIrq);
1920 free_irq(musb->nIrq, musb);
1921 }
1922 if (is_dma_capable() && musb->dma_controller) {
1923 struct dma_controller *c = musb->dma_controller;
1924
1925 (void) c->stop(c);
1926 dma_controller_destroy(c);
1927 }
1928
1929 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1930 usb_put_hcd(musb_to_hcd(musb));
1931 #else
1932 kfree(musb);
1933 #endif
1934 }
1935
1936 /*
1937 * Perform generic per-controller initialization.
1938 *
1939 * @pDevice: the controller (already clocked, etc)
1940 * @nIrq: irq
1941 * @mregs: virtual address of controller registers,
1942 * not yet corrected for platform-specific offsets
1943 */
1944 static int __init
1945 musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl)
1946 {
1947 int status;
1948 struct musb *musb;
1949 struct musb_hdrc_platform_data *plat = dev->platform_data;
1950
1951 /* The driver might handle more features than the board; OK.
1952 * Fail when the board needs a feature that's not enabled.
1953 */
1954 if (!plat) {
1955 dev_dbg(dev, "no platform_data?\n");
1956 status = -ENODEV;
1957 goto fail0;
1958 }
1959
1960 switch (plat->mode) {
1961 case MUSB_HOST:
1962 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1963 break;
1964 #else
1965 goto bad_config;
1966 #endif
1967 case MUSB_PERIPHERAL:
1968 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
1969 break;
1970 #else
1971 goto bad_config;
1972 #endif
1973 case MUSB_OTG:
1974 #ifdef CONFIG_USB_MUSB_OTG
1975 break;
1976 #else
1977 bad_config:
1978 #endif
1979 default:
1980 dev_err(dev, "incompatible Kconfig role setting\n");
1981 status = -EINVAL;
1982 goto fail0;
1983 }
1984
1985 /* allocate */
1986 musb = allocate_instance(dev, plat->config, ctrl);
1987 if (!musb) {
1988 status = -ENOMEM;
1989 goto fail0;
1990 }
1991
1992 spin_lock_init(&musb->lock);
1993 musb->board_mode = plat->mode;
1994 musb->board_set_power = plat->set_power;
1995 musb->min_power = plat->min_power;
1996 musb->ops = plat->platform_ops;
1997
1998 /* The musb_platform_init() call:
1999 * - adjusts musb->mregs and musb->isr if needed,
2000 * - may initialize an integrated tranceiver
2001 * - initializes musb->xceiv, usually by otg_get_transceiver()
2002 * - stops powering VBUS
2003 *
2004 * There are various transciever configurations. Blackfin,
2005 * DaVinci, TUSB60x0, and others integrate them. OMAP3 uses
2006 * external/discrete ones in various flavors (twl4030 family,
2007 * isp1504, non-OTG, etc) mostly hooking up through ULPI.
2008 */
2009 musb->isr = generic_interrupt;
2010 status = musb_platform_init(musb);
2011 if (status < 0)
2012 goto fail1;
2013
2014 if (!musb->isr) {
2015 status = -ENODEV;
2016 goto fail3;
2017 }
2018
2019 if (!musb->xceiv->io_ops) {
2020 musb->xceiv->io_priv = musb->mregs;
2021 musb->xceiv->io_ops = &musb_ulpi_access;
2022 }
2023
2024 #ifndef CONFIG_MUSB_PIO_ONLY
2025 if (use_dma && dev->dma_mask) {
2026 struct dma_controller *c;
2027
2028 c = dma_controller_create(musb, musb->mregs);
2029 musb->dma_controller = c;
2030 if (c)
2031 (void) c->start(c);
2032 }
2033 #endif
2034 /* ideally this would be abstracted in platform setup */
2035 if (!is_dma_capable() || !musb->dma_controller)
2036 dev->dma_mask = NULL;
2037
2038 /* be sure interrupts are disabled before connecting ISR */
2039 musb_platform_disable(musb);
2040 musb_generic_disable(musb);
2041
2042 /* setup musb parts of the core (especially endpoints) */
2043 status = musb_core_init(plat->config->multipoint
2044 ? MUSB_CONTROLLER_MHDRC
2045 : MUSB_CONTROLLER_HDRC, musb);
2046 if (status < 0)
2047 goto fail3;
2048
2049 #ifdef CONFIG_USB_MUSB_OTG
2050 setup_timer(&musb->otg_timer, musb_otg_timer_func, (unsigned long) musb);
2051 #endif
2052
2053 /* Init IRQ workqueue before request_irq */
2054 INIT_WORK(&musb->irq_work, musb_irq_work);
2055
2056 /* attach to the IRQ */
2057 if (request_irq(nIrq, musb->isr, 0, dev_name(dev), musb)) {
2058 dev_err(dev, "request_irq %d failed!\n", nIrq);
2059 status = -ENODEV;
2060 goto fail3;
2061 }
2062 musb->nIrq = nIrq;
2063 /* FIXME this handles wakeup irqs wrong */
2064 if (enable_irq_wake(nIrq) == 0) {
2065 musb->irq_wake = 1;
2066 device_init_wakeup(dev, 1);
2067 } else {
2068 musb->irq_wake = 0;
2069 }
2070
2071 /* host side needs more setup */
2072 if (is_host_enabled(musb)) {
2073 struct usb_hcd *hcd = musb_to_hcd(musb);
2074
2075 otg_set_host(musb->xceiv, &hcd->self);
2076
2077 if (is_otg_enabled(musb))
2078 hcd->self.otg_port = 1;
2079 musb->xceiv->host = &hcd->self;
2080 hcd->power_budget = 2 * (plat->power ? : 250);
2081
2082 /* program PHY to use external vBus if required */
2083 if (plat->extvbus) {
2084 u8 busctl = musb_read_ulpi_buscontrol(musb->mregs);
2085 busctl |= MUSB_ULPI_USE_EXTVBUS;
2086 musb_write_ulpi_buscontrol(musb->mregs, busctl);
2087 }
2088 }
2089
2090 /* For the host-only role, we can activate right away.
2091 * (We expect the ID pin to be forcibly grounded!!)
2092 * Otherwise, wait till the gadget driver hooks up.
2093 */
2094 if (!is_otg_enabled(musb) && is_host_enabled(musb)) {
2095 MUSB_HST_MODE(musb);
2096 musb->xceiv->default_a = 1;
2097 musb->xceiv->state = OTG_STATE_A_IDLE;
2098
2099 status = usb_add_hcd(musb_to_hcd(musb), -1, 0);
2100
2101 DBG(1, "%s mode, status %d, devctl %02x %c\n",
2102 "HOST", status,
2103 musb_readb(musb->mregs, MUSB_DEVCTL),
2104 (musb_readb(musb->mregs, MUSB_DEVCTL)
2105 & MUSB_DEVCTL_BDEVICE
2106 ? 'B' : 'A'));
2107
2108 } else /* peripheral is enabled */ {
2109 MUSB_DEV_MODE(musb);
2110 musb->xceiv->default_a = 0;
2111 musb->xceiv->state = OTG_STATE_B_IDLE;
2112
2113 status = musb_gadget_setup(musb);
2114
2115 DBG(1, "%s mode, status %d, dev%02x\n",
2116 is_otg_enabled(musb) ? "OTG" : "PERIPHERAL",
2117 status,
2118 musb_readb(musb->mregs, MUSB_DEVCTL));
2119
2120 }
2121 if (status < 0)
2122 goto fail3;
2123
2124 status = musb_init_debugfs(musb);
2125 if (status < 0)
2126 goto fail4;
2127
2128 #ifdef CONFIG_SYSFS
2129 status = sysfs_create_group(&musb->controller->kobj, &musb_attr_group);
2130 if (status)
2131 goto fail5;
2132 #endif
2133
2134 dev_info(dev, "USB %s mode controller at %p using %s, IRQ %d\n",
2135 ({char *s;
2136 switch (musb->board_mode) {
2137 case MUSB_HOST: s = "Host"; break;
2138 case MUSB_PERIPHERAL: s = "Peripheral"; break;
2139 default: s = "OTG"; break;
2140 }; s; }),
2141 ctrl,
2142 (is_dma_capable() && musb->dma_controller)
2143 ? "DMA" : "PIO",
2144 musb->nIrq);
2145
2146 return 0;
2147
2148 fail5:
2149 musb_exit_debugfs(musb);
2150
2151 fail4:
2152 if (!is_otg_enabled(musb) && is_host_enabled(musb))
2153 usb_remove_hcd(musb_to_hcd(musb));
2154 else
2155 musb_gadget_cleanup(musb);
2156
2157 fail3:
2158 if (musb->irq_wake)
2159 device_init_wakeup(dev, 0);
2160 musb_platform_exit(musb);
2161
2162 fail1:
2163 dev_err(musb->controller,
2164 "musb_init_controller failed with status %d\n", status);
2165
2166 musb_free(musb);
2167
2168 fail0:
2169
2170 return status;
2171
2172 }
2173
2174 /*-------------------------------------------------------------------------*/
2175
2176 /* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just
2177 * bridge to a platform device; this driver then suffices.
2178 */
2179
2180 #ifndef CONFIG_MUSB_PIO_ONLY
2181 static u64 *orig_dma_mask;
2182 #endif
2183
2184 static int __init musb_probe(struct platform_device *pdev)
2185 {
2186 struct device *dev = &pdev->dev;
2187 int irq = platform_get_irq_byname(pdev, "mc");
2188 int status;
2189 struct resource *iomem;
2190 void __iomem *base;
2191
2192 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2193 if (!iomem || irq == 0)
2194 return -ENODEV;
2195
2196 base = ioremap(iomem->start, resource_size(iomem));
2197 if (!base) {
2198 dev_err(dev, "ioremap failed\n");
2199 return -ENOMEM;
2200 }
2201
2202 #ifndef CONFIG_MUSB_PIO_ONLY
2203 /* clobbered by use_dma=n */
2204 orig_dma_mask = dev->dma_mask;
2205 #endif
2206 status = musb_init_controller(dev, irq, base);
2207 if (status < 0)
2208 iounmap(base);
2209
2210 return status;
2211 }
2212
2213 static int __exit musb_remove(struct platform_device *pdev)
2214 {
2215 struct musb *musb = dev_to_musb(&pdev->dev);
2216 void __iomem *ctrl_base = musb->ctrl_base;
2217
2218 /* this gets called on rmmod.
2219 * - Host mode: host may still be active
2220 * - Peripheral mode: peripheral is deactivated (or never-activated)
2221 * - OTG mode: both roles are deactivated (or never-activated)
2222 */
2223 musb_exit_debugfs(musb);
2224 musb_shutdown(pdev);
2225 #ifdef CONFIG_USB_MUSB_HDRC_HCD
2226 if (musb->board_mode == MUSB_HOST)
2227 usb_remove_hcd(musb_to_hcd(musb));
2228 #endif
2229 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
2230 musb_platform_exit(musb);
2231 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
2232
2233 musb_free(musb);
2234 iounmap(ctrl_base);
2235 device_init_wakeup(&pdev->dev, 0);
2236 #ifndef CONFIG_MUSB_PIO_ONLY
2237 pdev->dev.dma_mask = orig_dma_mask;
2238 #endif
2239 return 0;
2240 }
2241
2242 #ifdef CONFIG_PM
2243
2244 static void musb_save_context(struct musb *musb)
2245 {
2246 int i;
2247 void __iomem *musb_base = musb->mregs;
2248 void __iomem *epio;
2249
2250 if (is_host_enabled(musb)) {
2251 musb->context.frame = musb_readw(musb_base, MUSB_FRAME);
2252 musb->context.testmode = musb_readb(musb_base, MUSB_TESTMODE);
2253 musb->context.busctl = musb_read_ulpi_buscontrol(musb->mregs);
2254 }
2255 musb->context.power = musb_readb(musb_base, MUSB_POWER);
2256 musb->context.intrtxe = musb_readw(musb_base, MUSB_INTRTXE);
2257 musb->context.intrrxe = musb_readw(musb_base, MUSB_INTRRXE);
2258 musb->context.intrusbe = musb_readb(musb_base, MUSB_INTRUSBE);
2259 musb->context.index = musb_readb(musb_base, MUSB_INDEX);
2260 musb->context.devctl = musb_readb(musb_base, MUSB_DEVCTL);
2261
2262 for (i = 0; i < musb->config->num_eps; ++i) {
2263 epio = musb->endpoints[i].regs;
2264 musb->context.index_regs[i].txmaxp =
2265 musb_readw(epio, MUSB_TXMAXP);
2266 musb->context.index_regs[i].txcsr =
2267 musb_readw(epio, MUSB_TXCSR);
2268 musb->context.index_regs[i].rxmaxp =
2269 musb_readw(epio, MUSB_RXMAXP);
2270 musb->context.index_regs[i].rxcsr =
2271 musb_readw(epio, MUSB_RXCSR);
2272
2273 if (musb->dyn_fifo) {
2274 musb->context.index_regs[i].txfifoadd =
2275 musb_read_txfifoadd(musb_base);
2276 musb->context.index_regs[i].rxfifoadd =
2277 musb_read_rxfifoadd(musb_base);
2278 musb->context.index_regs[i].txfifosz =
2279 musb_read_txfifosz(musb_base);
2280 musb->context.index_regs[i].rxfifosz =
2281 musb_read_rxfifosz(musb_base);
2282 }
2283 if (is_host_enabled(musb)) {
2284 musb->context.index_regs[i].txtype =
2285 musb_readb(epio, MUSB_TXTYPE);
2286 musb->context.index_regs[i].txinterval =
2287 musb_readb(epio, MUSB_TXINTERVAL);
2288 musb->context.index_regs[i].rxtype =
2289 musb_readb(epio, MUSB_RXTYPE);
2290 musb->context.index_regs[i].rxinterval =
2291 musb_readb(epio, MUSB_RXINTERVAL);
2292
2293 musb->context.index_regs[i].txfunaddr =
2294 musb_read_txfunaddr(musb_base, i);
2295 musb->context.index_regs[i].txhubaddr =
2296 musb_read_txhubaddr(musb_base, i);
2297 musb->context.index_regs[i].txhubport =
2298 musb_read_txhubport(musb_base, i);
2299
2300 musb->context.index_regs[i].rxfunaddr =
2301 musb_read_rxfunaddr(musb_base, i);
2302 musb->context.index_regs[i].rxhubaddr =
2303 musb_read_rxhubaddr(musb_base, i);
2304 musb->context.index_regs[i].rxhubport =
2305 musb_read_rxhubport(musb_base, i);
2306 }
2307 }
2308 }
2309
2310 static void musb_restore_context(struct musb *musb)
2311 {
2312 int i;
2313 void __iomem *musb_base = musb->mregs;
2314 void __iomem *ep_target_regs;
2315 void __iomem *epio;
2316
2317 if (is_host_enabled(musb)) {
2318 musb_writew(musb_base, MUSB_FRAME, musb->context.frame);
2319 musb_writeb(musb_base, MUSB_TESTMODE, musb->context.testmode);
2320 musb_write_ulpi_buscontrol(musb->mregs, musb->context.busctl);
2321 }
2322 musb_writeb(musb_base, MUSB_POWER, musb->context.power);
2323 musb_writew(musb_base, MUSB_INTRTXE, musb->context.intrtxe);
2324 musb_writew(musb_base, MUSB_INTRRXE, musb->context.intrrxe);
2325 musb_writeb(musb_base, MUSB_INTRUSBE, musb->context.intrusbe);
2326 musb_writeb(musb_base, MUSB_DEVCTL, musb->context.devctl);
2327
2328 for (i = 0; i < musb->config->num_eps; ++i) {
2329 epio = musb->endpoints[i].regs;
2330 musb_writew(epio, MUSB_TXMAXP,
2331 musb->context.index_regs[i].txmaxp);
2332 musb_writew(epio, MUSB_TXCSR,
2333 musb->context.index_regs[i].txcsr);
2334 musb_writew(epio, MUSB_RXMAXP,
2335 musb->context.index_regs[i].rxmaxp);
2336 musb_writew(epio, MUSB_RXCSR,
2337 musb->context.index_regs[i].rxcsr);
2338
2339 if (musb->dyn_fifo) {
2340 musb_write_txfifosz(musb_base,
2341 musb->context.index_regs[i].txfifosz);
2342 musb_write_rxfifosz(musb_base,
2343 musb->context.index_regs[i].rxfifosz);
2344 musb_write_txfifoadd(musb_base,
2345 musb->context.index_regs[i].txfifoadd);
2346 musb_write_rxfifoadd(musb_base,
2347 musb->context.index_regs[i].rxfifoadd);
2348 }
2349
2350 if (is_host_enabled(musb)) {
2351 musb_writeb(epio, MUSB_TXTYPE,
2352 musb->context.index_regs[i].txtype);
2353 musb_writeb(epio, MUSB_TXINTERVAL,
2354 musb->context.index_regs[i].txinterval);
2355 musb_writeb(epio, MUSB_RXTYPE,
2356 musb->context.index_regs[i].rxtype);
2357 musb_writeb(epio, MUSB_RXINTERVAL,
2358
2359 musb->context.index_regs[i].rxinterval);
2360 musb_write_txfunaddr(musb_base, i,
2361 musb->context.index_regs[i].txfunaddr);
2362 musb_write_txhubaddr(musb_base, i,
2363 musb->context.index_regs[i].txhubaddr);
2364 musb_write_txhubport(musb_base, i,
2365 musb->context.index_regs[i].txhubport);
2366
2367 ep_target_regs =
2368 musb_read_target_reg_base(i, musb_base);
2369
2370 musb_write_rxfunaddr(ep_target_regs,
2371 musb->context.index_regs[i].rxfunaddr);
2372 musb_write_rxhubaddr(ep_target_regs,
2373 musb->context.index_regs[i].rxhubaddr);
2374 musb_write_rxhubport(ep_target_regs,
2375 musb->context.index_regs[i].rxhubport);
2376 }
2377 }
2378 }
2379
2380 static int musb_suspend(struct device *dev)
2381 {
2382 struct platform_device *pdev = to_platform_device(dev);
2383 unsigned long flags;
2384 struct musb *musb = dev_to_musb(&pdev->dev);
2385
2386 spin_lock_irqsave(&musb->lock, flags);
2387
2388 if (is_peripheral_active(musb)) {
2389 /* FIXME force disconnect unless we know USB will wake
2390 * the system up quickly enough to respond ...
2391 */
2392 } else if (is_host_active(musb)) {
2393 /* we know all the children are suspended; sometimes
2394 * they will even be wakeup-enabled.
2395 */
2396 }
2397
2398 musb_save_context(musb);
2399
2400 spin_unlock_irqrestore(&musb->lock, flags);
2401 return 0;
2402 }
2403
2404 static int musb_resume_noirq(struct device *dev)
2405 {
2406 struct platform_device *pdev = to_platform_device(dev);
2407 struct musb *musb = dev_to_musb(&pdev->dev);
2408
2409 musb_restore_context(musb);
2410
2411 /* for static cmos like DaVinci, register values were preserved
2412 * unless for some reason the whole soc powered down or the USB
2413 * module got reset through the PSC (vs just being disabled).
2414 */
2415 return 0;
2416 }
2417
2418 static const struct dev_pm_ops musb_dev_pm_ops = {
2419 .suspend = musb_suspend,
2420 .resume_noirq = musb_resume_noirq,
2421 };
2422
2423 #define MUSB_DEV_PM_OPS (&musb_dev_pm_ops)
2424 #else
2425 #define MUSB_DEV_PM_OPS NULL
2426 #endif
2427
2428 static struct platform_driver musb_driver = {
2429 .driver = {
2430 .name = (char *)musb_driver_name,
2431 .bus = &platform_bus_type,
2432 .owner = THIS_MODULE,
2433 .pm = MUSB_DEV_PM_OPS,
2434 },
2435 .remove = __exit_p(musb_remove),
2436 .shutdown = musb_shutdown,
2437 };
2438
2439 /*-------------------------------------------------------------------------*/
2440
2441 static int __init musb_init(void)
2442 {
2443 #ifdef CONFIG_USB_MUSB_HDRC_HCD
2444 if (usb_disabled())
2445 return 0;
2446 #endif
2447
2448 pr_info("%s: version " MUSB_VERSION ", "
2449 #ifdef CONFIG_MUSB_PIO_ONLY
2450 "pio"
2451 #elif defined(CONFIG_USB_TI_CPPI_DMA)
2452 "cppi-dma"
2453 #elif defined(CONFIG_USB_INVENTRA_DMA)
2454 "musb-dma"
2455 #elif defined(CONFIG_USB_TUSB_OMAP_DMA)
2456 "tusb-omap-dma"
2457 #else
2458 "?dma?"
2459 #endif
2460 ", "
2461 #ifdef CONFIG_USB_MUSB_OTG
2462 "otg (peripheral+host)"
2463 #elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
2464 "peripheral"
2465 #elif defined(CONFIG_USB_MUSB_HDRC_HCD)
2466 "host"
2467 #endif
2468 ", debug=%d\n",
2469 musb_driver_name, musb_debug);
2470 return platform_driver_probe(&musb_driver, musb_probe);
2471 }
2472
2473 /* make us init after usbcore and i2c (transceivers, regulators, etc)
2474 * and before usb gadget and host-side drivers start to register
2475 */
2476 fs_initcall(musb_init);
2477
2478 static void __exit musb_cleanup(void)
2479 {
2480 platform_driver_unregister(&musb_driver);
2481 }
2482 module_exit(musb_cleanup);
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree