2 * Copyright (C) 2007-2008 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <joerg.roedel@amd.com>
4 * Leo Duran <leo.duran@amd.com>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/pci.h>
21 #include <linux/acpi.h>
22 #include <linux/gfp.h>
23 #include <linux/list.h>
24 #include <asm/pci-direct.h>
25 #include <asm/amd_iommu_types.h>
26 #include <asm/amd_iommu.h>
30 * definitions for the ACPI scanning code
32 #define UPDATE_LAST_BDF(x) do {\
33 if ((x) > amd_iommu_last_bdf) \
34 amd_iommu_last_bdf = (x); \
37 #define DEVID(bus, devfn) (((bus) << 8) | (devfn))
38 #define PCI_BUS(x) (((x) >> 8) & 0xff)
39 #define IVRS_HEADER_LENGTH 48
40 #define TBL_SIZE(x) (1 << (PAGE_SHIFT + get_order(amd_iommu_last_bdf * (x))))
42 #define ACPI_IVHD_TYPE 0x10
43 #define ACPI_IVMD_TYPE_ALL 0x20
44 #define ACPI_IVMD_TYPE 0x21
45 #define ACPI_IVMD_TYPE_RANGE 0x22
47 #define IVHD_DEV_ALL 0x01
48 #define IVHD_DEV_SELECT 0x02
49 #define IVHD_DEV_SELECT_RANGE_START 0x03
50 #define IVHD_DEV_RANGE_END 0x04
51 #define IVHD_DEV_ALIAS 0x42
52 #define IVHD_DEV_ALIAS_RANGE 0x43
53 #define IVHD_DEV_EXT_SELECT 0x46
54 #define IVHD_DEV_EXT_SELECT_RANGE 0x47
56 #define IVHD_FLAG_HT_TUN_EN 0x00
57 #define IVHD_FLAG_PASSPW_EN 0x01
58 #define IVHD_FLAG_RESPASSPW_EN 0x02
59 #define IVHD_FLAG_ISOC_EN 0x03
61 #define IVMD_FLAG_EXCL_RANGE 0x08
62 #define IVMD_FLAG_UNITY_MAP 0x01
64 #define ACPI_DEVFLAG_INITPASS 0x01
65 #define ACPI_DEVFLAG_EXTINT 0x02
66 #define ACPI_DEVFLAG_NMI 0x04
67 #define ACPI_DEVFLAG_SYSMGT1 0x10
68 #define ACPI_DEVFLAG_SYSMGT2 0x20
69 #define ACPI_DEVFLAG_LINT0 0x40
70 #define ACPI_DEVFLAG_LINT1 0x80
71 #define ACPI_DEVFLAG_ATSDIS 0x10000000
83 } __attribute__((packed
));
90 } __attribute__((packed
));
101 } __attribute__((packed
));
103 static int __initdata amd_iommu_disable
;
105 u16 amd_iommu_last_bdf
;
106 struct list_head amd_iommu_unity_map
;
107 unsigned amd_iommu_aperture_order
= 26;
108 int amd_iommu_isolate
;
110 struct list_head amd_iommu_list
;
111 struct dev_table_entry
*amd_iommu_dev_table
;
112 u16
*amd_iommu_alias_table
;
113 struct amd_iommu
**amd_iommu_rlookup_table
;
114 struct protection_domain
**amd_iommu_pd_table
;
115 unsigned long *amd_iommu_pd_alloc_bitmap
;
117 static u32 dev_table_size
;
118 static u32 alias_table_size
;
119 static u32 rlookup_table_size
;
121 static void __init
iommu_set_exclusion_range(struct amd_iommu
*iommu
)
123 u64 start
= iommu
->exclusion_start
& PAGE_MASK
;
124 u64 limit
= (start
+ iommu
->exclusion_length
) & PAGE_MASK
;
127 if (!iommu
->exclusion_start
)
130 entry
= start
| MMIO_EXCL_ENABLE_MASK
;
131 memcpy_toio(iommu
->mmio_base
+ MMIO_EXCL_BASE_OFFSET
,
132 &entry
, sizeof(entry
));
135 memcpy_toio(iommu
->mmio_base
+ MMIO_EXCL_LIMIT_OFFSET
,
136 &entry
, sizeof(entry
));
139 static void __init
iommu_set_device_table(struct amd_iommu
*iommu
)
143 BUG_ON(iommu
->mmio_base
== NULL
);
145 entry
= virt_to_phys(amd_iommu_dev_table
);
146 entry
|= (dev_table_size
>> 12) - 1;
147 memcpy_toio(iommu
->mmio_base
+ MMIO_DEV_TABLE_OFFSET
,
148 &entry
, sizeof(entry
));
151 static void __init
iommu_feature_enable(struct amd_iommu
*iommu
, u8 bit
)
155 ctrl
= readl(iommu
->mmio_base
+ MMIO_CONTROL_OFFSET
);
157 writel(ctrl
, iommu
->mmio_base
+ MMIO_CONTROL_OFFSET
);
160 static void __init
iommu_feature_disable(struct amd_iommu
*iommu
, u8 bit
)
164 ctrl
= (u64
)readl(iommu
->mmio_base
+ MMIO_CONTROL_OFFSET
);
166 writel(ctrl
, iommu
->mmio_base
+ MMIO_CONTROL_OFFSET
);
169 void __init
iommu_enable(struct amd_iommu
*iommu
)
173 printk(KERN_INFO
"AMD IOMMU: Enabling IOMMU at ");
174 print_devid(iommu
->devid
, 0);
175 printk(" cap 0x%hx\n", iommu
->cap_ptr
);
177 iommu_feature_enable(iommu
, CONTROL_IOMMU_EN
);
178 ctrl
= readl(iommu
->mmio_base
+ MMIO_CONTROL_OFFSET
);
181 static u8
* __init
iommu_map_mmio_space(u64 address
)
185 if (!request_mem_region(address
, MMIO_REGION_LENGTH
, "amd_iommu"))
188 ret
= ioremap_nocache(address
, MMIO_REGION_LENGTH
);
192 release_mem_region(address
, MMIO_REGION_LENGTH
);
197 static void __init
iommu_unmap_mmio_space(struct amd_iommu
*iommu
)
199 if (iommu
->mmio_base
)
200 iounmap(iommu
->mmio_base
);
201 release_mem_region(iommu
->mmio_phys
, MMIO_REGION_LENGTH
);
204 static int __init
find_last_devid_on_pci(int bus
, int dev
, int fn
, int cap_ptr
)
208 cap
= read_pci_config(bus
, dev
, fn
, cap_ptr
+MMIO_RANGE_OFFSET
);
209 UPDATE_LAST_BDF(DEVID(MMIO_GET_BUS(cap
), MMIO_GET_LD(cap
)));
214 static int __init
find_last_devid_from_ivhd(struct ivhd_header
*h
)
216 u8
*p
= (void *)h
, *end
= (void *)h
;
217 struct ivhd_entry
*dev
;
222 find_last_devid_on_pci(PCI_BUS(h
->devid
),
228 dev
= (struct ivhd_entry
*)p
;
230 case IVHD_DEV_SELECT
:
231 case IVHD_DEV_RANGE_END
:
233 case IVHD_DEV_EXT_SELECT
:
234 UPDATE_LAST_BDF(dev
->devid
);
239 p
+= 0x04 << (*p
>> 6);
247 static int __init
find_last_devid_acpi(struct acpi_table_header
*table
)
250 u8 checksum
= 0, *p
= (u8
*)table
, *end
= (u8
*)table
;
251 struct ivhd_header
*h
;
254 * Validate checksum here so we don't need to do it when
255 * we actually parse the table
257 for (i
= 0; i
< table
->length
; ++i
)
260 /* ACPI table corrupt */
263 p
+= IVRS_HEADER_LENGTH
;
265 end
+= table
->length
;
267 h
= (struct ivhd_header
*)p
;
270 find_last_devid_from_ivhd(h
);
282 static u8
* __init
alloc_command_buffer(struct amd_iommu
*iommu
)
284 u8
*cmd_buf
= (u8
*)__get_free_pages(GFP_KERNEL
,
285 get_order(CMD_BUFFER_SIZE
));
291 iommu
->cmd_buf_size
= CMD_BUFFER_SIZE
;
293 memset(cmd_buf
, 0, CMD_BUFFER_SIZE
);
295 entry
= (u64
)virt_to_phys(cmd_buf
);
296 entry
|= MMIO_CMD_SIZE_512
;
297 memcpy_toio(iommu
->mmio_base
+ MMIO_CMD_BUF_OFFSET
,
298 &entry
, sizeof(entry
));
300 iommu_feature_enable(iommu
, CONTROL_CMDBUF_EN
);
305 static void __init
free_command_buffer(struct amd_iommu
*iommu
)
308 free_pages((unsigned long)iommu
->cmd_buf
,
309 get_order(CMD_BUFFER_SIZE
));
312 static void set_dev_entry_bit(u16 devid
, u8 bit
)
314 int i
= (bit
>> 5) & 0x07;
315 int _bit
= bit
& 0x1f;
317 amd_iommu_dev_table
[devid
].data
[i
] |= (1 << _bit
);
320 static void __init
set_dev_entry_from_acpi(u16 devid
, u32 flags
, u32 ext_flags
)
322 if (flags
& ACPI_DEVFLAG_INITPASS
)
323 set_dev_entry_bit(devid
, DEV_ENTRY_INIT_PASS
);
324 if (flags
& ACPI_DEVFLAG_EXTINT
)
325 set_dev_entry_bit(devid
, DEV_ENTRY_EINT_PASS
);
326 if (flags
& ACPI_DEVFLAG_NMI
)
327 set_dev_entry_bit(devid
, DEV_ENTRY_NMI_PASS
);
328 if (flags
& ACPI_DEVFLAG_SYSMGT1
)
329 set_dev_entry_bit(devid
, DEV_ENTRY_SYSMGT1
);
330 if (flags
& ACPI_DEVFLAG_SYSMGT2
)
331 set_dev_entry_bit(devid
, DEV_ENTRY_SYSMGT2
);
332 if (flags
& ACPI_DEVFLAG_LINT0
)
333 set_dev_entry_bit(devid
, DEV_ENTRY_LINT0_PASS
);
334 if (flags
& ACPI_DEVFLAG_LINT1
)
335 set_dev_entry_bit(devid
, DEV_ENTRY_LINT1_PASS
);
338 static void __init
set_iommu_for_device(struct amd_iommu
*iommu
, u16 devid
)
340 amd_iommu_rlookup_table
[devid
] = iommu
;
343 static void __init
set_device_exclusion_range(u16 devid
, struct ivmd_header
*m
)
345 struct amd_iommu
*iommu
= amd_iommu_rlookup_table
[devid
];
347 if (!(m
->flags
& IVMD_FLAG_EXCL_RANGE
))
351 set_dev_entry_bit(m
->devid
, DEV_ENTRY_EX
);
352 iommu
->exclusion_start
= m
->range_start
;
353 iommu
->exclusion_length
= m
->range_length
;
357 static void __init
init_iommu_from_pci(struct amd_iommu
*iommu
)
359 int bus
= PCI_BUS(iommu
->devid
);
360 int dev
= PCI_SLOT(iommu
->devid
);
361 int fn
= PCI_FUNC(iommu
->devid
);
362 int cap_ptr
= iommu
->cap_ptr
;
365 iommu
->cap
= read_pci_config(bus
, dev
, fn
, cap_ptr
+MMIO_CAP_HDR_OFFSET
);
367 range
= read_pci_config(bus
, dev
, fn
, cap_ptr
+MMIO_RANGE_OFFSET
);
368 iommu
->first_device
= DEVID(MMIO_GET_BUS(range
), MMIO_GET_FD(range
));
369 iommu
->last_device
= DEVID(MMIO_GET_BUS(range
), MMIO_GET_LD(range
));
372 static void __init
init_iommu_from_acpi(struct amd_iommu
*iommu
,
373 struct ivhd_header
*h
)
376 u8
*end
= p
, flags
= 0;
377 u16 dev_i
, devid
= 0, devid_start
= 0, devid_to
= 0;
380 struct ivhd_entry
*e
;
383 * First set the recommended feature enable bits from ACPI
384 * into the IOMMU control registers
386 h
->flags
& IVHD_FLAG_HT_TUN_EN
?
387 iommu_feature_enable(iommu
, CONTROL_HT_TUN_EN
) :
388 iommu_feature_disable(iommu
, CONTROL_HT_TUN_EN
);
390 h
->flags
& IVHD_FLAG_PASSPW_EN
?
391 iommu_feature_enable(iommu
, CONTROL_PASSPW_EN
) :
392 iommu_feature_disable(iommu
, CONTROL_PASSPW_EN
);
394 h
->flags
& IVHD_FLAG_RESPASSPW_EN
?
395 iommu_feature_enable(iommu
, CONTROL_RESPASSPW_EN
) :
396 iommu_feature_disable(iommu
, CONTROL_RESPASSPW_EN
);
398 h
->flags
& IVHD_FLAG_ISOC_EN
?
399 iommu_feature_enable(iommu
, CONTROL_ISOC_EN
) :
400 iommu_feature_disable(iommu
, CONTROL_ISOC_EN
);
403 * make IOMMU memory accesses cache coherent
405 iommu_feature_enable(iommu
, CONTROL_COHERENT_EN
);
408 * Done. Now parse the device entries
410 p
+= sizeof(struct ivhd_header
);
414 e
= (struct ivhd_entry
*)p
;
417 for (dev_i
= iommu
->first_device
;
418 dev_i
<= iommu
->last_device
; ++dev_i
)
419 set_dev_entry_from_acpi(dev_i
, e
->flags
, 0);
421 case IVHD_DEV_SELECT
:
423 set_dev_entry_from_acpi(devid
, e
->flags
, 0);
425 case IVHD_DEV_SELECT_RANGE_START
:
426 devid_start
= e
->devid
;
433 devid_to
= e
->ext
>> 8;
434 set_dev_entry_from_acpi(devid
, e
->flags
, 0);
435 amd_iommu_alias_table
[devid
] = devid_to
;
437 case IVHD_DEV_ALIAS_RANGE
:
438 devid_start
= e
->devid
;
440 devid_to
= e
->ext
>> 8;
444 case IVHD_DEV_EXT_SELECT
:
446 set_dev_entry_from_acpi(devid
, e
->flags
, e
->ext
);
448 case IVHD_DEV_EXT_SELECT_RANGE
:
449 devid_start
= e
->devid
;
454 case IVHD_DEV_RANGE_END
:
456 for (dev_i
= devid_start
; dev_i
<= devid
; ++dev_i
) {
458 amd_iommu_alias_table
[dev_i
] = devid_to
;
459 set_dev_entry_from_acpi(
460 amd_iommu_alias_table
[dev_i
],
468 p
+= 0x04 << (e
->type
>> 6);
472 static int __init
init_iommu_devices(struct amd_iommu
*iommu
)
476 for (i
= iommu
->first_device
; i
<= iommu
->last_device
; ++i
)
477 set_iommu_for_device(iommu
, i
);
482 static void __init
free_iommu_one(struct amd_iommu
*iommu
)
484 free_command_buffer(iommu
);
485 iommu_unmap_mmio_space(iommu
);
488 static void __init
free_iommu_all(void)
490 struct amd_iommu
*iommu
, *next
;
492 list_for_each_entry_safe(iommu
, next
, &amd_iommu_list
, list
) {
493 list_del(&iommu
->list
);
494 free_iommu_one(iommu
);
499 static int __init
init_iommu_one(struct amd_iommu
*iommu
, struct ivhd_header
*h
)
501 spin_lock_init(&iommu
->lock
);
502 list_add_tail(&iommu
->list
, &amd_iommu_list
);
505 * Copy data from ACPI table entry to the iommu struct
507 iommu
->devid
= h
->devid
;
508 iommu
->cap_ptr
= h
->cap_ptr
;
509 iommu
->mmio_phys
= h
->mmio_phys
;
510 iommu
->mmio_base
= iommu_map_mmio_space(h
->mmio_phys
);
511 if (!iommu
->mmio_base
)
514 iommu_set_device_table(iommu
);
515 iommu
->cmd_buf
= alloc_command_buffer(iommu
);
519 init_iommu_from_pci(iommu
);
520 init_iommu_from_acpi(iommu
, h
);
521 init_iommu_devices(iommu
);
526 static int __init
init_iommu_all(struct acpi_table_header
*table
)
528 u8
*p
= (u8
*)table
, *end
= (u8
*)table
;
529 struct ivhd_header
*h
;
530 struct amd_iommu
*iommu
;
533 INIT_LIST_HEAD(&amd_iommu_list
);
535 end
+= table
->length
;
536 p
+= IVRS_HEADER_LENGTH
;
539 h
= (struct ivhd_header
*)p
;
542 iommu
= kzalloc(sizeof(struct amd_iommu
), GFP_KERNEL
);
545 ret
= init_iommu_one(iommu
, h
);
560 static void __init
free_unity_maps(void)
562 struct unity_map_entry
*entry
, *next
;
564 list_for_each_entry_safe(entry
, next
, &amd_iommu_unity_map
, list
) {
565 list_del(&entry
->list
);
570 static int __init
init_exclusion_range(struct ivmd_header
*m
)
576 set_device_exclusion_range(m
->devid
, m
);
578 case ACPI_IVMD_TYPE_ALL
:
579 for (i
= 0; i
< amd_iommu_last_bdf
; ++i
)
580 set_device_exclusion_range(i
, m
);
582 case ACPI_IVMD_TYPE_RANGE
:
583 for (i
= m
->devid
; i
<= m
->aux
; ++i
)
584 set_device_exclusion_range(i
, m
);
593 static int __init
init_unity_map_range(struct ivmd_header
*m
)
595 struct unity_map_entry
*e
= 0;
597 e
= kzalloc(sizeof(*e
), GFP_KERNEL
);
604 e
->devid_start
= e
->devid_end
= m
->devid
;
606 case ACPI_IVMD_TYPE_ALL
:
608 e
->devid_end
= amd_iommu_last_bdf
;
610 case ACPI_IVMD_TYPE_RANGE
:
611 e
->devid_start
= m
->devid
;
612 e
->devid_end
= m
->aux
;
615 e
->address_start
= PAGE_ALIGN(m
->range_start
);
616 e
->address_end
= e
->address_start
+ PAGE_ALIGN(m
->range_length
);
617 e
->prot
= m
->flags
>> 1;
619 list_add_tail(&e
->list
, &amd_iommu_unity_map
);
624 static int __init
init_memory_definitions(struct acpi_table_header
*table
)
626 u8
*p
= (u8
*)table
, *end
= (u8
*)table
;
627 struct ivmd_header
*m
;
629 INIT_LIST_HEAD(&amd_iommu_unity_map
);
631 end
+= table
->length
;
632 p
+= IVRS_HEADER_LENGTH
;
635 m
= (struct ivmd_header
*)p
;
636 if (m
->flags
& IVMD_FLAG_EXCL_RANGE
)
637 init_exclusion_range(m
);
638 else if (m
->flags
& IVMD_FLAG_UNITY_MAP
)
639 init_unity_map_range(m
);
647 static void __init
enable_iommus(void)
649 struct amd_iommu
*iommu
;
651 list_for_each_entry(iommu
, &amd_iommu_list
, list
) {
652 iommu_set_exclusion_range(iommu
);
657 int __init
amd_iommu_init(void)
662 if (amd_iommu_disable
) {
663 printk(KERN_INFO
"AMD IOMMU disabled by kernel command line\n");
668 * First parse ACPI tables to find the largest Bus/Dev/Func
669 * we need to handle. Upon this information the shared data
670 * structures for the IOMMUs in the system will be allocated
672 if (acpi_table_parse("IVRS", find_last_devid_acpi
) != 0)
675 dev_table_size
= TBL_SIZE(DEV_TABLE_ENTRY_SIZE
);
676 alias_table_size
= TBL_SIZE(ALIAS_TABLE_ENTRY_SIZE
);
677 rlookup_table_size
= TBL_SIZE(RLOOKUP_TABLE_ENTRY_SIZE
);
681 /* Device table - directly used by all IOMMUs */
682 amd_iommu_dev_table
= (void *)__get_free_pages(GFP_KERNEL
,
683 get_order(dev_table_size
));
684 if (amd_iommu_dev_table
== NULL
)
688 * Alias table - map PCI Bus/Dev/Func to Bus/Dev/Func the
689 * IOMMU see for that device
691 amd_iommu_alias_table
= (void *)__get_free_pages(GFP_KERNEL
,
692 get_order(alias_table_size
));
693 if (amd_iommu_alias_table
== NULL
)
696 /* IOMMU rlookup table - find the IOMMU for a specific device */
697 amd_iommu_rlookup_table
= (void *)__get_free_pages(GFP_KERNEL
,
698 get_order(rlookup_table_size
));
699 if (amd_iommu_rlookup_table
== NULL
)
703 * Protection Domain table - maps devices to protection domains
704 * This table has the same size as the rlookup_table
706 amd_iommu_pd_table
= (void *)__get_free_pages(GFP_KERNEL
,
707 get_order(rlookup_table_size
));
708 if (amd_iommu_pd_table
== NULL
)
711 amd_iommu_pd_alloc_bitmap
= (void *)__get_free_pages(GFP_KERNEL
,
712 get_order(MAX_DOMAIN_ID
/8));
713 if (amd_iommu_pd_alloc_bitmap
== NULL
)
717 * memory is allocated now; initialize the device table with all zeroes
718 * and let all alias entries point to itself
720 memset(amd_iommu_dev_table
, 0, dev_table_size
);
721 for (i
= 0; i
< amd_iommu_last_bdf
; ++i
)
722 amd_iommu_alias_table
[i
] = i
;
724 memset(amd_iommu_pd_table
, 0, rlookup_table_size
);
725 memset(amd_iommu_pd_alloc_bitmap
, 0, MAX_DOMAIN_ID
/ 8);
728 * never allocate domain 0 because its used as the non-allocated and
729 * error value placeholder
731 amd_iommu_pd_alloc_bitmap
[0] = 1;
734 * now the data structures are allocated and basically initialized
735 * start the real acpi table scan
738 if (acpi_table_parse("IVRS", init_iommu_all
) != 0)
741 if (acpi_table_parse("IVRS", init_memory_definitions
) != 0)
744 ret
= amd_iommu_init_dma_ops();
750 printk(KERN_INFO
"AMD IOMMU: aperture size is %d MB\n",
751 (1 << (amd_iommu_aperture_order
-20)));
753 printk(KERN_INFO
"AMD IOMMU: device isolation ");
754 if (amd_iommu_isolate
)
757 printk("disabled\n");
763 if (amd_iommu_pd_alloc_bitmap
)
764 free_pages((unsigned long)amd_iommu_pd_alloc_bitmap
, 1);
766 if (amd_iommu_pd_table
)
767 free_pages((unsigned long)amd_iommu_pd_table
,
768 get_order(rlookup_table_size
));
770 if (amd_iommu_rlookup_table
)
771 free_pages((unsigned long)amd_iommu_rlookup_table
,
772 get_order(rlookup_table_size
));
774 if (amd_iommu_alias_table
)
775 free_pages((unsigned long)amd_iommu_alias_table
,
776 get_order(alias_table_size
));
778 if (amd_iommu_dev_table
)
779 free_pages((unsigned long)amd_iommu_dev_table
,
780 get_order(dev_table_size
));
789 static int __init
early_amd_iommu_detect(struct acpi_table_header
*table
)
794 void __init
amd_iommu_detect(void)
796 if (swiotlb
|| no_iommu
|| iommu_detected
)
799 if (amd_iommu_disable
)
802 if (acpi_table_parse("IVRS", early_amd_iommu_detect
) == 0) {
804 #ifdef CONFIG_GART_IOMMU
805 gart_iommu_aperture_disabled
= 1;
806 gart_iommu_aperture
= 0;
811 static int __init
parse_amd_iommu_options(char *str
)
813 for (; *str
; ++str
) {
814 if (strcmp(str
, "off") == 0)
815 amd_iommu_disable
= 1;
816 if (strcmp(str
, "isolate") == 0)
817 amd_iommu_isolate
= 1;
823 static int __init
parse_amd_iommu_size_options(char *str
)
825 for (; *str
; ++str
) {
826 if (strcmp(str
, "32M") == 0)
827 amd_iommu_aperture_order
= 25;
828 if (strcmp(str
, "64M") == 0)
829 amd_iommu_aperture_order
= 26;
830 if (strcmp(str
, "128M") == 0)
831 amd_iommu_aperture_order
= 27;
832 if (strcmp(str
, "256M") == 0)
833 amd_iommu_aperture_order
= 28;
834 if (strcmp(str
, "512M") == 0)
835 amd_iommu_aperture_order
= 29;
836 if (strcmp(str
, "1G") == 0)
837 amd_iommu_aperture_order
= 30;
843 __setup("amd_iommu=", parse_amd_iommu_options
);
844 __setup("amd_iommu_size=", parse_amd_iommu_size_options
);