2 * linux/arch/arm/vfp/vfpsingle.c
4 * This code is derived in part from John R. Housers softfloat library, which
5 * carries the following notice:
7 * ===========================================================================
8 * This C source file is part of the SoftFloat IEC/IEEE Floating-point
9 * Arithmetic Package, Release 2.
11 * Written by John R. Hauser. This work was made possible in part by the
12 * International Computer Science Institute, located at Suite 600, 1947 Center
13 * Street, Berkeley, California 94704. Funding was partially provided by the
14 * National Science Foundation under grant MIP-9311980. The original version
15 * of this code was written as part of a project to build a fixed-point vector
16 * processor in collaboration with the University of California at Berkeley,
17 * overseen by Profs. Nelson Morgan and John Wawrzynek. More information
18 * is available through the web page `http://HTTP.CS.Berkeley.EDU/~jhauser/
19 * arithmetic/softfloat.html'.
21 * THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE. Although reasonable effort
22 * has been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT
23 * TIMES RESULT IN INCORRECT BEHAVIOR. USE OF THIS SOFTWARE IS RESTRICTED TO
24 * PERSONS AND ORGANIZATIONS WHO CAN AND WILL TAKE FULL RESPONSIBILITY FOR ANY
25 * AND ALL LOSSES, COSTS, OR OTHER PROBLEMS ARISING FROM ITS USE.
27 * Derivative works are acceptable, even for commercial purposes, so long as
28 * (1) they include prominent notice that the work is derivative, and (2) they
29 * include prominent notice akin to these three paragraphs for those parts of
30 * this code that are retained.
31 * ===========================================================================
33 #include <linux/kernel.h>
34 #include <linux/bitops.h>
36 #include <asm/div64.h>
37 #include <asm/ptrace.h>
43 static struct vfp_single vfp_single_default_qnan
= {
46 .significand
= VFP_SINGLE_SIGNIFICAND_QNAN
,
49 static void vfp_single_dump(const char *str
, struct vfp_single
*s
)
51 pr_debug("VFP: %s: sign=%d exponent=%d significand=%08x\n",
52 str
, s
->sign
!= 0, s
->exponent
, s
->significand
);
55 static void vfp_single_normalise_denormal(struct vfp_single
*vs
)
57 int bits
= 31 - fls(vs
->significand
);
59 vfp_single_dump("normalise_denormal: in", vs
);
62 vs
->exponent
-= bits
- 1;
63 vs
->significand
<<= bits
;
66 vfp_single_dump("normalise_denormal: out", vs
);
70 #define vfp_single_normaliseround(sd,vsd,fpscr,except,func) __vfp_single_normaliseround(sd,vsd,fpscr,except)
71 u32
__vfp_single_normaliseround(int sd
, struct vfp_single
*vs
, u32 fpscr
, u32 exceptions
)
73 u32
vfp_single_normaliseround(int sd
, struct vfp_single
*vs
, u32 fpscr
, u32 exceptions
, const char *func
)
76 u32 significand
, incr
, rmode
;
77 int exponent
, shift
, underflow
;
79 vfp_single_dump("pack: in", vs
);
82 * Infinities and NaNs are a special case.
84 if (vs
->exponent
== 255 && (vs
->significand
== 0 || exceptions
))
90 if (vs
->significand
== 0) {
95 exponent
= vs
->exponent
;
96 significand
= vs
->significand
;
99 * Normalise first. Note that we shift the significand up to
100 * bit 31, so we have VFP_SINGLE_LOW_BITS + 1 below the least
103 shift
= 32 - fls(significand
);
104 if (shift
< 32 && shift
) {
106 significand
<<= shift
;
110 vs
->exponent
= exponent
;
111 vs
->significand
= significand
;
112 vfp_single_dump("pack: normalised", vs
);
118 underflow
= exponent
< 0;
120 significand
= vfp_shiftright32jamming(significand
, -exponent
);
123 vs
->exponent
= exponent
;
124 vs
->significand
= significand
;
125 vfp_single_dump("pack: tiny number", vs
);
127 if (!(significand
& ((1 << (VFP_SINGLE_LOW_BITS
+ 1)) - 1)))
132 * Select rounding increment.
135 rmode
= fpscr
& FPSCR_RMODE_MASK
;
137 if (rmode
== FPSCR_ROUND_NEAREST
) {
138 incr
= 1 << VFP_SINGLE_LOW_BITS
;
139 if ((significand
& (1 << (VFP_SINGLE_LOW_BITS
+ 1))) == 0)
141 } else if (rmode
== FPSCR_ROUND_TOZERO
) {
143 } else if ((rmode
== FPSCR_ROUND_PLUSINF
) ^ (vs
->sign
!= 0))
144 incr
= (1 << (VFP_SINGLE_LOW_BITS
+ 1)) - 1;
146 pr_debug("VFP: rounding increment = 0x%08x\n", incr
);
149 * Is our rounding going to overflow?
151 if ((significand
+ incr
) < significand
) {
153 significand
= (significand
>> 1) | (significand
& 1);
156 vs
->exponent
= exponent
;
157 vs
->significand
= significand
;
158 vfp_single_dump("pack: overflow", vs
);
163 * If any of the low bits (which will be shifted out of the
164 * number) are non-zero, the result is inexact.
166 if (significand
& ((1 << (VFP_SINGLE_LOW_BITS
+ 1)) - 1))
167 exceptions
|= FPSCR_IXC
;
177 if (exponent
>= 254) {
178 exceptions
|= FPSCR_OFC
| FPSCR_IXC
;
181 vs
->significand
= 0x7fffffff;
183 vs
->exponent
= 255; /* infinity */
187 if (significand
>> (VFP_SINGLE_LOW_BITS
+ 1) == 0)
189 if (exponent
|| significand
> 0x80000000)
192 exceptions
|= FPSCR_UFC
;
193 vs
->exponent
= exponent
;
194 vs
->significand
= significand
>> 1;
198 vfp_single_dump("pack: final", vs
);
200 s32 d
= vfp_single_pack(vs
);
201 pr_debug("VFP: %s: d(s%d)=%08x exceptions=%08x\n", func
,
203 vfp_put_float(sd
, d
);
210 * Propagate the NaN, setting exceptions if it is signalling.
211 * 'n' is always a NaN. 'm' may be a number, NaN or infinity.
214 vfp_propagate_nan(struct vfp_single
*vsd
, struct vfp_single
*vsn
,
215 struct vfp_single
*vsm
, u32 fpscr
)
217 struct vfp_single
*nan
;
220 tn
= vfp_single_type(vsn
);
223 tm
= vfp_single_type(vsm
);
225 if (fpscr
& FPSCR_DEFAULT_NAN
)
227 * Default NaN mode - always returns a quiet NaN
229 nan
= &vfp_single_default_qnan
;
232 * Contemporary mode - select the first signalling
233 * NAN, or if neither are signalling, the first
236 if (tn
== VFP_SNAN
|| (tm
!= VFP_SNAN
&& tn
== VFP_QNAN
))
241 * Make the NaN quiet.
243 nan
->significand
|= VFP_SINGLE_SIGNIFICAND_QNAN
;
249 * If one was a signalling NAN, raise invalid operation.
251 return tn
== VFP_SNAN
|| tm
== VFP_SNAN
? FPSCR_IOC
: VFP_NAN_FLAG
;
256 * Extended operations
258 static u32
vfp_single_fabs(int sd
, int unused
, s32 m
, u32 fpscr
)
260 vfp_put_float(sd
, vfp_single_packed_abs(m
));
264 static u32
vfp_single_fcpy(int sd
, int unused
, s32 m
, u32 fpscr
)
266 vfp_put_float(sd
, m
);
270 static u32
vfp_single_fneg(int sd
, int unused
, s32 m
, u32 fpscr
)
272 vfp_put_float(sd
, vfp_single_packed_negate(m
));
276 static const u16 sqrt_oddadjust
[] = {
277 0x0004, 0x0022, 0x005d, 0x00b1, 0x011d, 0x019f, 0x0236, 0x02e0,
278 0x039c, 0x0468, 0x0545, 0x0631, 0x072b, 0x0832, 0x0946, 0x0a67
281 static const u16 sqrt_evenadjust
[] = {
282 0x0a2d, 0x08af, 0x075a, 0x0629, 0x051a, 0x0429, 0x0356, 0x029e,
283 0x0200, 0x0179, 0x0109, 0x00af, 0x0068, 0x0034, 0x0012, 0x0002
286 u32
vfp_estimate_sqrt_significand(u32 exponent
, u32 significand
)
291 if ((significand
& 0xc0000000) != 0x40000000) {
292 printk(KERN_WARNING
"VFP: estimate_sqrt: invalid significand\n");
295 a
= significand
<< 1;
296 index
= (a
>> 27) & 15;
298 z
= 0x4000 + (a
>> 17) - sqrt_oddadjust
[index
];
299 z
= ((a
/ z
) << 14) + (z
<< 15);
302 z
= 0x8000 + (a
>> 17) - sqrt_evenadjust
[index
];
304 z
= (z
>= 0x20000) ? 0xffff8000 : (z
<< 15);
309 u64 v
= (u64
)a
<< 31;
315 static u32
vfp_single_fsqrt(int sd
, int unused
, s32 m
, u32 fpscr
)
317 struct vfp_single vsm
, vsd
;
320 vfp_single_unpack(&vsm
, m
);
321 tm
= vfp_single_type(&vsm
);
322 if (tm
& (VFP_NAN
|VFP_INFINITY
)) {
323 struct vfp_single
*vsp
= &vsd
;
326 ret
= vfp_propagate_nan(vsp
, &vsm
, NULL
, fpscr
);
327 else if (vsm
.sign
== 0) {
333 vsp
= &vfp_single_default_qnan
;
336 vfp_put_float(sd
, vfp_single_pack(vsp
));
341 * sqrt(+/- 0) == +/- 0
347 * Normalise a denormalised number
349 if (tm
& VFP_DENORMAL
)
350 vfp_single_normalise_denormal(&vsm
);
358 vfp_single_dump("sqrt", &vsm
);
361 * Estimate the square root.
364 vsd
.exponent
= ((vsm
.exponent
- 127) >> 1) + 127;
365 vsd
.significand
= vfp_estimate_sqrt_significand(vsm
.exponent
, vsm
.significand
) + 2;
367 vfp_single_dump("sqrt estimate", &vsd
);
372 if ((vsd
.significand
& VFP_SINGLE_LOW_BITS_MASK
) <= 5) {
373 if (vsd
.significand
< 2) {
374 vsd
.significand
= 0xffffffff;
378 vsm
.significand
<<= !(vsm
.exponent
& 1);
379 term
= (u64
)vsd
.significand
* vsd
.significand
;
380 rem
= ((u64
)vsm
.significand
<< 32) - term
;
382 pr_debug("VFP: term=%016llx rem=%016llx\n", term
, rem
);
385 vsd
.significand
-= 1;
386 rem
+= ((u64
)vsd
.significand
<< 1) | 1;
388 vsd
.significand
|= rem
!= 0;
391 vsd
.significand
= vfp_shiftright32jamming(vsd
.significand
, 1);
393 return vfp_single_normaliseround(sd
, &vsd
, fpscr
, 0, "fsqrt");
402 static u32
vfp_compare(int sd
, int signal_on_qnan
, s32 m
, u32 fpscr
)
407 d
= vfp_get_float(sd
);
408 if (vfp_single_packed_exponent(m
) == 255 && vfp_single_packed_mantissa(m
)) {
409 ret
|= FPSCR_C
| FPSCR_V
;
410 if (signal_on_qnan
|| !(vfp_single_packed_mantissa(m
) & (1 << (VFP_SINGLE_MANTISSA_BITS
- 1))))
412 * Signalling NaN, or signalling on quiet NaN
417 if (vfp_single_packed_exponent(d
) == 255 && vfp_single_packed_mantissa(d
)) {
418 ret
|= FPSCR_C
| FPSCR_V
;
419 if (signal_on_qnan
|| !(vfp_single_packed_mantissa(d
) & (1 << (VFP_SINGLE_MANTISSA_BITS
- 1))))
421 * Signalling NaN, or signalling on quiet NaN
427 if (d
== m
|| vfp_single_packed_abs(d
| m
) == 0) {
431 ret
|= FPSCR_Z
| FPSCR_C
;
432 } else if (vfp_single_packed_sign(d
^ m
)) {
436 if (vfp_single_packed_sign(d
))
438 * d is negative, so d < m
443 * d is positive, so d > m
446 } else if ((vfp_single_packed_sign(d
) != 0) ^ (d
< m
)) {
451 } else if ((vfp_single_packed_sign(d
) != 0) ^ (d
> m
)) {
461 static u32
vfp_single_fcmp(int sd
, int unused
, s32 m
, u32 fpscr
)
463 return vfp_compare(sd
, 0, m
, fpscr
);
466 static u32
vfp_single_fcmpe(int sd
, int unused
, s32 m
, u32 fpscr
)
468 return vfp_compare(sd
, 1, m
, fpscr
);
471 static u32
vfp_single_fcmpz(int sd
, int unused
, s32 m
, u32 fpscr
)
473 return vfp_compare(sd
, 0, 0, fpscr
);
476 static u32
vfp_single_fcmpez(int sd
, int unused
, s32 m
, u32 fpscr
)
478 return vfp_compare(sd
, 1, 0, fpscr
);
481 static u32
vfp_single_fcvtd(int dd
, int unused
, s32 m
, u32 fpscr
)
483 struct vfp_single vsm
;
484 struct vfp_double vdd
;
488 vfp_single_unpack(&vsm
, m
);
490 tm
= vfp_single_type(&vsm
);
493 * If we have a signalling NaN, signal invalid operation.
496 exceptions
= FPSCR_IOC
;
498 if (tm
& VFP_DENORMAL
)
499 vfp_single_normalise_denormal(&vsm
);
502 vdd
.significand
= (u64
)vsm
.significand
<< 32;
505 * If we have an infinity or NaN, the exponent must be 2047.
507 if (tm
& (VFP_INFINITY
|VFP_NAN
)) {
510 vdd
.significand
|= VFP_DOUBLE_SIGNIFICAND_QNAN
;
512 } else if (tm
& VFP_ZERO
)
515 vdd
.exponent
= vsm
.exponent
+ (1023 - 127);
518 * Technically, if bit 0 of dd is set, this is an invalid
519 * instruction. However, we ignore this for efficiency.
521 return vfp_double_normaliseround(dd
, &vdd
, fpscr
, exceptions
, "fcvtd");
524 vfp_put_double(dd
, vfp_double_pack(&vdd
));
528 static u32
vfp_single_fuito(int sd
, int unused
, s32 m
, u32 fpscr
)
530 struct vfp_single vs
;
533 vs
.exponent
= 127 + 31 - 1;
534 vs
.significand
= (u32
)m
;
536 return vfp_single_normaliseround(sd
, &vs
, fpscr
, 0, "fuito");
539 static u32
vfp_single_fsito(int sd
, int unused
, s32 m
, u32 fpscr
)
541 struct vfp_single vs
;
543 vs
.sign
= (m
& 0x80000000) >> 16;
544 vs
.exponent
= 127 + 31 - 1;
545 vs
.significand
= vs
.sign
? -m
: m
;
547 return vfp_single_normaliseround(sd
, &vs
, fpscr
, 0, "fsito");
550 static u32
vfp_single_ftoui(int sd
, int unused
, s32 m
, u32 fpscr
)
552 struct vfp_single vsm
;
553 u32 d
, exceptions
= 0;
554 int rmode
= fpscr
& FPSCR_RMODE_MASK
;
557 vfp_single_unpack(&vsm
, m
);
558 vfp_single_dump("VSM", &vsm
);
561 * Do we have a denormalised number?
563 tm
= vfp_single_type(&vsm
);
564 if (tm
& VFP_DENORMAL
)
565 exceptions
|= FPSCR_IDC
;
570 if (vsm
.exponent
>= 127 + 32) {
571 d
= vsm
.sign
? 0 : 0xffffffff;
572 exceptions
= FPSCR_IOC
;
573 } else if (vsm
.exponent
>= 127 - 1) {
574 int shift
= 127 + 31 - vsm
.exponent
;
578 * 2^0 <= m < 2^32-2^8
580 d
= (vsm
.significand
<< 1) >> shift
;
581 rem
= vsm
.significand
<< (33 - shift
);
583 if (rmode
== FPSCR_ROUND_NEAREST
) {
587 } else if (rmode
== FPSCR_ROUND_TOZERO
) {
589 } else if ((rmode
== FPSCR_ROUND_PLUSINF
) ^ (vsm
.sign
!= 0)) {
593 if ((rem
+ incr
) < rem
) {
597 exceptions
|= FPSCR_IOC
;
602 exceptions
|= FPSCR_IOC
;
604 exceptions
|= FPSCR_IXC
;
607 if (vsm
.exponent
| vsm
.significand
) {
608 exceptions
|= FPSCR_IXC
;
609 if (rmode
== FPSCR_ROUND_PLUSINF
&& vsm
.sign
== 0)
611 else if (rmode
== FPSCR_ROUND_MINUSINF
&& vsm
.sign
) {
613 exceptions
|= FPSCR_IOC
;
618 pr_debug("VFP: ftoui: d(s%d)=%08x exceptions=%08x\n", sd
, d
, exceptions
);
620 vfp_put_float(sd
, d
);
625 static u32
vfp_single_ftouiz(int sd
, int unused
, s32 m
, u32 fpscr
)
627 return vfp_single_ftoui(sd
, unused
, m
, FPSCR_ROUND_TOZERO
);
630 static u32
vfp_single_ftosi(int sd
, int unused
, s32 m
, u32 fpscr
)
632 struct vfp_single vsm
;
633 u32 d
, exceptions
= 0;
634 int rmode
= fpscr
& FPSCR_RMODE_MASK
;
637 vfp_single_unpack(&vsm
, m
);
638 vfp_single_dump("VSM", &vsm
);
641 * Do we have a denormalised number?
643 tm
= vfp_single_type(&vsm
);
644 if (vfp_single_type(&vsm
) & VFP_DENORMAL
)
645 exceptions
|= FPSCR_IDC
;
649 exceptions
|= FPSCR_IOC
;
650 } else if (vsm
.exponent
>= 127 + 32) {
652 * m >= 2^31-2^7: invalid
657 exceptions
|= FPSCR_IOC
;
658 } else if (vsm
.exponent
>= 127 - 1) {
659 int shift
= 127 + 31 - vsm
.exponent
;
662 /* 2^0 <= m <= 2^31-2^7 */
663 d
= (vsm
.significand
<< 1) >> shift
;
664 rem
= vsm
.significand
<< (33 - shift
);
666 if (rmode
== FPSCR_ROUND_NEAREST
) {
670 } else if (rmode
== FPSCR_ROUND_TOZERO
) {
672 } else if ((rmode
== FPSCR_ROUND_PLUSINF
) ^ (vsm
.sign
!= 0)) {
676 if ((rem
+ incr
) < rem
&& d
< 0xffffffff)
678 if (d
> 0x7fffffff + (vsm
.sign
!= 0)) {
679 d
= 0x7fffffff + (vsm
.sign
!= 0);
680 exceptions
|= FPSCR_IOC
;
682 exceptions
|= FPSCR_IXC
;
688 if (vsm
.exponent
| vsm
.significand
) {
689 exceptions
|= FPSCR_IXC
;
690 if (rmode
== FPSCR_ROUND_PLUSINF
&& vsm
.sign
== 0)
692 else if (rmode
== FPSCR_ROUND_MINUSINF
&& vsm
.sign
)
697 pr_debug("VFP: ftosi: d(s%d)=%08x exceptions=%08x\n", sd
, d
, exceptions
);
699 vfp_put_float(sd
, (s32
)d
);
704 static u32
vfp_single_ftosiz(int sd
, int unused
, s32 m
, u32 fpscr
)
706 return vfp_single_ftosi(sd
, unused
, m
, FPSCR_ROUND_TOZERO
);
709 static u32 (* const fop_extfns
[32])(int sd
, int unused
, s32 m
, u32 fpscr
) = {
710 [FEXT_TO_IDX(FEXT_FCPY
)] = vfp_single_fcpy
,
711 [FEXT_TO_IDX(FEXT_FABS
)] = vfp_single_fabs
,
712 [FEXT_TO_IDX(FEXT_FNEG
)] = vfp_single_fneg
,
713 [FEXT_TO_IDX(FEXT_FSQRT
)] = vfp_single_fsqrt
,
714 [FEXT_TO_IDX(FEXT_FCMP
)] = vfp_single_fcmp
,
715 [FEXT_TO_IDX(FEXT_FCMPE
)] = vfp_single_fcmpe
,
716 [FEXT_TO_IDX(FEXT_FCMPZ
)] = vfp_single_fcmpz
,
717 [FEXT_TO_IDX(FEXT_FCMPEZ
)] = vfp_single_fcmpez
,
718 [FEXT_TO_IDX(FEXT_FCVT
)] = vfp_single_fcvtd
,
719 [FEXT_TO_IDX(FEXT_FUITO
)] = vfp_single_fuito
,
720 [FEXT_TO_IDX(FEXT_FSITO
)] = vfp_single_fsito
,
721 [FEXT_TO_IDX(FEXT_FTOUI
)] = vfp_single_ftoui
,
722 [FEXT_TO_IDX(FEXT_FTOUIZ
)] = vfp_single_ftouiz
,
723 [FEXT_TO_IDX(FEXT_FTOSI
)] = vfp_single_ftosi
,
724 [FEXT_TO_IDX(FEXT_FTOSIZ
)] = vfp_single_ftosiz
,
732 vfp_single_fadd_nonnumber(struct vfp_single
*vsd
, struct vfp_single
*vsn
,
733 struct vfp_single
*vsm
, u32 fpscr
)
735 struct vfp_single
*vsp
;
739 tn
= vfp_single_type(vsn
);
740 tm
= vfp_single_type(vsm
);
742 if (tn
& tm
& VFP_INFINITY
) {
744 * Two infinities. Are they different signs?
746 if (vsn
->sign
^ vsm
->sign
) {
748 * different signs -> invalid
750 exceptions
= FPSCR_IOC
;
751 vsp
= &vfp_single_default_qnan
;
754 * same signs -> valid
758 } else if (tn
& VFP_INFINITY
&& tm
& VFP_NUMBER
) {
760 * One infinity and one number -> infinity
765 * 'n' is a NaN of some type
767 return vfp_propagate_nan(vsd
, vsn
, vsm
, fpscr
);
774 vfp_single_add(struct vfp_single
*vsd
, struct vfp_single
*vsn
,
775 struct vfp_single
*vsm
, u32 fpscr
)
779 if (vsn
->significand
& 0x80000000 ||
780 vsm
->significand
& 0x80000000) {
781 pr_info("VFP: bad FP values in %s\n", __func__
);
782 vfp_single_dump("VSN", vsn
);
783 vfp_single_dump("VSM", vsm
);
787 * Ensure that 'n' is the largest magnitude number. Note that
788 * if 'n' and 'm' have equal exponents, we do not swap them.
789 * This ensures that NaN propagation works correctly.
791 if (vsn
->exponent
< vsm
->exponent
) {
792 struct vfp_single
*t
= vsn
;
798 * Is 'n' an infinity or a NaN? Note that 'm' may be a number,
799 * infinity or a NaN here.
801 if (vsn
->exponent
== 255)
802 return vfp_single_fadd_nonnumber(vsd
, vsn
, vsm
, fpscr
);
805 * We have two proper numbers, where 'vsn' is the larger magnitude.
807 * Copy 'n' to 'd' before doing the arithmetic.
812 * Align both numbers.
814 exp_diff
= vsn
->exponent
- vsm
->exponent
;
815 m_sig
= vfp_shiftright32jamming(vsm
->significand
, exp_diff
);
818 * If the signs are different, we are really subtracting.
820 if (vsn
->sign
^ vsm
->sign
) {
821 m_sig
= vsn
->significand
- m_sig
;
822 if ((s32
)m_sig
< 0) {
823 vsd
->sign
= vfp_sign_negate(vsd
->sign
);
825 } else if (m_sig
== 0) {
826 vsd
->sign
= (fpscr
& FPSCR_RMODE_MASK
) ==
827 FPSCR_ROUND_MINUSINF
? 0x8000 : 0;
830 m_sig
= vsn
->significand
+ m_sig
;
832 vsd
->significand
= m_sig
;
838 vfp_single_multiply(struct vfp_single
*vsd
, struct vfp_single
*vsn
, struct vfp_single
*vsm
, u32 fpscr
)
840 vfp_single_dump("VSN", vsn
);
841 vfp_single_dump("VSM", vsm
);
844 * Ensure that 'n' is the largest magnitude number. Note that
845 * if 'n' and 'm' have equal exponents, we do not swap them.
846 * This ensures that NaN propagation works correctly.
848 if (vsn
->exponent
< vsm
->exponent
) {
849 struct vfp_single
*t
= vsn
;
852 pr_debug("VFP: swapping M <-> N\n");
855 vsd
->sign
= vsn
->sign
^ vsm
->sign
;
858 * If 'n' is an infinity or NaN, handle it. 'm' may be anything.
860 if (vsn
->exponent
== 255) {
861 if (vsn
->significand
|| (vsm
->exponent
== 255 && vsm
->significand
))
862 return vfp_propagate_nan(vsd
, vsn
, vsm
, fpscr
);
863 if ((vsm
->exponent
| vsm
->significand
) == 0) {
864 *vsd
= vfp_single_default_qnan
;
867 vsd
->exponent
= vsn
->exponent
;
868 vsd
->significand
= 0;
873 * If 'm' is zero, the result is always zero. In this case,
874 * 'n' may be zero or a number, but it doesn't matter which.
876 if ((vsm
->exponent
| vsm
->significand
) == 0) {
878 vsd
->significand
= 0;
883 * We add 2 to the destination exponent for the same reason as
884 * the addition case - though this time we have +1 from each
887 vsd
->exponent
= vsn
->exponent
+ vsm
->exponent
- 127 + 2;
888 vsd
->significand
= vfp_hi64to32jamming((u64
)vsn
->significand
* vsm
->significand
);
890 vfp_single_dump("VSD", vsd
);
894 #define NEG_MULTIPLY (1 << 0)
895 #define NEG_SUBTRACT (1 << 1)
898 vfp_single_multiply_accumulate(int sd
, int sn
, s32 m
, u32 fpscr
, u32 negate
, char *func
)
900 struct vfp_single vsd
, vsp
, vsn
, vsm
;
904 v
= vfp_get_float(sn
);
905 pr_debug("VFP: s%u = %08x\n", sn
, v
);
906 vfp_single_unpack(&vsn
, v
);
907 if (vsn
.exponent
== 0 && vsn
.significand
)
908 vfp_single_normalise_denormal(&vsn
);
910 vfp_single_unpack(&vsm
, m
);
911 if (vsm
.exponent
== 0 && vsm
.significand
)
912 vfp_single_normalise_denormal(&vsm
);
914 exceptions
= vfp_single_multiply(&vsp
, &vsn
, &vsm
, fpscr
);
915 if (negate
& NEG_MULTIPLY
)
916 vsp
.sign
= vfp_sign_negate(vsp
.sign
);
918 v
= vfp_get_float(sd
);
919 pr_debug("VFP: s%u = %08x\n", sd
, v
);
920 vfp_single_unpack(&vsn
, v
);
921 if (negate
& NEG_SUBTRACT
)
922 vsn
.sign
= vfp_sign_negate(vsn
.sign
);
924 exceptions
|= vfp_single_add(&vsd
, &vsn
, &vsp
, fpscr
);
926 return vfp_single_normaliseround(sd
, &vsd
, fpscr
, exceptions
, func
);
930 * Standard operations
934 * sd = sd + (sn * sm)
936 static u32
vfp_single_fmac(int sd
, int sn
, s32 m
, u32 fpscr
)
938 return vfp_single_multiply_accumulate(sd
, sn
, m
, fpscr
, 0, "fmac");
942 * sd = sd - (sn * sm)
944 static u32
vfp_single_fnmac(int sd
, int sn
, s32 m
, u32 fpscr
)
946 return vfp_single_multiply_accumulate(sd
, sn
, m
, fpscr
, NEG_MULTIPLY
, "fnmac");
950 * sd = -sd + (sn * sm)
952 static u32
vfp_single_fmsc(int sd
, int sn
, s32 m
, u32 fpscr
)
954 return vfp_single_multiply_accumulate(sd
, sn
, m
, fpscr
, NEG_SUBTRACT
, "fmsc");
958 * sd = -sd - (sn * sm)
960 static u32
vfp_single_fnmsc(int sd
, int sn
, s32 m
, u32 fpscr
)
962 return vfp_single_multiply_accumulate(sd
, sn
, m
, fpscr
, NEG_SUBTRACT
| NEG_MULTIPLY
, "fnmsc");
968 static u32
vfp_single_fmul(int sd
, int sn
, s32 m
, u32 fpscr
)
970 struct vfp_single vsd
, vsn
, vsm
;
972 s32 n
= vfp_get_float(sn
);
974 pr_debug("VFP: s%u = %08x\n", sn
, n
);
976 vfp_single_unpack(&vsn
, n
);
977 if (vsn
.exponent
== 0 && vsn
.significand
)
978 vfp_single_normalise_denormal(&vsn
);
980 vfp_single_unpack(&vsm
, m
);
981 if (vsm
.exponent
== 0 && vsm
.significand
)
982 vfp_single_normalise_denormal(&vsm
);
984 exceptions
= vfp_single_multiply(&vsd
, &vsn
, &vsm
, fpscr
);
985 return vfp_single_normaliseround(sd
, &vsd
, fpscr
, exceptions
, "fmul");
991 static u32
vfp_single_fnmul(int sd
, int sn
, s32 m
, u32 fpscr
)
993 struct vfp_single vsd
, vsn
, vsm
;
995 s32 n
= vfp_get_float(sn
);
997 pr_debug("VFP: s%u = %08x\n", sn
, n
);
999 vfp_single_unpack(&vsn
, n
);
1000 if (vsn
.exponent
== 0 && vsn
.significand
)
1001 vfp_single_normalise_denormal(&vsn
);
1003 vfp_single_unpack(&vsm
, m
);
1004 if (vsm
.exponent
== 0 && vsm
.significand
)
1005 vfp_single_normalise_denormal(&vsm
);
1007 exceptions
= vfp_single_multiply(&vsd
, &vsn
, &vsm
, fpscr
);
1008 vsd
.sign
= vfp_sign_negate(vsd
.sign
);
1009 return vfp_single_normaliseround(sd
, &vsd
, fpscr
, exceptions
, "fnmul");
1015 static u32
vfp_single_fadd(int sd
, int sn
, s32 m
, u32 fpscr
)
1017 struct vfp_single vsd
, vsn
, vsm
;
1019 s32 n
= vfp_get_float(sn
);
1021 pr_debug("VFP: s%u = %08x\n", sn
, n
);
1024 * Unpack and normalise denormals.
1026 vfp_single_unpack(&vsn
, n
);
1027 if (vsn
.exponent
== 0 && vsn
.significand
)
1028 vfp_single_normalise_denormal(&vsn
);
1030 vfp_single_unpack(&vsm
, m
);
1031 if (vsm
.exponent
== 0 && vsm
.significand
)
1032 vfp_single_normalise_denormal(&vsm
);
1034 exceptions
= vfp_single_add(&vsd
, &vsn
, &vsm
, fpscr
);
1036 return vfp_single_normaliseround(sd
, &vsd
, fpscr
, exceptions
, "fadd");
1042 static u32
vfp_single_fsub(int sd
, int sn
, s32 m
, u32 fpscr
)
1045 * Subtraction is addition with one sign inverted.
1047 return vfp_single_fadd(sd
, sn
, vfp_single_packed_negate(m
), fpscr
);
1053 static u32
vfp_single_fdiv(int sd
, int sn
, s32 m
, u32 fpscr
)
1055 struct vfp_single vsd
, vsn
, vsm
;
1057 s32 n
= vfp_get_float(sn
);
1060 pr_debug("VFP: s%u = %08x\n", sn
, n
);
1062 vfp_single_unpack(&vsn
, n
);
1063 vfp_single_unpack(&vsm
, m
);
1065 vsd
.sign
= vsn
.sign
^ vsm
.sign
;
1067 tn
= vfp_single_type(&vsn
);
1068 tm
= vfp_single_type(&vsm
);
1083 * If n and m are infinity, the result is invalid
1084 * If n and m are zero, the result is invalid
1086 if (tm
& tn
& (VFP_INFINITY
|VFP_ZERO
))
1090 * If n is infinity, the result is infinity
1092 if (tn
& VFP_INFINITY
)
1096 * If m is zero, raise div0 exception
1102 * If m is infinity, or n is zero, the result is zero
1104 if (tm
& VFP_INFINITY
|| tn
& VFP_ZERO
)
1107 if (tn
& VFP_DENORMAL
)
1108 vfp_single_normalise_denormal(&vsn
);
1109 if (tm
& VFP_DENORMAL
)
1110 vfp_single_normalise_denormal(&vsm
);
1113 * Ok, we have two numbers, we can perform division.
1115 vsd
.exponent
= vsn
.exponent
- vsm
.exponent
+ 127 - 1;
1116 vsm
.significand
<<= 1;
1117 if (vsm
.significand
<= (2 * vsn
.significand
)) {
1118 vsn
.significand
>>= 1;
1122 u64 significand
= (u64
)vsn
.significand
<< 32;
1123 do_div(significand
, vsm
.significand
);
1124 vsd
.significand
= significand
;
1126 if ((vsd
.significand
& 0x3f) == 0)
1127 vsd
.significand
|= ((u64
)vsm
.significand
* vsd
.significand
!= (u64
)vsn
.significand
<< 32);
1129 return vfp_single_normaliseround(sd
, &vsd
, fpscr
, 0, "fdiv");
1132 exceptions
= vfp_propagate_nan(&vsd
, &vsn
, &vsm
, fpscr
);
1134 vfp_put_float(sd
, vfp_single_pack(&vsd
));
1138 exceptions
= vfp_propagate_nan(&vsd
, &vsm
, &vsn
, fpscr
);
1143 vsd
.significand
= 0;
1147 exceptions
= FPSCR_DZC
;
1150 vsd
.significand
= 0;
1154 vfp_put_float(sd
, vfp_single_pack(&vfp_single_default_qnan
));
1158 static u32 (* const fop_fns
[16])(int sd
, int sn
, s32 m
, u32 fpscr
) = {
1159 [FOP_TO_IDX(FOP_FMAC
)] = vfp_single_fmac
,
1160 [FOP_TO_IDX(FOP_FNMAC
)] = vfp_single_fnmac
,
1161 [FOP_TO_IDX(FOP_FMSC
)] = vfp_single_fmsc
,
1162 [FOP_TO_IDX(FOP_FNMSC
)] = vfp_single_fnmsc
,
1163 [FOP_TO_IDX(FOP_FMUL
)] = vfp_single_fmul
,
1164 [FOP_TO_IDX(FOP_FNMUL
)] = vfp_single_fnmul
,
1165 [FOP_TO_IDX(FOP_FADD
)] = vfp_single_fadd
,
1166 [FOP_TO_IDX(FOP_FSUB
)] = vfp_single_fsub
,
1167 [FOP_TO_IDX(FOP_FDIV
)] = vfp_single_fdiv
,
1170 #define FREG_BANK(x) ((x) & 0x18)
1171 #define FREG_IDX(x) ((x) & 7)
1173 u32
vfp_single_cpdo(u32 inst
, u32 fpscr
)
1175 u32 op
= inst
& FOP_MASK
;
1177 unsigned int sd
= vfp_get_sd(inst
);
1178 unsigned int sn
= vfp_get_sn(inst
);
1179 unsigned int sm
= vfp_get_sm(inst
);
1180 unsigned int vecitr
, veclen
, vecstride
;
1181 u32 (*fop
)(int, int, s32
, u32
);
1183 veclen
= fpscr
& FPSCR_LENGTH_MASK
;
1184 vecstride
= 1 + ((fpscr
& FPSCR_STRIDE_MASK
) == FPSCR_STRIDE_MASK
);
1187 * If destination bank is zero, vector length is always '1'.
1188 * ARM DDI0100F C5.1.3, C5.3.2.
1190 if (FREG_BANK(sd
) == 0)
1193 pr_debug("VFP: vecstride=%u veclen=%u\n", vecstride
,
1194 (veclen
>> FPSCR_LENGTH_BIT
) + 1);
1196 fop
= (op
== FOP_EXT
) ? fop_extfns
[FEXT_TO_IDX(inst
)] : fop_fns
[FOP_TO_IDX(op
)];
1200 for (vecitr
= 0; vecitr
<= veclen
; vecitr
+= 1 << FPSCR_LENGTH_BIT
) {
1201 s32 m
= vfp_get_float(sm
);
1205 pr_debug("VFP: itr%d (s%u) = op[%u] (s%u=%08x)\n",
1206 vecitr
>> FPSCR_LENGTH_BIT
, sd
, sn
, sm
, m
);
1208 pr_debug("VFP: itr%d (s%u) = (s%u) op[%u] (s%u=%08x)\n",
1209 vecitr
>> FPSCR_LENGTH_BIT
, sd
, sn
,
1210 FOP_TO_IDX(op
), sm
, m
);
1212 except
= fop(sd
, sn
, m
, fpscr
);
1213 pr_debug("VFP: itr%d: exceptions=%08x\n",
1214 vecitr
>> FPSCR_LENGTH_BIT
, except
);
1216 exceptions
|= except
;
1219 * This ensures that comparisons only operate on scalars;
1220 * comparisons always return with one FPSCR status bit set.
1222 if (except
& (FPSCR_N
|FPSCR_Z
|FPSCR_C
|FPSCR_V
))
1226 * CHECK: It appears to be undefined whether we stop when
1227 * we encounter an exception. We continue.
1230 sd
= FREG_BANK(sd
) + ((FREG_IDX(sd
) + vecstride
) & 7);
1231 sn
= FREG_BANK(sn
) + ((FREG_IDX(sn
) + vecstride
) & 7);
1232 if (FREG_BANK(sm
) != 0)
1233 sm
= FREG_BANK(sm
) + ((FREG_IDX(sm
) + vecstride
) & 7);