2 * TI DaVinci DM365 EVM board support
4 * Copyright (C) 2009 Texas Instruments Incorporated
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 #include <linux/kernel.h>
16 #include <linux/init.h>
17 #include <linux/err.h>
18 #include <linux/i2c.h>
20 #include <linux/clk.h>
21 #include <linux/i2c/at24.h>
22 #include <linux/leds.h>
23 #include <linux/mtd/mtd.h>
24 #include <linux/mtd/partitions.h>
25 #include <linux/mtd/nand.h>
26 #include <linux/input.h>
27 #include <linux/spi/spi.h>
28 #include <linux/spi/eeprom.h>
30 #include <asm/mach-types.h>
31 #include <asm/mach/arch.h>
34 #include <mach/dm365.h>
35 #include <mach/common.h>
37 #include <mach/serial.h>
39 #include <mach/nand.h>
40 #include <mach/keyscan.h>
42 #include <media/tvp514x.h>
44 static inline int have_imager(void)
46 /* REVISIT when it's supported, trigger via Kconfig */
50 static inline int have_tvp7002(void)
52 /* REVISIT when it's supported, trigger via Kconfig */
57 #define DM365_ASYNC_EMIF_CONTROL_BASE 0x01d10000
58 #define DM365_ASYNC_EMIF_DATA_CE0_BASE 0x02000000
59 #define DM365_ASYNC_EMIF_DATA_CE1_BASE 0x04000000
61 #define DM365_EVM_PHY_MASK (0x2)
62 #define DM365_EVM_MDIO_FREQUENCY (2200000) /* PHY bus frequency */
65 * A MAX-II CPLD is used for various board control functions.
67 #define CPLD_OFFSET(a13a8,a2a1) (((a13a8) << 10) + ((a2a1) << 3))
69 #define CPLD_VERSION CPLD_OFFSET(0,0) /* r/o */
70 #define CPLD_TEST CPLD_OFFSET(0,1)
71 #define CPLD_LEDS CPLD_OFFSET(0,2)
72 #define CPLD_MUX CPLD_OFFSET(0,3)
73 #define CPLD_SWITCH CPLD_OFFSET(1,0) /* r/o */
74 #define CPLD_POWER CPLD_OFFSET(1,1)
75 #define CPLD_VIDEO CPLD_OFFSET(1,2)
76 #define CPLD_CARDSTAT CPLD_OFFSET(1,3) /* r/o */
78 #define CPLD_DILC_OUT CPLD_OFFSET(2,0)
79 #define CPLD_DILC_IN CPLD_OFFSET(2,1) /* r/o */
81 #define CPLD_IMG_DIR0 CPLD_OFFSET(2,2)
82 #define CPLD_IMG_MUX0 CPLD_OFFSET(2,3)
83 #define CPLD_IMG_MUX1 CPLD_OFFSET(3,0)
84 #define CPLD_IMG_DIR1 CPLD_OFFSET(3,1)
85 #define CPLD_IMG_MUX2 CPLD_OFFSET(3,2)
86 #define CPLD_IMG_MUX3 CPLD_OFFSET(3,3)
87 #define CPLD_IMG_DIR2 CPLD_OFFSET(4,0)
88 #define CPLD_IMG_MUX4 CPLD_OFFSET(4,1)
89 #define CPLD_IMG_MUX5 CPLD_OFFSET(4,2)
91 #define CPLD_RESETS CPLD_OFFSET(4,3)
93 #define CPLD_CCD_DIR1 CPLD_OFFSET(0x3e,0)
94 #define CPLD_CCD_IO1 CPLD_OFFSET(0x3e,1)
95 #define CPLD_CCD_DIR2 CPLD_OFFSET(0x3e,2)
96 #define CPLD_CCD_IO2 CPLD_OFFSET(0x3e,3)
97 #define CPLD_CCD_DIR3 CPLD_OFFSET(0x3f,0)
98 #define CPLD_CCD_IO3 CPLD_OFFSET(0x3f,1)
100 static void __iomem
*cpld
;
103 /* NOTE: this is geared for the standard config, with a socketed
104 * 2 GByte Micron NAND (MT29F16G08FAA) using 128KB sectors. If you
105 * swap chips with a different block size, partitioning will
106 * need to be changed. This NAND chip MT29F16G08FAA is the default
107 * NAND shipped with the Spectrum Digital DM365 EVM
109 #define NAND_BLOCK_SIZE SZ_128K
111 static struct mtd_partition davinci_nand_partitions
[] = {
113 /* UBL (a few copies) plus U-Boot */
114 .name
= "bootloader",
116 .size
= 28 * NAND_BLOCK_SIZE
,
117 .mask_flags
= MTD_WRITEABLE
, /* force read-only */
119 /* U-Boot environment */
121 .offset
= MTDPART_OFS_APPEND
,
122 .size
= 2 * NAND_BLOCK_SIZE
,
126 .offset
= MTDPART_OFS_APPEND
,
130 .name
= "filesystem1",
131 .offset
= MTDPART_OFS_APPEND
,
135 .name
= "filesystem2",
136 .offset
= MTDPART_OFS_APPEND
,
137 .size
= MTDPART_SIZ_FULL
,
140 /* two blocks with bad block table (and mirror) at the end */
143 static struct davinci_nand_pdata davinci_nand_data
= {
144 .mask_chipsel
= BIT(14),
145 .parts
= davinci_nand_partitions
,
146 .nr_parts
= ARRAY_SIZE(davinci_nand_partitions
),
147 .ecc_mode
= NAND_ECC_HW
,
148 .options
= NAND_USE_FLASH_BBT
,
152 static struct resource davinci_nand_resources
[] = {
154 .start
= DM365_ASYNC_EMIF_DATA_CE0_BASE
,
155 .end
= DM365_ASYNC_EMIF_DATA_CE0_BASE
+ SZ_32M
- 1,
156 .flags
= IORESOURCE_MEM
,
158 .start
= DM365_ASYNC_EMIF_CONTROL_BASE
,
159 .end
= DM365_ASYNC_EMIF_CONTROL_BASE
+ SZ_4K
- 1,
160 .flags
= IORESOURCE_MEM
,
164 static struct platform_device davinci_nand_device
= {
165 .name
= "davinci_nand",
167 .num_resources
= ARRAY_SIZE(davinci_nand_resources
),
168 .resource
= davinci_nand_resources
,
170 .platform_data
= &davinci_nand_data
,
174 static struct at24_platform_data eeprom_info
= {
175 .byte_len
= (256*1024) / 8,
177 .flags
= AT24_FLAG_ADDR16
,
178 .setup
= davinci_get_mac_addr
,
179 .context
= (void *)0x7f00,
182 static struct snd_platform_data dm365_evm_snd_data
;
184 static struct i2c_board_info i2c_info
[] = {
186 I2C_BOARD_INFO("24c256", 0x50),
187 .platform_data
= &eeprom_info
,
190 I2C_BOARD_INFO("tlv320aic3x", 0x18),
194 static struct davinci_i2c_platform_data i2c_pdata
= {
195 .bus_freq
= 400 /* kHz */,
196 .bus_delay
= 0 /* usec */,
199 static int dm365evm_keyscan_enable(struct device
*dev
)
201 return davinci_cfg_reg(DM365_KEYSCAN
);
204 static unsigned short dm365evm_keymap
[] = {
224 static struct davinci_ks_platform_data dm365evm_ks_data
= {
225 .device_enable
= dm365evm_keyscan_enable
,
226 .keymap
= dm365evm_keymap
,
227 .keymapsize
= ARRAY_SIZE(dm365evm_keymap
),
229 /* Scan period = strobe + interval */
232 .matrix_type
= DAVINCI_KEYSCAN_MATRIX_4X4
,
235 static int cpld_mmc_get_cd(int module
)
240 /* low == card present */
241 return !(__raw_readb(cpld
+ CPLD_CARDSTAT
) & BIT(module
? 4 : 0));
244 static int cpld_mmc_get_ro(int module
)
249 /* high == card's write protect switch active */
250 return !!(__raw_readb(cpld
+ CPLD_CARDSTAT
) & BIT(module
? 5 : 1));
253 static struct davinci_mmc_config dm365evm_mmc_config
= {
254 .get_cd
= cpld_mmc_get_cd
,
255 .get_ro
= cpld_mmc_get_ro
,
257 .max_freq
= 50000000,
258 .caps
= MMC_CAP_MMC_HIGHSPEED
| MMC_CAP_SD_HIGHSPEED
,
259 .version
= MMC_CTLR_VERSION_2
,
262 static void dm365evm_emac_configure(void)
265 * EMAC pins are multiplexed with GPIO and UART
266 * Further details are available at the DM365 ARM
267 * Subsystem Users Guide(sprufg5.pdf) pages 125 - 127
269 davinci_cfg_reg(DM365_EMAC_TX_EN
);
270 davinci_cfg_reg(DM365_EMAC_TX_CLK
);
271 davinci_cfg_reg(DM365_EMAC_COL
);
272 davinci_cfg_reg(DM365_EMAC_TXD3
);
273 davinci_cfg_reg(DM365_EMAC_TXD2
);
274 davinci_cfg_reg(DM365_EMAC_TXD1
);
275 davinci_cfg_reg(DM365_EMAC_TXD0
);
276 davinci_cfg_reg(DM365_EMAC_RXD3
);
277 davinci_cfg_reg(DM365_EMAC_RXD2
);
278 davinci_cfg_reg(DM365_EMAC_RXD1
);
279 davinci_cfg_reg(DM365_EMAC_RXD0
);
280 davinci_cfg_reg(DM365_EMAC_RX_CLK
);
281 davinci_cfg_reg(DM365_EMAC_RX_DV
);
282 davinci_cfg_reg(DM365_EMAC_RX_ER
);
283 davinci_cfg_reg(DM365_EMAC_CRS
);
284 davinci_cfg_reg(DM365_EMAC_MDIO
);
285 davinci_cfg_reg(DM365_EMAC_MDCLK
);
288 * EMAC interrupts are multiplexed with GPIO interrupts
289 * Details are available at the DM365 ARM
290 * Subsystem Users Guide(sprufg5.pdf) pages 133 - 134
292 davinci_cfg_reg(DM365_INT_EMAC_RXTHRESH
);
293 davinci_cfg_reg(DM365_INT_EMAC_RXPULSE
);
294 davinci_cfg_reg(DM365_INT_EMAC_TXPULSE
);
295 davinci_cfg_reg(DM365_INT_EMAC_MISCPULSE
);
298 static void dm365evm_mmc_configure(void)
301 * MMC/SD pins are multiplexed with GPIO and EMIF
302 * Further details are available at the DM365 ARM
303 * Subsystem Users Guide(sprufg5.pdf) pages 118, 128 - 131
305 davinci_cfg_reg(DM365_SD1_CLK
);
306 davinci_cfg_reg(DM365_SD1_CMD
);
307 davinci_cfg_reg(DM365_SD1_DATA3
);
308 davinci_cfg_reg(DM365_SD1_DATA2
);
309 davinci_cfg_reg(DM365_SD1_DATA1
);
310 davinci_cfg_reg(DM365_SD1_DATA0
);
313 static struct tvp514x_platform_data tvp5146_pdata
= {
319 #define TVP514X_STD_ALL (V4L2_STD_NTSC | V4L2_STD_PAL)
320 /* Inputs available at the TVP5146 */
321 static struct v4l2_input tvp5146_inputs
[] = {
325 .type
= V4L2_INPUT_TYPE_CAMERA
,
326 .std
= TVP514X_STD_ALL
,
331 .type
= V4L2_INPUT_TYPE_CAMERA
,
332 .std
= TVP514X_STD_ALL
,
337 * this is the route info for connecting each input to decoder
338 * ouput that goes to vpfe. There is a one to one correspondence
339 * with tvp5146_inputs
341 static struct vpfe_route tvp5146_routes
[] = {
343 .input
= INPUT_CVBS_VI2B
,
344 .output
= OUTPUT_10BIT_422_EMBEDDED_SYNC
,
347 .input
= INPUT_SVIDEO_VI2C_VI1C
,
348 .output
= OUTPUT_10BIT_422_EMBEDDED_SYNC
,
352 static struct vpfe_subdev_info vpfe_sub_devs
[] = {
356 .num_inputs
= ARRAY_SIZE(tvp5146_inputs
),
357 .inputs
= tvp5146_inputs
,
358 .routes
= tvp5146_routes
,
361 .if_type
= VPFE_BT656
,
362 .hdpol
= VPFE_PINPOL_POSITIVE
,
363 .vdpol
= VPFE_PINPOL_POSITIVE
,
366 I2C_BOARD_INFO("tvp5146", 0x5d),
367 .platform_data
= &tvp5146_pdata
,
372 static struct vpfe_config vpfe_cfg
= {
373 .num_subdevs
= ARRAY_SIZE(vpfe_sub_devs
),
374 .sub_devs
= vpfe_sub_devs
,
376 .card_name
= "DM365 EVM",
380 static void __init
evm_init_i2c(void)
382 davinci_init_i2c(&i2c_pdata
);
383 i2c_register_board_info(1, i2c_info
, ARRAY_SIZE(i2c_info
));
386 static struct platform_device
*dm365_evm_nand_devices
[] __initdata
= {
387 &davinci_nand_device
,
390 static inline int have_leds(void)
392 #ifdef CONFIG_LEDS_CLASS
400 struct led_classdev cdev
;
404 static const struct {
408 { "dm365evm::ds2", },
409 { "dm365evm::ds3", },
410 { "dm365evm::ds4", },
411 { "dm365evm::ds5", },
412 { "dm365evm::ds6", "nand-disk", },
413 { "dm365evm::ds7", "mmc1", },
414 { "dm365evm::ds8", "mmc0", },
415 { "dm365evm::ds9", "heartbeat", },
418 static void cpld_led_set(struct led_classdev
*cdev
, enum led_brightness b
)
420 struct cpld_led
*led
= container_of(cdev
, struct cpld_led
, cdev
);
421 u8 reg
= __raw_readb(cpld
+ CPLD_LEDS
);
427 __raw_writeb(reg
, cpld
+ CPLD_LEDS
);
430 static enum led_brightness
cpld_led_get(struct led_classdev
*cdev
)
432 struct cpld_led
*led
= container_of(cdev
, struct cpld_led
, cdev
);
433 u8 reg
= __raw_readb(cpld
+ CPLD_LEDS
);
435 return (reg
& led
->mask
) ? LED_OFF
: LED_FULL
;
438 static int __init
cpld_leds_init(void)
442 if (!have_leds() || !cpld
)
446 __raw_writeb(0xff, cpld
+ CPLD_LEDS
);
447 for (i
= 0; i
< ARRAY_SIZE(cpld_leds
); i
++) {
448 struct cpld_led
*led
;
450 led
= kzalloc(sizeof(*led
), GFP_KERNEL
);
454 led
->cdev
.name
= cpld_leds
[i
].name
;
455 led
->cdev
.brightness_set
= cpld_led_set
;
456 led
->cdev
.brightness_get
= cpld_led_get
;
457 led
->cdev
.default_trigger
= cpld_leds
[i
].trigger
;
460 if (led_classdev_register(NULL
, &led
->cdev
) < 0) {
468 /* run after subsys_initcall() for LEDs */
469 fs_initcall(cpld_leds_init
);
472 static void __init
evm_init_cpld(void)
476 struct clk
*aemif_clk
;
478 /* Make sure we can configure the CPLD through CS1. Then
479 * leave it on for later access to MMC and LED registers.
481 aemif_clk
= clk_get(NULL
, "aemif");
482 if (IS_ERR(aemif_clk
))
484 clk_enable(aemif_clk
);
486 if (request_mem_region(DM365_ASYNC_EMIF_DATA_CE1_BASE
, SECTION_SIZE
,
489 cpld
= ioremap(DM365_ASYNC_EMIF_DATA_CE1_BASE
, SECTION_SIZE
);
491 release_mem_region(DM365_ASYNC_EMIF_DATA_CE1_BASE
,
494 pr_err("ERROR: can't map CPLD\n");
495 clk_disable(aemif_clk
);
499 /* External muxing for some signals */
502 /* Read SW5 to set up NAND + keypad _or_ OneNAND (sync read).
503 * NOTE: SW4 bus width setting must match!
505 if ((__raw_readb(cpld
+ CPLD_SWITCH
) & BIT(5)) == 0) {
506 /* external keypad mux */
509 platform_add_devices(dm365_evm_nand_devices
,
510 ARRAY_SIZE(dm365_evm_nand_devices
));
512 /* no OneNAND support yet */
515 /* Leave external chips in reset when unused. */
516 resets
= BIT(3) | BIT(2) | BIT(1) | BIT(0);
518 /* Static video input config with SN74CBT16214 1-of-3 mux:
519 * - port b1 == tvp7002 (mux lowbits == 1 or 6)
520 * - port b2 == imager (mux lowbits == 2 or 7)
521 * - port b3 == tvp5146 (mux lowbits == 5)
523 * Runtime switching could work too, with limitations.
529 /* externally mux MMC1/ENET/AIC33 to imager */
530 mux
|= BIT(6) | BIT(5) | BIT(3);
532 struct davinci_soc_info
*soc_info
= &davinci_soc_info
;
534 /* we can use MMC1 ... */
535 dm365evm_mmc_configure();
536 davinci_setup_mmc(1, &dm365evm_mmc_config
);
538 /* ... and ENET ... */
539 dm365evm_emac_configure();
540 soc_info
->emac_pdata
->phy_mask
= DM365_EVM_PHY_MASK
;
541 soc_info
->emac_pdata
->mdio_max_freq
= DM365_EVM_MDIO_FREQUENCY
;
547 if (have_tvp7002()) {
550 label
= "tvp7002 HD";
552 /* default to tvp5146 */
555 label
= "tvp5146 SD";
558 __raw_writeb(mux
, cpld
+ CPLD_MUX
);
559 __raw_writeb(resets
, cpld
+ CPLD_RESETS
);
560 pr_info("EVM: %s video input\n", label
);
562 /* REVISIT export switches: NTSC/PAL (SW5.6), EXTRA1 (SW5.2), etc */
565 static struct davinci_uart_config uart_config __initdata
= {
566 .enabled_uarts
= (1 << 0),
569 static void __init
dm365_evm_map_io(void)
571 /* setup input configuration for VPFE input devices */
572 dm365_set_vpfe_config(&vpfe_cfg
);
576 static struct spi_eeprom at25640
= {
577 .byte_len
= SZ_64K
/ 8,
583 static struct spi_board_info dm365_evm_spi_info
[] __initconst
= {
586 .platform_data
= &at25640
,
587 .max_speed_hz
= 10 * 1000 * 1000,
594 static __init
void dm365_evm_init(void)
597 davinci_serial_init(&uart_config
);
599 dm365evm_emac_configure();
600 dm365evm_mmc_configure();
602 davinci_setup_mmc(0, &dm365evm_mmc_config
);
604 /* maybe setup mmc1/etc ... _after_ mmc0 */
607 dm365_init_asp(&dm365_evm_snd_data
);
609 dm365_init_ks(&dm365evm_ks_data
);
611 dm365_init_spi0(BIT(0), dm365_evm_spi_info
,
612 ARRAY_SIZE(dm365_evm_spi_info
));
615 static __init
void dm365_evm_irq_init(void)
620 MACHINE_START(DAVINCI_DM365_EVM
, "DaVinci DM365 EVM")
622 .io_pg_offst
= (__IO_ADDRESS(IO_PHYS
) >> 18) & 0xfffc,
623 .boot_params
= (0x80000100),
624 .map_io
= dm365_evm_map_io
,
625 .init_irq
= dm365_evm_irq_init
,
626 .timer
= &davinci_timer
,
627 .init_machine
= dm365_evm_init
,