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qlcnic: fix cdrp race condition
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / ethernet / qlogic / qlcnic / qlcnic.h
blob2a3e552e9ffbdbfc749b3e5c789aa0b54032b87a
1 /*
2 * QLogic qlcnic NIC Driver
3 * Copyright (c) 2009-2010 QLogic Corporation
4 *
5 * See LICENSE.qlcnic for copyright and licensing details.
6 */
7
8 #ifndef _QLCNIC_H_
9 #define _QLCNIC_H_
10
11 #include <linux/module.h>
12 #include <linux/kernel.h>
13 #include <linux/types.h>
14 #include <linux/ioport.h>
15 #include <linux/pci.h>
16 #include <linux/netdevice.h>
17 #include <linux/etherdevice.h>
18 #include <linux/ip.h>
19 #include <linux/in.h>
20 #include <linux/tcp.h>
21 #include <linux/skbuff.h>
22 #include <linux/firmware.h>
23
24 #include <linux/ethtool.h>
25 #include <linux/mii.h>
26 #include <linux/timer.h>
27
28 #include <linux/vmalloc.h>
29
30 #include <linux/io.h>
31 #include <asm/byteorder.h>
32 #include <linux/bitops.h>
33 #include <linux/if_vlan.h>
34
35 #include "qlcnic_hdr.h"
36
37 #define _QLCNIC_LINUX_MAJOR 5
38 #define _QLCNIC_LINUX_MINOR 0
39 #define _QLCNIC_LINUX_SUBVERSION 22
40 #define QLCNIC_LINUX_VERSIONID "5.0.22"
41 #define QLCNIC_DRV_IDC_VER 0x01
42 #define QLCNIC_DRIVER_VERSION ((_QLCNIC_LINUX_MAJOR << 16) |\
43 (_QLCNIC_LINUX_MINOR << 8) | (_QLCNIC_LINUX_SUBVERSION))
44
45 #define QLCNIC_VERSION_CODE(a, b, c) (((a) << 24) + ((b) << 16) + (c))
46 #define _major(v) (((v) >> 24) & 0xff)
47 #define _minor(v) (((v) >> 16) & 0xff)
48 #define _build(v) ((v) & 0xffff)
49
50 /* version in image has weird encoding:
51 * 7:0 - major
52 * 15:8 - minor
53 * 31:16 - build (little endian)
54 */
55 #define QLCNIC_DECODE_VERSION(v) \
56 QLCNIC_VERSION_CODE(((v) & 0xff), (((v) >> 8) & 0xff), ((v) >> 16))
57
58 #define QLCNIC_MIN_FW_VERSION QLCNIC_VERSION_CODE(4, 4, 2)
59 #define QLCNIC_NUM_FLASH_SECTORS (64)
60 #define QLCNIC_FLASH_SECTOR_SIZE (64 * 1024)
61 #define QLCNIC_FLASH_TOTAL_SIZE (QLCNIC_NUM_FLASH_SECTORS \
62 * QLCNIC_FLASH_SECTOR_SIZE)
63
64 #define RCV_DESC_RINGSIZE(rds_ring) \
65 (sizeof(struct rcv_desc) * (rds_ring)->num_desc)
66 #define RCV_BUFF_RINGSIZE(rds_ring) \
67 (sizeof(struct qlcnic_rx_buffer) * rds_ring->num_desc)
68 #define STATUS_DESC_RINGSIZE(sds_ring) \
69 (sizeof(struct status_desc) * (sds_ring)->num_desc)
70 #define TX_BUFF_RINGSIZE(tx_ring) \
71 (sizeof(struct qlcnic_cmd_buffer) * tx_ring->num_desc)
72 #define TX_DESC_RINGSIZE(tx_ring) \
73 (sizeof(struct cmd_desc_type0) * tx_ring->num_desc)
74
75 #define QLCNIC_P3P_A0 0x50
76 #define QLCNIC_P3P_C0 0x58
77
78 #define QLCNIC_IS_REVISION_P3P(REVISION) (REVISION >= QLCNIC_P3P_A0)
79
80 #define FIRST_PAGE_GROUP_START 0
81 #define FIRST_PAGE_GROUP_END 0x100000
82
83 #define P3P_MAX_MTU (9600)
84 #define P3P_MIN_MTU (68)
85 #define QLCNIC_MAX_ETHERHDR 32 /* This contains some padding */
86
87 #define QLCNIC_P3P_RX_BUF_MAX_LEN (QLCNIC_MAX_ETHERHDR + ETH_DATA_LEN)
88 #define QLCNIC_P3P_RX_JUMBO_BUF_MAX_LEN (QLCNIC_MAX_ETHERHDR + P3P_MAX_MTU)
89 #define QLCNIC_CT_DEFAULT_RX_BUF_LEN 2048
90 #define QLCNIC_LRO_BUFFER_EXTRA 2048
91
92 /* Opcodes to be used with the commands */
93 #define TX_ETHER_PKT 0x01
94 #define TX_TCP_PKT 0x02
95 #define TX_UDP_PKT 0x03
96 #define TX_IP_PKT 0x04
97 #define TX_TCP_LSO 0x05
98 #define TX_TCP_LSO6 0x06
99 #define TX_TCPV6_PKT 0x0b
100 #define TX_UDPV6_PKT 0x0c
101
102 /* Tx defines */
103 #define QLCNIC_MAX_FRAGS_PER_TX 14
104 #define MAX_TSO_HEADER_DESC 2
105 #define MGMT_CMD_DESC_RESV 4
106 #define TX_STOP_THRESH ((MAX_SKB_FRAGS >> 2) + MAX_TSO_HEADER_DESC \
107 + MGMT_CMD_DESC_RESV)
108 #define QLCNIC_MAX_TX_TIMEOUTS 2
109
110 /*
111 * Following are the states of the Phantom. Phantom will set them and
112 * Host will read to check if the fields are correct.
113 */
114 #define PHAN_INITIALIZE_FAILED 0xffff
115 #define PHAN_INITIALIZE_COMPLETE 0xff01
116
117 /* Host writes the following to notify that it has done the init-handshake */
118 #define PHAN_INITIALIZE_ACK 0xf00f
119 #define PHAN_PEG_RCV_INITIALIZED 0xff01
120
121 #define NUM_RCV_DESC_RINGS 3
122
123 #define RCV_RING_NORMAL 0
124 #define RCV_RING_JUMBO 1
125
126 #define MIN_CMD_DESCRIPTORS 64
127 #define MIN_RCV_DESCRIPTORS 64
128 #define MIN_JUMBO_DESCRIPTORS 32
129
130 #define MAX_CMD_DESCRIPTORS 1024
131 #define MAX_RCV_DESCRIPTORS_1G 4096
132 #define MAX_RCV_DESCRIPTORS_10G 8192
133 #define MAX_RCV_DESCRIPTORS_VF 2048
134 #define MAX_JUMBO_RCV_DESCRIPTORS_1G 512
135 #define MAX_JUMBO_RCV_DESCRIPTORS_10G 1024
136
137 #define DEFAULT_RCV_DESCRIPTORS_1G 2048
138 #define DEFAULT_RCV_DESCRIPTORS_10G 4096
139 #define DEFAULT_RCV_DESCRIPTORS_VF 1024
140 #define MAX_RDS_RINGS 2
141
142 #define get_next_index(index, length) \
143 (((index) + 1) & ((length) - 1))
144
145 /*
146 * Following data structures describe the descriptors that will be used.
147 * Added fileds of tcpHdrSize and ipHdrSize, The driver needs to do it only when
148 * we are doing LSO (above the 1500 size packet) only.
149 */
150
151 #define FLAGS_VLAN_TAGGED 0x10
152 #define FLAGS_VLAN_OOB 0x40
153
154 #define qlcnic_set_tx_vlan_tci(cmd_desc, v) \
155 (cmd_desc)->vlan_TCI = cpu_to_le16(v);
156 #define qlcnic_set_cmd_desc_port(cmd_desc, var) \
157 ((cmd_desc)->port_ctxid |= ((var) & 0x0F))
158 #define qlcnic_set_cmd_desc_ctxid(cmd_desc, var) \
159 ((cmd_desc)->port_ctxid |= ((var) << 4 & 0xF0))
160
161 #define qlcnic_set_tx_port(_desc, _port) \
162 ((_desc)->port_ctxid = ((_port) & 0xf) | (((_port) << 4) & 0xf0))
163
164 #define qlcnic_set_tx_flags_opcode(_desc, _flags, _opcode) \
165 ((_desc)->flags_opcode |= \
166 cpu_to_le16(((_flags) & 0x7f) | (((_opcode) & 0x3f) << 7)))
167
168 #define qlcnic_set_tx_frags_len(_desc, _frags, _len) \
169 ((_desc)->nfrags__length = \
170 cpu_to_le32(((_frags) & 0xff) | (((_len) & 0xffffff) << 8)))
171
172 struct cmd_desc_type0 {
173 u8 tcp_hdr_offset; /* For LSO only */
174 u8 ip_hdr_offset; /* For LSO only */
175 __le16 flags_opcode; /* 15:13 unused, 12:7 opcode, 6:0 flags */
176 __le32 nfrags__length; /* 31:8 total len, 7:0 frag count */
177
178 __le64 addr_buffer2;
179
180 __le16 reference_handle;
181 __le16 mss;
182 u8 port_ctxid; /* 7:4 ctxid 3:0 port */
183 u8 total_hdr_length; /* LSO only : MAC+IP+TCP Hdr size */
184 __le16 conn_id; /* IPSec offoad only */
185
186 __le64 addr_buffer3;
187 __le64 addr_buffer1;
188
189 __le16 buffer_length[4];
190
191 __le64 addr_buffer4;
192
193 u8 eth_addr[ETH_ALEN];
194 __le16 vlan_TCI;
195
196 } __attribute__ ((aligned(64)));
197
198 /* Note: sizeof(rcv_desc) should always be a mutliple of 2 */
199 struct rcv_desc {
200 __le16 reference_handle;
201 __le16 reserved;
202 __le32 buffer_length; /* allocated buffer length (usually 2K) */
203 __le64 addr_buffer;
204 } __packed;
205
206 /* opcode field in status_desc */
207 #define QLCNIC_SYN_OFFLOAD 0x03
208 #define QLCNIC_RXPKT_DESC 0x04
209 #define QLCNIC_OLD_RXPKT_DESC 0x3f
210 #define QLCNIC_RESPONSE_DESC 0x05
211 #define QLCNIC_LRO_DESC 0x12
212
213 /* for status field in status_desc */
214 #define STATUS_CKSUM_LOOP 0
215 #define STATUS_CKSUM_OK 2
216
217 /* owner bits of status_desc */
218 #define STATUS_OWNER_HOST (0x1ULL << 56)
219 #define STATUS_OWNER_PHANTOM (0x2ULL << 56)
220
221 /* Status descriptor:
222 0-3 port, 4-7 status, 8-11 type, 12-27 total_length
223 28-43 reference_handle, 44-47 protocol, 48-52 pkt_offset
224 53-55 desc_cnt, 56-57 owner, 58-63 opcode
225 */
226 #define qlcnic_get_sts_port(sts_data) \
227 ((sts_data) & 0x0F)
228 #define qlcnic_get_sts_status(sts_data) \
229 (((sts_data) >> 4) & 0x0F)
230 #define qlcnic_get_sts_type(sts_data) \
231 (((sts_data) >> 8) & 0x0F)
232 #define qlcnic_get_sts_totallength(sts_data) \
233 (((sts_data) >> 12) & 0xFFFF)
234 #define qlcnic_get_sts_refhandle(sts_data) \
235 (((sts_data) >> 28) & 0xFFFF)
236 #define qlcnic_get_sts_prot(sts_data) \
237 (((sts_data) >> 44) & 0x0F)
238 #define qlcnic_get_sts_pkt_offset(sts_data) \
239 (((sts_data) >> 48) & 0x1F)
240 #define qlcnic_get_sts_desc_cnt(sts_data) \
241 (((sts_data) >> 53) & 0x7)
242 #define qlcnic_get_sts_opcode(sts_data) \
243 (((sts_data) >> 58) & 0x03F)
244
245 #define qlcnic_get_lro_sts_refhandle(sts_data) \
246 ((sts_data) & 0x0FFFF)
247 #define qlcnic_get_lro_sts_length(sts_data) \
248 (((sts_data) >> 16) & 0x0FFFF)
249 #define qlcnic_get_lro_sts_l2_hdr_offset(sts_data) \
250 (((sts_data) >> 32) & 0x0FF)
251 #define qlcnic_get_lro_sts_l4_hdr_offset(sts_data) \
252 (((sts_data) >> 40) & 0x0FF)
253 #define qlcnic_get_lro_sts_timestamp(sts_data) \
254 (((sts_data) >> 48) & 0x1)
255 #define qlcnic_get_lro_sts_type(sts_data) \
256 (((sts_data) >> 49) & 0x7)
257 #define qlcnic_get_lro_sts_push_flag(sts_data) \
258 (((sts_data) >> 52) & 0x1)
259 #define qlcnic_get_lro_sts_seq_number(sts_data) \
260 ((sts_data) & 0x0FFFFFFFF)
261
262
263 struct status_desc {
264 __le64 status_desc_data[2];
265 } __attribute__ ((aligned(16)));
266
267 /* UNIFIED ROMIMAGE */
268 #define QLCNIC_UNI_FW_MIN_SIZE 0xc8000
269 #define QLCNIC_UNI_DIR_SECT_PRODUCT_TBL 0x0
270 #define QLCNIC_UNI_DIR_SECT_BOOTLD 0x6
271 #define QLCNIC_UNI_DIR_SECT_FW 0x7
272
273 /*Offsets */
274 #define QLCNIC_UNI_CHIP_REV_OFF 10
275 #define QLCNIC_UNI_FLAGS_OFF 11
276 #define QLCNIC_UNI_BIOS_VERSION_OFF 12
277 #define QLCNIC_UNI_BOOTLD_IDX_OFF 27
278 #define QLCNIC_UNI_FIRMWARE_IDX_OFF 29
279
280 struct uni_table_desc{
281 u32 findex;
282 u32 num_entries;
283 u32 entry_size;
284 u32 reserved[5];
285 };
286
287 struct uni_data_desc{
288 u32 findex;
289 u32 size;
290 u32 reserved[5];
291 };
292
293 /* Flash Defines and Structures */
294 #define QLCNIC_FLT_LOCATION 0x3F1000
295 #define QLCNIC_B0_FW_IMAGE_REGION 0x74
296 #define QLCNIC_C0_FW_IMAGE_REGION 0x97
297 #define QLCNIC_BOOTLD_REGION 0X72
298 struct qlcnic_flt_header {
299 u16 version;
300 u16 len;
301 u16 checksum;
302 u16 reserved;
303 };
304
305 struct qlcnic_flt_entry {
306 u8 region;
307 u8 reserved0;
308 u8 attrib;
309 u8 reserved1;
310 u32 size;
311 u32 start_addr;
312 u32 end_addr;
313 };
314
315 /* Magic number to let user know flash is programmed */
316 #define QLCNIC_BDINFO_MAGIC 0x12345678
317
318 #define QLCNIC_BRDTYPE_P3P_REF_QG 0x0021
319 #define QLCNIC_BRDTYPE_P3P_HMEZ 0x0022
320 #define QLCNIC_BRDTYPE_P3P_10G_CX4_LP 0x0023
321 #define QLCNIC_BRDTYPE_P3P_4_GB 0x0024
322 #define QLCNIC_BRDTYPE_P3P_IMEZ 0x0025
323 #define QLCNIC_BRDTYPE_P3P_10G_SFP_PLUS 0x0026
324 #define QLCNIC_BRDTYPE_P3P_10000_BASE_T 0x0027
325 #define QLCNIC_BRDTYPE_P3P_XG_LOM 0x0028
326 #define QLCNIC_BRDTYPE_P3P_4_GB_MM 0x0029
327 #define QLCNIC_BRDTYPE_P3P_10G_SFP_CT 0x002a
328 #define QLCNIC_BRDTYPE_P3P_10G_SFP_QT 0x002b
329 #define QLCNIC_BRDTYPE_P3P_10G_CX4 0x0031
330 #define QLCNIC_BRDTYPE_P3P_10G_XFP 0x0032
331 #define QLCNIC_BRDTYPE_P3P_10G_TP 0x0080
332
333 #define QLCNIC_MSIX_TABLE_OFFSET 0x44
334
335 /* Flash memory map */
336 #define QLCNIC_BRDCFG_START 0x4000 /* board config */
337 #define QLCNIC_BOOTLD_START 0x10000 /* bootld */
338 #define QLCNIC_IMAGE_START 0x43000 /* compressed image */
339 #define QLCNIC_USER_START 0x3E8000 /* Firmare info */
340
341 #define QLCNIC_FW_VERSION_OFFSET (QLCNIC_USER_START+0x408)
342 #define QLCNIC_FW_SIZE_OFFSET (QLCNIC_USER_START+0x40c)
343 #define QLCNIC_FW_SERIAL_NUM_OFFSET (QLCNIC_USER_START+0x81c)
344 #define QLCNIC_BIOS_VERSION_OFFSET (QLCNIC_USER_START+0x83c)
345
346 #define QLCNIC_BRDTYPE_OFFSET (QLCNIC_BRDCFG_START+0x8)
347 #define QLCNIC_FW_MAGIC_OFFSET (QLCNIC_BRDCFG_START+0x128)
348
349 #define QLCNIC_FW_MIN_SIZE (0x3fffff)
350 #define QLCNIC_UNIFIED_ROMIMAGE 0
351 #define QLCNIC_FLASH_ROMIMAGE 1
352 #define QLCNIC_UNKNOWN_ROMIMAGE 0xff
353
354 #define QLCNIC_UNIFIED_ROMIMAGE_NAME "phanfw.bin"
355 #define QLCNIC_FLASH_ROMIMAGE_NAME "flash"
356
357 extern char qlcnic_driver_name[];
358
359 /* Number of status descriptors to handle per interrupt */
360 #define MAX_STATUS_HANDLE (64)
361
362 /*
363 * qlcnic_skb_frag{} is to contain mapping info for each SG list. This
364 * has to be freed when DMA is complete. This is part of qlcnic_tx_buffer{}.
365 */
366 struct qlcnic_skb_frag {
367 u64 dma;
368 u64 length;
369 };
370
371 /* Following defines are for the state of the buffers */
372 #define QLCNIC_BUFFER_FREE 0
373 #define QLCNIC_BUFFER_BUSY 1
374
375 /*
376 * There will be one qlcnic_buffer per skb packet. These will be
377 * used to save the dma info for pci_unmap_page()
378 */
379 struct qlcnic_cmd_buffer {
380 struct sk_buff *skb;
381 struct qlcnic_skb_frag frag_array[MAX_SKB_FRAGS + 1];
382 u32 frag_count;
383 };
384
385 /* In rx_buffer, we do not need multiple fragments as is a single buffer */
386 struct qlcnic_rx_buffer {
387 u16 ref_handle;
388 struct sk_buff *skb;
389 struct list_head list;
390 u64 dma;
391 };
392
393 /* Board types */
394 #define QLCNIC_GBE 0x01
395 #define QLCNIC_XGBE 0x02
396
397 /*
398 * Interrupt coalescing defaults. The defaults are for 1500 MTU. It is
399 * adjusted based on configured MTU.
400 */
401 #define QLCNIC_DEFAULT_INTR_COALESCE_RX_TIME_US 3
402 #define QLCNIC_DEFAULT_INTR_COALESCE_RX_PACKETS 256
403
404 #define QLCNIC_INTR_DEFAULT 0x04
405 #define QLCNIC_CONFIG_INTR_COALESCE 3
406
407 struct qlcnic_nic_intr_coalesce {
408 u8 type;
409 u8 sts_ring_mask;
410 u16 rx_packets;
411 u16 rx_time_us;
412 u16 flag;
413 u32 timer_out;
414 };
415
416 struct qlcnic_dump_template_hdr {
417 __le32 type;
418 __le32 offset;
419 __le32 size;
420 __le32 cap_mask;
421 __le32 num_entries;
422 __le32 version;
423 __le32 timestamp;
424 __le32 checksum;
425 __le32 drv_cap_mask;
426 __le32 sys_info[3];
427 __le32 saved_state[16];
428 __le32 cap_sizes[8];
429 __le32 rsvd[0];
430 };
431
432 struct qlcnic_fw_dump {
433 u8 clr; /* flag to indicate if dump is cleared */
434 u8 enable; /* enable/disable dump */
435 u32 size; /* total size of the dump */
436 void *data; /* dump data area */
437 struct qlcnic_dump_template_hdr *tmpl_hdr;
438 };
439
440 /*
441 * One hardware_context{} per adapter
442 * contains interrupt info as well shared hardware info.
443 */
444 struct qlcnic_hardware_context {
445 void __iomem *pci_base0;
446 void __iomem *ocm_win_crb;
447
448 unsigned long pci_len0;
449
450 rwlock_t crb_lock;
451 struct mutex mem_lock;
452
453 u8 revision_id;
454 u8 pci_func;
455 u8 linkup;
456 u8 loopback_state;
457 u16 port_type;
458 u16 board_type;
459
460 struct qlcnic_nic_intr_coalesce coal;
461 struct qlcnic_fw_dump fw_dump;
462 };
463
464 struct qlcnic_adapter_stats {
465 u64 xmitcalled;
466 u64 xmitfinished;
467 u64 rxdropped;
468 u64 txdropped;
469 u64 csummed;
470 u64 rx_pkts;
471 u64 lro_pkts;
472 u64 rxbytes;
473 u64 txbytes;
474 u64 lrobytes;
475 u64 lso_frames;
476 u64 xmit_on;
477 u64 xmit_off;
478 u64 skb_alloc_failure;
479 u64 null_rxbuf;
480 u64 rx_dma_map_error;
481 u64 tx_dma_map_error;
482 };
483
484 /*
485 * Rcv Descriptor Context. One such per Rcv Descriptor. There may
486 * be one Rcv Descriptor for normal packets, one for jumbo and may be others.
487 */
488 struct qlcnic_host_rds_ring {
489 void __iomem *crb_rcv_producer;
490 struct rcv_desc *desc_head;
491 struct qlcnic_rx_buffer *rx_buf_arr;
492 u32 num_desc;
493 u32 producer;
494 u32 dma_size;
495 u32 skb_size;
496 u32 flags;
497 struct list_head free_list;
498 spinlock_t lock;
499 dma_addr_t phys_addr;
500 } ____cacheline_internodealigned_in_smp;
501
502 struct qlcnic_host_sds_ring {
503 u32 consumer;
504 u32 num_desc;
505 void __iomem *crb_sts_consumer;
506
507 struct status_desc *desc_head;
508 struct qlcnic_adapter *adapter;
509 struct napi_struct napi;
510 struct list_head free_list[NUM_RCV_DESC_RINGS];
511
512 void __iomem *crb_intr_mask;
513 int irq;
514
515 dma_addr_t phys_addr;
516 char name[IFNAMSIZ+4];
517 } ____cacheline_internodealigned_in_smp;
518
519 struct qlcnic_host_tx_ring {
520 u32 producer;
521 u32 sw_consumer;
522 u32 num_desc;
523 void __iomem *crb_cmd_producer;
524 struct cmd_desc_type0 *desc_head;
525 struct qlcnic_cmd_buffer *cmd_buf_arr;
526 __le32 *hw_consumer;
527
528 dma_addr_t phys_addr;
529 dma_addr_t hw_cons_phys_addr;
530 struct netdev_queue *txq;
531 } ____cacheline_internodealigned_in_smp;
532
533 /*
534 * Receive context. There is one such structure per instance of the
535 * receive processing. Any state information that is relevant to
536 * the receive, and is must be in this structure. The global data may be
537 * present elsewhere.
538 */
539 struct qlcnic_recv_context {
540 struct qlcnic_host_rds_ring *rds_rings;
541 struct qlcnic_host_sds_ring *sds_rings;
542 u32 state;
543 u16 context_id;
544 u16 virt_port;
545
546 };
547
548 /* HW context creation */
549
550 #define QLCNIC_OS_CRB_RETRY_COUNT 4000
551 #define QLCNIC_CDRP_SIGNATURE_MAKE(pcifn, version) \
552 (((pcifn) & 0xff) | (((version) & 0xff) << 8) | (0xcafe << 16))
553
554 #define QLCNIC_CDRP_CMD_BIT 0x80000000
555
556 /*
557 * All responses must have the QLCNIC_CDRP_CMD_BIT cleared
558 * in the crb QLCNIC_CDRP_CRB_OFFSET.
559 */
560 #define QLCNIC_CDRP_FORM_RSP(rsp) (rsp)
561 #define QLCNIC_CDRP_IS_RSP(rsp) (((rsp) & QLCNIC_CDRP_CMD_BIT) == 0)
562
563 #define QLCNIC_CDRP_RSP_OK 0x00000001
564 #define QLCNIC_CDRP_RSP_FAIL 0x00000002
565 #define QLCNIC_CDRP_RSP_TIMEOUT 0x00000003
566
567 /*
568 * All commands must have the QLCNIC_CDRP_CMD_BIT set in
569 * the crb QLCNIC_CDRP_CRB_OFFSET.
570 */
571 #define QLCNIC_CDRP_FORM_CMD(cmd) (QLCNIC_CDRP_CMD_BIT | (cmd))
572 #define QLCNIC_CDRP_IS_CMD(cmd) (((cmd) & QLCNIC_CDRP_CMD_BIT) != 0)
573
574 #define QLCNIC_CDRP_CMD_SUBMIT_CAPABILITIES 0x00000001
575 #define QLCNIC_CDRP_CMD_READ_MAX_RDS_PER_CTX 0x00000002
576 #define QLCNIC_CDRP_CMD_READ_MAX_SDS_PER_CTX 0x00000003
577 #define QLCNIC_CDRP_CMD_READ_MAX_RULES_PER_CTX 0x00000004
578 #define QLCNIC_CDRP_CMD_READ_MAX_RX_CTX 0x00000005
579 #define QLCNIC_CDRP_CMD_READ_MAX_TX_CTX 0x00000006
580 #define QLCNIC_CDRP_CMD_CREATE_RX_CTX 0x00000007
581 #define QLCNIC_CDRP_CMD_DESTROY_RX_CTX 0x00000008
582 #define QLCNIC_CDRP_CMD_CREATE_TX_CTX 0x00000009
583 #define QLCNIC_CDRP_CMD_DESTROY_TX_CTX 0x0000000a
584 #define QLCNIC_CDRP_CMD_SET_MTU 0x00000012
585 #define QLCNIC_CDRP_CMD_READ_PHY 0x00000013
586 #define QLCNIC_CDRP_CMD_WRITE_PHY 0x00000014
587 #define QLCNIC_CDRP_CMD_READ_HW_REG 0x00000015
588 #define QLCNIC_CDRP_CMD_GET_FLOW_CTL 0x00000016
589 #define QLCNIC_CDRP_CMD_SET_FLOW_CTL 0x00000017
590 #define QLCNIC_CDRP_CMD_READ_MAX_MTU 0x00000018
591 #define QLCNIC_CDRP_CMD_READ_MAX_LRO 0x00000019
592 #define QLCNIC_CDRP_CMD_MAC_ADDRESS 0x0000001f
593
594 #define QLCNIC_CDRP_CMD_GET_PCI_INFO 0x00000020
595 #define QLCNIC_CDRP_CMD_GET_NIC_INFO 0x00000021
596 #define QLCNIC_CDRP_CMD_SET_NIC_INFO 0x00000022
597 #define QLCNIC_CDRP_CMD_GET_ESWITCH_CAPABILITY 0x00000024
598 #define QLCNIC_CDRP_CMD_TOGGLE_ESWITCH 0x00000025
599 #define QLCNIC_CDRP_CMD_GET_ESWITCH_STATUS 0x00000026
600 #define QLCNIC_CDRP_CMD_SET_PORTMIRRORING 0x00000027
601 #define QLCNIC_CDRP_CMD_CONFIGURE_ESWITCH 0x00000028
602 #define QLCNIC_CDRP_CMD_GET_ESWITCH_PORT_CONFIG 0x00000029
603 #define QLCNIC_CDRP_CMD_GET_ESWITCH_STATS 0x0000002a
604 #define QLCNIC_CDRP_CMD_CONFIG_PORT 0x0000002E
605 #define QLCNIC_CDRP_CMD_TEMP_SIZE 0x0000002f
606 #define QLCNIC_CDRP_CMD_GET_TEMP_HDR 0x00000030
607
608 #define QLCNIC_RCODE_SUCCESS 0
609 #define QLCNIC_RCODE_NOT_SUPPORTED 9
610 #define QLCNIC_RCODE_TIMEOUT 17
611 #define QLCNIC_DESTROY_CTX_RESET 0
612
613 /*
614 * Capabilities Announced
615 */
616 #define QLCNIC_CAP0_LEGACY_CONTEXT (1)
617 #define QLCNIC_CAP0_LEGACY_MN (1 << 2)
618 #define QLCNIC_CAP0_LSO (1 << 6)
619 #define QLCNIC_CAP0_JUMBO_CONTIGUOUS (1 << 7)
620 #define QLCNIC_CAP0_LRO_CONTIGUOUS (1 << 8)
621 #define QLCNIC_CAP0_VALIDOFF (1 << 11)
622
623 /*
624 * Context state
625 */
626 #define QLCNIC_HOST_CTX_STATE_FREED 0
627 #define QLCNIC_HOST_CTX_STATE_ACTIVE 2
628
629 /*
630 * Rx context
631 */
632
633 struct qlcnic_hostrq_sds_ring {
634 __le64 host_phys_addr; /* Ring base addr */
635 __le32 ring_size; /* Ring entries */
636 __le16 msi_index;
637 __le16 rsvd; /* Padding */
638 } __packed;
639
640 struct qlcnic_hostrq_rds_ring {
641 __le64 host_phys_addr; /* Ring base addr */
642 __le64 buff_size; /* Packet buffer size */
643 __le32 ring_size; /* Ring entries */
644 __le32 ring_kind; /* Class of ring */
645 } __packed;
646
647 struct qlcnic_hostrq_rx_ctx {
648 __le64 host_rsp_dma_addr; /* Response dma'd here */
649 __le32 capabilities[4]; /* Flag bit vector */
650 __le32 host_int_crb_mode; /* Interrupt crb usage */
651 __le32 host_rds_crb_mode; /* RDS crb usage */
652 /* These ring offsets are relative to data[0] below */
653 __le32 rds_ring_offset; /* Offset to RDS config */
654 __le32 sds_ring_offset; /* Offset to SDS config */
655 __le16 num_rds_rings; /* Count of RDS rings */
656 __le16 num_sds_rings; /* Count of SDS rings */
657 __le16 valid_field_offset;
658 u8 txrx_sds_binding;
659 u8 msix_handler;
660 u8 reserved[128]; /* reserve space for future expansion*/
661 /* MUST BE 64-bit aligned.
662 The following is packed:
663 - N hostrq_rds_rings
664 - N hostrq_sds_rings */
665 char data[0];
666 } __packed;
667
668 struct qlcnic_cardrsp_rds_ring{
669 __le32 host_producer_crb; /* Crb to use */
670 __le32 rsvd1; /* Padding */
671 } __packed;
672
673 struct qlcnic_cardrsp_sds_ring {
674 __le32 host_consumer_crb; /* Crb to use */
675 __le32 interrupt_crb; /* Crb to use */
676 } __packed;
677
678 struct qlcnic_cardrsp_rx_ctx {
679 /* These ring offsets are relative to data[0] below */
680 __le32 rds_ring_offset; /* Offset to RDS config */
681 __le32 sds_ring_offset; /* Offset to SDS config */
682 __le32 host_ctx_state; /* Starting State */
683 __le32 num_fn_per_port; /* How many PCI fn share the port */
684 __le16 num_rds_rings; /* Count of RDS rings */
685 __le16 num_sds_rings; /* Count of SDS rings */
686 __le16 context_id; /* Handle for context */
687 u8 phys_port; /* Physical id of port */
688 u8 virt_port; /* Virtual/Logical id of port */
689 u8 reserved[128]; /* save space for future expansion */
690 /* MUST BE 64-bit aligned.
691 The following is packed:
692 - N cardrsp_rds_rings
693 - N cardrs_sds_rings */
694 char data[0];
695 } __packed;
696
697 #define SIZEOF_HOSTRQ_RX(HOSTRQ_RX, rds_rings, sds_rings) \
698 (sizeof(HOSTRQ_RX) + \
699 (rds_rings)*(sizeof(struct qlcnic_hostrq_rds_ring)) + \
700 (sds_rings)*(sizeof(struct qlcnic_hostrq_sds_ring)))
701
702 #define SIZEOF_CARDRSP_RX(CARDRSP_RX, rds_rings, sds_rings) \
703 (sizeof(CARDRSP_RX) + \
704 (rds_rings)*(sizeof(struct qlcnic_cardrsp_rds_ring)) + \
705 (sds_rings)*(sizeof(struct qlcnic_cardrsp_sds_ring)))
706
707 /*
708 * Tx context
709 */
710
711 struct qlcnic_hostrq_cds_ring {
712 __le64 host_phys_addr; /* Ring base addr */
713 __le32 ring_size; /* Ring entries */
714 __le32 rsvd; /* Padding */
715 } __packed;
716
717 struct qlcnic_hostrq_tx_ctx {
718 __le64 host_rsp_dma_addr; /* Response dma'd here */
719 __le64 cmd_cons_dma_addr; /* */
720 __le64 dummy_dma_addr; /* */
721 __le32 capabilities[4]; /* Flag bit vector */
722 __le32 host_int_crb_mode; /* Interrupt crb usage */
723 __le32 rsvd1; /* Padding */
724 __le16 rsvd2; /* Padding */
725 __le16 interrupt_ctl;
726 __le16 msi_index;
727 __le16 rsvd3; /* Padding */
728 struct qlcnic_hostrq_cds_ring cds_ring; /* Desc of cds ring */
729 u8 reserved[128]; /* future expansion */
730 } __packed;
731
732 struct qlcnic_cardrsp_cds_ring {
733 __le32 host_producer_crb; /* Crb to use */
734 __le32 interrupt_crb; /* Crb to use */
735 } __packed;
736
737 struct qlcnic_cardrsp_tx_ctx {
738 __le32 host_ctx_state; /* Starting state */
739 __le16 context_id; /* Handle for context */
740 u8 phys_port; /* Physical id of port */
741 u8 virt_port; /* Virtual/Logical id of port */
742 struct qlcnic_cardrsp_cds_ring cds_ring; /* Card cds settings */
743 u8 reserved[128]; /* future expansion */
744 } __packed;
745
746 #define SIZEOF_HOSTRQ_TX(HOSTRQ_TX) (sizeof(HOSTRQ_TX))
747 #define SIZEOF_CARDRSP_TX(CARDRSP_TX) (sizeof(CARDRSP_TX))
748
749 /* CRB */
750
751 #define QLCNIC_HOST_RDS_CRB_MODE_UNIQUE 0
752 #define QLCNIC_HOST_RDS_CRB_MODE_SHARED 1
753 #define QLCNIC_HOST_RDS_CRB_MODE_CUSTOM 2
754 #define QLCNIC_HOST_RDS_CRB_MODE_MAX 3
755
756 #define QLCNIC_HOST_INT_CRB_MODE_UNIQUE 0
757 #define QLCNIC_HOST_INT_CRB_MODE_SHARED 1
758 #define QLCNIC_HOST_INT_CRB_MODE_NORX 2
759 #define QLCNIC_HOST_INT_CRB_MODE_NOTX 3
760 #define QLCNIC_HOST_INT_CRB_MODE_NORXTX 4
761
762
763 /* MAC */
764
765 #define MC_COUNT_P3P 38
766
767 #define QLCNIC_MAC_NOOP 0
768 #define QLCNIC_MAC_ADD 1
769 #define QLCNIC_MAC_DEL 2
770 #define QLCNIC_MAC_VLAN_ADD 3
771 #define QLCNIC_MAC_VLAN_DEL 4
772
773 struct qlcnic_mac_list_s {
774 struct list_head list;
775 uint8_t mac_addr[ETH_ALEN+2];
776 };
777
778 #define QLCNIC_HOST_REQUEST 0x13
779 #define QLCNIC_REQUEST 0x14
780
781 #define QLCNIC_MAC_EVENT 0x1
782
783 #define QLCNIC_IP_UP 2
784 #define QLCNIC_IP_DOWN 3
785
786 #define QLCNIC_ILB_MODE 0x1
787 #define QLCNIC_ELB_MODE 0x2
788
789 #define QLCNIC_LINKEVENT 0x1
790 #define QLCNIC_LB_RESPONSE 0x2
791 #define QLCNIC_IS_LB_CONFIGURED(VAL) \
792 (VAL == (QLCNIC_LINKEVENT | QLCNIC_LB_RESPONSE))
793
794 /*
795 * Driver --> Firmware
796 */
797 #define QLCNIC_H2C_OPCODE_CONFIG_RSS 0x1
798 #define QLCNIC_H2C_OPCODE_CONFIG_INTR_COALESCE 0x3
799 #define QLCNIC_H2C_OPCODE_CONFIG_LED 0x4
800 #define QLCNIC_H2C_OPCODE_LRO_REQUEST 0x7
801 #define QLCNIC_H2C_OPCODE_SET_MAC_RECEIVE_MODE 0xc
802 #define QLCNIC_H2C_OPCODE_CONFIG_IPADDR 0x12
803
804 #define QLCNIC_H2C_OPCODE_GET_LINKEVENT 0x15
805 #define QLCNIC_H2C_OPCODE_CONFIG_BRIDGING 0x17
806 #define QLCNIC_H2C_OPCODE_CONFIG_HW_LRO 0x18
807 #define QLCNIC_H2C_OPCODE_CONFIG_LOOPBACK 0x13
808
809 /*
810 * Firmware --> Driver
811 */
812
813 #define QLCNIC_C2H_OPCODE_CONFIG_LOOPBACK 0x8f
814 #define QLCNIC_C2H_OPCODE_GET_LINKEVENT_RESPONSE 141
815
816 #define VPORT_MISS_MODE_DROP 0 /* drop all unmatched */
817 #define VPORT_MISS_MODE_ACCEPT_ALL 1 /* accept all packets */
818 #define VPORT_MISS_MODE_ACCEPT_MULTI 2 /* accept unmatched multicast */
819
820 #define QLCNIC_LRO_REQUEST_CLEANUP 4
821
822 /* Capabilites received */
823 #define QLCNIC_FW_CAPABILITY_TSO BIT_1
824 #define QLCNIC_FW_CAPABILITY_BDG BIT_8
825 #define QLCNIC_FW_CAPABILITY_FVLANTX BIT_9
826 #define QLCNIC_FW_CAPABILITY_HW_LRO BIT_10
827 #define QLCNIC_FW_CAPABILITY_MULTI_LOOPBACK BIT_27
828
829 /* module types */
830 #define LINKEVENT_MODULE_NOT_PRESENT 1
831 #define LINKEVENT_MODULE_OPTICAL_UNKNOWN 2
832 #define LINKEVENT_MODULE_OPTICAL_SRLR 3
833 #define LINKEVENT_MODULE_OPTICAL_LRM 4
834 #define LINKEVENT_MODULE_OPTICAL_SFP_1G 5
835 #define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE 6
836 #define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN 7
837 #define LINKEVENT_MODULE_TWINAX 8
838
839 #define LINKSPEED_10GBPS 10000
840 #define LINKSPEED_1GBPS 1000
841 #define LINKSPEED_100MBPS 100
842 #define LINKSPEED_10MBPS 10
843
844 #define LINKSPEED_ENCODED_10MBPS 0
845 #define LINKSPEED_ENCODED_100MBPS 1
846 #define LINKSPEED_ENCODED_1GBPS 2
847
848 #define LINKEVENT_AUTONEG_DISABLED 0
849 #define LINKEVENT_AUTONEG_ENABLED 1
850
851 #define LINKEVENT_HALF_DUPLEX 0
852 #define LINKEVENT_FULL_DUPLEX 1
853
854 #define LINKEVENT_LINKSPEED_MBPS 0
855 #define LINKEVENT_LINKSPEED_ENCODED 1
856
857 /* firmware response header:
858 * 63:58 - message type
859 * 57:56 - owner
860 * 55:53 - desc count
861 * 52:48 - reserved
862 * 47:40 - completion id
863 * 39:32 - opcode
864 * 31:16 - error code
865 * 15:00 - reserved
866 */
867 #define qlcnic_get_nic_msg_opcode(msg_hdr) \
868 ((msg_hdr >> 32) & 0xFF)
869
870 struct qlcnic_fw_msg {
871 union {
872 struct {
873 u64 hdr;
874 u64 body[7];
875 };
876 u64 words[8];
877 };
878 };
879
880 struct qlcnic_nic_req {
881 __le64 qhdr;
882 __le64 req_hdr;
883 __le64 words[6];
884 } __packed;
885
886 struct qlcnic_mac_req {
887 u8 op;
888 u8 tag;
889 u8 mac_addr[6];
890 };
891
892 struct qlcnic_vlan_req {
893 __le16 vlan_id;
894 __le16 rsvd[3];
895 } __packed;
896
897 struct qlcnic_ipaddr {
898 __be32 ipv4;
899 __be32 ipv6[4];
900 };
901
902 #define QLCNIC_MSI_ENABLED 0x02
903 #define QLCNIC_MSIX_ENABLED 0x04
904 #define QLCNIC_LRO_ENABLED 0x08
905 #define QLCNIC_LRO_DISABLED 0x00
906 #define QLCNIC_BRIDGE_ENABLED 0X10
907 #define QLCNIC_DIAG_ENABLED 0x20
908 #define QLCNIC_ESWITCH_ENABLED 0x40
909 #define QLCNIC_ADAPTER_INITIALIZED 0x80
910 #define QLCNIC_TAGGING_ENABLED 0x100
911 #define QLCNIC_MACSPOOF 0x200
912 #define QLCNIC_MAC_OVERRIDE_DISABLED 0x400
913 #define QLCNIC_PROMISC_DISABLED 0x800
914 #define QLCNIC_NEED_FLR 0x1000
915 #define QLCNIC_FW_RESET_OWNER 0x2000
916 #define QLCNIC_FW_HANG 0x4000
917 #define QLCNIC_IS_MSI_FAMILY(adapter) \
918 ((adapter)->flags & (QLCNIC_MSI_ENABLED | QLCNIC_MSIX_ENABLED))
919
920 #define QLCNIC_DEF_NUM_STS_DESC_RINGS 4
921 #define QLCNIC_MSIX_TBL_SPACE 8192
922 #define QLCNIC_PCI_REG_MSIX_TBL 0x44
923 #define QLCNIC_MSIX_TBL_PGSIZE 4096
924
925 #define QLCNIC_NETDEV_WEIGHT 128
926 #define QLCNIC_ADAPTER_UP_MAGIC 777
927
928 #define __QLCNIC_FW_ATTACHED 0
929 #define __QLCNIC_DEV_UP 1
930 #define __QLCNIC_RESETTING 2
931 #define __QLCNIC_START_FW 4
932 #define __QLCNIC_AER 5
933 #define __QLCNIC_DIAG_RES_ALLOC 6
934
935 #define QLCNIC_INTERRUPT_TEST 1
936 #define QLCNIC_LOOPBACK_TEST 2
937 #define QLCNIC_LED_TEST 3
938
939 #define QLCNIC_FILTER_AGE 80
940 #define QLCNIC_READD_AGE 20
941 #define QLCNIC_LB_MAX_FILTERS 64
942
943 /* QLCNIC Driver Error Code */
944 #define QLCNIC_FW_NOT_RESPOND 51
945 #define QLCNIC_TEST_IN_PROGRESS 52
946 #define QLCNIC_UNDEFINED_ERROR 53
947 #define QLCNIC_LB_CABLE_NOT_CONN 54
948
949 struct qlcnic_filter {
950 struct hlist_node fnode;
951 u8 faddr[ETH_ALEN];
952 __le16 vlan_id;
953 unsigned long ftime;
954 };
955
956 struct qlcnic_filter_hash {
957 struct hlist_head *fhead;
958 u8 fnum;
959 u8 fmax;
960 };
961
962 struct qlcnic_adapter {
963 struct qlcnic_hardware_context *ahw;
964 struct qlcnic_recv_context *recv_ctx;
965 struct qlcnic_host_tx_ring *tx_ring;
966 struct net_device *netdev;
967 struct pci_dev *pdev;
968
969 unsigned long state;
970 u32 flags;
971
972 u16 num_txd;
973 u16 num_rxd;
974 u16 num_jumbo_rxd;
975 u16 max_rxd;
976 u16 max_jumbo_rxd;
977
978 u8 max_rds_rings;
979 u8 max_sds_rings;
980 u8 msix_supported;
981 u8 portnum;
982 u8 physical_port;
983 u8 reset_context;
984
985 u8 mc_enabled;
986 u8 max_mc_count;
987 u8 fw_wait_cnt;
988 u8 fw_fail_cnt;
989 u8 tx_timeo_cnt;
990 u8 need_fw_reset;
991
992 u8 has_link_events;
993 u8 fw_type;
994 u16 tx_context_id;
995 u16 is_up;
996
997 u16 link_speed;
998 u16 link_duplex;
999 u16 link_autoneg;
1000 u16 module_type;
1001
1002 u16 op_mode;
1003 u16 switch_mode;
1004 u16 max_tx_ques;
1005 u16 max_rx_ques;
1006 u16 max_mtu;
1007 u16 pvid;
1008
1009 u32 fw_hal_version;
1010 u32 capabilities;
1011 u32 irq;
1012 u32 temp;
1013
1014 u32 int_vec_bit;
1015 u32 heartbeat;
1016
1017 u8 max_mac_filters;
1018 u8 dev_state;
1019 u8 diag_test;
1020 char diag_cnt;
1021 u8 reset_ack_timeo;
1022 u8 dev_init_timeo;
1023 u16 msg_enable;
1024
1025 u8 mac_addr[ETH_ALEN];
1026
1027 u64 dev_rst_time;
1028 u8 mac_learn;
1029 unsigned long vlans[BITS_TO_LONGS(VLAN_N_VID)];
1030
1031 struct qlcnic_npar_info *npars;
1032 struct qlcnic_eswitch *eswitch;
1033 struct qlcnic_nic_template *nic_ops;
1034
1035 struct qlcnic_adapter_stats stats;
1036 struct list_head mac_list;
1037
1038 void __iomem *tgt_mask_reg;
1039 void __iomem *tgt_status_reg;
1040 void __iomem *crb_int_state_reg;
1041 void __iomem *isr_int_vec;
1042
1043 struct msix_entry *msix_entries;
1044
1045 struct delayed_work fw_work;
1046
1047
1048 struct qlcnic_filter_hash fhash;
1049
1050 spinlock_t tx_clean_lock;
1051 spinlock_t mac_learn_lock;
1052 __le32 file_prd_off; /*File fw product offset*/
1053 u32 fw_version;
1054 const struct firmware *fw;
1055 };
1056
1057 struct qlcnic_info {
1058 __le16 pci_func;
1059 __le16 op_mode; /* 1 = Priv, 2 = NP, 3 = NP passthru */
1060 __le16 phys_port;
1061 __le16 switch_mode; /* 0 = disabled, 1 = int, 2 = ext */
1062
1063 __le32 capabilities;
1064 u8 max_mac_filters;
1065 u8 reserved1;
1066 __le16 max_mtu;
1067
1068 __le16 max_tx_ques;
1069 __le16 max_rx_ques;
1070 __le16 min_tx_bw;
1071 __le16 max_tx_bw;
1072 u8 reserved2[104];
1073 } __packed;
1074
1075 struct qlcnic_pci_info {
1076 __le16 id; /* pci function id */
1077 __le16 active; /* 1 = Enabled */
1078 __le16 type; /* 1 = NIC, 2 = FCoE, 3 = iSCSI */
1079 __le16 default_port; /* default port number */
1080
1081 __le16 tx_min_bw; /* Multiple of 100mbpc */
1082 __le16 tx_max_bw;
1083 __le16 reserved1[2];
1084
1085 u8 mac[ETH_ALEN];
1086 u8 reserved2[106];
1087 } __packed;
1088
1089 struct qlcnic_npar_info {
1090 u16 pvid;
1091 u16 min_bw;
1092 u16 max_bw;
1093 u8 phy_port;
1094 u8 type;
1095 u8 active;
1096 u8 enable_pm;
1097 u8 dest_npar;
1098 u8 discard_tagged;
1099 u8 mac_override;
1100 u8 mac_anti_spoof;
1101 u8 promisc_mode;
1102 u8 offload_flags;
1103 };
1104
1105 struct qlcnic_eswitch {
1106 u8 port;
1107 u8 active_vports;
1108 u8 active_vlans;
1109 u8 active_ucast_filters;
1110 u8 max_ucast_filters;
1111 u8 max_active_vlans;
1112
1113 u32 flags;
1114 #define QLCNIC_SWITCH_ENABLE BIT_1
1115 #define QLCNIC_SWITCH_VLAN_FILTERING BIT_2
1116 #define QLCNIC_SWITCH_PROMISC_MODE BIT_3
1117 #define QLCNIC_SWITCH_PORT_MIRRORING BIT_4
1118 };
1119
1120
1121 /* Return codes for Error handling */
1122 #define QL_STATUS_INVALID_PARAM -1
1123
1124 #define MAX_BW 100 /* % of link speed */
1125 #define MAX_VLAN_ID 4095
1126 #define MIN_VLAN_ID 2
1127 #define DEFAULT_MAC_LEARN 1
1128
1129 #define IS_VALID_VLAN(vlan) (vlan >= MIN_VLAN_ID && vlan < MAX_VLAN_ID)
1130 #define IS_VALID_BW(bw) (bw <= MAX_BW)
1131
1132 struct qlcnic_pci_func_cfg {
1133 u16 func_type;
1134 u16 min_bw;
1135 u16 max_bw;
1136 u16 port_num;
1137 u8 pci_func;
1138 u8 func_state;
1139 u8 def_mac_addr[6];
1140 };
1141
1142 struct qlcnic_npar_func_cfg {
1143 u32 fw_capab;
1144 u16 port_num;
1145 u16 min_bw;
1146 u16 max_bw;
1147 u16 max_tx_queues;
1148 u16 max_rx_queues;
1149 u8 pci_func;
1150 u8 op_mode;
1151 };
1152
1153 struct qlcnic_pm_func_cfg {
1154 u8 pci_func;
1155 u8 action;
1156 u8 dest_npar;
1157 u8 reserved[5];
1158 };
1159
1160 struct qlcnic_esw_func_cfg {
1161 u16 vlan_id;
1162 u8 op_mode;
1163 u8 op_type;
1164 u8 pci_func;
1165 u8 host_vlan_tag;
1166 u8 promisc_mode;
1167 u8 discard_tagged;
1168 u8 mac_override;
1169 u8 mac_anti_spoof;
1170 u8 offload_flags;
1171 u8 reserved[5];
1172 };
1173
1174 #define QLCNIC_STATS_VERSION 1
1175 #define QLCNIC_STATS_PORT 1
1176 #define QLCNIC_STATS_ESWITCH 2
1177 #define QLCNIC_QUERY_RX_COUNTER 0
1178 #define QLCNIC_QUERY_TX_COUNTER 1
1179 #define QLCNIC_ESW_STATS_NOT_AVAIL 0xffffffffffffffffULL
1180
1181 #define QLCNIC_ADD_ESW_STATS(VAL1, VAL2)\
1182 do { \
1183 if (((VAL1) == QLCNIC_ESW_STATS_NOT_AVAIL) && \
1184 ((VAL2) != QLCNIC_ESW_STATS_NOT_AVAIL)) \
1185 (VAL1) = (VAL2); \
1186 else if (((VAL1) != QLCNIC_ESW_STATS_NOT_AVAIL) && \
1187 ((VAL2) != QLCNIC_ESW_STATS_NOT_AVAIL)) \
1188 (VAL1) += (VAL2); \
1189 } while (0)
1190
1191 struct __qlcnic_esw_statistics {
1192 __le16 context_id;
1193 __le16 version;
1194 __le16 size;
1195 __le16 unused;
1196 __le64 unicast_frames;
1197 __le64 multicast_frames;
1198 __le64 broadcast_frames;
1199 __le64 dropped_frames;
1200 __le64 errors;
1201 __le64 local_frames;
1202 __le64 numbytes;
1203 __le64 rsvd[3];
1204 } __packed;
1205
1206 struct qlcnic_esw_statistics {
1207 struct __qlcnic_esw_statistics rx;
1208 struct __qlcnic_esw_statistics tx;
1209 };
1210
1211 struct qlcnic_common_entry_hdr {
1212 __le32 type;
1213 __le32 offset;
1214 __le32 cap_size;
1215 u8 mask;
1216 u8 rsvd[2];
1217 u8 flags;
1218 } __packed;
1219
1220 struct __crb {
1221 __le32 addr;
1222 u8 stride;
1223 u8 rsvd1[3];
1224 __le32 data_size;
1225 __le32 no_ops;
1226 __le32 rsvd2[4];
1227 } __packed;
1228
1229 struct __ctrl {
1230 __le32 addr;
1231 u8 stride;
1232 u8 index_a;
1233 __le16 timeout;
1234 __le32 data_size;
1235 __le32 no_ops;
1236 u8 opcode;
1237 u8 index_v;
1238 u8 shl_val;
1239 u8 shr_val;
1240 __le32 val1;
1241 __le32 val2;
1242 __le32 val3;
1243 } __packed;
1244
1245 struct __cache {
1246 __le32 addr;
1247 __le16 stride;
1248 __le16 init_tag_val;
1249 __le32 size;
1250 __le32 no_ops;
1251 __le32 ctrl_addr;
1252 __le32 ctrl_val;
1253 __le32 read_addr;
1254 u8 read_addr_stride;
1255 u8 read_addr_num;
1256 u8 rsvd1[2];
1257 } __packed;
1258
1259 struct __ocm {
1260 u8 rsvd[8];
1261 __le32 size;
1262 __le32 no_ops;
1263 u8 rsvd1[8];
1264 __le32 read_addr;
1265 __le32 read_addr_stride;
1266 } __packed;
1267
1268 struct __mem {
1269 u8 rsvd[24];
1270 __le32 addr;
1271 __le32 size;
1272 } __packed;
1273
1274 struct __mux {
1275 __le32 addr;
1276 u8 rsvd[4];
1277 __le32 size;
1278 __le32 no_ops;
1279 __le32 val;
1280 __le32 val_stride;
1281 __le32 read_addr;
1282 u8 rsvd2[4];
1283 } __packed;
1284
1285 struct __queue {
1286 __le32 sel_addr;
1287 __le16 stride;
1288 u8 rsvd[2];
1289 __le32 size;
1290 __le32 no_ops;
1291 u8 rsvd2[8];
1292 __le32 read_addr;
1293 u8 read_addr_stride;
1294 u8 read_addr_cnt;
1295 u8 rsvd3[2];
1296 } __packed;
1297
1298 struct qlcnic_dump_entry {
1299 struct qlcnic_common_entry_hdr hdr;
1300 union {
1301 struct __crb crb;
1302 struct __cache cache;
1303 struct __ocm ocm;
1304 struct __mem mem;
1305 struct __mux mux;
1306 struct __queue que;
1307 struct __ctrl ctrl;
1308 } region;
1309 } __packed;
1310
1311 enum op_codes {
1312 QLCNIC_DUMP_NOP = 0,
1313 QLCNIC_DUMP_READ_CRB = 1,
1314 QLCNIC_DUMP_READ_MUX = 2,
1315 QLCNIC_DUMP_QUEUE = 3,
1316 QLCNIC_DUMP_BRD_CONFIG = 4,
1317 QLCNIC_DUMP_READ_OCM = 6,
1318 QLCNIC_DUMP_PEG_REG = 7,
1319 QLCNIC_DUMP_L1_DTAG = 8,
1320 QLCNIC_DUMP_L1_ITAG = 9,
1321 QLCNIC_DUMP_L1_DATA = 11,
1322 QLCNIC_DUMP_L1_INST = 12,
1323 QLCNIC_DUMP_L2_DTAG = 21,
1324 QLCNIC_DUMP_L2_ITAG = 22,
1325 QLCNIC_DUMP_L2_DATA = 23,
1326 QLCNIC_DUMP_L2_INST = 24,
1327 QLCNIC_DUMP_READ_ROM = 71,
1328 QLCNIC_DUMP_READ_MEM = 72,
1329 QLCNIC_DUMP_READ_CTRL = 98,
1330 QLCNIC_DUMP_TLHDR = 99,
1331 QLCNIC_DUMP_RDEND = 255
1332 };
1333
1334 #define QLCNIC_DUMP_WCRB BIT_0
1335 #define QLCNIC_DUMP_RWCRB BIT_1
1336 #define QLCNIC_DUMP_ANDCRB BIT_2
1337 #define QLCNIC_DUMP_ORCRB BIT_3
1338 #define QLCNIC_DUMP_POLLCRB BIT_4
1339 #define QLCNIC_DUMP_RD_SAVE BIT_5
1340 #define QLCNIC_DUMP_WRT_SAVED BIT_6
1341 #define QLCNIC_DUMP_MOD_SAVE_ST BIT_7
1342 #define QLCNIC_DUMP_SKIP BIT_7
1343
1344 #define QLCNIC_DUMP_MASK_MIN 3
1345 #define QLCNIC_DUMP_MASK_DEF 0x1f
1346 #define QLCNIC_DUMP_MASK_MAX 0xff
1347 #define QLCNIC_FORCE_FW_DUMP_KEY 0xdeadfeed
1348 #define QLCNIC_ENABLE_FW_DUMP 0xaddfeed
1349 #define QLCNIC_DISABLE_FW_DUMP 0xbadfeed
1350 #define QLCNIC_FORCE_FW_RESET 0xdeaddead
1351
1352 struct qlcnic_dump_operations {
1353 enum op_codes opcode;
1354 u32 (*handler)(struct qlcnic_adapter *,
1355 struct qlcnic_dump_entry *, u32 *);
1356 };
1357
1358 int qlcnic_fw_cmd_get_minidump_temp(struct qlcnic_adapter *adapter);
1359 int qlcnic_fw_cmd_set_port(struct qlcnic_adapter *adapter, u32 config);
1360
1361 u32 qlcnic_hw_read_wx_2M(struct qlcnic_adapter *adapter, ulong off);
1362 int qlcnic_hw_write_wx_2M(struct qlcnic_adapter *, ulong off, u32 data);
1363 int qlcnic_pci_mem_write_2M(struct qlcnic_adapter *, u64 off, u64 data);
1364 int qlcnic_pci_mem_read_2M(struct qlcnic_adapter *, u64 off, u64 *data);
1365 void qlcnic_pci_camqm_read_2M(struct qlcnic_adapter *, u64, u64 *);
1366 void qlcnic_pci_camqm_write_2M(struct qlcnic_adapter *, u64, u64);
1367
1368 #define ADDR_IN_RANGE(addr, low, high) \
1369 (((addr) < (high)) && ((addr) >= (low)))
1370
1371 #define QLCRD32(adapter, off) \
1372 (qlcnic_hw_read_wx_2M(adapter, off))
1373 #define QLCWR32(adapter, off, val) \
1374 (qlcnic_hw_write_wx_2M(adapter, off, val))
1375
1376 int qlcnic_pcie_sem_lock(struct qlcnic_adapter *, int, u32);
1377 void qlcnic_pcie_sem_unlock(struct qlcnic_adapter *, int);
1378
1379 #define qlcnic_rom_lock(a) \
1380 qlcnic_pcie_sem_lock((a), 2, QLCNIC_ROM_LOCK_ID)
1381 #define qlcnic_rom_unlock(a) \
1382 qlcnic_pcie_sem_unlock((a), 2)
1383 #define qlcnic_phy_lock(a) \
1384 qlcnic_pcie_sem_lock((a), 3, QLCNIC_PHY_LOCK_ID)
1385 #define qlcnic_phy_unlock(a) \
1386 qlcnic_pcie_sem_unlock((a), 3)
1387 #define qlcnic_api_lock(a) \
1388 qlcnic_pcie_sem_lock((a), 5, 0)
1389 #define qlcnic_api_unlock(a) \
1390 qlcnic_pcie_sem_unlock((a), 5)
1391 #define qlcnic_sw_lock(a) \
1392 qlcnic_pcie_sem_lock((a), 6, 0)
1393 #define qlcnic_sw_unlock(a) \
1394 qlcnic_pcie_sem_unlock((a), 6)
1395 #define crb_win_lock(a) \
1396 qlcnic_pcie_sem_lock((a), 7, QLCNIC_CRB_WIN_LOCK_ID)
1397 #define crb_win_unlock(a) \
1398 qlcnic_pcie_sem_unlock((a), 7)
1399
1400 int qlcnic_get_board_info(struct qlcnic_adapter *adapter);
1401 int qlcnic_wol_supported(struct qlcnic_adapter *adapter);
1402 int qlcnic_config_led(struct qlcnic_adapter *adapter, u32 state, u32 rate);
1403 void qlcnic_prune_lb_filters(struct qlcnic_adapter *adapter);
1404 void qlcnic_delete_lb_filters(struct qlcnic_adapter *adapter);
1405 int qlcnic_dump_fw(struct qlcnic_adapter *);
1406
1407 /* Functions from qlcnic_init.c */
1408 int qlcnic_load_firmware(struct qlcnic_adapter *adapter);
1409 int qlcnic_need_fw_reset(struct qlcnic_adapter *adapter);
1410 void qlcnic_request_firmware(struct qlcnic_adapter *adapter);
1411 void qlcnic_release_firmware(struct qlcnic_adapter *adapter);
1412 int qlcnic_pinit_from_rom(struct qlcnic_adapter *adapter);
1413 int qlcnic_setup_idc_param(struct qlcnic_adapter *adapter);
1414 int qlcnic_check_flash_fw_ver(struct qlcnic_adapter *adapter);
1415
1416 int qlcnic_rom_fast_read(struct qlcnic_adapter *adapter, u32 addr, u32 *valp);
1417 int qlcnic_rom_fast_read_words(struct qlcnic_adapter *adapter, int addr,
1418 u8 *bytes, size_t size);
1419 int qlcnic_alloc_sw_resources(struct qlcnic_adapter *adapter);
1420 void qlcnic_free_sw_resources(struct qlcnic_adapter *adapter);
1421
1422 void __iomem *qlcnic_get_ioaddr(struct qlcnic_adapter *, u32);
1423
1424 int qlcnic_alloc_hw_resources(struct qlcnic_adapter *adapter);
1425 void qlcnic_free_hw_resources(struct qlcnic_adapter *adapter);
1426
1427 int qlcnic_fw_create_ctx(struct qlcnic_adapter *adapter);
1428 void qlcnic_fw_destroy_ctx(struct qlcnic_adapter *adapter);
1429
1430 void qlcnic_reset_rx_buffers_list(struct qlcnic_adapter *adapter);
1431 void qlcnic_release_rx_buffers(struct qlcnic_adapter *adapter);
1432 void qlcnic_release_tx_buffers(struct qlcnic_adapter *adapter);
1433
1434 int qlcnic_check_fw_status(struct qlcnic_adapter *adapter);
1435 void qlcnic_watchdog_task(struct work_struct *work);
1436 void qlcnic_post_rx_buffers(struct qlcnic_adapter *adapter,
1437 struct qlcnic_host_rds_ring *rds_ring);
1438 int qlcnic_process_rcv_ring(struct qlcnic_host_sds_ring *sds_ring, int max);
1439 void qlcnic_set_multi(struct net_device *netdev);
1440 void qlcnic_free_mac_list(struct qlcnic_adapter *adapter);
1441 int qlcnic_nic_set_promisc(struct qlcnic_adapter *adapter, u32);
1442 int qlcnic_config_intr_coalesce(struct qlcnic_adapter *adapter);
1443 int qlcnic_config_rss(struct qlcnic_adapter *adapter, int enable);
1444 int qlcnic_config_ipaddr(struct qlcnic_adapter *adapter, __be32 ip, int cmd);
1445 int qlcnic_linkevent_request(struct qlcnic_adapter *adapter, int enable);
1446 void qlcnic_advert_link_change(struct qlcnic_adapter *adapter, int linkup);
1447
1448 int qlcnic_fw_cmd_set_mtu(struct qlcnic_adapter *adapter, int mtu);
1449 int qlcnic_change_mtu(struct net_device *netdev, int new_mtu);
1450 u32 qlcnic_fix_features(struct net_device *netdev, u32 features);
1451 int qlcnic_set_features(struct net_device *netdev, u32 features);
1452 int qlcnic_config_hw_lro(struct qlcnic_adapter *adapter, int enable);
1453 int qlcnic_config_bridged_mode(struct qlcnic_adapter *adapter, u32 enable);
1454 int qlcnic_send_lro_cleanup(struct qlcnic_adapter *adapter);
1455 void qlcnic_update_cmd_producer(struct qlcnic_adapter *adapter,
1456 struct qlcnic_host_tx_ring *tx_ring);
1457 void qlcnic_fetch_mac(struct qlcnic_adapter *, u32, u32, u8, u8 *);
1458 void qlcnic_process_rcv_ring_diag(struct qlcnic_host_sds_ring *sds_ring);
1459 void qlcnic_clear_lb_mode(struct qlcnic_adapter *adapter);
1460 int qlcnic_set_lb_mode(struct qlcnic_adapter *adapter, u8 mode);
1461
1462 /* Functions from qlcnic_ethtool.c */
1463 int qlcnic_check_loopback_buff(unsigned char *data, u8 mac[]);
1464
1465 /* Functions from qlcnic_main.c */
1466 int qlcnic_reset_context(struct qlcnic_adapter *);
1467 u32 qlcnic_issue_cmd(struct qlcnic_adapter *adapter,
1468 u32 pci_fn, u32 version, u32 arg1, u32 arg2, u32 arg3, u32 cmd,
1469 u32 *rd_args[3]);
1470 void qlcnic_diag_free_res(struct net_device *netdev, int max_sds_rings);
1471 int qlcnic_diag_alloc_res(struct net_device *netdev, int test);
1472 netdev_tx_t qlcnic_xmit_frame(struct sk_buff *skb, struct net_device *netdev);
1473 int qlcnic_validate_max_rss(struct net_device *netdev, u8 max_hw, u8 val);
1474 int qlcnic_set_max_rss(struct qlcnic_adapter *adapter, u8 data);
1475 void qlcnic_dev_request_reset(struct qlcnic_adapter *);
1476 void qlcnic_alloc_lb_filters_mem(struct qlcnic_adapter *adapter);
1477
1478 /* Management functions */
1479 int qlcnic_get_mac_address(struct qlcnic_adapter *, u8*);
1480 int qlcnic_get_nic_info(struct qlcnic_adapter *, struct qlcnic_info *, u8);
1481 int qlcnic_set_nic_info(struct qlcnic_adapter *, struct qlcnic_info *);
1482 int qlcnic_get_pci_info(struct qlcnic_adapter *, struct qlcnic_pci_info*);
1483
1484 /* eSwitch management functions */
1485 int qlcnic_config_switch_port(struct qlcnic_adapter *,
1486 struct qlcnic_esw_func_cfg *);
1487 int qlcnic_get_eswitch_port_config(struct qlcnic_adapter *,
1488 struct qlcnic_esw_func_cfg *);
1489 int qlcnic_config_port_mirroring(struct qlcnic_adapter *, u8, u8, u8);
1490 int qlcnic_get_port_stats(struct qlcnic_adapter *, const u8, const u8,
1491 struct __qlcnic_esw_statistics *);
1492 int qlcnic_get_eswitch_stats(struct qlcnic_adapter *, const u8, u8,
1493 struct __qlcnic_esw_statistics *);
1494 int qlcnic_clear_esw_stats(struct qlcnic_adapter *adapter, u8, u8, u8);
1495 extern int qlcnic_config_tso;
1496
1497 /*
1498 * QLOGIC Board information
1499 */
1500
1501 #define QLCNIC_MAX_BOARD_NAME_LEN 100
1502 struct qlcnic_brdinfo {
1503 unsigned short vendor;
1504 unsigned short device;
1505 unsigned short sub_vendor;
1506 unsigned short sub_device;
1507 char short_name[QLCNIC_MAX_BOARD_NAME_LEN];
1508 };
1509
1510 static const struct qlcnic_brdinfo qlcnic_boards[] = {
1511 {0x1077, 0x8020, 0x1077, 0x203,
1512 "8200 Series Single Port 10GbE Converged Network Adapter "
1513 "(TCP/IP Networking)"},
1514 {0x1077, 0x8020, 0x1077, 0x207,
1515 "8200 Series Dual Port 10GbE Converged Network Adapter "
1516 "(TCP/IP Networking)"},
1517 {0x1077, 0x8020, 0x1077, 0x20b,
1518 "3200 Series Dual Port 10Gb Intelligent Ethernet Adapter"},
1519 {0x1077, 0x8020, 0x1077, 0x20c,
1520 "3200 Series Quad Port 1Gb Intelligent Ethernet Adapter"},
1521 {0x1077, 0x8020, 0x1077, 0x20f,
1522 "3200 Series Single Port 10Gb Intelligent Ethernet Adapter"},
1523 {0x1077, 0x8020, 0x103c, 0x3733,
1524 "NC523SFP 10Gb 2-port Server Adapter"},
1525 {0x1077, 0x8020, 0x103c, 0x3346,
1526 "CN1000Q Dual Port Converged Network Adapter"},
1527 {0x1077, 0x8020, 0x1077, 0x210,
1528 "QME8242-k 10GbE Dual Port Mezzanine Card"},
1529 {0x1077, 0x8020, 0x0, 0x0, "cLOM8214 1/10GbE Controller"},
1530 };
1531
1532 #define NUM_SUPPORTED_BOARDS ARRAY_SIZE(qlcnic_boards)
1533
1534 static inline u32 qlcnic_tx_avail(struct qlcnic_host_tx_ring *tx_ring)
1535 {
1536 if (likely(tx_ring->producer < tx_ring->sw_consumer))
1537 return tx_ring->sw_consumer - tx_ring->producer;
1538 else
1539 return tx_ring->sw_consumer + tx_ring->num_desc -
1540 tx_ring->producer;
1541 }
1542
1543 extern const struct ethtool_ops qlcnic_ethtool_ops;
1544
1545 struct qlcnic_nic_template {
1546 int (*config_bridged_mode) (struct qlcnic_adapter *, u32);
1547 int (*config_led) (struct qlcnic_adapter *, u32, u32);
1548 int (*start_firmware) (struct qlcnic_adapter *);
1549 };
1550
1551 #define QLCDB(adapter, lvl, _fmt, _args...) do { \
1552 if (NETIF_MSG_##lvl & adapter->msg_enable) \
1553 printk(KERN_INFO "%s: %s: " _fmt, \
1554 dev_name(&adapter->pdev->dev), \
1555 __func__, ##_args); \
1556 } while (0)
1557
1558 #endif /* __QLCNIC_H_ */
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree