drivers/net/s2io.h

   1 /************************************************************************
   2  * s2io.h: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC
   3  * Copyright(c) 2002-2007 Neterion Inc.
   4
   5  * This software may be used and distributed according to the terms of
   6  * the GNU General Public License (GPL), incorporated herein by reference.
   7  * Drivers based on or derived from this code fall under the GPL and must
   8  * retain the authorship, copyright and license notice.  This file is not
   9  * a complete program and may only be used when the entire operating
  10  * system is licensed under the GPL.
  11  * See the file COPYING in this distribution for more information.
  12  ************************************************************************/
  13 #ifndef _S2IO_H
  14 #define _S2IO_H
  15
  16 #define TBD 0
  17 #define s2BIT(loc)              (0x8000000000000000ULL >> (loc))
  18 #define vBIT(val, loc, sz)      (((u64)val) << (64-loc-sz))
  19 #define INV(d)  ((d&0xff)<<24) | (((d>>8)&0xff)<<16) | (((d>>16)&0xff)<<8)| ((d>>24)&0xff)
  20
  21 #ifndef BOOL
  22 #define BOOL    int
  23 #endif
  24
  25 #ifndef TRUE
  26 #define TRUE    1
  27 #define FALSE   0
  28 #endif
  29
  30 #undef SUCCESS
  31 #define SUCCESS 0
  32 #define FAILURE -1
  33 #define S2IO_MINUS_ONE 0xFFFFFFFFFFFFFFFFULL
  34 #define S2IO_DISABLE_MAC_ENTRY 0xFFFFFFFFFFFFULL
  35 #define S2IO_MAX_PCI_CONFIG_SPACE_REINIT 100
  36 #define S2IO_BIT_RESET 1
  37 #define S2IO_BIT_SET 2
  38 #define CHECKBIT(value, nbit) (value & (1 << nbit))
  39
  40 /* Maximum time to flicker LED when asked to identify NIC using ethtool */
  41 #define MAX_FLICKER_TIME        60000 /* 60 Secs */
  42
  43 /* Maximum outstanding splits to be configured into xena. */
  44 enum {
  45         XENA_ONE_SPLIT_TRANSACTION = 0,
  46         XENA_TWO_SPLIT_TRANSACTION = 1,
  47         XENA_THREE_SPLIT_TRANSACTION = 2,
  48         XENA_FOUR_SPLIT_TRANSACTION = 3,
  49         XENA_EIGHT_SPLIT_TRANSACTION = 4,
  50         XENA_TWELVE_SPLIT_TRANSACTION = 5,
  51         XENA_SIXTEEN_SPLIT_TRANSACTION = 6,
  52         XENA_THIRTYTWO_SPLIT_TRANSACTION = 7
  53 };
  54 #define XENA_MAX_OUTSTANDING_SPLITS(n) (n << 4)
  55
  56 /*  OS concerned variables and constants */
  57 #define WATCH_DOG_TIMEOUT               15*HZ
  58 #define EFILL                           0x1234
  59 #define ALIGN_SIZE                      127
  60 #define PCIX_COMMAND_REGISTER           0x62
  61
  62 /*
  63  * Debug related variables.
  64  */
  65 /* different debug levels. */
  66 #define ERR_DBG         0
  67 #define INIT_DBG        1
  68 #define INFO_DBG        2
  69 #define TX_DBG          3
  70 #define INTR_DBG        4
  71
  72 /* Global variable that defines the present debug level of the driver. */
  73 static int debug_level = ERR_DBG;
  74
  75 /* DEBUG message print. */
  76 #define DBG_PRINT(dbg_level, args...)  if(!(debug_level<dbg_level)) printk(args)
  77
  78 /* Protocol assist features of the NIC */
  79 #define L3_CKSUM_OK 0xFFFF
  80 #define L4_CKSUM_OK 0xFFFF
  81 #define S2IO_JUMBO_SIZE 9600
  82
  83 /* Driver statistics maintained by driver */
  84 struct swStat {
  85         unsigned long long single_ecc_errs;
  86         unsigned long long double_ecc_errs;
  87         unsigned long long parity_err_cnt;
  88         unsigned long long serious_err_cnt;
  89         unsigned long long soft_reset_cnt;
  90         unsigned long long fifo_full_cnt;
  91         unsigned long long ring_full_cnt[8];
  92         /* LRO statistics */
  93         unsigned long long clubbed_frms_cnt;
  94         unsigned long long sending_both;
  95         unsigned long long outof_sequence_pkts;
  96         unsigned long long flush_max_pkts;
  97         unsigned long long sum_avg_pkts_aggregated;
  98         unsigned long long num_aggregations;
  99         /* Other statistics */
 100         unsigned long long mem_alloc_fail_cnt;
 101         unsigned long long pci_map_fail_cnt;
 102         unsigned long long watchdog_timer_cnt;
 103         unsigned long long mem_allocated;
 104         unsigned long long mem_freed;
 105         unsigned long long link_up_cnt;
 106         unsigned long long link_down_cnt;
 107         unsigned long long link_up_time;
 108         unsigned long long link_down_time;
 109
 110         /* Transfer Code statistics */
 111         unsigned long long tx_buf_abort_cnt;
 112         unsigned long long tx_desc_abort_cnt;
 113         unsigned long long tx_parity_err_cnt;
 114         unsigned long long tx_link_loss_cnt;
 115         unsigned long long tx_list_proc_err_cnt;
 116
 117         unsigned long long rx_parity_err_cnt;
 118         unsigned long long rx_abort_cnt;
 119         unsigned long long rx_parity_abort_cnt;
 120         unsigned long long rx_rda_fail_cnt;
 121         unsigned long long rx_unkn_prot_cnt;
 122         unsigned long long rx_fcs_err_cnt;
 123         unsigned long long rx_buf_size_err_cnt;
 124         unsigned long long rx_rxd_corrupt_cnt;
 125         unsigned long long rx_unkn_err_cnt;
 126
 127         /* Error/alarm statistics*/
 128         unsigned long long tda_err_cnt;
 129         unsigned long long pfc_err_cnt;
 130         unsigned long long pcc_err_cnt;
 131         unsigned long long tti_err_cnt;
 132         unsigned long long lso_err_cnt;
 133         unsigned long long tpa_err_cnt;
 134         unsigned long long sm_err_cnt;
 135         unsigned long long mac_tmac_err_cnt;
 136         unsigned long long mac_rmac_err_cnt;
 137         unsigned long long xgxs_txgxs_err_cnt;
 138         unsigned long long xgxs_rxgxs_err_cnt;
 139         unsigned long long rc_err_cnt;
 140         unsigned long long prc_pcix_err_cnt;
 141         unsigned long long rpa_err_cnt;
 142         unsigned long long rda_err_cnt;
 143         unsigned long long rti_err_cnt;
 144         unsigned long long mc_err_cnt;
 145
 146 };
 147
 148 /* Xpak releated alarm and warnings */
 149 struct xpakStat {
 150         u64 alarm_transceiver_temp_high;
 151         u64 alarm_transceiver_temp_low;
 152         u64 alarm_laser_bias_current_high;
 153         u64 alarm_laser_bias_current_low;
 154         u64 alarm_laser_output_power_high;
 155         u64 alarm_laser_output_power_low;
 156         u64 warn_transceiver_temp_high;
 157         u64 warn_transceiver_temp_low;
 158         u64 warn_laser_bias_current_high;
 159         u64 warn_laser_bias_current_low;
 160         u64 warn_laser_output_power_high;
 161         u64 warn_laser_output_power_low;
 162         u64 xpak_regs_stat;
 163         u32 xpak_timer_count;
 164 };
 165
 166
 167 /* The statistics block of Xena */
 168 struct stat_block {
 169 /* Tx MAC statistics counters. */
 170         __le32 tmac_data_octets;
 171         __le32 tmac_frms;
 172         __le64 tmac_drop_frms;
 173         __le32 tmac_bcst_frms;
 174         __le32 tmac_mcst_frms;
 175         __le64 tmac_pause_ctrl_frms;
 176         __le32 tmac_ucst_frms;
 177         __le32 tmac_ttl_octets;
 178         __le32 tmac_any_err_frms;
 179         __le32 tmac_nucst_frms;
 180         __le64 tmac_ttl_less_fb_octets;
 181         __le64 tmac_vld_ip_octets;
 182         __le32 tmac_drop_ip;
 183         __le32 tmac_vld_ip;
 184         __le32 tmac_rst_tcp;
 185         __le32 tmac_icmp;
 186         __le64 tmac_tcp;
 187         __le32 reserved_0;
 188         __le32 tmac_udp;
 189
 190 /* Rx MAC Statistics counters. */
 191         __le32 rmac_data_octets;
 192         __le32 rmac_vld_frms;
 193         __le64 rmac_fcs_err_frms;
 194         __le64 rmac_drop_frms;
 195         __le32 rmac_vld_bcst_frms;
 196         __le32 rmac_vld_mcst_frms;
 197         __le32 rmac_out_rng_len_err_frms;
 198         __le32 rmac_in_rng_len_err_frms;
 199         __le64 rmac_long_frms;
 200         __le64 rmac_pause_ctrl_frms;
 201         __le64 rmac_unsup_ctrl_frms;
 202         __le32 rmac_accepted_ucst_frms;
 203         __le32 rmac_ttl_octets;
 204         __le32 rmac_discarded_frms;
 205         __le32 rmac_accepted_nucst_frms;
 206         __le32 reserved_1;
 207         __le32 rmac_drop_events;
 208         __le64 rmac_ttl_less_fb_octets;
 209         __le64 rmac_ttl_frms;
 210         __le64 reserved_2;
 211         __le32 rmac_usized_frms;
 212         __le32 reserved_3;
 213         __le32 rmac_frag_frms;
 214         __le32 rmac_osized_frms;
 215         __le32 reserved_4;
 216         __le32 rmac_jabber_frms;
 217         __le64 rmac_ttl_64_frms;
 218         __le64 rmac_ttl_65_127_frms;
 219         __le64 reserved_5;
 220         __le64 rmac_ttl_128_255_frms;
 221         __le64 rmac_ttl_256_511_frms;
 222         __le64 reserved_6;
 223         __le64 rmac_ttl_512_1023_frms;
 224         __le64 rmac_ttl_1024_1518_frms;
 225         __le32 rmac_ip;
 226         __le32 reserved_7;
 227         __le64 rmac_ip_octets;
 228         __le32 rmac_drop_ip;
 229         __le32 rmac_hdr_err_ip;
 230         __le32 reserved_8;
 231         __le32 rmac_icmp;
 232         __le64 rmac_tcp;
 233         __le32 rmac_err_drp_udp;
 234         __le32 rmac_udp;
 235         __le64 rmac_xgmii_err_sym;
 236         __le64 rmac_frms_q0;
 237         __le64 rmac_frms_q1;
 238         __le64 rmac_frms_q2;
 239         __le64 rmac_frms_q3;
 240         __le64 rmac_frms_q4;
 241         __le64 rmac_frms_q5;
 242         __le64 rmac_frms_q6;
 243         __le64 rmac_frms_q7;
 244         __le16 rmac_full_q3;
 245         __le16 rmac_full_q2;
 246         __le16 rmac_full_q1;
 247         __le16 rmac_full_q0;
 248         __le16 rmac_full_q7;
 249         __le16 rmac_full_q6;
 250         __le16 rmac_full_q5;
 251         __le16 rmac_full_q4;
 252         __le32 reserved_9;
 253         __le32 rmac_pause_cnt;
 254         __le64 rmac_xgmii_data_err_cnt;
 255         __le64 rmac_xgmii_ctrl_err_cnt;
 256         __le32 rmac_err_tcp;
 257         __le32 rmac_accepted_ip;
 258
 259 /* PCI/PCI-X Read transaction statistics. */
 260         __le32 new_rd_req_cnt;
 261         __le32 rd_req_cnt;
 262         __le32 rd_rtry_cnt;
 263         __le32 new_rd_req_rtry_cnt;
 264
 265 /* PCI/PCI-X Write/Read transaction statistics. */
 266         __le32 wr_req_cnt;
 267         __le32 wr_rtry_rd_ack_cnt;
 268         __le32 new_wr_req_rtry_cnt;
 269         __le32 new_wr_req_cnt;
 270         __le32 wr_disc_cnt;
 271         __le32 wr_rtry_cnt;
 272
 273 /*      PCI/PCI-X Write / DMA Transaction statistics. */
 274         __le32 txp_wr_cnt;
 275         __le32 rd_rtry_wr_ack_cnt;
 276         __le32 txd_wr_cnt;
 277         __le32 txd_rd_cnt;
 278         __le32 rxd_wr_cnt;
 279         __le32 rxd_rd_cnt;
 280         __le32 rxf_wr_cnt;
 281         __le32 txf_rd_cnt;
 282
 283 /* Tx MAC statistics overflow counters. */
 284         __le32 tmac_data_octets_oflow;
 285         __le32 tmac_frms_oflow;
 286         __le32 tmac_bcst_frms_oflow;
 287         __le32 tmac_mcst_frms_oflow;
 288         __le32 tmac_ucst_frms_oflow;
 289         __le32 tmac_ttl_octets_oflow;
 290         __le32 tmac_any_err_frms_oflow;
 291         __le32 tmac_nucst_frms_oflow;
 292         __le64 tmac_vlan_frms;
 293         __le32 tmac_drop_ip_oflow;
 294         __le32 tmac_vld_ip_oflow;
 295         __le32 tmac_rst_tcp_oflow;
 296         __le32 tmac_icmp_oflow;
 297         __le32 tpa_unknown_protocol;
 298         __le32 tmac_udp_oflow;
 299         __le32 reserved_10;
 300         __le32 tpa_parse_failure;
 301
 302 /* Rx MAC Statistics overflow counters. */
 303         __le32 rmac_data_octets_oflow;
 304         __le32 rmac_vld_frms_oflow;
 305         __le32 rmac_vld_bcst_frms_oflow;
 306         __le32 rmac_vld_mcst_frms_oflow;
 307         __le32 rmac_accepted_ucst_frms_oflow;
 308         __le32 rmac_ttl_octets_oflow;
 309         __le32 rmac_discarded_frms_oflow;
 310         __le32 rmac_accepted_nucst_frms_oflow;
 311         __le32 rmac_usized_frms_oflow;
 312         __le32 rmac_drop_events_oflow;
 313         __le32 rmac_frag_frms_oflow;
 314         __le32 rmac_osized_frms_oflow;
 315         __le32 rmac_ip_oflow;
 316         __le32 rmac_jabber_frms_oflow;
 317         __le32 rmac_icmp_oflow;
 318         __le32 rmac_drop_ip_oflow;
 319         __le32 rmac_err_drp_udp_oflow;
 320         __le32 rmac_udp_oflow;
 321         __le32 reserved_11;
 322         __le32 rmac_pause_cnt_oflow;
 323         __le64 rmac_ttl_1519_4095_frms;
 324         __le64 rmac_ttl_4096_8191_frms;
 325         __le64 rmac_ttl_8192_max_frms;
 326         __le64 rmac_ttl_gt_max_frms;
 327         __le64 rmac_osized_alt_frms;
 328         __le64 rmac_jabber_alt_frms;
 329         __le64 rmac_gt_max_alt_frms;
 330         __le64 rmac_vlan_frms;
 331         __le32 rmac_len_discard;
 332         __le32 rmac_fcs_discard;
 333         __le32 rmac_pf_discard;
 334         __le32 rmac_da_discard;
 335         __le32 rmac_red_discard;
 336         __le32 rmac_rts_discard;
 337         __le32 reserved_12;
 338         __le32 rmac_ingm_full_discard;
 339         __le32 reserved_13;
 340         __le32 rmac_accepted_ip_oflow;
 341         __le32 reserved_14;
 342         __le32 link_fault_cnt;
 343         u8  buffer[20];
 344         struct swStat sw_stat;
 345         struct xpakStat xpak_stat;
 346 };
 347
 348 /* Default value for 'vlan_strip_tag' configuration parameter */
 349 #define NO_STRIP_IN_PROMISC 2
 350
 351 /*
 352  * Structures representing different init time configuration
 353  * parameters of the NIC.
 354  */
 355
 356 #define MAX_TX_FIFOS 8
 357 #define MAX_RX_RINGS 8
 358
 359 #define FIFO_DEFAULT_NUM        5
 360 #define FIFO_UDP_MAX_NUM                        2 /* 0 - even, 1 -odd ports */
 361 #define FIFO_OTHER_MAX_NUM                      1
 362
 363
 364 #define MAX_RX_DESC_1  (MAX_RX_RINGS * MAX_RX_BLOCKS_PER_RING * 127 )
 365 #define MAX_RX_DESC_2  (MAX_RX_RINGS * MAX_RX_BLOCKS_PER_RING * 85 )
 366 #define MAX_RX_DESC_3  (MAX_RX_RINGS * MAX_RX_BLOCKS_PER_RING * 85 )
 367 #define MAX_TX_DESC    (MAX_AVAILABLE_TXDS)
 368
 369 /* FIFO mappings for all possible number of fifos configured */
 370 static int fifo_map[][MAX_TX_FIFOS] = {
 371         {0, 0, 0, 0, 0, 0, 0, 0},
 372         {0, 0, 0, 0, 1, 1, 1, 1},
 373         {0, 0, 0, 1, 1, 1, 2, 2},
 374         {0, 0, 1, 1, 2, 2, 3, 3},
 375         {0, 0, 1, 1, 2, 2, 3, 4},
 376         {0, 0, 1, 1, 2, 3, 4, 5},
 377         {0, 0, 1, 2, 3, 4, 5, 6},
 378         {0, 1, 2, 3, 4, 5, 6, 7},
 379 };
 380
 381 static u16 fifo_selector[MAX_TX_FIFOS] = {0, 1, 3, 3, 7, 7, 7, 7};
 382
 383 /* Maintains Per FIFO related information. */
 384 struct tx_fifo_config {
 385 #define MAX_AVAILABLE_TXDS      8192
 386         u32 fifo_len;           /* specifies len of FIFO upto 8192, ie no of TxDLs */
 387 /* Priority definition */
 388 #define TX_FIFO_PRI_0               0   /*Highest */
 389 #define TX_FIFO_PRI_1               1
 390 #define TX_FIFO_PRI_2               2
 391 #define TX_FIFO_PRI_3               3
 392 #define TX_FIFO_PRI_4               4
 393 #define TX_FIFO_PRI_5               5
 394 #define TX_FIFO_PRI_6               6
 395 #define TX_FIFO_PRI_7               7   /*lowest */
 396         u8 fifo_priority;       /* specifies pointer level for FIFO */
 397         /* user should not set twos fifos with same pri */
 398         u8 f_no_snoop;
 399 #define NO_SNOOP_TXD                0x01
 400 #define NO_SNOOP_TXD_BUFFER          0x02
 401 };
 402
 403
 404 /* Maintains per Ring related information */
 405 struct rx_ring_config {
 406         u32 num_rxd;            /*No of RxDs per Rx Ring */
 407 #define RX_RING_PRI_0               0   /* highest */
 408 #define RX_RING_PRI_1               1
 409 #define RX_RING_PRI_2               2
 410 #define RX_RING_PRI_3               3
 411 #define RX_RING_PRI_4               4
 412 #define RX_RING_PRI_5               5
 413 #define RX_RING_PRI_6               6
 414 #define RX_RING_PRI_7               7   /* lowest */
 415
 416         u8 ring_priority;       /*Specifies service priority of ring */
 417         /* OSM should not set any two rings with same priority */
 418         u8 ring_org;            /*Organization of ring */
 419 #define RING_ORG_BUFF1          0x01
 420 #define RX_RING_ORG_BUFF3       0x03
 421 #define RX_RING_ORG_BUFF5       0x05
 422
 423         u8 f_no_snoop;
 424 #define NO_SNOOP_RXD                0x01
 425 #define NO_SNOOP_RXD_BUFFER         0x02
 426 };
 427
 428 /* This structure provides contains values of the tunable parameters
 429  * of the H/W
 430  */
 431 struct config_param {
 432 /* Tx Side */
 433         u32 tx_fifo_num;        /*Number of Tx FIFOs */
 434
 435         /* 0-No steering, 1-Priority steering, 2-Default fifo map */
 436 #define NO_STEERING                             0
 437 #define TX_PRIORITY_STEERING                    0x1
 438 #define TX_DEFAULT_STEERING                     0x2
 439         u8 tx_steering_type;
 440
 441         u8 fifo_mapping[MAX_TX_FIFOS];
 442         struct tx_fifo_config tx_cfg[MAX_TX_FIFOS];     /*Per-Tx FIFO config */
 443         u32 max_txds;           /*Max no. of Tx buffer descriptor per TxDL */
 444         u64 tx_intr_type;
 445 #define INTA    0
 446 #define MSI_X   2
 447         u8 intr_type;
 448         u8 napi;
 449
 450         /* Specifies if Tx Intr is UTILZ or PER_LIST type. */
 451
 452 /* Rx Side */
 453         u32 rx_ring_num;        /*Number of receive rings */
 454 #define MAX_RX_BLOCKS_PER_RING  150
 455
 456         struct rx_ring_config rx_cfg[MAX_RX_RINGS];     /*Per-Rx Ring config */
 457
 458 #define HEADER_ETHERNET_II_802_3_SIZE 14
 459 #define HEADER_802_2_SIZE              3
 460 #define HEADER_SNAP_SIZE               5
 461 #define HEADER_VLAN_SIZE               4
 462
 463 #define MIN_MTU                       46
 464 #define MAX_PYLD                    1500
 465 #define MAX_MTU                     (MAX_PYLD+18)
 466 #define MAX_MTU_VLAN                (MAX_PYLD+22)
 467 #define MAX_PYLD_JUMBO              9600
 468 #define MAX_MTU_JUMBO               (MAX_PYLD_JUMBO+18)
 469 #define MAX_MTU_JUMBO_VLAN          (MAX_PYLD_JUMBO+22)
 470         u16 bus_speed;
 471         int max_mc_addr;        /* xena=64 herc=256 */
 472         int max_mac_addr;       /* xena=16 herc=64 */
 473         int mc_start_offset;    /* xena=16 herc=64 */
 474         u8 multiq;
 475 };
 476
 477 /* Structure representing MAC Addrs */
 478 struct mac_addr {
 479         u8 mac_addr[ETH_ALEN];
 480 };
 481
 482 /* Structure that represent every FIFO element in the BAR1
 483  * Address location.
 484  */
 485 struct TxFIFO_element {
 486         u64 TxDL_Pointer;
 487
 488         u64 List_Control;
 489 #define TX_FIFO_LAST_TXD_NUM( val)     vBIT(val,0,8)
 490 #define TX_FIFO_FIRST_LIST             s2BIT(14)
 491 #define TX_FIFO_LAST_LIST              s2BIT(15)
 492 #define TX_FIFO_FIRSTNLAST_LIST        vBIT(3,14,2)
 493 #define TX_FIFO_SPECIAL_FUNC           s2BIT(23)
 494 #define TX_FIFO_DS_NO_SNOOP            s2BIT(31)
 495 #define TX_FIFO_BUFF_NO_SNOOP          s2BIT(30)
 496 };
 497
 498 /* Tx descriptor structure */
 499 struct TxD {
 500         u64 Control_1;
 501 /* bit mask */
 502 #define TXD_LIST_OWN_XENA       s2BIT(7)
 503 #define TXD_T_CODE              (s2BIT(12)|s2BIT(13)|s2BIT(14)|s2BIT(15))
 504 #define TXD_T_CODE_OK(val)      (|(val & TXD_T_CODE))
 505 #define GET_TXD_T_CODE(val)     ((val & TXD_T_CODE)<<12)
 506 #define TXD_GATHER_CODE         (s2BIT(22) | s2BIT(23))
 507 #define TXD_GATHER_CODE_FIRST   s2BIT(22)
 508 #define TXD_GATHER_CODE_LAST    s2BIT(23)
 509 #define TXD_TCP_LSO_EN          s2BIT(30)
 510 #define TXD_UDP_COF_EN          s2BIT(31)
 511 #define TXD_UFO_EN              s2BIT(31) | s2BIT(30)
 512 #define TXD_TCP_LSO_MSS(val)    vBIT(val,34,14)
 513 #define TXD_UFO_MSS(val)        vBIT(val,34,14)
 514 #define TXD_BUFFER0_SIZE(val)   vBIT(val,48,16)
 515
 516         u64 Control_2;
 517 #define TXD_TX_CKO_CONTROL      (s2BIT(5)|s2BIT(6)|s2BIT(7))
 518 #define TXD_TX_CKO_IPV4_EN      s2BIT(5)
 519 #define TXD_TX_CKO_TCP_EN       s2BIT(6)
 520 #define TXD_TX_CKO_UDP_EN       s2BIT(7)
 521 #define TXD_VLAN_ENABLE         s2BIT(15)
 522 #define TXD_VLAN_TAG(val)       vBIT(val,16,16)
 523 #define TXD_INT_NUMBER(val)     vBIT(val,34,6)
 524 #define TXD_INT_TYPE_PER_LIST   s2BIT(47)
 525 #define TXD_INT_TYPE_UTILZ      s2BIT(46)
 526 #define TXD_SET_MARKER         vBIT(0x6,0,4)
 527
 528         u64 Buffer_Pointer;
 529         u64 Host_Control;       /* reserved for host */
 530 };
 531
 532 /* Structure to hold the phy and virt addr of every TxDL. */
 533 struct list_info_hold {
 534         dma_addr_t list_phy_addr;
 535         void *list_virt_addr;
 536 };
 537
 538 /* Rx descriptor structure for 1 buffer mode */
 539 struct RxD_t {
 540         u64 Host_Control;       /* reserved for host */
 541         u64 Control_1;
 542 #define RXD_OWN_XENA            s2BIT(7)
 543 #define RXD_T_CODE              (s2BIT(12)|s2BIT(13)|s2BIT(14)|s2BIT(15))
 544 #define RXD_FRAME_PROTO         vBIT(0xFFFF,24,8)
 545 #define RXD_FRAME_VLAN_TAG      s2BIT(24)
 546 #define RXD_FRAME_PROTO_IPV4    s2BIT(27)
 547 #define RXD_FRAME_PROTO_IPV6    s2BIT(28)
 548 #define RXD_FRAME_IP_FRAG       s2BIT(29)
 549 #define RXD_FRAME_PROTO_TCP     s2BIT(30)
 550 #define RXD_FRAME_PROTO_UDP     s2BIT(31)
 551 #define TCP_OR_UDP_FRAME        (RXD_FRAME_PROTO_TCP | RXD_FRAME_PROTO_UDP)
 552 #define RXD_GET_L3_CKSUM(val)   ((u16)(val>> 16) & 0xFFFF)
 553 #define RXD_GET_L4_CKSUM(val)   ((u16)(val) & 0xFFFF)
 554
 555         u64 Control_2;
 556 #define THE_RXD_MARK            0x3
 557 #define SET_RXD_MARKER          vBIT(THE_RXD_MARK, 0, 2)
 558 #define GET_RXD_MARKER(ctrl)    ((ctrl & SET_RXD_MARKER) >> 62)
 559
 560 #define MASK_VLAN_TAG           vBIT(0xFFFF,48,16)
 561 #define SET_VLAN_TAG(val)       vBIT(val,48,16)
 562 #define SET_NUM_TAG(val)       vBIT(val,16,32)
 563
 564
 565 };
 566 /* Rx descriptor structure for 1 buffer mode */
 567 struct RxD1 {
 568         struct RxD_t h;
 569
 570 #define MASK_BUFFER0_SIZE_1       vBIT(0x3FFF,2,14)
 571 #define SET_BUFFER0_SIZE_1(val)   vBIT(val,2,14)
 572 #define RXD_GET_BUFFER0_SIZE_1(_Control_2) \
 573         (u16)((_Control_2 & MASK_BUFFER0_SIZE_1) >> 48)
 574         u64 Buffer0_ptr;
 575 };
 576 /* Rx descriptor structure for 3 or 2 buffer mode */
 577
 578 struct RxD3 {
 579         struct RxD_t h;
 580
 581 #define MASK_BUFFER0_SIZE_3       vBIT(0xFF,2,14)
 582 #define MASK_BUFFER1_SIZE_3       vBIT(0xFFFF,16,16)
 583 #define MASK_BUFFER2_SIZE_3       vBIT(0xFFFF,32,16)
 584 #define SET_BUFFER0_SIZE_3(val)   vBIT(val,8,8)
 585 #define SET_BUFFER1_SIZE_3(val)   vBIT(val,16,16)
 586 #define SET_BUFFER2_SIZE_3(val)   vBIT(val,32,16)
 587 #define RXD_GET_BUFFER0_SIZE_3(Control_2) \
 588         (u8)((Control_2 & MASK_BUFFER0_SIZE_3) >> 48)
 589 #define RXD_GET_BUFFER1_SIZE_3(Control_2) \
 590         (u16)((Control_2 & MASK_BUFFER1_SIZE_3) >> 32)
 591 #define RXD_GET_BUFFER2_SIZE_3(Control_2) \
 592         (u16)((Control_2 & MASK_BUFFER2_SIZE_3) >> 16)
 593 #define BUF0_LEN        40
 594 #define BUF1_LEN        1
 595
 596         u64 Buffer0_ptr;
 597         u64 Buffer1_ptr;
 598         u64 Buffer2_ptr;
 599 };
 600
 601
 602 /* Structure that represents the Rx descriptor block which contains
 603  * 128 Rx descriptors.
 604  */
 605 struct RxD_block {
 606 #define MAX_RXDS_PER_BLOCK_1            127
 607         struct RxD1 rxd[MAX_RXDS_PER_BLOCK_1];
 608
 609         u64 reserved_0;
 610 #define END_OF_BLOCK    0xFEFFFFFFFFFFFFFFULL
 611         u64 reserved_1;         /* 0xFEFFFFFFFFFFFFFF to mark last
 612                                  * Rxd in this blk */
 613         u64 reserved_2_pNext_RxD_block; /* Logical ptr to next */
 614         u64 pNext_RxD_Blk_physical;     /* Buff0_ptr.In a 32 bit arch
 615                                          * the upper 32 bits should
 616                                          * be 0 */
 617 };
 618
 619 #define SIZE_OF_BLOCK   4096
 620
 621 #define RXD_MODE_1      0 /* One Buffer mode */
 622 #define RXD_MODE_3B     1 /* Two Buffer mode */
 623
 624 /* Structure to hold virtual addresses of Buf0 and Buf1 in
 625  * 2buf mode. */
 626 struct buffAdd {
 627         void *ba_0_org;
 628         void *ba_1_org;
 629         void *ba_0;
 630         void *ba_1;
 631 };
 632
 633 /* Structure which stores all the MAC control parameters */
 634
 635 /* This structure stores the offset of the RxD in the ring
 636  * from which the Rx Interrupt processor can start picking
 637  * up the RxDs for processing.
 638  */
 639 struct rx_curr_get_info {
 640         u32 block_index;
 641         u32 offset;
 642         u32 ring_len;
 643 };
 644
 645 struct rx_curr_put_info {
 646         u32 block_index;
 647         u32 offset;
 648         u32 ring_len;
 649 };
 650
 651 /* This structure stores the offset of the TxDl in the FIFO
 652  * from which the Tx Interrupt processor can start picking
 653  * up the TxDLs for send complete interrupt processing.
 654  */
 655 struct tx_curr_get_info {
 656         u32 offset;
 657         u32 fifo_len;
 658 };
 659
 660 struct tx_curr_put_info {
 661         u32 offset;
 662         u32 fifo_len;
 663 };
 664
 665 struct rxd_info {
 666         void *virt_addr;
 667         dma_addr_t dma_addr;
 668 };
 669
 670 /* Structure that holds the Phy and virt addresses of the Blocks */
 671 struct rx_block_info {
 672         void *block_virt_addr;
 673         dma_addr_t block_dma_addr;
 674         struct rxd_info *rxds;
 675 };
 676
 677 /* Data structure to represent a LRO session */
 678 struct lro {
 679         struct sk_buff  *parent;
 680         struct sk_buff  *last_frag;
 681         u8              *l2h;
 682         struct iphdr    *iph;
 683         struct tcphdr   *tcph;
 684         u32             tcp_next_seq;
 685         __be32          tcp_ack;
 686         int             total_len;
 687         int             frags_len;
 688         int             sg_num;
 689         int             in_use;
 690         __be16          window;
 691         u16             vlan_tag;
 692         u32             cur_tsval;
 693         __be32          cur_tsecr;
 694         u8              saw_ts;
 695 } ____cacheline_aligned;
 696
 697 /* Ring specific structure */
 698 struct ring_info {
 699         /* The ring number */
 700         int ring_no;
 701
 702         /* per-ring buffer counter */
 703         u32 rx_bufs_left;
 704
 705 #define MAX_LRO_SESSIONS       32
 706         struct lro lro0_n[MAX_LRO_SESSIONS];
 707         u8              lro;
 708
 709         /* copy of sp->rxd_mode flag */
 710         int rxd_mode;
 711
 712         /* Number of rxds per block for the rxd_mode */
 713         int rxd_count;
 714
 715         /* copy of sp pointer */
 716         struct s2io_nic *nic;
 717
 718         /* copy of sp->dev pointer */
 719         struct net_device *dev;
 720
 721         /* copy of sp->pdev pointer */
 722         struct pci_dev *pdev;
 723
 724         /* Per ring napi struct */
 725         struct napi_struct napi;
 726
 727         unsigned long interrupt_count;
 728
 729         /*
 730          *  Place holders for the virtual and physical addresses of
 731          *  all the Rx Blocks
 732          */
 733         struct rx_block_info rx_blocks[MAX_RX_BLOCKS_PER_RING];
 734         int block_count;
 735         int pkt_cnt;
 736
 737         /*
 738          * Put pointer info which indictes which RxD has to be replenished
 739          * with a new buffer.
 740          */
 741         struct rx_curr_put_info rx_curr_put_info;
 742
 743         /*
 744          * Get pointer info which indictes which is the last RxD that was
 745          * processed by the driver.
 746          */
 747         struct rx_curr_get_info rx_curr_get_info;
 748
 749         /* interface MTU value */
 750         unsigned mtu;
 751
 752         /* Buffer Address store. */
 753         struct buffAdd **ba;
 754
 755         /* per-Ring statistics */
 756         unsigned long rx_packets;
 757         unsigned long rx_bytes;
 758 } ____cacheline_aligned;
 759
 760 /* Fifo specific structure */
 761 struct fifo_info {
 762         /* FIFO number */
 763         int fifo_no;
 764
 765         /* Maximum TxDs per TxDL */
 766         int max_txds;
 767
 768         /* Place holder of all the TX List's Phy and Virt addresses. */
 769         struct list_info_hold *list_info;
 770
 771         /*
 772          * Current offset within the tx FIFO where driver would write
 773          * new Tx frame
 774          */
 775         struct tx_curr_put_info tx_curr_put_info;
 776
 777         /*
 778          * Current offset within tx FIFO from where the driver would start freeing
 779          * the buffers
 780          */
 781         struct tx_curr_get_info tx_curr_get_info;
 782 #define FIFO_QUEUE_START 0
 783 #define FIFO_QUEUE_STOP 1
 784         int queue_state;
 785
 786         /* copy of sp->dev pointer */
 787         struct net_device *dev;
 788
 789         /* copy of multiq status */
 790         u8 multiq;
 791
 792         /* Per fifo lock */
 793         spinlock_t tx_lock;
 794
 795         /* Per fifo UFO in band structure */
 796         u64 *ufo_in_band_v;
 797
 798         struct s2io_nic *nic;
 799 } ____cacheline_aligned;
 800
 801 /* Information related to the Tx and Rx FIFOs and Rings of Xena
 802  * is maintained in this structure.
 803  */
 804 struct mac_info {
 805 /* tx side stuff */
 806         /* logical pointer of start of each Tx FIFO */
 807         struct TxFIFO_element __iomem *tx_FIFO_start[MAX_TX_FIFOS];
 808
 809         /* Fifo specific structure */
 810         struct fifo_info fifos[MAX_TX_FIFOS];
 811
 812         /* Save virtual address of TxD page with zero DMA addr(if any) */
 813         void *zerodma_virt_addr;
 814
 815 /* rx side stuff */
 816         /* Ring specific structure */
 817         struct ring_info rings[MAX_RX_RINGS];
 818
 819         u16 rmac_pause_time;
 820         u16 mc_pause_threshold_q0q3;
 821         u16 mc_pause_threshold_q4q7;
 822
 823         void *stats_mem;        /* orignal pointer to allocated mem */
 824         dma_addr_t stats_mem_phy;       /* Physical address of the stat block */
 825         u32 stats_mem_sz;
 826         struct stat_block *stats_info;  /* Logical address of the stat block */
 827 };
 828
 829 /* structure representing the user defined MAC addresses */
 830 struct usr_addr {
 831         char addr[ETH_ALEN];
 832         int usage_cnt;
 833 };
 834
 835 /* Default Tunable parameters of the NIC. */
 836 #define DEFAULT_FIFO_0_LEN 4096
 837 #define DEFAULT_FIFO_1_7_LEN 512
 838 #define SMALL_BLK_CNT   30
 839 #define LARGE_BLK_CNT   100
 840
 841 /*
 842  * Structure to keep track of the MSI-X vectors and the corresponding
 843  * argument registered against each vector
 844  */
 845 #define MAX_REQUESTED_MSI_X     9
 846 struct s2io_msix_entry
 847 {
 848         u16 vector;
 849         u16 entry;
 850         void *arg;
 851
 852         u8 type;
 853 #define        MSIX_ALARM_TYPE         1
 854 #define        MSIX_RING_TYPE          2
 855
 856         u8 in_use;
 857 #define MSIX_REGISTERED_SUCCESS 0xAA
 858 };
 859
 860 struct msix_info_st {
 861         u64 addr;
 862         u64 data;
 863 };
 864
 865 /* These flags represent the devices temporary state */
 866 enum s2io_device_state_t
 867 {
 868         __S2IO_STATE_LINK_TASK=0,
 869         __S2IO_STATE_CARD_UP
 870 };
 871
 872 /* Structure representing one instance of the NIC */
 873 struct s2io_nic {
 874         int rxd_mode;
 875         /*
 876          * Count of packets to be processed in a given iteration, it will be indicated
 877          * by the quota field of the device structure when NAPI is enabled.
 878          */
 879         int pkts_to_process;
 880         struct net_device *dev;
 881         struct mac_info mac_control;
 882         struct config_param config;
 883         struct pci_dev *pdev;
 884         void __iomem *bar0;
 885         void __iomem *bar1;
 886 #define MAX_MAC_SUPPORTED   16
 887 #define MAX_SUPPORTED_MULTICASTS MAX_MAC_SUPPORTED
 888
 889         struct mac_addr def_mac_addr[256];
 890
 891         struct net_device_stats stats;
 892         int high_dma_flag;
 893         int device_enabled_once;
 894
 895         char name[60];
 896
 897         /* Timer that handles I/O errors/exceptions */
 898         struct timer_list alarm_timer;
 899
 900         /* Space to back up the PCI config space */
 901         u32 config_space[256 / sizeof(u32)];
 902
 903 #define PROMISC     1
 904 #define ALL_MULTI   2
 905
 906 #define MAX_ADDRS_SUPPORTED 64
 907         u16 usr_addr_count;
 908         u16 mc_addr_count;
 909         struct usr_addr usr_addrs[256];
 910
 911         u16 m_cast_flg;
 912         u16 all_multi_pos;
 913         u16 promisc_flg;
 914
 915         /*  Id timer, used to blink NIC to physically identify NIC. */
 916         struct timer_list id_timer;
 917
 918         /*  Restart timer, used to restart NIC if the device is stuck and
 919          *  a schedule task that will set the correct Link state once the
 920          *  NIC's PHY has stabilized after a state change.
 921          */
 922         struct work_struct rst_timer_task;
 923         struct work_struct set_link_task;
 924
 925         /* Flag that can be used to turn on or turn off the Rx checksum
 926          * offload feature.
 927          */
 928         int rx_csum;
 929
 930         /* Below variables are used for fifo selection to transmit a packet */
 931         u16 fifo_selector[MAX_TX_FIFOS];
 932
 933         /* Total fifos for tcp packets */
 934         u8 total_tcp_fifos;
 935
 936         /*
 937         * Beginning index of udp for udp packets
 938         * Value will be equal to
 939         * (tx_fifo_num - FIFO_UDP_MAX_NUM - FIFO_OTHER_MAX_NUM)
 940         */
 941         u8 udp_fifo_idx;
 942
 943         u8 total_udp_fifos;
 944
 945         /*
 946          * Beginning index of fifo for all other packets
 947          * Value will be equal to (tx_fifo_num - FIFO_OTHER_MAX_NUM)
 948         */
 949         u8 other_fifo_idx;
 950
 951         struct napi_struct napi;
 952         /*  after blink, the adapter must be restored with original
 953          *  values.
 954          */
 955         u64 adapt_ctrl_org;
 956
 957         /* Last known link state. */
 958         u16 last_link_state;
 959 #define LINK_DOWN       1
 960 #define LINK_UP         2
 961
 962         int task_flag;
 963         unsigned long long start_time;
 964         struct vlan_group *vlgrp;
 965         int vlan_strip_flag;
 966 #define MSIX_FLG                0xA5
 967         int num_entries;
 968         struct msix_entry *entries;
 969         int msi_detected;
 970         wait_queue_head_t msi_wait;
 971         struct s2io_msix_entry *s2io_entries;
 972         char desc[MAX_REQUESTED_MSI_X][25];
 973
 974         int avail_msix_vectors; /* No. of MSI-X vectors granted by system */
 975
 976         struct msix_info_st msix_info[0x3f];
 977
 978 #define XFRAME_I_DEVICE         1
 979 #define XFRAME_II_DEVICE        2
 980         u8 device_type;
 981
 982         unsigned long   clubbed_frms_cnt;
 983         unsigned long   sending_both;
 984         u8              lro;
 985         u16             lro_max_aggr_per_sess;
 986         volatile unsigned long state;
 987         u64             general_int_mask;
 988
 989 #define VPD_STRING_LEN 80
 990         u8  product_name[VPD_STRING_LEN];
 991         u8  serial_num[VPD_STRING_LEN];
 992 };
 993
 994 #define RESET_ERROR 1;
 995 #define CMD_ERROR   2;
 996
 997 /*  OS related system calls */
 998 #ifndef readq
 999 static inline u64 readq(void __iomem *addr)
1000 {
1001         u64 ret = 0;
1002         ret = readl(addr + 4);
1003         ret <<= 32;
1004         ret |= readl(addr);
1005
1006         return ret;
1007 }
1008 #endif
1009
1010 #ifndef writeq
1011 static inline void writeq(u64 val, void __iomem *addr)
1012 {
1013         writel((u32) (val), addr);
1014         writel((u32) (val >> 32), (addr + 4));
1015 }
1016 #endif
1017
1018 /*
1019  * Some registers have to be written in a particular order to
1020  * expect correct hardware operation. The macro SPECIAL_REG_WRITE
1021  * is used to perform such ordered writes. Defines UF (Upper First)
1022  * and LF (Lower First) will be used to specify the required write order.
1023  */
1024 #define UF      1
1025 #define LF      2
1026 static inline void SPECIAL_REG_WRITE(u64 val, void __iomem *addr, int order)
1027 {
1028         u32 ret;
1029
1030         if (order == LF) {
1031                 writel((u32) (val), addr);
1032                 ret = readl(addr);
1033                 writel((u32) (val >> 32), (addr + 4));
1034                 ret = readl(addr + 4);
1035         } else {
1036                 writel((u32) (val >> 32), (addr + 4));
1037                 ret = readl(addr + 4);
1038                 writel((u32) (val), addr);
1039                 ret = readl(addr);
1040         }
1041 }
1042
1043 /*  Interrupt related values of Xena */
1044
1045 #define ENABLE_INTRS    1
1046 #define DISABLE_INTRS   2
1047
1048 /*  Highest level interrupt blocks */
1049 #define TX_PIC_INTR     (0x0001<<0)
1050 #define TX_DMA_INTR     (0x0001<<1)
1051 #define TX_MAC_INTR     (0x0001<<2)
1052 #define TX_XGXS_INTR    (0x0001<<3)
1053 #define TX_TRAFFIC_INTR (0x0001<<4)
1054 #define RX_PIC_INTR     (0x0001<<5)
1055 #define RX_DMA_INTR     (0x0001<<6)
1056 #define RX_MAC_INTR     (0x0001<<7)
1057 #define RX_XGXS_INTR    (0x0001<<8)
1058 #define RX_TRAFFIC_INTR (0x0001<<9)
1059 #define MC_INTR         (0x0001<<10)
1060 #define ENA_ALL_INTRS    (   TX_PIC_INTR     | \
1061                             TX_DMA_INTR     | \
1062                             TX_MAC_INTR     | \
1063                             TX_XGXS_INTR    | \
1064                             TX_TRAFFIC_INTR | \
1065                             RX_PIC_INTR     | \
1066                             RX_DMA_INTR     | \
1067                             RX_MAC_INTR     | \
1068                             RX_XGXS_INTR    | \
1069                             RX_TRAFFIC_INTR | \
1070                             MC_INTR )
1071
1072 /*  Interrupt masks for the general interrupt mask register */
1073 #define DISABLE_ALL_INTRS   0xFFFFFFFFFFFFFFFFULL
1074
1075 #define TXPIC_INT_M         s2BIT(0)
1076 #define TXDMA_INT_M         s2BIT(1)
1077 #define TXMAC_INT_M         s2BIT(2)
1078 #define TXXGXS_INT_M        s2BIT(3)
1079 #define TXTRAFFIC_INT_M     s2BIT(8)
1080 #define PIC_RX_INT_M        s2BIT(32)
1081 #define RXDMA_INT_M         s2BIT(33)
1082 #define RXMAC_INT_M         s2BIT(34)
1083 #define MC_INT_M            s2BIT(35)
1084 #define RXXGXS_INT_M        s2BIT(36)
1085 #define RXTRAFFIC_INT_M     s2BIT(40)
1086
1087 /*  PIC level Interrupts TODO*/
1088
1089 /*  DMA level Inressupts */
1090 #define TXDMA_PFC_INT_M     s2BIT(0)
1091 #define TXDMA_PCC_INT_M     s2BIT(2)
1092
1093 /*  PFC block interrupts */
1094 #define PFC_MISC_ERR_1      s2BIT(0)    /* Interrupt to indicate FIFO full */
1095
1096 /* PCC block interrupts. */
1097 #define PCC_FB_ECC_ERR     vBIT(0xff, 16, 8)    /* Interrupt to indicate
1098                                                    PCC_FB_ECC Error. */
1099
1100 #define RXD_GET_VLAN_TAG(Control_2) (u16)(Control_2 & MASK_VLAN_TAG)
1101 /*
1102  * Prototype declaration.
1103  */
1104 static int __devinit s2io_init_nic(struct pci_dev *pdev,
1105                                    const struct pci_device_id *pre);
1106 static void __devexit s2io_rem_nic(struct pci_dev *pdev);
1107 static int init_shared_mem(struct s2io_nic *sp);
1108 static void free_shared_mem(struct s2io_nic *sp);
1109 static int init_nic(struct s2io_nic *nic);
1110 static int rx_intr_handler(struct ring_info *ring_data, int budget);
1111 static void s2io_txpic_intr_handle(struct s2io_nic *sp);
1112 static void tx_intr_handler(struct fifo_info *fifo_data);
1113 static void s2io_handle_errors(void * dev_id);
1114
1115 static int s2io_starter(void);
1116 static void s2io_closer(void);
1117 static void s2io_tx_watchdog(struct net_device *dev);
1118 static void s2io_set_multicast(struct net_device *dev);
1119 static int rx_osm_handler(struct ring_info *ring_data, struct RxD_t * rxdp);
1120 static void s2io_link(struct s2io_nic * sp, int link);
1121 static void s2io_reset(struct s2io_nic * sp);
1122 static int s2io_poll_msix(struct napi_struct *napi, int budget);
1123 static int s2io_poll_inta(struct napi_struct *napi, int budget);
1124 static void s2io_init_pci(struct s2io_nic * sp);
1125 static int do_s2io_prog_unicast(struct net_device *dev, u8 *addr);
1126 static void s2io_alarm_handle(unsigned long data);
1127 static irqreturn_t
1128 s2io_msix_ring_handle(int irq, void *dev_id);
1129 static irqreturn_t
1130 s2io_msix_fifo_handle(int irq, void *dev_id);
1131 static irqreturn_t s2io_isr(int irq, void *dev_id);
1132 static int verify_xena_quiescence(struct s2io_nic *sp);
1133 static const struct ethtool_ops netdev_ethtool_ops;
1134 static void s2io_set_link(struct work_struct *work);
1135 static int s2io_set_swapper(struct s2io_nic * sp);
1136 static void s2io_card_down(struct s2io_nic *nic);
1137 static int s2io_card_up(struct s2io_nic *nic);
1138 static int wait_for_cmd_complete(void __iomem *addr, u64 busy_bit,
1139                                         int bit_state);
1140 static int s2io_add_isr(struct s2io_nic * sp);
1141 static void s2io_rem_isr(struct s2io_nic * sp);
1142
1143 static void restore_xmsi_data(struct s2io_nic *nic);
1144 static void do_s2io_store_unicast_mc(struct s2io_nic *sp);
1145 static void do_s2io_restore_unicast_mc(struct s2io_nic *sp);
1146 static u64 do_s2io_read_unicast_mc(struct s2io_nic *sp, int offset);
1147 static int do_s2io_add_mc(struct s2io_nic *sp, u8 *addr);
1148 static int do_s2io_add_mac(struct s2io_nic *sp, u64 addr, int offset);
1149 static int do_s2io_delete_unicast_mc(struct s2io_nic *sp, u64 addr);
1150
1151 static int s2io_club_tcp_session(struct ring_info *ring_data, u8 *buffer,
1152         u8 **tcp, u32 *tcp_len, struct lro **lro, struct RxD_t *rxdp,
1153         struct s2io_nic *sp);
1154 static void clear_lro_session(struct lro *lro);
1155 static void queue_rx_frame(struct sk_buff *skb, u16 vlan_tag);
1156 static void update_L3L4_header(struct s2io_nic *sp, struct lro *lro);
1157 static void lro_append_pkt(struct s2io_nic *sp, struct lro *lro,
1158                            struct sk_buff *skb, u32 tcp_len);
1159 static int rts_ds_steer(struct s2io_nic *nic, u8 ds_codepoint, u8 ring);
1160
1161 static pci_ers_result_t s2io_io_error_detected(struct pci_dev *pdev,
1162                                               pci_channel_state_t state);
1163 static pci_ers_result_t s2io_io_slot_reset(struct pci_dev *pdev);
1164 static void s2io_io_resume(struct pci_dev *pdev);
1165
1166 #define s2io_tcp_mss(skb) skb_shinfo(skb)->gso_size
1167 #define s2io_udp_mss(skb) skb_shinfo(skb)->gso_size
1168 #define s2io_offload_type(skb) skb_shinfo(skb)->gso_type
1169
1170 #define S2IO_PARM_INT(X, def_val) \
1171         static unsigned int X = def_val;\
1172                 module_param(X , uint, 0);
1173
1174 #endif                          /* _S2IO_H */