2 * Copyright (C) 2006-2007 Freescale Semicondutor, Inc. All rights reserved.
4 * Author: Shlomi Gridish <gridish@freescale.com>
5 * Li Yang <leoli@freescale.com>
8 * QE UCC Gigabit Ethernet Driver
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
15 #include <linux/kernel.h>
16 #include <linux/init.h>
17 #include <linux/errno.h>
18 #include <linux/slab.h>
19 #include <linux/stddef.h>
20 #include <linux/interrupt.h>
21 #include <linux/netdevice.h>
22 #include <linux/etherdevice.h>
23 #include <linux/skbuff.h>
24 #include <linux/spinlock.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/mii.h>
28 #include <linux/phy.h>
29 #include <linux/workqueue.h>
30 #include <linux/of_mdio.h>
31 #include <linux/of_platform.h>
33 #include <asm/uaccess.h>
36 #include <asm/immap_qe.h>
39 #include <asm/ucc_fast.h>
42 #include "fsl_pq_mdio.h"
46 #define ugeth_printk(level, format, arg...) \
47 printk(level format "\n", ## arg)
49 #define ugeth_dbg(format, arg...) \
50 ugeth_printk(KERN_DEBUG , format , ## arg)
51 #define ugeth_err(format, arg...) \
52 ugeth_printk(KERN_ERR , format , ## arg)
53 #define ugeth_info(format, arg...) \
54 ugeth_printk(KERN_INFO , format , ## arg)
55 #define ugeth_warn(format, arg...) \
56 ugeth_printk(KERN_WARNING , format , ## arg)
58 #ifdef UGETH_VERBOSE_DEBUG
59 #define ugeth_vdbg ugeth_dbg
61 #define ugeth_vdbg(fmt, args...) do { } while (0)
62 #endif /* UGETH_VERBOSE_DEBUG */
63 #define UGETH_MSG_DEFAULT (NETIF_MSG_IFUP << 1 ) - 1
66 static DEFINE_SPINLOCK(ugeth_lock
);
72 module_param_named(debug
, debug
.msg_enable
, int, 0);
73 MODULE_PARM_DESC(debug
, "Debug verbosity level (0=none, ..., 0xffff=all)");
75 static struct ucc_geth_info ugeth_primary_info
= {
77 .bd_mem_part
= MEM_PART_SYSTEM
,
78 .rtsm
= UCC_FAST_SEND_IDLES_BETWEEN_FRAMES
,
79 .max_rx_buf_length
= 1536,
80 /* adjusted at startup if max-speed 1000 */
81 .urfs
= UCC_GETH_URFS_INIT
,
82 .urfet
= UCC_GETH_URFET_INIT
,
83 .urfset
= UCC_GETH_URFSET_INIT
,
84 .utfs
= UCC_GETH_UTFS_INIT
,
85 .utfet
= UCC_GETH_UTFET_INIT
,
86 .utftt
= UCC_GETH_UTFTT_INIT
,
88 .mode
= UCC_FAST_PROTOCOL_MODE_ETHERNET
,
89 .ttx_trx
= UCC_FAST_GUMR_TRANSPARENT_TTX_TRX_NORMAL
,
90 .tenc
= UCC_FAST_TX_ENCODING_NRZ
,
91 .renc
= UCC_FAST_RX_ENCODING_NRZ
,
92 .tcrc
= UCC_FAST_16_BIT_CRC
,
93 .synl
= UCC_FAST_SYNC_LEN_NOT_USED
,
97 .extendedFilteringChainPointer
= ((uint32_t) NULL
),
98 .typeorlen
= 3072 /*1536 */ ,
99 .nonBackToBackIfgPart1
= 0x40,
100 .nonBackToBackIfgPart2
= 0x60,
101 .miminumInterFrameGapEnforcement
= 0x50,
102 .backToBackInterFrameGap
= 0x60,
106 .strictpriorityq
= 0xff,
107 .altBebTruncation
= 0xa,
109 .maxRetransmission
= 0xf,
110 .collisionWindow
= 0x37,
111 .receiveFlowControl
= 1,
112 .transmitFlowControl
= 1,
113 .maxGroupAddrInHash
= 4,
114 .maxIndAddrInHash
= 4,
116 .maxFrameLength
= 1518,
117 .minFrameLength
= 64,
121 .ecamptr
= ((uint32_t) NULL
),
122 .eventRegMask
= UCCE_OTHER
,
123 .pausePeriod
= 0xf000,
124 .interruptcoalescingmaxvalue
= {1, 1, 1, 1, 1, 1, 1, 1},
145 .numStationAddresses
= UCC_GETH_NUM_OF_STATION_ADDRESSES_1
,
146 .largestexternallookupkeysize
=
147 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_NONE
,
148 .statisticsMode
= UCC_GETH_STATISTICS_GATHERING_MODE_HARDWARE
|
149 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX
|
150 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX
,
151 .vlanOperationTagged
= UCC_GETH_VLAN_OPERATION_TAGGED_NOP
,
152 .vlanOperationNonTagged
= UCC_GETH_VLAN_OPERATION_NON_TAGGED_NOP
,
153 .rxQoSMode
= UCC_GETH_QOS_MODE_DEFAULT
,
154 .aufc
= UPSMR_AUTOMATIC_FLOW_CONTROL_MODE_NONE
,
155 .padAndCrc
= MACCFG2_PAD_AND_CRC_MODE_PAD_AND_CRC
,
156 .numThreadsTx
= UCC_GETH_NUM_OF_THREADS_1
,
157 .numThreadsRx
= UCC_GETH_NUM_OF_THREADS_1
,
158 .riscTx
= QE_RISC_ALLOCATION_RISC1_AND_RISC2
,
159 .riscRx
= QE_RISC_ALLOCATION_RISC1_AND_RISC2
,
162 static struct ucc_geth_info ugeth_info
[8];
165 static void mem_disp(u8
*addr
, int size
)
168 int size16Aling
= (size
>> 4) << 4;
169 int size4Aling
= (size
>> 2) << 2;
174 for (i
= addr
; (u32
) i
< (u32
) addr
+ size16Aling
; i
+= 16)
175 printk("0x%08x: %08x %08x %08x %08x\r\n",
179 *((u32
*) (i
+ 8)), *((u32
*) (i
+ 12)));
181 printk("0x%08x: ", (u32
) i
);
182 for (; (u32
) i
< (u32
) addr
+ size4Aling
; i
+= 4)
183 printk("%08x ", *((u32
*) (i
)));
184 for (; (u32
) i
< (u32
) addr
+ size
; i
++)
185 printk("%02x", *((u8
*) (i
)));
191 static struct list_head
*dequeue(struct list_head
*lh
)
195 spin_lock_irqsave(&ugeth_lock
, flags
);
196 if (!list_empty(lh
)) {
197 struct list_head
*node
= lh
->next
;
199 spin_unlock_irqrestore(&ugeth_lock
, flags
);
202 spin_unlock_irqrestore(&ugeth_lock
, flags
);
207 static struct sk_buff
*get_new_skb(struct ucc_geth_private
*ugeth
,
210 struct sk_buff
*skb
= NULL
;
212 skb
= dev_alloc_skb(ugeth
->ug_info
->uf_info
.max_rx_buf_length
+
213 UCC_GETH_RX_DATA_BUF_ALIGNMENT
);
218 /* We need the data buffer to be aligned properly. We will reserve
219 * as many bytes as needed to align the data properly
222 UCC_GETH_RX_DATA_BUF_ALIGNMENT
-
223 (((unsigned)skb
->data
) & (UCC_GETH_RX_DATA_BUF_ALIGNMENT
-
226 skb
->dev
= ugeth
->ndev
;
228 out_be32(&((struct qe_bd __iomem
*)bd
)->buf
,
229 dma_map_single(ugeth
->dev
,
231 ugeth
->ug_info
->uf_info
.max_rx_buf_length
+
232 UCC_GETH_RX_DATA_BUF_ALIGNMENT
,
235 out_be32((u32 __iomem
*)bd
,
236 (R_E
| R_I
| (in_be32((u32 __iomem
*)bd
) & R_W
)));
241 static int rx_bd_buffer_set(struct ucc_geth_private
*ugeth
, u8 rxQ
)
248 bd
= ugeth
->p_rx_bd_ring
[rxQ
];
252 bd_status
= in_be32((u32 __iomem
*)bd
);
253 skb
= get_new_skb(ugeth
, bd
);
255 if (!skb
) /* If can not allocate data buffer,
256 abort. Cleanup will be elsewhere */
259 ugeth
->rx_skbuff
[rxQ
][i
] = skb
;
261 /* advance the BD pointer */
262 bd
+= sizeof(struct qe_bd
);
264 } while (!(bd_status
& R_W
));
269 static int fill_init_enet_entries(struct ucc_geth_private
*ugeth
,
273 u32 thread_alignment
,
274 enum qe_risc_allocation risc
,
275 int skip_page_for_first_entry
)
277 u32 init_enet_offset
;
281 for (i
= 0; i
< num_entries
; i
++) {
282 if ((snum
= qe_get_snum()) < 0) {
283 if (netif_msg_ifup(ugeth
))
284 ugeth_err("fill_init_enet_entries: Can not get SNUM.");
287 if ((i
== 0) && skip_page_for_first_entry
)
288 /* First entry of Rx does not have page */
289 init_enet_offset
= 0;
292 qe_muram_alloc(thread_size
, thread_alignment
);
293 if (IS_ERR_VALUE(init_enet_offset
)) {
294 if (netif_msg_ifup(ugeth
))
295 ugeth_err("fill_init_enet_entries: Can not allocate DPRAM memory.");
296 qe_put_snum((u8
) snum
);
301 ((u8
) snum
<< ENET_INIT_PARAM_SNUM_SHIFT
) | init_enet_offset
308 static int return_init_enet_entries(struct ucc_geth_private
*ugeth
,
311 enum qe_risc_allocation risc
,
312 int skip_page_for_first_entry
)
314 u32 init_enet_offset
;
318 for (i
= 0; i
< num_entries
; i
++) {
321 /* Check that this entry was actually valid --
322 needed in case failed in allocations */
323 if ((val
& ENET_INIT_PARAM_RISC_MASK
) == risc
) {
325 (u32
) (val
& ENET_INIT_PARAM_SNUM_MASK
) >>
326 ENET_INIT_PARAM_SNUM_SHIFT
;
327 qe_put_snum((u8
) snum
);
328 if (!((i
== 0) && skip_page_for_first_entry
)) {
329 /* First entry of Rx does not have page */
331 (val
& ENET_INIT_PARAM_PTR_MASK
);
332 qe_muram_free(init_enet_offset
);
342 static int dump_init_enet_entries(struct ucc_geth_private
*ugeth
,
343 u32 __iomem
*p_start
,
346 enum qe_risc_allocation risc
,
347 int skip_page_for_first_entry
)
349 u32 init_enet_offset
;
353 for (i
= 0; i
< num_entries
; i
++) {
354 u32 val
= in_be32(p_start
);
356 /* Check that this entry was actually valid --
357 needed in case failed in allocations */
358 if ((val
& ENET_INIT_PARAM_RISC_MASK
) == risc
) {
360 (u32
) (val
& ENET_INIT_PARAM_SNUM_MASK
) >>
361 ENET_INIT_PARAM_SNUM_SHIFT
;
362 qe_put_snum((u8
) snum
);
363 if (!((i
== 0) && skip_page_for_first_entry
)) {
364 /* First entry of Rx does not have page */
367 ENET_INIT_PARAM_PTR_MASK
);
368 ugeth_info("Init enet entry %d:", i
);
369 ugeth_info("Base address: 0x%08x",
371 qe_muram_addr(init_enet_offset
));
372 mem_disp(qe_muram_addr(init_enet_offset
),
383 static void put_enet_addr_container(struct enet_addr_container
*enet_addr_cont
)
385 kfree(enet_addr_cont
);
388 static void set_mac_addr(__be16 __iomem
*reg
, u8
*mac
)
390 out_be16(®
[0], ((u16
)mac
[5] << 8) | mac
[4]);
391 out_be16(®
[1], ((u16
)mac
[3] << 8) | mac
[2]);
392 out_be16(®
[2], ((u16
)mac
[1] << 8) | mac
[0]);
395 static int hw_clear_addr_in_paddr(struct ucc_geth_private
*ugeth
, u8 paddr_num
)
397 struct ucc_geth_82xx_address_filtering_pram __iomem
*p_82xx_addr_filt
;
399 if (!(paddr_num
< NUM_OF_PADDRS
)) {
400 ugeth_warn("%s: Illagel paddr_num.", __func__
);
405 (struct ucc_geth_82xx_address_filtering_pram __iomem
*) ugeth
->p_rx_glbl_pram
->
408 /* Writing address ff.ff.ff.ff.ff.ff disables address
409 recognition for this register */
410 out_be16(&p_82xx_addr_filt
->paddr
[paddr_num
].h
, 0xffff);
411 out_be16(&p_82xx_addr_filt
->paddr
[paddr_num
].m
, 0xffff);
412 out_be16(&p_82xx_addr_filt
->paddr
[paddr_num
].l
, 0xffff);
417 static void hw_add_addr_in_hash(struct ucc_geth_private
*ugeth
,
420 struct ucc_geth_82xx_address_filtering_pram __iomem
*p_82xx_addr_filt
;
424 (struct ucc_geth_82xx_address_filtering_pram __iomem
*) ugeth
->p_rx_glbl_pram
->
428 ucc_fast_get_qe_cr_subblock(ugeth
->ug_info
->uf_info
.ucc_num
);
430 /* Ethernet frames are defined in Little Endian mode,
431 therefor to insert */
432 /* the address to the hash (Big Endian mode), we reverse the bytes.*/
434 set_mac_addr(&p_82xx_addr_filt
->taddr
.h
, p_enet_addr
);
436 qe_issue_cmd(QE_SET_GROUP_ADDRESS
, cecr_subblock
,
437 QE_CR_PROTOCOL_ETHERNET
, 0);
440 #ifdef CONFIG_UGETH_MAGIC_PACKET
441 static void magic_packet_detection_enable(struct ucc_geth_private
*ugeth
)
443 struct ucc_fast_private
*uccf
;
444 struct ucc_geth __iomem
*ug_regs
;
447 ug_regs
= ugeth
->ug_regs
;
449 /* Enable interrupts for magic packet detection */
450 setbits32(uccf
->p_uccm
, UCC_GETH_UCCE_MPD
);
452 /* Enable magic packet detection */
453 setbits32(&ug_regs
->maccfg2
, MACCFG2_MPE
);
456 static void magic_packet_detection_disable(struct ucc_geth_private
*ugeth
)
458 struct ucc_fast_private
*uccf
;
459 struct ucc_geth __iomem
*ug_regs
;
462 ug_regs
= ugeth
->ug_regs
;
464 /* Disable interrupts for magic packet detection */
465 clrbits32(uccf
->p_uccm
, UCC_GETH_UCCE_MPD
);
467 /* Disable magic packet detection */
468 clrbits32(&ug_regs
->maccfg2
, MACCFG2_MPE
);
470 #endif /* MAGIC_PACKET */
472 static inline int compare_addr(u8
**addr1
, u8
**addr2
)
474 return memcmp(addr1
, addr2
, ENET_NUM_OCTETS_PER_ADDRESS
);
478 static void get_statistics(struct ucc_geth_private
*ugeth
,
479 struct ucc_geth_tx_firmware_statistics
*
480 tx_firmware_statistics
,
481 struct ucc_geth_rx_firmware_statistics
*
482 rx_firmware_statistics
,
483 struct ucc_geth_hardware_statistics
*hardware_statistics
)
485 struct ucc_fast __iomem
*uf_regs
;
486 struct ucc_geth __iomem
*ug_regs
;
487 struct ucc_geth_tx_firmware_statistics_pram
*p_tx_fw_statistics_pram
;
488 struct ucc_geth_rx_firmware_statistics_pram
*p_rx_fw_statistics_pram
;
490 ug_regs
= ugeth
->ug_regs
;
491 uf_regs
= (struct ucc_fast __iomem
*) ug_regs
;
492 p_tx_fw_statistics_pram
= ugeth
->p_tx_fw_statistics_pram
;
493 p_rx_fw_statistics_pram
= ugeth
->p_rx_fw_statistics_pram
;
495 /* Tx firmware only if user handed pointer and driver actually
496 gathers Tx firmware statistics */
497 if (tx_firmware_statistics
&& p_tx_fw_statistics_pram
) {
498 tx_firmware_statistics
->sicoltx
=
499 in_be32(&p_tx_fw_statistics_pram
->sicoltx
);
500 tx_firmware_statistics
->mulcoltx
=
501 in_be32(&p_tx_fw_statistics_pram
->mulcoltx
);
502 tx_firmware_statistics
->latecoltxfr
=
503 in_be32(&p_tx_fw_statistics_pram
->latecoltxfr
);
504 tx_firmware_statistics
->frabortduecol
=
505 in_be32(&p_tx_fw_statistics_pram
->frabortduecol
);
506 tx_firmware_statistics
->frlostinmactxer
=
507 in_be32(&p_tx_fw_statistics_pram
->frlostinmactxer
);
508 tx_firmware_statistics
->carriersenseertx
=
509 in_be32(&p_tx_fw_statistics_pram
->carriersenseertx
);
510 tx_firmware_statistics
->frtxok
=
511 in_be32(&p_tx_fw_statistics_pram
->frtxok
);
512 tx_firmware_statistics
->txfrexcessivedefer
=
513 in_be32(&p_tx_fw_statistics_pram
->txfrexcessivedefer
);
514 tx_firmware_statistics
->txpkts256
=
515 in_be32(&p_tx_fw_statistics_pram
->txpkts256
);
516 tx_firmware_statistics
->txpkts512
=
517 in_be32(&p_tx_fw_statistics_pram
->txpkts512
);
518 tx_firmware_statistics
->txpkts1024
=
519 in_be32(&p_tx_fw_statistics_pram
->txpkts1024
);
520 tx_firmware_statistics
->txpktsjumbo
=
521 in_be32(&p_tx_fw_statistics_pram
->txpktsjumbo
);
524 /* Rx firmware only if user handed pointer and driver actually
525 * gathers Rx firmware statistics */
526 if (rx_firmware_statistics
&& p_rx_fw_statistics_pram
) {
528 rx_firmware_statistics
->frrxfcser
=
529 in_be32(&p_rx_fw_statistics_pram
->frrxfcser
);
530 rx_firmware_statistics
->fraligner
=
531 in_be32(&p_rx_fw_statistics_pram
->fraligner
);
532 rx_firmware_statistics
->inrangelenrxer
=
533 in_be32(&p_rx_fw_statistics_pram
->inrangelenrxer
);
534 rx_firmware_statistics
->outrangelenrxer
=
535 in_be32(&p_rx_fw_statistics_pram
->outrangelenrxer
);
536 rx_firmware_statistics
->frtoolong
=
537 in_be32(&p_rx_fw_statistics_pram
->frtoolong
);
538 rx_firmware_statistics
->runt
=
539 in_be32(&p_rx_fw_statistics_pram
->runt
);
540 rx_firmware_statistics
->verylongevent
=
541 in_be32(&p_rx_fw_statistics_pram
->verylongevent
);
542 rx_firmware_statistics
->symbolerror
=
543 in_be32(&p_rx_fw_statistics_pram
->symbolerror
);
544 rx_firmware_statistics
->dropbsy
=
545 in_be32(&p_rx_fw_statistics_pram
->dropbsy
);
546 for (i
= 0; i
< 0x8; i
++)
547 rx_firmware_statistics
->res0
[i
] =
548 p_rx_fw_statistics_pram
->res0
[i
];
549 rx_firmware_statistics
->mismatchdrop
=
550 in_be32(&p_rx_fw_statistics_pram
->mismatchdrop
);
551 rx_firmware_statistics
->underpkts
=
552 in_be32(&p_rx_fw_statistics_pram
->underpkts
);
553 rx_firmware_statistics
->pkts256
=
554 in_be32(&p_rx_fw_statistics_pram
->pkts256
);
555 rx_firmware_statistics
->pkts512
=
556 in_be32(&p_rx_fw_statistics_pram
->pkts512
);
557 rx_firmware_statistics
->pkts1024
=
558 in_be32(&p_rx_fw_statistics_pram
->pkts1024
);
559 rx_firmware_statistics
->pktsjumbo
=
560 in_be32(&p_rx_fw_statistics_pram
->pktsjumbo
);
561 rx_firmware_statistics
->frlossinmacer
=
562 in_be32(&p_rx_fw_statistics_pram
->frlossinmacer
);
563 rx_firmware_statistics
->pausefr
=
564 in_be32(&p_rx_fw_statistics_pram
->pausefr
);
565 for (i
= 0; i
< 0x4; i
++)
566 rx_firmware_statistics
->res1
[i
] =
567 p_rx_fw_statistics_pram
->res1
[i
];
568 rx_firmware_statistics
->removevlan
=
569 in_be32(&p_rx_fw_statistics_pram
->removevlan
);
570 rx_firmware_statistics
->replacevlan
=
571 in_be32(&p_rx_fw_statistics_pram
->replacevlan
);
572 rx_firmware_statistics
->insertvlan
=
573 in_be32(&p_rx_fw_statistics_pram
->insertvlan
);
576 /* Hardware only if user handed pointer and driver actually
577 gathers hardware statistics */
578 if (hardware_statistics
&&
579 (in_be32(&uf_regs
->upsmr
) & UCC_GETH_UPSMR_HSE
)) {
580 hardware_statistics
->tx64
= in_be32(&ug_regs
->tx64
);
581 hardware_statistics
->tx127
= in_be32(&ug_regs
->tx127
);
582 hardware_statistics
->tx255
= in_be32(&ug_regs
->tx255
);
583 hardware_statistics
->rx64
= in_be32(&ug_regs
->rx64
);
584 hardware_statistics
->rx127
= in_be32(&ug_regs
->rx127
);
585 hardware_statistics
->rx255
= in_be32(&ug_regs
->rx255
);
586 hardware_statistics
->txok
= in_be32(&ug_regs
->txok
);
587 hardware_statistics
->txcf
= in_be16(&ug_regs
->txcf
);
588 hardware_statistics
->tmca
= in_be32(&ug_regs
->tmca
);
589 hardware_statistics
->tbca
= in_be32(&ug_regs
->tbca
);
590 hardware_statistics
->rxfok
= in_be32(&ug_regs
->rxfok
);
591 hardware_statistics
->rxbok
= in_be32(&ug_regs
->rxbok
);
592 hardware_statistics
->rbyt
= in_be32(&ug_regs
->rbyt
);
593 hardware_statistics
->rmca
= in_be32(&ug_regs
->rmca
);
594 hardware_statistics
->rbca
= in_be32(&ug_regs
->rbca
);
598 static void dump_bds(struct ucc_geth_private
*ugeth
)
603 for (i
= 0; i
< ugeth
->ug_info
->numQueuesTx
; i
++) {
604 if (ugeth
->p_tx_bd_ring
[i
]) {
606 (ugeth
->ug_info
->bdRingLenTx
[i
] *
607 sizeof(struct qe_bd
));
608 ugeth_info("TX BDs[%d]", i
);
609 mem_disp(ugeth
->p_tx_bd_ring
[i
], length
);
612 for (i
= 0; i
< ugeth
->ug_info
->numQueuesRx
; i
++) {
613 if (ugeth
->p_rx_bd_ring
[i
]) {
615 (ugeth
->ug_info
->bdRingLenRx
[i
] *
616 sizeof(struct qe_bd
));
617 ugeth_info("RX BDs[%d]", i
);
618 mem_disp(ugeth
->p_rx_bd_ring
[i
], length
);
623 static void dump_regs(struct ucc_geth_private
*ugeth
)
627 ugeth_info("UCC%d Geth registers:", ugeth
->ug_info
->uf_info
.ucc_num
);
628 ugeth_info("Base address: 0x%08x", (u32
) ugeth
->ug_regs
);
630 ugeth_info("maccfg1 : addr - 0x%08x, val - 0x%08x",
631 (u32
) & ugeth
->ug_regs
->maccfg1
,
632 in_be32(&ugeth
->ug_regs
->maccfg1
));
633 ugeth_info("maccfg2 : addr - 0x%08x, val - 0x%08x",
634 (u32
) & ugeth
->ug_regs
->maccfg2
,
635 in_be32(&ugeth
->ug_regs
->maccfg2
));
636 ugeth_info("ipgifg : addr - 0x%08x, val - 0x%08x",
637 (u32
) & ugeth
->ug_regs
->ipgifg
,
638 in_be32(&ugeth
->ug_regs
->ipgifg
));
639 ugeth_info("hafdup : addr - 0x%08x, val - 0x%08x",
640 (u32
) & ugeth
->ug_regs
->hafdup
,
641 in_be32(&ugeth
->ug_regs
->hafdup
));
642 ugeth_info("ifctl : addr - 0x%08x, val - 0x%08x",
643 (u32
) & ugeth
->ug_regs
->ifctl
,
644 in_be32(&ugeth
->ug_regs
->ifctl
));
645 ugeth_info("ifstat : addr - 0x%08x, val - 0x%08x",
646 (u32
) & ugeth
->ug_regs
->ifstat
,
647 in_be32(&ugeth
->ug_regs
->ifstat
));
648 ugeth_info("macstnaddr1: addr - 0x%08x, val - 0x%08x",
649 (u32
) & ugeth
->ug_regs
->macstnaddr1
,
650 in_be32(&ugeth
->ug_regs
->macstnaddr1
));
651 ugeth_info("macstnaddr2: addr - 0x%08x, val - 0x%08x",
652 (u32
) & ugeth
->ug_regs
->macstnaddr2
,
653 in_be32(&ugeth
->ug_regs
->macstnaddr2
));
654 ugeth_info("uempr : addr - 0x%08x, val - 0x%08x",
655 (u32
) & ugeth
->ug_regs
->uempr
,
656 in_be32(&ugeth
->ug_regs
->uempr
));
657 ugeth_info("utbipar : addr - 0x%08x, val - 0x%08x",
658 (u32
) & ugeth
->ug_regs
->utbipar
,
659 in_be32(&ugeth
->ug_regs
->utbipar
));
660 ugeth_info("uescr : addr - 0x%08x, val - 0x%04x",
661 (u32
) & ugeth
->ug_regs
->uescr
,
662 in_be16(&ugeth
->ug_regs
->uescr
));
663 ugeth_info("tx64 : addr - 0x%08x, val - 0x%08x",
664 (u32
) & ugeth
->ug_regs
->tx64
,
665 in_be32(&ugeth
->ug_regs
->tx64
));
666 ugeth_info("tx127 : addr - 0x%08x, val - 0x%08x",
667 (u32
) & ugeth
->ug_regs
->tx127
,
668 in_be32(&ugeth
->ug_regs
->tx127
));
669 ugeth_info("tx255 : addr - 0x%08x, val - 0x%08x",
670 (u32
) & ugeth
->ug_regs
->tx255
,
671 in_be32(&ugeth
->ug_regs
->tx255
));
672 ugeth_info("rx64 : addr - 0x%08x, val - 0x%08x",
673 (u32
) & ugeth
->ug_regs
->rx64
,
674 in_be32(&ugeth
->ug_regs
->rx64
));
675 ugeth_info("rx127 : addr - 0x%08x, val - 0x%08x",
676 (u32
) & ugeth
->ug_regs
->rx127
,
677 in_be32(&ugeth
->ug_regs
->rx127
));
678 ugeth_info("rx255 : addr - 0x%08x, val - 0x%08x",
679 (u32
) & ugeth
->ug_regs
->rx255
,
680 in_be32(&ugeth
->ug_regs
->rx255
));
681 ugeth_info("txok : addr - 0x%08x, val - 0x%08x",
682 (u32
) & ugeth
->ug_regs
->txok
,
683 in_be32(&ugeth
->ug_regs
->txok
));
684 ugeth_info("txcf : addr - 0x%08x, val - 0x%04x",
685 (u32
) & ugeth
->ug_regs
->txcf
,
686 in_be16(&ugeth
->ug_regs
->txcf
));
687 ugeth_info("tmca : addr - 0x%08x, val - 0x%08x",
688 (u32
) & ugeth
->ug_regs
->tmca
,
689 in_be32(&ugeth
->ug_regs
->tmca
));
690 ugeth_info("tbca : addr - 0x%08x, val - 0x%08x",
691 (u32
) & ugeth
->ug_regs
->tbca
,
692 in_be32(&ugeth
->ug_regs
->tbca
));
693 ugeth_info("rxfok : addr - 0x%08x, val - 0x%08x",
694 (u32
) & ugeth
->ug_regs
->rxfok
,
695 in_be32(&ugeth
->ug_regs
->rxfok
));
696 ugeth_info("rxbok : addr - 0x%08x, val - 0x%08x",
697 (u32
) & ugeth
->ug_regs
->rxbok
,
698 in_be32(&ugeth
->ug_regs
->rxbok
));
699 ugeth_info("rbyt : addr - 0x%08x, val - 0x%08x",
700 (u32
) & ugeth
->ug_regs
->rbyt
,
701 in_be32(&ugeth
->ug_regs
->rbyt
));
702 ugeth_info("rmca : addr - 0x%08x, val - 0x%08x",
703 (u32
) & ugeth
->ug_regs
->rmca
,
704 in_be32(&ugeth
->ug_regs
->rmca
));
705 ugeth_info("rbca : addr - 0x%08x, val - 0x%08x",
706 (u32
) & ugeth
->ug_regs
->rbca
,
707 in_be32(&ugeth
->ug_regs
->rbca
));
708 ugeth_info("scar : addr - 0x%08x, val - 0x%08x",
709 (u32
) & ugeth
->ug_regs
->scar
,
710 in_be32(&ugeth
->ug_regs
->scar
));
711 ugeth_info("scam : addr - 0x%08x, val - 0x%08x",
712 (u32
) & ugeth
->ug_regs
->scam
,
713 in_be32(&ugeth
->ug_regs
->scam
));
715 if (ugeth
->p_thread_data_tx
) {
716 int numThreadsTxNumerical
;
717 switch (ugeth
->ug_info
->numThreadsTx
) {
718 case UCC_GETH_NUM_OF_THREADS_1
:
719 numThreadsTxNumerical
= 1;
721 case UCC_GETH_NUM_OF_THREADS_2
:
722 numThreadsTxNumerical
= 2;
724 case UCC_GETH_NUM_OF_THREADS_4
:
725 numThreadsTxNumerical
= 4;
727 case UCC_GETH_NUM_OF_THREADS_6
:
728 numThreadsTxNumerical
= 6;
730 case UCC_GETH_NUM_OF_THREADS_8
:
731 numThreadsTxNumerical
= 8;
734 numThreadsTxNumerical
= 0;
738 ugeth_info("Thread data TXs:");
739 ugeth_info("Base address: 0x%08x",
740 (u32
) ugeth
->p_thread_data_tx
);
741 for (i
= 0; i
< numThreadsTxNumerical
; i
++) {
742 ugeth_info("Thread data TX[%d]:", i
);
743 ugeth_info("Base address: 0x%08x",
744 (u32
) & ugeth
->p_thread_data_tx
[i
]);
745 mem_disp((u8
*) & ugeth
->p_thread_data_tx
[i
],
746 sizeof(struct ucc_geth_thread_data_tx
));
749 if (ugeth
->p_thread_data_rx
) {
750 int numThreadsRxNumerical
;
751 switch (ugeth
->ug_info
->numThreadsRx
) {
752 case UCC_GETH_NUM_OF_THREADS_1
:
753 numThreadsRxNumerical
= 1;
755 case UCC_GETH_NUM_OF_THREADS_2
:
756 numThreadsRxNumerical
= 2;
758 case UCC_GETH_NUM_OF_THREADS_4
:
759 numThreadsRxNumerical
= 4;
761 case UCC_GETH_NUM_OF_THREADS_6
:
762 numThreadsRxNumerical
= 6;
764 case UCC_GETH_NUM_OF_THREADS_8
:
765 numThreadsRxNumerical
= 8;
768 numThreadsRxNumerical
= 0;
772 ugeth_info("Thread data RX:");
773 ugeth_info("Base address: 0x%08x",
774 (u32
) ugeth
->p_thread_data_rx
);
775 for (i
= 0; i
< numThreadsRxNumerical
; i
++) {
776 ugeth_info("Thread data RX[%d]:", i
);
777 ugeth_info("Base address: 0x%08x",
778 (u32
) & ugeth
->p_thread_data_rx
[i
]);
779 mem_disp((u8
*) & ugeth
->p_thread_data_rx
[i
],
780 sizeof(struct ucc_geth_thread_data_rx
));
783 if (ugeth
->p_exf_glbl_param
) {
784 ugeth_info("EXF global param:");
785 ugeth_info("Base address: 0x%08x",
786 (u32
) ugeth
->p_exf_glbl_param
);
787 mem_disp((u8
*) ugeth
->p_exf_glbl_param
,
788 sizeof(*ugeth
->p_exf_glbl_param
));
790 if (ugeth
->p_tx_glbl_pram
) {
791 ugeth_info("TX global param:");
792 ugeth_info("Base address: 0x%08x", (u32
) ugeth
->p_tx_glbl_pram
);
793 ugeth_info("temoder : addr - 0x%08x, val - 0x%04x",
794 (u32
) & ugeth
->p_tx_glbl_pram
->temoder
,
795 in_be16(&ugeth
->p_tx_glbl_pram
->temoder
));
796 ugeth_info("sqptr : addr - 0x%08x, val - 0x%08x",
797 (u32
) & ugeth
->p_tx_glbl_pram
->sqptr
,
798 in_be32(&ugeth
->p_tx_glbl_pram
->sqptr
));
799 ugeth_info("schedulerbasepointer: addr - 0x%08x, val - 0x%08x",
800 (u32
) & ugeth
->p_tx_glbl_pram
->schedulerbasepointer
,
801 in_be32(&ugeth
->p_tx_glbl_pram
->
802 schedulerbasepointer
));
803 ugeth_info("txrmonbaseptr: addr - 0x%08x, val - 0x%08x",
804 (u32
) & ugeth
->p_tx_glbl_pram
->txrmonbaseptr
,
805 in_be32(&ugeth
->p_tx_glbl_pram
->txrmonbaseptr
));
806 ugeth_info("tstate : addr - 0x%08x, val - 0x%08x",
807 (u32
) & ugeth
->p_tx_glbl_pram
->tstate
,
808 in_be32(&ugeth
->p_tx_glbl_pram
->tstate
));
809 ugeth_info("iphoffset[0] : addr - 0x%08x, val - 0x%02x",
810 (u32
) & ugeth
->p_tx_glbl_pram
->iphoffset
[0],
811 ugeth
->p_tx_glbl_pram
->iphoffset
[0]);
812 ugeth_info("iphoffset[1] : addr - 0x%08x, val - 0x%02x",
813 (u32
) & ugeth
->p_tx_glbl_pram
->iphoffset
[1],
814 ugeth
->p_tx_glbl_pram
->iphoffset
[1]);
815 ugeth_info("iphoffset[2] : addr - 0x%08x, val - 0x%02x",
816 (u32
) & ugeth
->p_tx_glbl_pram
->iphoffset
[2],
817 ugeth
->p_tx_glbl_pram
->iphoffset
[2]);
818 ugeth_info("iphoffset[3] : addr - 0x%08x, val - 0x%02x",
819 (u32
) & ugeth
->p_tx_glbl_pram
->iphoffset
[3],
820 ugeth
->p_tx_glbl_pram
->iphoffset
[3]);
821 ugeth_info("iphoffset[4] : addr - 0x%08x, val - 0x%02x",
822 (u32
) & ugeth
->p_tx_glbl_pram
->iphoffset
[4],
823 ugeth
->p_tx_glbl_pram
->iphoffset
[4]);
824 ugeth_info("iphoffset[5] : addr - 0x%08x, val - 0x%02x",
825 (u32
) & ugeth
->p_tx_glbl_pram
->iphoffset
[5],
826 ugeth
->p_tx_glbl_pram
->iphoffset
[5]);
827 ugeth_info("iphoffset[6] : addr - 0x%08x, val - 0x%02x",
828 (u32
) & ugeth
->p_tx_glbl_pram
->iphoffset
[6],
829 ugeth
->p_tx_glbl_pram
->iphoffset
[6]);
830 ugeth_info("iphoffset[7] : addr - 0x%08x, val - 0x%02x",
831 (u32
) & ugeth
->p_tx_glbl_pram
->iphoffset
[7],
832 ugeth
->p_tx_glbl_pram
->iphoffset
[7]);
833 ugeth_info("vtagtable[0] : addr - 0x%08x, val - 0x%08x",
834 (u32
) & ugeth
->p_tx_glbl_pram
->vtagtable
[0],
835 in_be32(&ugeth
->p_tx_glbl_pram
->vtagtable
[0]));
836 ugeth_info("vtagtable[1] : addr - 0x%08x, val - 0x%08x",
837 (u32
) & ugeth
->p_tx_glbl_pram
->vtagtable
[1],
838 in_be32(&ugeth
->p_tx_glbl_pram
->vtagtable
[1]));
839 ugeth_info("vtagtable[2] : addr - 0x%08x, val - 0x%08x",
840 (u32
) & ugeth
->p_tx_glbl_pram
->vtagtable
[2],
841 in_be32(&ugeth
->p_tx_glbl_pram
->vtagtable
[2]));
842 ugeth_info("vtagtable[3] : addr - 0x%08x, val - 0x%08x",
843 (u32
) & ugeth
->p_tx_glbl_pram
->vtagtable
[3],
844 in_be32(&ugeth
->p_tx_glbl_pram
->vtagtable
[3]));
845 ugeth_info("vtagtable[4] : addr - 0x%08x, val - 0x%08x",
846 (u32
) & ugeth
->p_tx_glbl_pram
->vtagtable
[4],
847 in_be32(&ugeth
->p_tx_glbl_pram
->vtagtable
[4]));
848 ugeth_info("vtagtable[5] : addr - 0x%08x, val - 0x%08x",
849 (u32
) & ugeth
->p_tx_glbl_pram
->vtagtable
[5],
850 in_be32(&ugeth
->p_tx_glbl_pram
->vtagtable
[5]));
851 ugeth_info("vtagtable[6] : addr - 0x%08x, val - 0x%08x",
852 (u32
) & ugeth
->p_tx_glbl_pram
->vtagtable
[6],
853 in_be32(&ugeth
->p_tx_glbl_pram
->vtagtable
[6]));
854 ugeth_info("vtagtable[7] : addr - 0x%08x, val - 0x%08x",
855 (u32
) & ugeth
->p_tx_glbl_pram
->vtagtable
[7],
856 in_be32(&ugeth
->p_tx_glbl_pram
->vtagtable
[7]));
857 ugeth_info("tqptr : addr - 0x%08x, val - 0x%08x",
858 (u32
) & ugeth
->p_tx_glbl_pram
->tqptr
,
859 in_be32(&ugeth
->p_tx_glbl_pram
->tqptr
));
861 if (ugeth
->p_rx_glbl_pram
) {
862 ugeth_info("RX global param:");
863 ugeth_info("Base address: 0x%08x", (u32
) ugeth
->p_rx_glbl_pram
);
864 ugeth_info("remoder : addr - 0x%08x, val - 0x%08x",
865 (u32
) & ugeth
->p_rx_glbl_pram
->remoder
,
866 in_be32(&ugeth
->p_rx_glbl_pram
->remoder
));
867 ugeth_info("rqptr : addr - 0x%08x, val - 0x%08x",
868 (u32
) & ugeth
->p_rx_glbl_pram
->rqptr
,
869 in_be32(&ugeth
->p_rx_glbl_pram
->rqptr
));
870 ugeth_info("typeorlen : addr - 0x%08x, val - 0x%04x",
871 (u32
) & ugeth
->p_rx_glbl_pram
->typeorlen
,
872 in_be16(&ugeth
->p_rx_glbl_pram
->typeorlen
));
873 ugeth_info("rxgstpack : addr - 0x%08x, val - 0x%02x",
874 (u32
) & ugeth
->p_rx_glbl_pram
->rxgstpack
,
875 ugeth
->p_rx_glbl_pram
->rxgstpack
);
876 ugeth_info("rxrmonbaseptr : addr - 0x%08x, val - 0x%08x",
877 (u32
) & ugeth
->p_rx_glbl_pram
->rxrmonbaseptr
,
878 in_be32(&ugeth
->p_rx_glbl_pram
->rxrmonbaseptr
));
879 ugeth_info("intcoalescingptr: addr - 0x%08x, val - 0x%08x",
880 (u32
) & ugeth
->p_rx_glbl_pram
->intcoalescingptr
,
881 in_be32(&ugeth
->p_rx_glbl_pram
->intcoalescingptr
));
882 ugeth_info("rstate : addr - 0x%08x, val - 0x%02x",
883 (u32
) & ugeth
->p_rx_glbl_pram
->rstate
,
884 ugeth
->p_rx_glbl_pram
->rstate
);
885 ugeth_info("mrblr : addr - 0x%08x, val - 0x%04x",
886 (u32
) & ugeth
->p_rx_glbl_pram
->mrblr
,
887 in_be16(&ugeth
->p_rx_glbl_pram
->mrblr
));
888 ugeth_info("rbdqptr : addr - 0x%08x, val - 0x%08x",
889 (u32
) & ugeth
->p_rx_glbl_pram
->rbdqptr
,
890 in_be32(&ugeth
->p_rx_glbl_pram
->rbdqptr
));
891 ugeth_info("mflr : addr - 0x%08x, val - 0x%04x",
892 (u32
) & ugeth
->p_rx_glbl_pram
->mflr
,
893 in_be16(&ugeth
->p_rx_glbl_pram
->mflr
));
894 ugeth_info("minflr : addr - 0x%08x, val - 0x%04x",
895 (u32
) & ugeth
->p_rx_glbl_pram
->minflr
,
896 in_be16(&ugeth
->p_rx_glbl_pram
->minflr
));
897 ugeth_info("maxd1 : addr - 0x%08x, val - 0x%04x",
898 (u32
) & ugeth
->p_rx_glbl_pram
->maxd1
,
899 in_be16(&ugeth
->p_rx_glbl_pram
->maxd1
));
900 ugeth_info("maxd2 : addr - 0x%08x, val - 0x%04x",
901 (u32
) & ugeth
->p_rx_glbl_pram
->maxd2
,
902 in_be16(&ugeth
->p_rx_glbl_pram
->maxd2
));
903 ugeth_info("ecamptr : addr - 0x%08x, val - 0x%08x",
904 (u32
) & ugeth
->p_rx_glbl_pram
->ecamptr
,
905 in_be32(&ugeth
->p_rx_glbl_pram
->ecamptr
));
906 ugeth_info("l2qt : addr - 0x%08x, val - 0x%08x",
907 (u32
) & ugeth
->p_rx_glbl_pram
->l2qt
,
908 in_be32(&ugeth
->p_rx_glbl_pram
->l2qt
));
909 ugeth_info("l3qt[0] : addr - 0x%08x, val - 0x%08x",
910 (u32
) & ugeth
->p_rx_glbl_pram
->l3qt
[0],
911 in_be32(&ugeth
->p_rx_glbl_pram
->l3qt
[0]));
912 ugeth_info("l3qt[1] : addr - 0x%08x, val - 0x%08x",
913 (u32
) & ugeth
->p_rx_glbl_pram
->l3qt
[1],
914 in_be32(&ugeth
->p_rx_glbl_pram
->l3qt
[1]));
915 ugeth_info("l3qt[2] : addr - 0x%08x, val - 0x%08x",
916 (u32
) & ugeth
->p_rx_glbl_pram
->l3qt
[2],
917 in_be32(&ugeth
->p_rx_glbl_pram
->l3qt
[2]));
918 ugeth_info("l3qt[3] : addr - 0x%08x, val - 0x%08x",
919 (u32
) & ugeth
->p_rx_glbl_pram
->l3qt
[3],
920 in_be32(&ugeth
->p_rx_glbl_pram
->l3qt
[3]));
921 ugeth_info("l3qt[4] : addr - 0x%08x, val - 0x%08x",
922 (u32
) & ugeth
->p_rx_glbl_pram
->l3qt
[4],
923 in_be32(&ugeth
->p_rx_glbl_pram
->l3qt
[4]));
924 ugeth_info("l3qt[5] : addr - 0x%08x, val - 0x%08x",
925 (u32
) & ugeth
->p_rx_glbl_pram
->l3qt
[5],
926 in_be32(&ugeth
->p_rx_glbl_pram
->l3qt
[5]));
927 ugeth_info("l3qt[6] : addr - 0x%08x, val - 0x%08x",
928 (u32
) & ugeth
->p_rx_glbl_pram
->l3qt
[6],
929 in_be32(&ugeth
->p_rx_glbl_pram
->l3qt
[6]));
930 ugeth_info("l3qt[7] : addr - 0x%08x, val - 0x%08x",
931 (u32
) & ugeth
->p_rx_glbl_pram
->l3qt
[7],
932 in_be32(&ugeth
->p_rx_glbl_pram
->l3qt
[7]));
933 ugeth_info("vlantype : addr - 0x%08x, val - 0x%04x",
934 (u32
) & ugeth
->p_rx_glbl_pram
->vlantype
,
935 in_be16(&ugeth
->p_rx_glbl_pram
->vlantype
));
936 ugeth_info("vlantci : addr - 0x%08x, val - 0x%04x",
937 (u32
) & ugeth
->p_rx_glbl_pram
->vlantci
,
938 in_be16(&ugeth
->p_rx_glbl_pram
->vlantci
));
939 for (i
= 0; i
< 64; i
++)
941 ("addressfiltering[%d]: addr - 0x%08x, val - 0x%02x",
943 (u32
) & ugeth
->p_rx_glbl_pram
->addressfiltering
[i
],
944 ugeth
->p_rx_glbl_pram
->addressfiltering
[i
]);
945 ugeth_info("exfGlobalParam : addr - 0x%08x, val - 0x%08x",
946 (u32
) & ugeth
->p_rx_glbl_pram
->exfGlobalParam
,
947 in_be32(&ugeth
->p_rx_glbl_pram
->exfGlobalParam
));
949 if (ugeth
->p_send_q_mem_reg
) {
950 ugeth_info("Send Q memory registers:");
951 ugeth_info("Base address: 0x%08x",
952 (u32
) ugeth
->p_send_q_mem_reg
);
953 for (i
= 0; i
< ugeth
->ug_info
->numQueuesTx
; i
++) {
954 ugeth_info("SQQD[%d]:", i
);
955 ugeth_info("Base address: 0x%08x",
956 (u32
) & ugeth
->p_send_q_mem_reg
->sqqd
[i
]);
957 mem_disp((u8
*) & ugeth
->p_send_q_mem_reg
->sqqd
[i
],
958 sizeof(struct ucc_geth_send_queue_qd
));
961 if (ugeth
->p_scheduler
) {
962 ugeth_info("Scheduler:");
963 ugeth_info("Base address: 0x%08x", (u32
) ugeth
->p_scheduler
);
964 mem_disp((u8
*) ugeth
->p_scheduler
,
965 sizeof(*ugeth
->p_scheduler
));
967 if (ugeth
->p_tx_fw_statistics_pram
) {
968 ugeth_info("TX FW statistics pram:");
969 ugeth_info("Base address: 0x%08x",
970 (u32
) ugeth
->p_tx_fw_statistics_pram
);
971 mem_disp((u8
*) ugeth
->p_tx_fw_statistics_pram
,
972 sizeof(*ugeth
->p_tx_fw_statistics_pram
));
974 if (ugeth
->p_rx_fw_statistics_pram
) {
975 ugeth_info("RX FW statistics pram:");
976 ugeth_info("Base address: 0x%08x",
977 (u32
) ugeth
->p_rx_fw_statistics_pram
);
978 mem_disp((u8
*) ugeth
->p_rx_fw_statistics_pram
,
979 sizeof(*ugeth
->p_rx_fw_statistics_pram
));
981 if (ugeth
->p_rx_irq_coalescing_tbl
) {
982 ugeth_info("RX IRQ coalescing tables:");
983 ugeth_info("Base address: 0x%08x",
984 (u32
) ugeth
->p_rx_irq_coalescing_tbl
);
985 for (i
= 0; i
< ugeth
->ug_info
->numQueuesRx
; i
++) {
986 ugeth_info("RX IRQ coalescing table entry[%d]:", i
);
987 ugeth_info("Base address: 0x%08x",
988 (u32
) & ugeth
->p_rx_irq_coalescing_tbl
->
991 ("interruptcoalescingmaxvalue: addr - 0x%08x, val - 0x%08x",
992 (u32
) & ugeth
->p_rx_irq_coalescing_tbl
->
993 coalescingentry
[i
].interruptcoalescingmaxvalue
,
994 in_be32(&ugeth
->p_rx_irq_coalescing_tbl
->
996 interruptcoalescingmaxvalue
));
998 ("interruptcoalescingcounter : addr - 0x%08x, val - 0x%08x",
999 (u32
) & ugeth
->p_rx_irq_coalescing_tbl
->
1000 coalescingentry
[i
].interruptcoalescingcounter
,
1001 in_be32(&ugeth
->p_rx_irq_coalescing_tbl
->
1003 interruptcoalescingcounter
));
1006 if (ugeth
->p_rx_bd_qs_tbl
) {
1007 ugeth_info("RX BD QS tables:");
1008 ugeth_info("Base address: 0x%08x", (u32
) ugeth
->p_rx_bd_qs_tbl
);
1009 for (i
= 0; i
< ugeth
->ug_info
->numQueuesRx
; i
++) {
1010 ugeth_info("RX BD QS table[%d]:", i
);
1011 ugeth_info("Base address: 0x%08x",
1012 (u32
) & ugeth
->p_rx_bd_qs_tbl
[i
]);
1014 ("bdbaseptr : addr - 0x%08x, val - 0x%08x",
1015 (u32
) & ugeth
->p_rx_bd_qs_tbl
[i
].bdbaseptr
,
1016 in_be32(&ugeth
->p_rx_bd_qs_tbl
[i
].bdbaseptr
));
1018 ("bdptr : addr - 0x%08x, val - 0x%08x",
1019 (u32
) & ugeth
->p_rx_bd_qs_tbl
[i
].bdptr
,
1020 in_be32(&ugeth
->p_rx_bd_qs_tbl
[i
].bdptr
));
1022 ("externalbdbaseptr: addr - 0x%08x, val - 0x%08x",
1023 (u32
) & ugeth
->p_rx_bd_qs_tbl
[i
].externalbdbaseptr
,
1024 in_be32(&ugeth
->p_rx_bd_qs_tbl
[i
].
1025 externalbdbaseptr
));
1027 ("externalbdptr : addr - 0x%08x, val - 0x%08x",
1028 (u32
) & ugeth
->p_rx_bd_qs_tbl
[i
].externalbdptr
,
1029 in_be32(&ugeth
->p_rx_bd_qs_tbl
[i
].externalbdptr
));
1030 ugeth_info("ucode RX Prefetched BDs:");
1031 ugeth_info("Base address: 0x%08x",
1033 qe_muram_addr(in_be32
1034 (&ugeth
->p_rx_bd_qs_tbl
[i
].
1037 qe_muram_addr(in_be32
1038 (&ugeth
->p_rx_bd_qs_tbl
[i
].
1040 sizeof(struct ucc_geth_rx_prefetched_bds
));
1043 if (ugeth
->p_init_enet_param_shadow
) {
1045 ugeth_info("Init enet param shadow:");
1046 ugeth_info("Base address: 0x%08x",
1047 (u32
) ugeth
->p_init_enet_param_shadow
);
1048 mem_disp((u8
*) ugeth
->p_init_enet_param_shadow
,
1049 sizeof(*ugeth
->p_init_enet_param_shadow
));
1051 size
= sizeof(struct ucc_geth_thread_rx_pram
);
1052 if (ugeth
->ug_info
->rxExtendedFiltering
) {
1054 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING
;
1055 if (ugeth
->ug_info
->largestexternallookupkeysize
==
1056 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES
)
1058 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_8
;
1059 if (ugeth
->ug_info
->largestexternallookupkeysize
==
1060 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES
)
1062 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_16
;
1065 dump_init_enet_entries(ugeth
,
1066 &(ugeth
->p_init_enet_param_shadow
->
1068 ENET_INIT_PARAM_MAX_ENTRIES_TX
,
1069 sizeof(struct ucc_geth_thread_tx_pram
),
1070 ugeth
->ug_info
->riscTx
, 0);
1071 dump_init_enet_entries(ugeth
,
1072 &(ugeth
->p_init_enet_param_shadow
->
1074 ENET_INIT_PARAM_MAX_ENTRIES_RX
, size
,
1075 ugeth
->ug_info
->riscRx
, 1);
1080 static void init_default_reg_vals(u32 __iomem
*upsmr_register
,
1081 u32 __iomem
*maccfg1_register
,
1082 u32 __iomem
*maccfg2_register
)
1084 out_be32(upsmr_register
, UCC_GETH_UPSMR_INIT
);
1085 out_be32(maccfg1_register
, UCC_GETH_MACCFG1_INIT
);
1086 out_be32(maccfg2_register
, UCC_GETH_MACCFG2_INIT
);
1089 static int init_half_duplex_params(int alt_beb
,
1090 int back_pressure_no_backoff
,
1093 u8 alt_beb_truncation
,
1094 u8 max_retransmissions
,
1095 u8 collision_window
,
1096 u32 __iomem
*hafdup_register
)
1100 if ((alt_beb_truncation
> HALFDUP_ALT_BEB_TRUNCATION_MAX
) ||
1101 (max_retransmissions
> HALFDUP_MAX_RETRANSMISSION_MAX
) ||
1102 (collision_window
> HALFDUP_COLLISION_WINDOW_MAX
))
1105 value
= (u32
) (alt_beb_truncation
<< HALFDUP_ALT_BEB_TRUNCATION_SHIFT
);
1108 value
|= HALFDUP_ALT_BEB
;
1109 if (back_pressure_no_backoff
)
1110 value
|= HALFDUP_BACK_PRESSURE_NO_BACKOFF
;
1112 value
|= HALFDUP_NO_BACKOFF
;
1114 value
|= HALFDUP_EXCESSIVE_DEFER
;
1116 value
|= (max_retransmissions
<< HALFDUP_MAX_RETRANSMISSION_SHIFT
);
1118 value
|= collision_window
;
1120 out_be32(hafdup_register
, value
);
1124 static int init_inter_frame_gap_params(u8 non_btb_cs_ipg
,
1128 u32 __iomem
*ipgifg_register
)
1132 /* Non-Back-to-back IPG part 1 should be <= Non-Back-to-back
1134 if (non_btb_cs_ipg
> non_btb_ipg
)
1137 if ((non_btb_cs_ipg
> IPGIFG_NON_BACK_TO_BACK_IFG_PART1_MAX
) ||
1138 (non_btb_ipg
> IPGIFG_NON_BACK_TO_BACK_IFG_PART2_MAX
) ||
1139 /*(min_ifg > IPGIFG_MINIMUM_IFG_ENFORCEMENT_MAX) || */
1140 (btb_ipg
> IPGIFG_BACK_TO_BACK_IFG_MAX
))
1144 ((non_btb_cs_ipg
<< IPGIFG_NON_BACK_TO_BACK_IFG_PART1_SHIFT
) &
1145 IPGIFG_NBTB_CS_IPG_MASK
);
1147 ((non_btb_ipg
<< IPGIFG_NON_BACK_TO_BACK_IFG_PART2_SHIFT
) &
1148 IPGIFG_NBTB_IPG_MASK
);
1150 ((min_ifg
<< IPGIFG_MINIMUM_IFG_ENFORCEMENT_SHIFT
) &
1151 IPGIFG_MIN_IFG_MASK
);
1152 value
|= (btb_ipg
& IPGIFG_BTB_IPG_MASK
);
1154 out_be32(ipgifg_register
, value
);
1158 int init_flow_control_params(u32 automatic_flow_control_mode
,
1159 int rx_flow_control_enable
,
1160 int tx_flow_control_enable
,
1162 u16 extension_field
,
1163 u32 __iomem
*upsmr_register
,
1164 u32 __iomem
*uempr_register
,
1165 u32 __iomem
*maccfg1_register
)
1169 /* Set UEMPR register */
1170 value
= (u32
) pause_period
<< UEMPR_PAUSE_TIME_VALUE_SHIFT
;
1171 value
|= (u32
) extension_field
<< UEMPR_EXTENDED_PAUSE_TIME_VALUE_SHIFT
;
1172 out_be32(uempr_register
, value
);
1174 /* Set UPSMR register */
1175 setbits32(upsmr_register
, automatic_flow_control_mode
);
1177 value
= in_be32(maccfg1_register
);
1178 if (rx_flow_control_enable
)
1179 value
|= MACCFG1_FLOW_RX
;
1180 if (tx_flow_control_enable
)
1181 value
|= MACCFG1_FLOW_TX
;
1182 out_be32(maccfg1_register
, value
);
1187 static int init_hw_statistics_gathering_mode(int enable_hardware_statistics
,
1188 int auto_zero_hardware_statistics
,
1189 u32 __iomem
*upsmr_register
,
1190 u16 __iomem
*uescr_register
)
1192 u16 uescr_value
= 0;
1194 /* Enable hardware statistics gathering if requested */
1195 if (enable_hardware_statistics
)
1196 setbits32(upsmr_register
, UCC_GETH_UPSMR_HSE
);
1198 /* Clear hardware statistics counters */
1199 uescr_value
= in_be16(uescr_register
);
1200 uescr_value
|= UESCR_CLRCNT
;
1201 /* Automatically zero hardware statistics counters on read,
1203 if (auto_zero_hardware_statistics
)
1204 uescr_value
|= UESCR_AUTOZ
;
1205 out_be16(uescr_register
, uescr_value
);
1210 static int init_firmware_statistics_gathering_mode(int
1211 enable_tx_firmware_statistics
,
1212 int enable_rx_firmware_statistics
,
1213 u32 __iomem
*tx_rmon_base_ptr
,
1214 u32 tx_firmware_statistics_structure_address
,
1215 u32 __iomem
*rx_rmon_base_ptr
,
1216 u32 rx_firmware_statistics_structure_address
,
1217 u16 __iomem
*temoder_register
,
1218 u32 __iomem
*remoder_register
)
1220 /* Note: this function does not check if */
1221 /* the parameters it receives are NULL */
1223 if (enable_tx_firmware_statistics
) {
1224 out_be32(tx_rmon_base_ptr
,
1225 tx_firmware_statistics_structure_address
);
1226 setbits16(temoder_register
, TEMODER_TX_RMON_STATISTICS_ENABLE
);
1229 if (enable_rx_firmware_statistics
) {
1230 out_be32(rx_rmon_base_ptr
,
1231 rx_firmware_statistics_structure_address
);
1232 setbits32(remoder_register
, REMODER_RX_RMON_STATISTICS_ENABLE
);
1238 static int init_mac_station_addr_regs(u8 address_byte_0
,
1244 u32 __iomem
*macstnaddr1_register
,
1245 u32 __iomem
*macstnaddr2_register
)
1249 /* Example: for a station address of 0x12345678ABCD, */
1250 /* 0x12 is byte 0, 0x34 is byte 1 and so on and 0xCD is byte 5 */
1252 /* MACSTNADDR1 Register: */
1255 /* station address byte 5 station address byte 4 */
1257 /* station address byte 3 station address byte 2 */
1258 value
|= (u32
) ((address_byte_2
<< 0) & 0x000000FF);
1259 value
|= (u32
) ((address_byte_3
<< 8) & 0x0000FF00);
1260 value
|= (u32
) ((address_byte_4
<< 16) & 0x00FF0000);
1261 value
|= (u32
) ((address_byte_5
<< 24) & 0xFF000000);
1263 out_be32(macstnaddr1_register
, value
);
1265 /* MACSTNADDR2 Register: */
1268 /* station address byte 1 station address byte 0 */
1270 /* reserved reserved */
1272 value
|= (u32
) ((address_byte_0
<< 16) & 0x00FF0000);
1273 value
|= (u32
) ((address_byte_1
<< 24) & 0xFF000000);
1275 out_be32(macstnaddr2_register
, value
);
1280 static int init_check_frame_length_mode(int length_check
,
1281 u32 __iomem
*maccfg2_register
)
1285 value
= in_be32(maccfg2_register
);
1288 value
|= MACCFG2_LC
;
1290 value
&= ~MACCFG2_LC
;
1292 out_be32(maccfg2_register
, value
);
1296 static int init_preamble_length(u8 preamble_length
,
1297 u32 __iomem
*maccfg2_register
)
1299 if ((preamble_length
< 3) || (preamble_length
> 7))
1302 clrsetbits_be32(maccfg2_register
, MACCFG2_PREL_MASK
,
1303 preamble_length
<< MACCFG2_PREL_SHIFT
);
1308 static int init_rx_parameters(int reject_broadcast
,
1309 int receive_short_frames
,
1310 int promiscuous
, u32 __iomem
*upsmr_register
)
1314 value
= in_be32(upsmr_register
);
1316 if (reject_broadcast
)
1317 value
|= UCC_GETH_UPSMR_BRO
;
1319 value
&= ~UCC_GETH_UPSMR_BRO
;
1321 if (receive_short_frames
)
1322 value
|= UCC_GETH_UPSMR_RSH
;
1324 value
&= ~UCC_GETH_UPSMR_RSH
;
1327 value
|= UCC_GETH_UPSMR_PRO
;
1329 value
&= ~UCC_GETH_UPSMR_PRO
;
1331 out_be32(upsmr_register
, value
);
1336 static int init_max_rx_buff_len(u16 max_rx_buf_len
,
1337 u16 __iomem
*mrblr_register
)
1339 /* max_rx_buf_len value must be a multiple of 128 */
1340 if ((max_rx_buf_len
== 0)
1341 || (max_rx_buf_len
% UCC_GETH_MRBLR_ALIGNMENT
))
1344 out_be16(mrblr_register
, max_rx_buf_len
);
1348 static int init_min_frame_len(u16 min_frame_length
,
1349 u16 __iomem
*minflr_register
,
1350 u16 __iomem
*mrblr_register
)
1352 u16 mrblr_value
= 0;
1354 mrblr_value
= in_be16(mrblr_register
);
1355 if (min_frame_length
>= (mrblr_value
- 4))
1358 out_be16(minflr_register
, min_frame_length
);
1362 static int adjust_enet_interface(struct ucc_geth_private
*ugeth
)
1364 struct ucc_geth_info
*ug_info
;
1365 struct ucc_geth __iomem
*ug_regs
;
1366 struct ucc_fast __iomem
*uf_regs
;
1368 u32 upsmr
, maccfg2
, tbiBaseAddress
;
1371 ugeth_vdbg("%s: IN", __func__
);
1373 ug_info
= ugeth
->ug_info
;
1374 ug_regs
= ugeth
->ug_regs
;
1375 uf_regs
= ugeth
->uccf
->uf_regs
;
1378 maccfg2
= in_be32(&ug_regs
->maccfg2
);
1379 maccfg2
&= ~MACCFG2_INTERFACE_MODE_MASK
;
1380 if ((ugeth
->max_speed
== SPEED_10
) ||
1381 (ugeth
->max_speed
== SPEED_100
))
1382 maccfg2
|= MACCFG2_INTERFACE_MODE_NIBBLE
;
1383 else if (ugeth
->max_speed
== SPEED_1000
)
1384 maccfg2
|= MACCFG2_INTERFACE_MODE_BYTE
;
1385 maccfg2
|= ug_info
->padAndCrc
;
1386 out_be32(&ug_regs
->maccfg2
, maccfg2
);
1389 upsmr
= in_be32(&uf_regs
->upsmr
);
1390 upsmr
&= ~(UCC_GETH_UPSMR_RPM
| UCC_GETH_UPSMR_R10M
|
1391 UCC_GETH_UPSMR_TBIM
| UCC_GETH_UPSMR_RMM
);
1392 if ((ugeth
->phy_interface
== PHY_INTERFACE_MODE_RMII
) ||
1393 (ugeth
->phy_interface
== PHY_INTERFACE_MODE_RGMII
) ||
1394 (ugeth
->phy_interface
== PHY_INTERFACE_MODE_RGMII_ID
) ||
1395 (ugeth
->phy_interface
== PHY_INTERFACE_MODE_RGMII_RXID
) ||
1396 (ugeth
->phy_interface
== PHY_INTERFACE_MODE_RGMII_TXID
) ||
1397 (ugeth
->phy_interface
== PHY_INTERFACE_MODE_RTBI
)) {
1398 if (ugeth
->phy_interface
!= PHY_INTERFACE_MODE_RMII
)
1399 upsmr
|= UCC_GETH_UPSMR_RPM
;
1400 switch (ugeth
->max_speed
) {
1402 upsmr
|= UCC_GETH_UPSMR_R10M
;
1405 if (ugeth
->phy_interface
!= PHY_INTERFACE_MODE_RTBI
)
1406 upsmr
|= UCC_GETH_UPSMR_RMM
;
1409 if ((ugeth
->phy_interface
== PHY_INTERFACE_MODE_TBI
) ||
1410 (ugeth
->phy_interface
== PHY_INTERFACE_MODE_RTBI
)) {
1411 upsmr
|= UCC_GETH_UPSMR_TBIM
;
1413 out_be32(&uf_regs
->upsmr
, upsmr
);
1415 /* Disable autonegotiation in tbi mode, because by default it
1416 comes up in autonegotiation mode. */
1417 /* Note that this depends on proper setting in utbipar register. */
1418 if ((ugeth
->phy_interface
== PHY_INTERFACE_MODE_TBI
) ||
1419 (ugeth
->phy_interface
== PHY_INTERFACE_MODE_RTBI
)) {
1420 tbiBaseAddress
= in_be32(&ug_regs
->utbipar
);
1421 tbiBaseAddress
&= UTBIPAR_PHY_ADDRESS_MASK
;
1422 tbiBaseAddress
>>= UTBIPAR_PHY_ADDRESS_SHIFT
;
1423 value
= ugeth
->phydev
->bus
->read(ugeth
->phydev
->bus
,
1424 (u8
) tbiBaseAddress
, ENET_TBI_MII_CR
);
1425 value
&= ~0x1000; /* Turn off autonegotiation */
1426 ugeth
->phydev
->bus
->write(ugeth
->phydev
->bus
,
1427 (u8
) tbiBaseAddress
, ENET_TBI_MII_CR
, value
);
1430 init_check_frame_length_mode(ug_info
->lengthCheckRx
, &ug_regs
->maccfg2
);
1432 ret_val
= init_preamble_length(ug_info
->prel
, &ug_regs
->maccfg2
);
1434 if (netif_msg_probe(ugeth
))
1435 ugeth_err("%s: Preamble length must be between 3 and 7 inclusive.",
1443 /* Called every time the controller might need to be made
1444 * aware of new link state. The PHY code conveys this
1445 * information through variables in the ugeth structure, and this
1446 * function converts those variables into the appropriate
1447 * register values, and can bring down the device if needed.
1450 static void adjust_link(struct net_device
*dev
)
1452 struct ucc_geth_private
*ugeth
= netdev_priv(dev
);
1453 struct ucc_geth __iomem
*ug_regs
;
1454 struct ucc_fast __iomem
*uf_regs
;
1455 struct phy_device
*phydev
= ugeth
->phydev
;
1456 unsigned long flags
;
1459 ug_regs
= ugeth
->ug_regs
;
1460 uf_regs
= ugeth
->uccf
->uf_regs
;
1462 spin_lock_irqsave(&ugeth
->lock
, flags
);
1465 u32 tempval
= in_be32(&ug_regs
->maccfg2
);
1466 u32 upsmr
= in_be32(&uf_regs
->upsmr
);
1467 /* Now we make sure that we can be in full duplex mode.
1468 * If not, we operate in half-duplex mode. */
1469 if (phydev
->duplex
!= ugeth
->oldduplex
) {
1471 if (!(phydev
->duplex
))
1472 tempval
&= ~(MACCFG2_FDX
);
1474 tempval
|= MACCFG2_FDX
;
1475 ugeth
->oldduplex
= phydev
->duplex
;
1478 if (phydev
->speed
!= ugeth
->oldspeed
) {
1480 switch (phydev
->speed
) {
1482 tempval
= ((tempval
&
1483 ~(MACCFG2_INTERFACE_MODE_MASK
)) |
1484 MACCFG2_INTERFACE_MODE_BYTE
);
1488 tempval
= ((tempval
&
1489 ~(MACCFG2_INTERFACE_MODE_MASK
)) |
1490 MACCFG2_INTERFACE_MODE_NIBBLE
);
1491 /* if reduced mode, re-set UPSMR.R10M */
1492 if ((ugeth
->phy_interface
== PHY_INTERFACE_MODE_RMII
) ||
1493 (ugeth
->phy_interface
== PHY_INTERFACE_MODE_RGMII
) ||
1494 (ugeth
->phy_interface
== PHY_INTERFACE_MODE_RGMII_ID
) ||
1495 (ugeth
->phy_interface
== PHY_INTERFACE_MODE_RGMII_RXID
) ||
1496 (ugeth
->phy_interface
== PHY_INTERFACE_MODE_RGMII_TXID
) ||
1497 (ugeth
->phy_interface
== PHY_INTERFACE_MODE_RTBI
)) {
1498 if (phydev
->speed
== SPEED_10
)
1499 upsmr
|= UCC_GETH_UPSMR_R10M
;
1501 upsmr
&= ~UCC_GETH_UPSMR_R10M
;
1505 if (netif_msg_link(ugeth
))
1507 "%s: Ack! Speed (%d) is not 10/100/1000!",
1508 dev
->name
, phydev
->speed
);
1511 ugeth
->oldspeed
= phydev
->speed
;
1514 out_be32(&ug_regs
->maccfg2
, tempval
);
1515 out_be32(&uf_regs
->upsmr
, upsmr
);
1517 if (!ugeth
->oldlink
) {
1521 } else if (ugeth
->oldlink
) {
1524 ugeth
->oldspeed
= 0;
1525 ugeth
->oldduplex
= -1;
1528 if (new_state
&& netif_msg_link(ugeth
))
1529 phy_print_status(phydev
);
1531 spin_unlock_irqrestore(&ugeth
->lock
, flags
);
1534 /* Configure the PHY for dev.
1535 * returns 0 if success. -1 if failure
1537 static int init_phy(struct net_device
*dev
)
1539 struct ucc_geth_private
*priv
= netdev_priv(dev
);
1540 struct ucc_geth_info
*ug_info
= priv
->ug_info
;
1541 struct phy_device
*phydev
;
1545 priv
->oldduplex
= -1;
1547 if (!ug_info
->phy_node
)
1550 phydev
= of_phy_connect(dev
, ug_info
->phy_node
, &adjust_link
, 0,
1551 priv
->phy_interface
);
1553 printk("%s: Could not attach to PHY\n", dev
->name
);
1557 phydev
->supported
&= (ADVERTISED_10baseT_Half
|
1558 ADVERTISED_10baseT_Full
|
1559 ADVERTISED_100baseT_Half
|
1560 ADVERTISED_100baseT_Full
);
1562 if (priv
->max_speed
== SPEED_1000
)
1563 phydev
->supported
|= ADVERTISED_1000baseT_Full
;
1565 phydev
->advertising
= phydev
->supported
;
1567 priv
->phydev
= phydev
;
1574 static int ugeth_graceful_stop_tx(struct ucc_geth_private
*ugeth
)
1576 struct ucc_fast_private
*uccf
;
1583 /* Mask GRACEFUL STOP TX interrupt bit and clear it */
1584 clrbits32(uccf
->p_uccm
, UCC_GETH_UCCE_GRA
);
1585 out_be32(uccf
->p_ucce
, UCC_GETH_UCCE_GRA
); /* clear by writing 1 */
1587 /* Issue host command */
1589 ucc_fast_get_qe_cr_subblock(ugeth
->ug_info
->uf_info
.ucc_num
);
1590 qe_issue_cmd(QE_GRACEFUL_STOP_TX
, cecr_subblock
,
1591 QE_CR_PROTOCOL_ETHERNET
, 0);
1593 /* Wait for command to complete */
1596 temp
= in_be32(uccf
->p_ucce
);
1597 } while (!(temp
& UCC_GETH_UCCE_GRA
) && --i
);
1599 uccf
->stopped_tx
= 1;
1604 static int ugeth_graceful_stop_rx(struct ucc_geth_private
* ugeth
)
1606 struct ucc_fast_private
*uccf
;
1613 /* Clear acknowledge bit */
1614 temp
= in_8(&ugeth
->p_rx_glbl_pram
->rxgstpack
);
1615 temp
&= ~GRACEFUL_STOP_ACKNOWLEDGE_RX
;
1616 out_8(&ugeth
->p_rx_glbl_pram
->rxgstpack
, temp
);
1618 /* Keep issuing command and checking acknowledge bit until
1619 it is asserted, according to spec */
1621 /* Issue host command */
1623 ucc_fast_get_qe_cr_subblock(ugeth
->ug_info
->uf_info
.
1625 qe_issue_cmd(QE_GRACEFUL_STOP_RX
, cecr_subblock
,
1626 QE_CR_PROTOCOL_ETHERNET
, 0);
1628 temp
= in_8(&ugeth
->p_rx_glbl_pram
->rxgstpack
);
1629 } while (!(temp
& GRACEFUL_STOP_ACKNOWLEDGE_RX
) && --i
);
1631 uccf
->stopped_rx
= 1;
1636 static int ugeth_restart_tx(struct ucc_geth_private
*ugeth
)
1638 struct ucc_fast_private
*uccf
;
1644 ucc_fast_get_qe_cr_subblock(ugeth
->ug_info
->uf_info
.ucc_num
);
1645 qe_issue_cmd(QE_RESTART_TX
, cecr_subblock
, QE_CR_PROTOCOL_ETHERNET
, 0);
1646 uccf
->stopped_tx
= 0;
1651 static int ugeth_restart_rx(struct ucc_geth_private
*ugeth
)
1653 struct ucc_fast_private
*uccf
;
1659 ucc_fast_get_qe_cr_subblock(ugeth
->ug_info
->uf_info
.ucc_num
);
1660 qe_issue_cmd(QE_RESTART_RX
, cecr_subblock
, QE_CR_PROTOCOL_ETHERNET
,
1662 uccf
->stopped_rx
= 0;
1667 static int ugeth_enable(struct ucc_geth_private
*ugeth
, enum comm_dir mode
)
1669 struct ucc_fast_private
*uccf
;
1670 int enabled_tx
, enabled_rx
;
1674 /* check if the UCC number is in range. */
1675 if (ugeth
->ug_info
->uf_info
.ucc_num
>= UCC_MAX_NUM
) {
1676 if (netif_msg_probe(ugeth
))
1677 ugeth_err("%s: ucc_num out of range.", __func__
);
1681 enabled_tx
= uccf
->enabled_tx
;
1682 enabled_rx
= uccf
->enabled_rx
;
1684 /* Get Tx and Rx going again, in case this channel was actively
1686 if ((mode
& COMM_DIR_TX
) && (!enabled_tx
) && uccf
->stopped_tx
)
1687 ugeth_restart_tx(ugeth
);
1688 if ((mode
& COMM_DIR_RX
) && (!enabled_rx
) && uccf
->stopped_rx
)
1689 ugeth_restart_rx(ugeth
);
1691 ucc_fast_enable(uccf
, mode
); /* OK to do even if not disabled */
1697 static int ugeth_disable(struct ucc_geth_private
* ugeth
, enum comm_dir mode
)
1699 struct ucc_fast_private
*uccf
;
1703 /* check if the UCC number is in range. */
1704 if (ugeth
->ug_info
->uf_info
.ucc_num
>= UCC_MAX_NUM
) {
1705 if (netif_msg_probe(ugeth
))
1706 ugeth_err("%s: ucc_num out of range.", __func__
);
1710 /* Stop any transmissions */
1711 if ((mode
& COMM_DIR_TX
) && uccf
->enabled_tx
&& !uccf
->stopped_tx
)
1712 ugeth_graceful_stop_tx(ugeth
);
1714 /* Stop any receptions */
1715 if ((mode
& COMM_DIR_RX
) && uccf
->enabled_rx
&& !uccf
->stopped_rx
)
1716 ugeth_graceful_stop_rx(ugeth
);
1718 ucc_fast_disable(ugeth
->uccf
, mode
); /* OK to do even if not enabled */
1723 static void ugeth_dump_regs(struct ucc_geth_private
*ugeth
)
1726 ucc_fast_dump_regs(ugeth
->uccf
);
1732 static int ugeth_82xx_filtering_clear_all_addr_in_hash(struct ucc_geth_private
*
1737 struct ucc_geth_82xx_address_filtering_pram __iomem
*p_82xx_addr_filt
;
1738 struct ucc_fast_private
*uccf
;
1739 enum comm_dir comm_dir
;
1740 struct list_head
*p_lh
;
1742 u32 __iomem
*addr_h
;
1743 u32 __iomem
*addr_l
;
1749 (struct ucc_geth_82xx_address_filtering_pram __iomem
*)
1750 ugeth
->p_rx_glbl_pram
->addressfiltering
;
1752 if (enet_addr_type
== ENET_ADDR_TYPE_GROUP
) {
1753 addr_h
= &(p_82xx_addr_filt
->gaddr_h
);
1754 addr_l
= &(p_82xx_addr_filt
->gaddr_l
);
1755 p_lh
= &ugeth
->group_hash_q
;
1756 p_counter
= &(ugeth
->numGroupAddrInHash
);
1757 } else if (enet_addr_type
== ENET_ADDR_TYPE_INDIVIDUAL
) {
1758 addr_h
= &(p_82xx_addr_filt
->iaddr_h
);
1759 addr_l
= &(p_82xx_addr_filt
->iaddr_l
);
1760 p_lh
= &ugeth
->ind_hash_q
;
1761 p_counter
= &(ugeth
->numIndAddrInHash
);
1766 if (uccf
->enabled_tx
)
1767 comm_dir
|= COMM_DIR_TX
;
1768 if (uccf
->enabled_rx
)
1769 comm_dir
|= COMM_DIR_RX
;
1771 ugeth_disable(ugeth
, comm_dir
);
1773 /* Clear the hash table. */
1774 out_be32(addr_h
, 0x00000000);
1775 out_be32(addr_l
, 0x00000000);
1782 /* Delete all remaining CQ elements */
1783 for (i
= 0; i
< num
; i
++)
1784 put_enet_addr_container(ENET_ADDR_CONT_ENTRY(dequeue(p_lh
)));
1789 ugeth_enable(ugeth
, comm_dir
);
1794 static int ugeth_82xx_filtering_clear_addr_in_paddr(struct ucc_geth_private
*ugeth
,
1797 ugeth
->indAddrRegUsed
[paddr_num
] = 0; /* mark this paddr as not used */
1798 return hw_clear_addr_in_paddr(ugeth
, paddr_num
);/* clear in hardware */
1801 static void ucc_geth_memclean(struct ucc_geth_private
*ugeth
)
1810 ucc_fast_free(ugeth
->uccf
);
1814 if (ugeth
->p_thread_data_tx
) {
1815 qe_muram_free(ugeth
->thread_dat_tx_offset
);
1816 ugeth
->p_thread_data_tx
= NULL
;
1818 if (ugeth
->p_thread_data_rx
) {
1819 qe_muram_free(ugeth
->thread_dat_rx_offset
);
1820 ugeth
->p_thread_data_rx
= NULL
;
1822 if (ugeth
->p_exf_glbl_param
) {
1823 qe_muram_free(ugeth
->exf_glbl_param_offset
);
1824 ugeth
->p_exf_glbl_param
= NULL
;
1826 if (ugeth
->p_rx_glbl_pram
) {
1827 qe_muram_free(ugeth
->rx_glbl_pram_offset
);
1828 ugeth
->p_rx_glbl_pram
= NULL
;
1830 if (ugeth
->p_tx_glbl_pram
) {
1831 qe_muram_free(ugeth
->tx_glbl_pram_offset
);
1832 ugeth
->p_tx_glbl_pram
= NULL
;
1834 if (ugeth
->p_send_q_mem_reg
) {
1835 qe_muram_free(ugeth
->send_q_mem_reg_offset
);
1836 ugeth
->p_send_q_mem_reg
= NULL
;
1838 if (ugeth
->p_scheduler
) {
1839 qe_muram_free(ugeth
->scheduler_offset
);
1840 ugeth
->p_scheduler
= NULL
;
1842 if (ugeth
->p_tx_fw_statistics_pram
) {
1843 qe_muram_free(ugeth
->tx_fw_statistics_pram_offset
);
1844 ugeth
->p_tx_fw_statistics_pram
= NULL
;
1846 if (ugeth
->p_rx_fw_statistics_pram
) {
1847 qe_muram_free(ugeth
->rx_fw_statistics_pram_offset
);
1848 ugeth
->p_rx_fw_statistics_pram
= NULL
;
1850 if (ugeth
->p_rx_irq_coalescing_tbl
) {
1851 qe_muram_free(ugeth
->rx_irq_coalescing_tbl_offset
);
1852 ugeth
->p_rx_irq_coalescing_tbl
= NULL
;
1854 if (ugeth
->p_rx_bd_qs_tbl
) {
1855 qe_muram_free(ugeth
->rx_bd_qs_tbl_offset
);
1856 ugeth
->p_rx_bd_qs_tbl
= NULL
;
1858 if (ugeth
->p_init_enet_param_shadow
) {
1859 return_init_enet_entries(ugeth
,
1860 &(ugeth
->p_init_enet_param_shadow
->
1862 ENET_INIT_PARAM_MAX_ENTRIES_RX
,
1863 ugeth
->ug_info
->riscRx
, 1);
1864 return_init_enet_entries(ugeth
,
1865 &(ugeth
->p_init_enet_param_shadow
->
1867 ENET_INIT_PARAM_MAX_ENTRIES_TX
,
1868 ugeth
->ug_info
->riscTx
, 0);
1869 kfree(ugeth
->p_init_enet_param_shadow
);
1870 ugeth
->p_init_enet_param_shadow
= NULL
;
1872 for (i
= 0; i
< ugeth
->ug_info
->numQueuesTx
; i
++) {
1873 bd
= ugeth
->p_tx_bd_ring
[i
];
1876 for (j
= 0; j
< ugeth
->ug_info
->bdRingLenTx
[i
]; j
++) {
1877 if (ugeth
->tx_skbuff
[i
][j
]) {
1878 dma_unmap_single(ugeth
->dev
,
1879 in_be32(&((struct qe_bd __iomem
*)bd
)->buf
),
1880 (in_be32((u32 __iomem
*)bd
) &
1883 dev_kfree_skb_any(ugeth
->tx_skbuff
[i
][j
]);
1884 ugeth
->tx_skbuff
[i
][j
] = NULL
;
1888 kfree(ugeth
->tx_skbuff
[i
]);
1890 if (ugeth
->p_tx_bd_ring
[i
]) {
1891 if (ugeth
->ug_info
->uf_info
.bd_mem_part
==
1893 kfree((void *)ugeth
->tx_bd_ring_offset
[i
]);
1894 else if (ugeth
->ug_info
->uf_info
.bd_mem_part
==
1896 qe_muram_free(ugeth
->tx_bd_ring_offset
[i
]);
1897 ugeth
->p_tx_bd_ring
[i
] = NULL
;
1900 for (i
= 0; i
< ugeth
->ug_info
->numQueuesRx
; i
++) {
1901 if (ugeth
->p_rx_bd_ring
[i
]) {
1902 /* Return existing data buffers in ring */
1903 bd
= ugeth
->p_rx_bd_ring
[i
];
1904 for (j
= 0; j
< ugeth
->ug_info
->bdRingLenRx
[i
]; j
++) {
1905 if (ugeth
->rx_skbuff
[i
][j
]) {
1906 dma_unmap_single(ugeth
->dev
,
1907 in_be32(&((struct qe_bd __iomem
*)bd
)->buf
),
1909 uf_info
.max_rx_buf_length
+
1910 UCC_GETH_RX_DATA_BUF_ALIGNMENT
,
1913 ugeth
->rx_skbuff
[i
][j
]);
1914 ugeth
->rx_skbuff
[i
][j
] = NULL
;
1916 bd
+= sizeof(struct qe_bd
);
1919 kfree(ugeth
->rx_skbuff
[i
]);
1921 if (ugeth
->ug_info
->uf_info
.bd_mem_part
==
1923 kfree((void *)ugeth
->rx_bd_ring_offset
[i
]);
1924 else if (ugeth
->ug_info
->uf_info
.bd_mem_part
==
1926 qe_muram_free(ugeth
->rx_bd_ring_offset
[i
]);
1927 ugeth
->p_rx_bd_ring
[i
] = NULL
;
1930 while (!list_empty(&ugeth
->group_hash_q
))
1931 put_enet_addr_container(ENET_ADDR_CONT_ENTRY
1932 (dequeue(&ugeth
->group_hash_q
)));
1933 while (!list_empty(&ugeth
->ind_hash_q
))
1934 put_enet_addr_container(ENET_ADDR_CONT_ENTRY
1935 (dequeue(&ugeth
->ind_hash_q
)));
1936 if (ugeth
->ug_regs
) {
1937 iounmap(ugeth
->ug_regs
);
1938 ugeth
->ug_regs
= NULL
;
1942 static void ucc_geth_set_multi(struct net_device
*dev
)
1944 struct ucc_geth_private
*ugeth
;
1945 struct dev_mc_list
*dmi
;
1946 struct ucc_fast __iomem
*uf_regs
;
1947 struct ucc_geth_82xx_address_filtering_pram __iomem
*p_82xx_addr_filt
;
1950 ugeth
= netdev_priv(dev
);
1952 uf_regs
= ugeth
->uccf
->uf_regs
;
1954 if (dev
->flags
& IFF_PROMISC
) {
1955 setbits32(&uf_regs
->upsmr
, UCC_GETH_UPSMR_PRO
);
1957 clrbits32(&uf_regs
->upsmr
, UCC_GETH_UPSMR_PRO
);
1960 (struct ucc_geth_82xx_address_filtering_pram __iomem
*) ugeth
->
1961 p_rx_glbl_pram
->addressfiltering
;
1963 if (dev
->flags
& IFF_ALLMULTI
) {
1964 /* Catch all multicast addresses, so set the
1965 * filter to all 1's.
1967 out_be32(&p_82xx_addr_filt
->gaddr_h
, 0xffffffff);
1968 out_be32(&p_82xx_addr_filt
->gaddr_l
, 0xffffffff);
1970 /* Clear filter and add the addresses in the list.
1972 out_be32(&p_82xx_addr_filt
->gaddr_h
, 0x0);
1973 out_be32(&p_82xx_addr_filt
->gaddr_l
, 0x0);
1977 for (i
= 0; i
< dev
->mc_count
; i
++, dmi
= dmi
->next
) {
1979 /* Only support group multicast for now.
1981 if (!(dmi
->dmi_addr
[0] & 1))
1984 /* Ask CPM to run CRC and set bit in
1987 hw_add_addr_in_hash(ugeth
, dmi
->dmi_addr
);
1993 static void ucc_geth_stop(struct ucc_geth_private
*ugeth
)
1995 struct ucc_geth __iomem
*ug_regs
= ugeth
->ug_regs
;
1996 struct phy_device
*phydev
= ugeth
->phydev
;
1998 ugeth_vdbg("%s: IN", __func__
);
2000 /* Disable the controller */
2001 ugeth_disable(ugeth
, COMM_DIR_RX_AND_TX
);
2003 /* Tell the kernel the link is down */
2006 /* Mask all interrupts */
2007 out_be32(ugeth
->uccf
->p_uccm
, 0x00000000);
2009 /* Clear all interrupts */
2010 out_be32(ugeth
->uccf
->p_ucce
, 0xffffffff);
2012 /* Disable Rx and Tx */
2013 clrbits32(&ug_regs
->maccfg1
, MACCFG1_ENABLE_RX
| MACCFG1_ENABLE_TX
);
2015 phy_disconnect(ugeth
->phydev
);
2016 ugeth
->phydev
= NULL
;
2018 ucc_geth_memclean(ugeth
);
2021 static int ucc_struct_init(struct ucc_geth_private
*ugeth
)
2023 struct ucc_geth_info
*ug_info
;
2024 struct ucc_fast_info
*uf_info
;
2027 ug_info
= ugeth
->ug_info
;
2028 uf_info
= &ug_info
->uf_info
;
2030 if (!((uf_info
->bd_mem_part
== MEM_PART_SYSTEM
) ||
2031 (uf_info
->bd_mem_part
== MEM_PART_MURAM
))) {
2032 if (netif_msg_probe(ugeth
))
2033 ugeth_err("%s: Bad memory partition value.",
2039 for (i
= 0; i
< ug_info
->numQueuesRx
; i
++) {
2040 if ((ug_info
->bdRingLenRx
[i
] < UCC_GETH_RX_BD_RING_SIZE_MIN
) ||
2041 (ug_info
->bdRingLenRx
[i
] %
2042 UCC_GETH_RX_BD_RING_SIZE_ALIGNMENT
)) {
2043 if (netif_msg_probe(ugeth
))
2045 ("%s: Rx BD ring length must be multiple of 4, no smaller than 8.",
2052 for (i
= 0; i
< ug_info
->numQueuesTx
; i
++) {
2053 if (ug_info
->bdRingLenTx
[i
] < UCC_GETH_TX_BD_RING_SIZE_MIN
) {
2054 if (netif_msg_probe(ugeth
))
2056 ("%s: Tx BD ring length must be no smaller than 2.",
2063 if ((uf_info
->max_rx_buf_length
== 0) ||
2064 (uf_info
->max_rx_buf_length
% UCC_GETH_MRBLR_ALIGNMENT
)) {
2065 if (netif_msg_probe(ugeth
))
2067 ("%s: max_rx_buf_length must be non-zero multiple of 128.",
2073 if (ug_info
->numQueuesTx
> NUM_TX_QUEUES
) {
2074 if (netif_msg_probe(ugeth
))
2075 ugeth_err("%s: number of tx queues too large.", __func__
);
2080 if (ug_info
->numQueuesRx
> NUM_RX_QUEUES
) {
2081 if (netif_msg_probe(ugeth
))
2082 ugeth_err("%s: number of rx queues too large.", __func__
);
2087 for (i
= 0; i
< UCC_GETH_VLAN_PRIORITY_MAX
; i
++) {
2088 if (ug_info
->l2qt
[i
] >= ug_info
->numQueuesRx
) {
2089 if (netif_msg_probe(ugeth
))
2091 ("%s: VLAN priority table entry must not be"
2092 " larger than number of Rx queues.",
2099 for (i
= 0; i
< UCC_GETH_IP_PRIORITY_MAX
; i
++) {
2100 if (ug_info
->l3qt
[i
] >= ug_info
->numQueuesRx
) {
2101 if (netif_msg_probe(ugeth
))
2103 ("%s: IP priority table entry must not be"
2104 " larger than number of Rx queues.",
2110 if (ug_info
->cam
&& !ug_info
->ecamptr
) {
2111 if (netif_msg_probe(ugeth
))
2112 ugeth_err("%s: If cam mode is chosen, must supply cam ptr.",
2117 if ((ug_info
->numStationAddresses
!=
2118 UCC_GETH_NUM_OF_STATION_ADDRESSES_1
)
2119 && ug_info
->rxExtendedFiltering
) {
2120 if (netif_msg_probe(ugeth
))
2121 ugeth_err("%s: Number of station addresses greater than 1 "
2122 "not allowed in extended parsing mode.",
2127 /* Generate uccm_mask for receive */
2128 uf_info
->uccm_mask
= ug_info
->eventRegMask
& UCCE_OTHER
;/* Errors */
2129 for (i
= 0; i
< ug_info
->numQueuesRx
; i
++)
2130 uf_info
->uccm_mask
|= (UCC_GETH_UCCE_RXF0
<< i
);
2132 for (i
= 0; i
< ug_info
->numQueuesTx
; i
++)
2133 uf_info
->uccm_mask
|= (UCC_GETH_UCCE_TXB0
<< i
);
2134 /* Initialize the general fast UCC block. */
2135 if (ucc_fast_init(uf_info
, &ugeth
->uccf
)) {
2136 if (netif_msg_probe(ugeth
))
2137 ugeth_err("%s: Failed to init uccf.", __func__
);
2141 ugeth
->ug_regs
= ioremap(uf_info
->regs
, sizeof(*ugeth
->ug_regs
));
2142 if (!ugeth
->ug_regs
) {
2143 if (netif_msg_probe(ugeth
))
2144 ugeth_err("%s: Failed to ioremap regs.", __func__
);
2151 static int ucc_geth_startup(struct ucc_geth_private
*ugeth
)
2153 struct ucc_geth_82xx_address_filtering_pram __iomem
*p_82xx_addr_filt
;
2154 struct ucc_geth_init_pram __iomem
*p_init_enet_pram
;
2155 struct ucc_fast_private
*uccf
;
2156 struct ucc_geth_info
*ug_info
;
2157 struct ucc_fast_info
*uf_info
;
2158 struct ucc_fast __iomem
*uf_regs
;
2159 struct ucc_geth __iomem
*ug_regs
;
2160 int ret_val
= -EINVAL
;
2161 u32 remoder
= UCC_GETH_REMODER_INIT
;
2162 u32 init_enet_pram_offset
, cecr_subblock
, command
;
2163 u32 ifstat
, i
, j
, size
, l2qt
, l3qt
, length
;
2164 u16 temoder
= UCC_GETH_TEMODER_INIT
;
2166 u8 function_code
= 0;
2168 u8 __iomem
*endOfRing
;
2169 u8 numThreadsRxNumerical
, numThreadsTxNumerical
;
2171 ugeth_vdbg("%s: IN", __func__
);
2173 ug_info
= ugeth
->ug_info
;
2174 uf_info
= &ug_info
->uf_info
;
2175 uf_regs
= uccf
->uf_regs
;
2176 ug_regs
= ugeth
->ug_regs
;
2178 switch (ug_info
->numThreadsRx
) {
2179 case UCC_GETH_NUM_OF_THREADS_1
:
2180 numThreadsRxNumerical
= 1;
2182 case UCC_GETH_NUM_OF_THREADS_2
:
2183 numThreadsRxNumerical
= 2;
2185 case UCC_GETH_NUM_OF_THREADS_4
:
2186 numThreadsRxNumerical
= 4;
2188 case UCC_GETH_NUM_OF_THREADS_6
:
2189 numThreadsRxNumerical
= 6;
2191 case UCC_GETH_NUM_OF_THREADS_8
:
2192 numThreadsRxNumerical
= 8;
2195 if (netif_msg_ifup(ugeth
))
2196 ugeth_err("%s: Bad number of Rx threads value.",
2202 switch (ug_info
->numThreadsTx
) {
2203 case UCC_GETH_NUM_OF_THREADS_1
:
2204 numThreadsTxNumerical
= 1;
2206 case UCC_GETH_NUM_OF_THREADS_2
:
2207 numThreadsTxNumerical
= 2;
2209 case UCC_GETH_NUM_OF_THREADS_4
:
2210 numThreadsTxNumerical
= 4;
2212 case UCC_GETH_NUM_OF_THREADS_6
:
2213 numThreadsTxNumerical
= 6;
2215 case UCC_GETH_NUM_OF_THREADS_8
:
2216 numThreadsTxNumerical
= 8;
2219 if (netif_msg_ifup(ugeth
))
2220 ugeth_err("%s: Bad number of Tx threads value.",
2226 /* Calculate rx_extended_features */
2227 ugeth
->rx_non_dynamic_extended_features
= ug_info
->ipCheckSumCheck
||
2228 ug_info
->ipAddressAlignment
||
2229 (ug_info
->numStationAddresses
!=
2230 UCC_GETH_NUM_OF_STATION_ADDRESSES_1
);
2232 ugeth
->rx_extended_features
= ugeth
->rx_non_dynamic_extended_features
||
2233 (ug_info
->vlanOperationTagged
!= UCC_GETH_VLAN_OPERATION_TAGGED_NOP
)
2234 || (ug_info
->vlanOperationNonTagged
!=
2235 UCC_GETH_VLAN_OPERATION_NON_TAGGED_NOP
);
2237 init_default_reg_vals(&uf_regs
->upsmr
,
2238 &ug_regs
->maccfg1
, &ug_regs
->maccfg2
);
2241 /* For more details see the hardware spec. */
2242 init_rx_parameters(ug_info
->bro
,
2243 ug_info
->rsh
, ug_info
->pro
, &uf_regs
->upsmr
);
2245 /* We're going to ignore other registers for now, */
2246 /* except as needed to get up and running */
2249 /* For more details see the hardware spec. */
2250 init_flow_control_params(ug_info
->aufc
,
2251 ug_info
->receiveFlowControl
,
2252 ug_info
->transmitFlowControl
,
2253 ug_info
->pausePeriod
,
2254 ug_info
->extensionField
,
2256 &ug_regs
->uempr
, &ug_regs
->maccfg1
);
2258 setbits32(&ug_regs
->maccfg1
, MACCFG1_ENABLE_RX
| MACCFG1_ENABLE_TX
);
2261 /* For more details see the hardware spec. */
2262 ret_val
= init_inter_frame_gap_params(ug_info
->nonBackToBackIfgPart1
,
2263 ug_info
->nonBackToBackIfgPart2
,
2265 miminumInterFrameGapEnforcement
,
2266 ug_info
->backToBackInterFrameGap
,
2269 if (netif_msg_ifup(ugeth
))
2270 ugeth_err("%s: IPGIFG initialization parameter too large.",
2276 /* For more details see the hardware spec. */
2277 ret_val
= init_half_duplex_params(ug_info
->altBeb
,
2278 ug_info
->backPressureNoBackoff
,
2280 ug_info
->excessDefer
,
2281 ug_info
->altBebTruncation
,
2282 ug_info
->maxRetransmission
,
2283 ug_info
->collisionWindow
,
2286 if (netif_msg_ifup(ugeth
))
2287 ugeth_err("%s: Half Duplex initialization parameter too large.",
2293 /* For more details see the hardware spec. */
2294 /* Read only - resets upon read */
2295 ifstat
= in_be32(&ug_regs
->ifstat
);
2298 /* For more details see the hardware spec. */
2299 out_be32(&ug_regs
->uempr
, 0);
2302 /* For more details see the hardware spec. */
2303 init_hw_statistics_gathering_mode((ug_info
->statisticsMode
&
2304 UCC_GETH_STATISTICS_GATHERING_MODE_HARDWARE
),
2305 0, &uf_regs
->upsmr
, &ug_regs
->uescr
);
2307 /* Allocate Tx bds */
2308 for (j
= 0; j
< ug_info
->numQueuesTx
; j
++) {
2309 /* Allocate in multiple of
2310 UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT,
2311 according to spec */
2312 length
= ((ug_info
->bdRingLenTx
[j
] * sizeof(struct qe_bd
))
2313 / UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT
)
2314 * UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT
;
2315 if ((ug_info
->bdRingLenTx
[j
] * sizeof(struct qe_bd
)) %
2316 UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT
)
2317 length
+= UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT
;
2318 if (uf_info
->bd_mem_part
== MEM_PART_SYSTEM
) {
2320 if (UCC_GETH_TX_BD_RING_ALIGNMENT
> 4)
2321 align
= UCC_GETH_TX_BD_RING_ALIGNMENT
;
2322 ugeth
->tx_bd_ring_offset
[j
] =
2323 (u32
) kmalloc((u32
) (length
+ align
), GFP_KERNEL
);
2325 if (ugeth
->tx_bd_ring_offset
[j
] != 0)
2326 ugeth
->p_tx_bd_ring
[j
] =
2327 (u8 __iomem
*)((ugeth
->tx_bd_ring_offset
[j
] +
2328 align
) & ~(align
- 1));
2329 } else if (uf_info
->bd_mem_part
== MEM_PART_MURAM
) {
2330 ugeth
->tx_bd_ring_offset
[j
] =
2331 qe_muram_alloc(length
,
2332 UCC_GETH_TX_BD_RING_ALIGNMENT
);
2333 if (!IS_ERR_VALUE(ugeth
->tx_bd_ring_offset
[j
]))
2334 ugeth
->p_tx_bd_ring
[j
] =
2335 (u8 __iomem
*) qe_muram_addr(ugeth
->
2336 tx_bd_ring_offset
[j
]);
2338 if (!ugeth
->p_tx_bd_ring
[j
]) {
2339 if (netif_msg_ifup(ugeth
))
2341 ("%s: Can not allocate memory for Tx bd rings.",
2345 /* Zero unused end of bd ring, according to spec */
2346 memset_io((void __iomem
*)(ugeth
->p_tx_bd_ring
[j
] +
2347 ug_info
->bdRingLenTx
[j
] * sizeof(struct qe_bd
)), 0,
2348 length
- ug_info
->bdRingLenTx
[j
] * sizeof(struct qe_bd
));
2351 /* Allocate Rx bds */
2352 for (j
= 0; j
< ug_info
->numQueuesRx
; j
++) {
2353 length
= ug_info
->bdRingLenRx
[j
] * sizeof(struct qe_bd
);
2354 if (uf_info
->bd_mem_part
== MEM_PART_SYSTEM
) {
2356 if (UCC_GETH_RX_BD_RING_ALIGNMENT
> 4)
2357 align
= UCC_GETH_RX_BD_RING_ALIGNMENT
;
2358 ugeth
->rx_bd_ring_offset
[j
] =
2359 (u32
) kmalloc((u32
) (length
+ align
), GFP_KERNEL
);
2360 if (ugeth
->rx_bd_ring_offset
[j
] != 0)
2361 ugeth
->p_rx_bd_ring
[j
] =
2362 (u8 __iomem
*)((ugeth
->rx_bd_ring_offset
[j
] +
2363 align
) & ~(align
- 1));
2364 } else if (uf_info
->bd_mem_part
== MEM_PART_MURAM
) {
2365 ugeth
->rx_bd_ring_offset
[j
] =
2366 qe_muram_alloc(length
,
2367 UCC_GETH_RX_BD_RING_ALIGNMENT
);
2368 if (!IS_ERR_VALUE(ugeth
->rx_bd_ring_offset
[j
]))
2369 ugeth
->p_rx_bd_ring
[j
] =
2370 (u8 __iomem
*) qe_muram_addr(ugeth
->
2371 rx_bd_ring_offset
[j
]);
2373 if (!ugeth
->p_rx_bd_ring
[j
]) {
2374 if (netif_msg_ifup(ugeth
))
2376 ("%s: Can not allocate memory for Rx bd rings.",
2383 for (j
= 0; j
< ug_info
->numQueuesTx
; j
++) {
2384 /* Setup the skbuff rings */
2385 ugeth
->tx_skbuff
[j
] = kmalloc(sizeof(struct sk_buff
*) *
2386 ugeth
->ug_info
->bdRingLenTx
[j
],
2389 if (ugeth
->tx_skbuff
[j
] == NULL
) {
2390 if (netif_msg_ifup(ugeth
))
2391 ugeth_err("%s: Could not allocate tx_skbuff",
2396 for (i
= 0; i
< ugeth
->ug_info
->bdRingLenTx
[j
]; i
++)
2397 ugeth
->tx_skbuff
[j
][i
] = NULL
;
2399 ugeth
->skb_curtx
[j
] = ugeth
->skb_dirtytx
[j
] = 0;
2400 bd
= ugeth
->confBd
[j
] = ugeth
->txBd
[j
] = ugeth
->p_tx_bd_ring
[j
];
2401 for (i
= 0; i
< ug_info
->bdRingLenTx
[j
]; i
++) {
2402 /* clear bd buffer */
2403 out_be32(&((struct qe_bd __iomem
*)bd
)->buf
, 0);
2404 /* set bd status and length */
2405 out_be32((u32 __iomem
*)bd
, 0);
2406 bd
+= sizeof(struct qe_bd
);
2408 bd
-= sizeof(struct qe_bd
);
2409 /* set bd status and length */
2410 out_be32((u32 __iomem
*)bd
, T_W
); /* for last BD set Wrap bit */
2414 for (j
= 0; j
< ug_info
->numQueuesRx
; j
++) {
2415 /* Setup the skbuff rings */
2416 ugeth
->rx_skbuff
[j
] = kmalloc(sizeof(struct sk_buff
*) *
2417 ugeth
->ug_info
->bdRingLenRx
[j
],
2420 if (ugeth
->rx_skbuff
[j
] == NULL
) {
2421 if (netif_msg_ifup(ugeth
))
2422 ugeth_err("%s: Could not allocate rx_skbuff",
2427 for (i
= 0; i
< ugeth
->ug_info
->bdRingLenRx
[j
]; i
++)
2428 ugeth
->rx_skbuff
[j
][i
] = NULL
;
2430 ugeth
->skb_currx
[j
] = 0;
2431 bd
= ugeth
->rxBd
[j
] = ugeth
->p_rx_bd_ring
[j
];
2432 for (i
= 0; i
< ug_info
->bdRingLenRx
[j
]; i
++) {
2433 /* set bd status and length */
2434 out_be32((u32 __iomem
*)bd
, R_I
);
2435 /* clear bd buffer */
2436 out_be32(&((struct qe_bd __iomem
*)bd
)->buf
, 0);
2437 bd
+= sizeof(struct qe_bd
);
2439 bd
-= sizeof(struct qe_bd
);
2440 /* set bd status and length */
2441 out_be32((u32 __iomem
*)bd
, R_W
); /* for last BD set Wrap bit */
2447 /* Tx global PRAM */
2448 /* Allocate global tx parameter RAM page */
2449 ugeth
->tx_glbl_pram_offset
=
2450 qe_muram_alloc(sizeof(struct ucc_geth_tx_global_pram
),
2451 UCC_GETH_TX_GLOBAL_PRAM_ALIGNMENT
);
2452 if (IS_ERR_VALUE(ugeth
->tx_glbl_pram_offset
)) {
2453 if (netif_msg_ifup(ugeth
))
2455 ("%s: Can not allocate DPRAM memory for p_tx_glbl_pram.",
2459 ugeth
->p_tx_glbl_pram
=
2460 (struct ucc_geth_tx_global_pram __iomem
*) qe_muram_addr(ugeth
->
2461 tx_glbl_pram_offset
);
2462 /* Zero out p_tx_glbl_pram */
2463 memset_io((void __iomem
*)ugeth
->p_tx_glbl_pram
, 0, sizeof(struct ucc_geth_tx_global_pram
));
2465 /* Fill global PRAM */
2468 /* Size varies with number of Tx threads */
2469 ugeth
->thread_dat_tx_offset
=
2470 qe_muram_alloc(numThreadsTxNumerical
*
2471 sizeof(struct ucc_geth_thread_data_tx
) +
2472 32 * (numThreadsTxNumerical
== 1),
2473 UCC_GETH_THREAD_DATA_ALIGNMENT
);
2474 if (IS_ERR_VALUE(ugeth
->thread_dat_tx_offset
)) {
2475 if (netif_msg_ifup(ugeth
))
2477 ("%s: Can not allocate DPRAM memory for p_thread_data_tx.",
2482 ugeth
->p_thread_data_tx
=
2483 (struct ucc_geth_thread_data_tx __iomem
*) qe_muram_addr(ugeth
->
2484 thread_dat_tx_offset
);
2485 out_be32(&ugeth
->p_tx_glbl_pram
->tqptr
, ugeth
->thread_dat_tx_offset
);
2488 for (i
= 0; i
< UCC_GETH_TX_VTAG_TABLE_ENTRY_MAX
; i
++)
2489 out_be32(&ugeth
->p_tx_glbl_pram
->vtagtable
[i
],
2490 ug_info
->vtagtable
[i
]);
2493 for (i
= 0; i
< TX_IP_OFFSET_ENTRY_MAX
; i
++)
2494 out_8(&ugeth
->p_tx_glbl_pram
->iphoffset
[i
],
2495 ug_info
->iphoffset
[i
]);
2498 /* Size varies with number of Tx queues */
2499 ugeth
->send_q_mem_reg_offset
=
2500 qe_muram_alloc(ug_info
->numQueuesTx
*
2501 sizeof(struct ucc_geth_send_queue_qd
),
2502 UCC_GETH_SEND_QUEUE_QUEUE_DESCRIPTOR_ALIGNMENT
);
2503 if (IS_ERR_VALUE(ugeth
->send_q_mem_reg_offset
)) {
2504 if (netif_msg_ifup(ugeth
))
2506 ("%s: Can not allocate DPRAM memory for p_send_q_mem_reg.",
2511 ugeth
->p_send_q_mem_reg
=
2512 (struct ucc_geth_send_queue_mem_region __iomem
*) qe_muram_addr(ugeth
->
2513 send_q_mem_reg_offset
);
2514 out_be32(&ugeth
->p_tx_glbl_pram
->sqptr
, ugeth
->send_q_mem_reg_offset
);
2516 /* Setup the table */
2517 /* Assume BD rings are already established */
2518 for (i
= 0; i
< ug_info
->numQueuesTx
; i
++) {
2520 ugeth
->p_tx_bd_ring
[i
] + (ug_info
->bdRingLenTx
[i
] -
2521 1) * sizeof(struct qe_bd
);
2522 if (ugeth
->ug_info
->uf_info
.bd_mem_part
== MEM_PART_SYSTEM
) {
2523 out_be32(&ugeth
->p_send_q_mem_reg
->sqqd
[i
].bd_ring_base
,
2524 (u32
) virt_to_phys(ugeth
->p_tx_bd_ring
[i
]));
2525 out_be32(&ugeth
->p_send_q_mem_reg
->sqqd
[i
].
2526 last_bd_completed_address
,
2527 (u32
) virt_to_phys(endOfRing
));
2528 } else if (ugeth
->ug_info
->uf_info
.bd_mem_part
==
2530 out_be32(&ugeth
->p_send_q_mem_reg
->sqqd
[i
].bd_ring_base
,
2531 (u32
) immrbar_virt_to_phys(ugeth
->
2533 out_be32(&ugeth
->p_send_q_mem_reg
->sqqd
[i
].
2534 last_bd_completed_address
,
2535 (u32
) immrbar_virt_to_phys(endOfRing
));
2539 /* schedulerbasepointer */
2541 if (ug_info
->numQueuesTx
> 1) {
2542 /* scheduler exists only if more than 1 tx queue */
2543 ugeth
->scheduler_offset
=
2544 qe_muram_alloc(sizeof(struct ucc_geth_scheduler
),
2545 UCC_GETH_SCHEDULER_ALIGNMENT
);
2546 if (IS_ERR_VALUE(ugeth
->scheduler_offset
)) {
2547 if (netif_msg_ifup(ugeth
))
2549 ("%s: Can not allocate DPRAM memory for p_scheduler.",
2554 ugeth
->p_scheduler
=
2555 (struct ucc_geth_scheduler __iomem
*) qe_muram_addr(ugeth
->
2557 out_be32(&ugeth
->p_tx_glbl_pram
->schedulerbasepointer
,
2558 ugeth
->scheduler_offset
);
2559 /* Zero out p_scheduler */
2560 memset_io((void __iomem
*)ugeth
->p_scheduler
, 0, sizeof(struct ucc_geth_scheduler
));
2562 /* Set values in scheduler */
2563 out_be32(&ugeth
->p_scheduler
->mblinterval
,
2564 ug_info
->mblinterval
);
2565 out_be16(&ugeth
->p_scheduler
->nortsrbytetime
,
2566 ug_info
->nortsrbytetime
);
2567 out_8(&ugeth
->p_scheduler
->fracsiz
, ug_info
->fracsiz
);
2568 out_8(&ugeth
->p_scheduler
->strictpriorityq
,
2569 ug_info
->strictpriorityq
);
2570 out_8(&ugeth
->p_scheduler
->txasap
, ug_info
->txasap
);
2571 out_8(&ugeth
->p_scheduler
->extrabw
, ug_info
->extrabw
);
2572 for (i
= 0; i
< NUM_TX_QUEUES
; i
++)
2573 out_8(&ugeth
->p_scheduler
->weightfactor
[i
],
2574 ug_info
->weightfactor
[i
]);
2576 /* Set pointers to cpucount registers in scheduler */
2577 ugeth
->p_cpucount
[0] = &(ugeth
->p_scheduler
->cpucount0
);
2578 ugeth
->p_cpucount
[1] = &(ugeth
->p_scheduler
->cpucount1
);
2579 ugeth
->p_cpucount
[2] = &(ugeth
->p_scheduler
->cpucount2
);
2580 ugeth
->p_cpucount
[3] = &(ugeth
->p_scheduler
->cpucount3
);
2581 ugeth
->p_cpucount
[4] = &(ugeth
->p_scheduler
->cpucount4
);
2582 ugeth
->p_cpucount
[5] = &(ugeth
->p_scheduler
->cpucount5
);
2583 ugeth
->p_cpucount
[6] = &(ugeth
->p_scheduler
->cpucount6
);
2584 ugeth
->p_cpucount
[7] = &(ugeth
->p_scheduler
->cpucount7
);
2587 /* schedulerbasepointer */
2588 /* TxRMON_PTR (statistics) */
2590 statisticsMode
& UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX
) {
2591 ugeth
->tx_fw_statistics_pram_offset
=
2592 qe_muram_alloc(sizeof
2593 (struct ucc_geth_tx_firmware_statistics_pram
),
2594 UCC_GETH_TX_STATISTICS_ALIGNMENT
);
2595 if (IS_ERR_VALUE(ugeth
->tx_fw_statistics_pram_offset
)) {
2596 if (netif_msg_ifup(ugeth
))
2598 ("%s: Can not allocate DPRAM memory for"
2599 " p_tx_fw_statistics_pram.",
2603 ugeth
->p_tx_fw_statistics_pram
=
2604 (struct ucc_geth_tx_firmware_statistics_pram __iomem
*)
2605 qe_muram_addr(ugeth
->tx_fw_statistics_pram_offset
);
2606 /* Zero out p_tx_fw_statistics_pram */
2607 memset_io((void __iomem
*)ugeth
->p_tx_fw_statistics_pram
,
2608 0, sizeof(struct ucc_geth_tx_firmware_statistics_pram
));
2612 /* Already has speed set */
2614 if (ug_info
->numQueuesTx
> 1)
2615 temoder
|= TEMODER_SCHEDULER_ENABLE
;
2616 if (ug_info
->ipCheckSumGenerate
)
2617 temoder
|= TEMODER_IP_CHECKSUM_GENERATE
;
2618 temoder
|= ((ug_info
->numQueuesTx
- 1) << TEMODER_NUM_OF_QUEUES_SHIFT
);
2619 out_be16(&ugeth
->p_tx_glbl_pram
->temoder
, temoder
);
2621 test
= in_be16(&ugeth
->p_tx_glbl_pram
->temoder
);
2623 /* Function code register value to be used later */
2624 function_code
= UCC_BMR_BO_BE
| UCC_BMR_GBL
;
2625 /* Required for QE */
2627 /* function code register */
2628 out_be32(&ugeth
->p_tx_glbl_pram
->tstate
, ((u32
) function_code
) << 24);
2630 /* Rx global PRAM */
2631 /* Allocate global rx parameter RAM page */
2632 ugeth
->rx_glbl_pram_offset
=
2633 qe_muram_alloc(sizeof(struct ucc_geth_rx_global_pram
),
2634 UCC_GETH_RX_GLOBAL_PRAM_ALIGNMENT
);
2635 if (IS_ERR_VALUE(ugeth
->rx_glbl_pram_offset
)) {
2636 if (netif_msg_ifup(ugeth
))
2638 ("%s: Can not allocate DPRAM memory for p_rx_glbl_pram.",
2642 ugeth
->p_rx_glbl_pram
=
2643 (struct ucc_geth_rx_global_pram __iomem
*) qe_muram_addr(ugeth
->
2644 rx_glbl_pram_offset
);
2645 /* Zero out p_rx_glbl_pram */
2646 memset_io((void __iomem
*)ugeth
->p_rx_glbl_pram
, 0, sizeof(struct ucc_geth_rx_global_pram
));
2648 /* Fill global PRAM */
2651 /* Size varies with number of Rx threads */
2652 ugeth
->thread_dat_rx_offset
=
2653 qe_muram_alloc(numThreadsRxNumerical
*
2654 sizeof(struct ucc_geth_thread_data_rx
),
2655 UCC_GETH_THREAD_DATA_ALIGNMENT
);
2656 if (IS_ERR_VALUE(ugeth
->thread_dat_rx_offset
)) {
2657 if (netif_msg_ifup(ugeth
))
2659 ("%s: Can not allocate DPRAM memory for p_thread_data_rx.",
2664 ugeth
->p_thread_data_rx
=
2665 (struct ucc_geth_thread_data_rx __iomem
*) qe_muram_addr(ugeth
->
2666 thread_dat_rx_offset
);
2667 out_be32(&ugeth
->p_rx_glbl_pram
->rqptr
, ugeth
->thread_dat_rx_offset
);
2670 out_be16(&ugeth
->p_rx_glbl_pram
->typeorlen
, ug_info
->typeorlen
);
2672 /* rxrmonbaseptr (statistics) */
2674 statisticsMode
& UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX
) {
2675 ugeth
->rx_fw_statistics_pram_offset
=
2676 qe_muram_alloc(sizeof
2677 (struct ucc_geth_rx_firmware_statistics_pram
),
2678 UCC_GETH_RX_STATISTICS_ALIGNMENT
);
2679 if (IS_ERR_VALUE(ugeth
->rx_fw_statistics_pram_offset
)) {
2680 if (netif_msg_ifup(ugeth
))
2682 ("%s: Can not allocate DPRAM memory for"
2683 " p_rx_fw_statistics_pram.", __func__
);
2686 ugeth
->p_rx_fw_statistics_pram
=
2687 (struct ucc_geth_rx_firmware_statistics_pram __iomem
*)
2688 qe_muram_addr(ugeth
->rx_fw_statistics_pram_offset
);
2689 /* Zero out p_rx_fw_statistics_pram */
2690 memset_io((void __iomem
*)ugeth
->p_rx_fw_statistics_pram
, 0,
2691 sizeof(struct ucc_geth_rx_firmware_statistics_pram
));
2694 /* intCoalescingPtr */
2696 /* Size varies with number of Rx queues */
2697 ugeth
->rx_irq_coalescing_tbl_offset
=
2698 qe_muram_alloc(ug_info
->numQueuesRx
*
2699 sizeof(struct ucc_geth_rx_interrupt_coalescing_entry
)
2700 + 4, UCC_GETH_RX_INTERRUPT_COALESCING_ALIGNMENT
);
2701 if (IS_ERR_VALUE(ugeth
->rx_irq_coalescing_tbl_offset
)) {
2702 if (netif_msg_ifup(ugeth
))
2704 ("%s: Can not allocate DPRAM memory for"
2705 " p_rx_irq_coalescing_tbl.", __func__
);
2709 ugeth
->p_rx_irq_coalescing_tbl
=
2710 (struct ucc_geth_rx_interrupt_coalescing_table __iomem
*)
2711 qe_muram_addr(ugeth
->rx_irq_coalescing_tbl_offset
);
2712 out_be32(&ugeth
->p_rx_glbl_pram
->intcoalescingptr
,
2713 ugeth
->rx_irq_coalescing_tbl_offset
);
2715 /* Fill interrupt coalescing table */
2716 for (i
= 0; i
< ug_info
->numQueuesRx
; i
++) {
2717 out_be32(&ugeth
->p_rx_irq_coalescing_tbl
->coalescingentry
[i
].
2718 interruptcoalescingmaxvalue
,
2719 ug_info
->interruptcoalescingmaxvalue
[i
]);
2720 out_be32(&ugeth
->p_rx_irq_coalescing_tbl
->coalescingentry
[i
].
2721 interruptcoalescingcounter
,
2722 ug_info
->interruptcoalescingmaxvalue
[i
]);
2726 init_max_rx_buff_len(uf_info
->max_rx_buf_length
,
2727 &ugeth
->p_rx_glbl_pram
->mrblr
);
2729 out_be16(&ugeth
->p_rx_glbl_pram
->mflr
, ug_info
->maxFrameLength
);
2731 init_min_frame_len(ug_info
->minFrameLength
,
2732 &ugeth
->p_rx_glbl_pram
->minflr
,
2733 &ugeth
->p_rx_glbl_pram
->mrblr
);
2735 out_be16(&ugeth
->p_rx_glbl_pram
->maxd1
, ug_info
->maxD1Length
);
2737 out_be16(&ugeth
->p_rx_glbl_pram
->maxd2
, ug_info
->maxD2Length
);
2741 for (i
= 0; i
< UCC_GETH_VLAN_PRIORITY_MAX
; i
++)
2742 l2qt
|= (ug_info
->l2qt
[i
] << (28 - 4 * i
));
2743 out_be32(&ugeth
->p_rx_glbl_pram
->l2qt
, l2qt
);
2746 for (j
= 0; j
< UCC_GETH_IP_PRIORITY_MAX
; j
+= 8) {
2748 for (i
= 0; i
< 8; i
++)
2749 l3qt
|= (ug_info
->l3qt
[j
+ i
] << (28 - 4 * i
));
2750 out_be32(&ugeth
->p_rx_glbl_pram
->l3qt
[j
/8], l3qt
);
2754 out_be16(&ugeth
->p_rx_glbl_pram
->vlantype
, ug_info
->vlantype
);
2757 out_be16(&ugeth
->p_rx_glbl_pram
->vlantci
, ug_info
->vlantci
);
2760 out_be32(&ugeth
->p_rx_glbl_pram
->ecamptr
, ug_info
->ecamptr
);
2763 /* Size varies with number of Rx queues */
2764 ugeth
->rx_bd_qs_tbl_offset
=
2765 qe_muram_alloc(ug_info
->numQueuesRx
*
2766 (sizeof(struct ucc_geth_rx_bd_queues_entry
) +
2767 sizeof(struct ucc_geth_rx_prefetched_bds
)),
2768 UCC_GETH_RX_BD_QUEUES_ALIGNMENT
);
2769 if (IS_ERR_VALUE(ugeth
->rx_bd_qs_tbl_offset
)) {
2770 if (netif_msg_ifup(ugeth
))
2772 ("%s: Can not allocate DPRAM memory for p_rx_bd_qs_tbl.",
2777 ugeth
->p_rx_bd_qs_tbl
=
2778 (struct ucc_geth_rx_bd_queues_entry __iomem
*) qe_muram_addr(ugeth
->
2779 rx_bd_qs_tbl_offset
);
2780 out_be32(&ugeth
->p_rx_glbl_pram
->rbdqptr
, ugeth
->rx_bd_qs_tbl_offset
);
2781 /* Zero out p_rx_bd_qs_tbl */
2782 memset_io((void __iomem
*)ugeth
->p_rx_bd_qs_tbl
,
2784 ug_info
->numQueuesRx
* (sizeof(struct ucc_geth_rx_bd_queues_entry
) +
2785 sizeof(struct ucc_geth_rx_prefetched_bds
)));
2787 /* Setup the table */
2788 /* Assume BD rings are already established */
2789 for (i
= 0; i
< ug_info
->numQueuesRx
; i
++) {
2790 if (ugeth
->ug_info
->uf_info
.bd_mem_part
== MEM_PART_SYSTEM
) {
2791 out_be32(&ugeth
->p_rx_bd_qs_tbl
[i
].externalbdbaseptr
,
2792 (u32
) virt_to_phys(ugeth
->p_rx_bd_ring
[i
]));
2793 } else if (ugeth
->ug_info
->uf_info
.bd_mem_part
==
2795 out_be32(&ugeth
->p_rx_bd_qs_tbl
[i
].externalbdbaseptr
,
2796 (u32
) immrbar_virt_to_phys(ugeth
->
2799 /* rest of fields handled by QE */
2803 /* Already has speed set */
2805 if (ugeth
->rx_extended_features
)
2806 remoder
|= REMODER_RX_EXTENDED_FEATURES
;
2807 if (ug_info
->rxExtendedFiltering
)
2808 remoder
|= REMODER_RX_EXTENDED_FILTERING
;
2809 if (ug_info
->dynamicMaxFrameLength
)
2810 remoder
|= REMODER_DYNAMIC_MAX_FRAME_LENGTH
;
2811 if (ug_info
->dynamicMinFrameLength
)
2812 remoder
|= REMODER_DYNAMIC_MIN_FRAME_LENGTH
;
2814 ug_info
->vlanOperationTagged
<< REMODER_VLAN_OPERATION_TAGGED_SHIFT
;
2817 vlanOperationNonTagged
<< REMODER_VLAN_OPERATION_NON_TAGGED_SHIFT
;
2818 remoder
|= ug_info
->rxQoSMode
<< REMODER_RX_QOS_MODE_SHIFT
;
2819 remoder
|= ((ug_info
->numQueuesRx
- 1) << REMODER_NUM_OF_QUEUES_SHIFT
);
2820 if (ug_info
->ipCheckSumCheck
)
2821 remoder
|= REMODER_IP_CHECKSUM_CHECK
;
2822 if (ug_info
->ipAddressAlignment
)
2823 remoder
|= REMODER_IP_ADDRESS_ALIGNMENT
;
2824 out_be32(&ugeth
->p_rx_glbl_pram
->remoder
, remoder
);
2826 /* Note that this function must be called */
2827 /* ONLY AFTER p_tx_fw_statistics_pram */
2828 /* andp_UccGethRxFirmwareStatisticsPram are allocated ! */
2829 init_firmware_statistics_gathering_mode((ug_info
->
2831 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX
),
2832 (ug_info
->statisticsMode
&
2833 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX
),
2834 &ugeth
->p_tx_glbl_pram
->txrmonbaseptr
,
2835 ugeth
->tx_fw_statistics_pram_offset
,
2836 &ugeth
->p_rx_glbl_pram
->rxrmonbaseptr
,
2837 ugeth
->rx_fw_statistics_pram_offset
,
2838 &ugeth
->p_tx_glbl_pram
->temoder
,
2839 &ugeth
->p_rx_glbl_pram
->remoder
);
2841 /* function code register */
2842 out_8(&ugeth
->p_rx_glbl_pram
->rstate
, function_code
);
2844 /* initialize extended filtering */
2845 if (ug_info
->rxExtendedFiltering
) {
2846 if (!ug_info
->extendedFilteringChainPointer
) {
2847 if (netif_msg_ifup(ugeth
))
2848 ugeth_err("%s: Null Extended Filtering Chain Pointer.",
2853 /* Allocate memory for extended filtering Mode Global
2855 ugeth
->exf_glbl_param_offset
=
2856 qe_muram_alloc(sizeof(struct ucc_geth_exf_global_pram
),
2857 UCC_GETH_RX_EXTENDED_FILTERING_GLOBAL_PARAMETERS_ALIGNMENT
);
2858 if (IS_ERR_VALUE(ugeth
->exf_glbl_param_offset
)) {
2859 if (netif_msg_ifup(ugeth
))
2861 ("%s: Can not allocate DPRAM memory for"
2862 " p_exf_glbl_param.", __func__
);
2866 ugeth
->p_exf_glbl_param
=
2867 (struct ucc_geth_exf_global_pram __iomem
*) qe_muram_addr(ugeth
->
2868 exf_glbl_param_offset
);
2869 out_be32(&ugeth
->p_rx_glbl_pram
->exfGlobalParam
,
2870 ugeth
->exf_glbl_param_offset
);
2871 out_be32(&ugeth
->p_exf_glbl_param
->l2pcdptr
,
2872 (u32
) ug_info
->extendedFilteringChainPointer
);
2874 } else { /* initialize 82xx style address filtering */
2876 /* Init individual address recognition registers to disabled */
2878 for (j
= 0; j
< NUM_OF_PADDRS
; j
++)
2879 ugeth_82xx_filtering_clear_addr_in_paddr(ugeth
, (u8
) j
);
2882 (struct ucc_geth_82xx_address_filtering_pram __iomem
*) ugeth
->
2883 p_rx_glbl_pram
->addressfiltering
;
2885 ugeth_82xx_filtering_clear_all_addr_in_hash(ugeth
,
2886 ENET_ADDR_TYPE_GROUP
);
2887 ugeth_82xx_filtering_clear_all_addr_in_hash(ugeth
,
2888 ENET_ADDR_TYPE_INDIVIDUAL
);
2892 * Initialize UCC at QE level
2895 command
= QE_INIT_TX_RX
;
2897 /* Allocate shadow InitEnet command parameter structure.
2898 * This is needed because after the InitEnet command is executed,
2899 * the structure in DPRAM is released, because DPRAM is a premium
2901 * This shadow structure keeps a copy of what was done so that the
2902 * allocated resources can be released when the channel is freed.
2904 if (!(ugeth
->p_init_enet_param_shadow
=
2905 kmalloc(sizeof(struct ucc_geth_init_pram
), GFP_KERNEL
))) {
2906 if (netif_msg_ifup(ugeth
))
2908 ("%s: Can not allocate memory for"
2909 " p_UccInitEnetParamShadows.", __func__
);
2912 /* Zero out *p_init_enet_param_shadow */
2913 memset((char *)ugeth
->p_init_enet_param_shadow
,
2914 0, sizeof(struct ucc_geth_init_pram
));
2916 /* Fill shadow InitEnet command parameter structure */
2918 ugeth
->p_init_enet_param_shadow
->resinit1
=
2919 ENET_INIT_PARAM_MAGIC_RES_INIT1
;
2920 ugeth
->p_init_enet_param_shadow
->resinit2
=
2921 ENET_INIT_PARAM_MAGIC_RES_INIT2
;
2922 ugeth
->p_init_enet_param_shadow
->resinit3
=
2923 ENET_INIT_PARAM_MAGIC_RES_INIT3
;
2924 ugeth
->p_init_enet_param_shadow
->resinit4
=
2925 ENET_INIT_PARAM_MAGIC_RES_INIT4
;
2926 ugeth
->p_init_enet_param_shadow
->resinit5
=
2927 ENET_INIT_PARAM_MAGIC_RES_INIT5
;
2928 ugeth
->p_init_enet_param_shadow
->rgftgfrxglobal
|=
2929 ((u32
) ug_info
->numThreadsRx
) << ENET_INIT_PARAM_RGF_SHIFT
;
2930 ugeth
->p_init_enet_param_shadow
->rgftgfrxglobal
|=
2931 ((u32
) ug_info
->numThreadsTx
) << ENET_INIT_PARAM_TGF_SHIFT
;
2933 ugeth
->p_init_enet_param_shadow
->rgftgfrxglobal
|=
2934 ugeth
->rx_glbl_pram_offset
| ug_info
->riscRx
;
2935 if ((ug_info
->largestexternallookupkeysize
!=
2936 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_NONE
)
2937 && (ug_info
->largestexternallookupkeysize
!=
2938 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_8_BYTES
)
2939 && (ug_info
->largestexternallookupkeysize
!=
2940 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_16_BYTES
)) {
2941 if (netif_msg_ifup(ugeth
))
2942 ugeth_err("%s: Invalid largest External Lookup Key Size.",
2946 ugeth
->p_init_enet_param_shadow
->largestexternallookupkeysize
=
2947 ug_info
->largestexternallookupkeysize
;
2948 size
= sizeof(struct ucc_geth_thread_rx_pram
);
2949 if (ug_info
->rxExtendedFiltering
) {
2950 size
+= THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING
;
2951 if (ug_info
->largestexternallookupkeysize
==
2952 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES
)
2954 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_8
;
2955 if (ug_info
->largestexternallookupkeysize
==
2956 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES
)
2958 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_16
;
2961 if ((ret_val
= fill_init_enet_entries(ugeth
, &(ugeth
->
2962 p_init_enet_param_shadow
->rxthread
[0]),
2963 (u8
) (numThreadsRxNumerical
+ 1)
2964 /* Rx needs one extra for terminator */
2965 , size
, UCC_GETH_THREAD_RX_PRAM_ALIGNMENT
,
2966 ug_info
->riscRx
, 1)) != 0) {
2967 if (netif_msg_ifup(ugeth
))
2968 ugeth_err("%s: Can not fill p_init_enet_param_shadow.",
2973 ugeth
->p_init_enet_param_shadow
->txglobal
=
2974 ugeth
->tx_glbl_pram_offset
| ug_info
->riscTx
;
2976 fill_init_enet_entries(ugeth
,
2977 &(ugeth
->p_init_enet_param_shadow
->
2978 txthread
[0]), numThreadsTxNumerical
,
2979 sizeof(struct ucc_geth_thread_tx_pram
),
2980 UCC_GETH_THREAD_TX_PRAM_ALIGNMENT
,
2981 ug_info
->riscTx
, 0)) != 0) {
2982 if (netif_msg_ifup(ugeth
))
2983 ugeth_err("%s: Can not fill p_init_enet_param_shadow.",
2988 /* Load Rx bds with buffers */
2989 for (i
= 0; i
< ug_info
->numQueuesRx
; i
++) {
2990 if ((ret_val
= rx_bd_buffer_set(ugeth
, (u8
) i
)) != 0) {
2991 if (netif_msg_ifup(ugeth
))
2992 ugeth_err("%s: Can not fill Rx bds with buffers.",
2998 /* Allocate InitEnet command parameter structure */
2999 init_enet_pram_offset
= qe_muram_alloc(sizeof(struct ucc_geth_init_pram
), 4);
3000 if (IS_ERR_VALUE(init_enet_pram_offset
)) {
3001 if (netif_msg_ifup(ugeth
))
3003 ("%s: Can not allocate DPRAM memory for p_init_enet_pram.",
3008 (struct ucc_geth_init_pram __iomem
*) qe_muram_addr(init_enet_pram_offset
);
3010 /* Copy shadow InitEnet command parameter structure into PRAM */
3011 out_8(&p_init_enet_pram
->resinit1
,
3012 ugeth
->p_init_enet_param_shadow
->resinit1
);
3013 out_8(&p_init_enet_pram
->resinit2
,
3014 ugeth
->p_init_enet_param_shadow
->resinit2
);
3015 out_8(&p_init_enet_pram
->resinit3
,
3016 ugeth
->p_init_enet_param_shadow
->resinit3
);
3017 out_8(&p_init_enet_pram
->resinit4
,
3018 ugeth
->p_init_enet_param_shadow
->resinit4
);
3019 out_be16(&p_init_enet_pram
->resinit5
,
3020 ugeth
->p_init_enet_param_shadow
->resinit5
);
3021 out_8(&p_init_enet_pram
->largestexternallookupkeysize
,
3022 ugeth
->p_init_enet_param_shadow
->largestexternallookupkeysize
);
3023 out_be32(&p_init_enet_pram
->rgftgfrxglobal
,
3024 ugeth
->p_init_enet_param_shadow
->rgftgfrxglobal
);
3025 for (i
= 0; i
< ENET_INIT_PARAM_MAX_ENTRIES_RX
; i
++)
3026 out_be32(&p_init_enet_pram
->rxthread
[i
],
3027 ugeth
->p_init_enet_param_shadow
->rxthread
[i
]);
3028 out_be32(&p_init_enet_pram
->txglobal
,
3029 ugeth
->p_init_enet_param_shadow
->txglobal
);
3030 for (i
= 0; i
< ENET_INIT_PARAM_MAX_ENTRIES_TX
; i
++)
3031 out_be32(&p_init_enet_pram
->txthread
[i
],
3032 ugeth
->p_init_enet_param_shadow
->txthread
[i
]);
3034 /* Issue QE command */
3036 ucc_fast_get_qe_cr_subblock(ugeth
->ug_info
->uf_info
.ucc_num
);
3037 qe_issue_cmd(command
, cecr_subblock
, QE_CR_PROTOCOL_ETHERNET
,
3038 init_enet_pram_offset
);
3040 /* Free InitEnet command parameter */
3041 qe_muram_free(init_enet_pram_offset
);
3046 /* This is called by the kernel when a frame is ready for transmission. */
3047 /* It is pointed to by the dev->hard_start_xmit function pointer */
3048 static int ucc_geth_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
3050 struct ucc_geth_private
*ugeth
= netdev_priv(dev
);
3051 #ifdef CONFIG_UGETH_TX_ON_DEMAND
3052 struct ucc_fast_private
*uccf
;
3054 u8 __iomem
*bd
; /* BD pointer */
3058 ugeth_vdbg("%s: IN", __func__
);
3060 spin_lock_irq(&ugeth
->lock
);
3062 dev
->stats
.tx_bytes
+= skb
->len
;
3064 /* Start from the next BD that should be filled */
3065 bd
= ugeth
->txBd
[txQ
];
3066 bd_status
= in_be32((u32 __iomem
*)bd
);
3067 /* Save the skb pointer so we can free it later */
3068 ugeth
->tx_skbuff
[txQ
][ugeth
->skb_curtx
[txQ
]] = skb
;
3070 /* Update the current skb pointer (wrapping if this was the last) */
3071 ugeth
->skb_curtx
[txQ
] =
3072 (ugeth
->skb_curtx
[txQ
] +
3073 1) & TX_RING_MOD_MASK(ugeth
->ug_info
->bdRingLenTx
[txQ
]);
3075 /* set up the buffer descriptor */
3076 out_be32(&((struct qe_bd __iomem
*)bd
)->buf
,
3077 dma_map_single(ugeth
->dev
, skb
->data
,
3078 skb
->len
, DMA_TO_DEVICE
));
3080 /* printk(KERN_DEBUG"skb->data is 0x%x\n",skb->data); */
3082 bd_status
= (bd_status
& T_W
) | T_R
| T_I
| T_L
| skb
->len
;
3084 /* set bd status and length */
3085 out_be32((u32 __iomem
*)bd
, bd_status
);
3087 dev
->trans_start
= jiffies
;
3089 /* Move to next BD in the ring */
3090 if (!(bd_status
& T_W
))
3091 bd
+= sizeof(struct qe_bd
);
3093 bd
= ugeth
->p_tx_bd_ring
[txQ
];
3095 /* If the next BD still needs to be cleaned up, then the bds
3096 are full. We need to tell the kernel to stop sending us stuff. */
3097 if (bd
== ugeth
->confBd
[txQ
]) {
3098 if (!netif_queue_stopped(dev
))
3099 netif_stop_queue(dev
);
3102 ugeth
->txBd
[txQ
] = bd
;
3104 if (ugeth
->p_scheduler
) {
3105 ugeth
->cpucount
[txQ
]++;
3106 /* Indicate to QE that there are more Tx bds ready for
3108 /* This is done by writing a running counter of the bd
3109 count to the scheduler PRAM. */
3110 out_be16(ugeth
->p_cpucount
[txQ
], ugeth
->cpucount
[txQ
]);
3113 #ifdef CONFIG_UGETH_TX_ON_DEMAND
3115 out_be16(uccf
->p_utodr
, UCC_FAST_TOD
);
3117 spin_unlock_irq(&ugeth
->lock
);
3122 static int ucc_geth_rx(struct ucc_geth_private
*ugeth
, u8 rxQ
, int rx_work_limit
)
3124 struct sk_buff
*skb
;
3126 u16 length
, howmany
= 0;
3129 struct net_device
*dev
;
3131 ugeth_vdbg("%s: IN", __func__
);
3135 /* collect received buffers */
3136 bd
= ugeth
->rxBd
[rxQ
];
3138 bd_status
= in_be32((u32 __iomem
*)bd
);
3140 /* while there are received buffers and BD is full (~R_E) */
3141 while (!((bd_status
& (R_E
)) || (--rx_work_limit
< 0))) {
3142 bdBuffer
= (u8
*) in_be32(&((struct qe_bd __iomem
*)bd
)->buf
);
3143 length
= (u16
) ((bd_status
& BD_LENGTH_MASK
) - 4);
3144 skb
= ugeth
->rx_skbuff
[rxQ
][ugeth
->skb_currx
[rxQ
]];
3146 /* determine whether buffer is first, last, first and last
3147 (single buffer frame) or middle (not first and not last) */
3149 (!(bd_status
& (R_F
| R_L
))) ||
3150 (bd_status
& R_ERRORS_FATAL
)) {
3151 if (netif_msg_rx_err(ugeth
))
3152 ugeth_err("%s, %d: ERROR!!! skb - 0x%08x",
3153 __func__
, __LINE__
, (u32
) skb
);
3155 dev_kfree_skb_any(skb
);
3157 ugeth
->rx_skbuff
[rxQ
][ugeth
->skb_currx
[rxQ
]] = NULL
;
3158 dev
->stats
.rx_dropped
++;
3160 dev
->stats
.rx_packets
++;
3163 /* Prep the skb for the packet */
3164 skb_put(skb
, length
);
3166 /* Tell the skb what kind of packet this is */
3167 skb
->protocol
= eth_type_trans(skb
, ugeth
->ndev
);
3169 dev
->stats
.rx_bytes
+= length
;
3170 /* Send the packet up the stack */
3171 netif_receive_skb(skb
);
3174 skb
= get_new_skb(ugeth
, bd
);
3176 if (netif_msg_rx_err(ugeth
))
3177 ugeth_warn("%s: No Rx Data Buffer", __func__
);
3178 dev
->stats
.rx_dropped
++;
3182 ugeth
->rx_skbuff
[rxQ
][ugeth
->skb_currx
[rxQ
]] = skb
;
3184 /* update to point at the next skb */
3185 ugeth
->skb_currx
[rxQ
] =
3186 (ugeth
->skb_currx
[rxQ
] +
3187 1) & RX_RING_MOD_MASK(ugeth
->ug_info
->bdRingLenRx
[rxQ
]);
3189 if (bd_status
& R_W
)
3190 bd
= ugeth
->p_rx_bd_ring
[rxQ
];
3192 bd
+= sizeof(struct qe_bd
);
3194 bd_status
= in_be32((u32 __iomem
*)bd
);
3197 ugeth
->rxBd
[rxQ
] = bd
;
3201 static int ucc_geth_tx(struct net_device
*dev
, u8 txQ
)
3203 /* Start from the next BD that should be filled */
3204 struct ucc_geth_private
*ugeth
= netdev_priv(dev
);
3205 u8 __iomem
*bd
; /* BD pointer */
3208 bd
= ugeth
->confBd
[txQ
];
3209 bd_status
= in_be32((u32 __iomem
*)bd
);
3211 /* Normal processing. */
3212 while ((bd_status
& T_R
) == 0) {
3213 /* BD contains already transmitted buffer. */
3214 /* Handle the transmitted buffer and release */
3215 /* the BD to be used with the current frame */
3217 if ((bd
== ugeth
->txBd
[txQ
]) && (netif_queue_stopped(dev
) == 0))
3220 dev
->stats
.tx_packets
++;
3222 /* Free the sk buffer associated with this TxBD */
3223 dev_kfree_skb(ugeth
->
3224 tx_skbuff
[txQ
][ugeth
->skb_dirtytx
[txQ
]]);
3225 ugeth
->tx_skbuff
[txQ
][ugeth
->skb_dirtytx
[txQ
]] = NULL
;
3226 ugeth
->skb_dirtytx
[txQ
] =
3227 (ugeth
->skb_dirtytx
[txQ
] +
3228 1) & TX_RING_MOD_MASK(ugeth
->ug_info
->bdRingLenTx
[txQ
]);
3230 /* We freed a buffer, so now we can restart transmission */
3231 if (netif_queue_stopped(dev
))
3232 netif_wake_queue(dev
);
3234 /* Advance the confirmation BD pointer */
3235 if (!(bd_status
& T_W
))
3236 bd
+= sizeof(struct qe_bd
);
3238 bd
= ugeth
->p_tx_bd_ring
[txQ
];
3239 bd_status
= in_be32((u32 __iomem
*)bd
);
3241 ugeth
->confBd
[txQ
] = bd
;
3245 static int ucc_geth_poll(struct napi_struct
*napi
, int budget
)
3247 struct ucc_geth_private
*ugeth
= container_of(napi
, struct ucc_geth_private
, napi
);
3248 struct ucc_geth_info
*ug_info
;
3251 ug_info
= ugeth
->ug_info
;
3254 for (i
= 0; i
< ug_info
->numQueuesRx
; i
++)
3255 howmany
+= ucc_geth_rx(ugeth
, i
, budget
- howmany
);
3257 /* Tx event processing */
3258 spin_lock(&ugeth
->lock
);
3259 for (i
= 0; i
< ug_info
->numQueuesTx
; i
++)
3260 ucc_geth_tx(ugeth
->ndev
, i
);
3261 spin_unlock(&ugeth
->lock
);
3263 if (howmany
< budget
) {
3264 napi_complete(napi
);
3265 setbits32(ugeth
->uccf
->p_uccm
, UCCE_RX_EVENTS
| UCCE_TX_EVENTS
);
3271 static irqreturn_t
ucc_geth_irq_handler(int irq
, void *info
)
3273 struct net_device
*dev
= info
;
3274 struct ucc_geth_private
*ugeth
= netdev_priv(dev
);
3275 struct ucc_fast_private
*uccf
;
3276 struct ucc_geth_info
*ug_info
;
3280 ugeth_vdbg("%s: IN", __func__
);
3283 ug_info
= ugeth
->ug_info
;
3285 /* read and clear events */
3286 ucce
= (u32
) in_be32(uccf
->p_ucce
);
3287 uccm
= (u32
) in_be32(uccf
->p_uccm
);
3289 out_be32(uccf
->p_ucce
, ucce
);
3291 /* check for receive events that require processing */
3292 if (ucce
& (UCCE_RX_EVENTS
| UCCE_TX_EVENTS
)) {
3293 if (napi_schedule_prep(&ugeth
->napi
)) {
3294 uccm
&= ~(UCCE_RX_EVENTS
| UCCE_TX_EVENTS
);
3295 out_be32(uccf
->p_uccm
, uccm
);
3296 __napi_schedule(&ugeth
->napi
);
3300 /* Errors and other events */
3301 if (ucce
& UCCE_OTHER
) {
3302 if (ucce
& UCC_GETH_UCCE_BSY
)
3303 dev
->stats
.rx_errors
++;
3304 if (ucce
& UCC_GETH_UCCE_TXE
)
3305 dev
->stats
.tx_errors
++;
3311 #ifdef CONFIG_NET_POLL_CONTROLLER
3313 * Polling 'interrupt' - used by things like netconsole to send skbs
3314 * without having to re-enable interrupts. It's not called while
3315 * the interrupt routine is executing.
3317 static void ucc_netpoll(struct net_device
*dev
)
3319 struct ucc_geth_private
*ugeth
= netdev_priv(dev
);
3320 int irq
= ugeth
->ug_info
->uf_info
.irq
;
3323 ucc_geth_irq_handler(irq
, dev
);
3326 #endif /* CONFIG_NET_POLL_CONTROLLER */
3328 /* Called when something needs to use the ethernet device */
3329 /* Returns 0 for success. */
3330 static int ucc_geth_open(struct net_device
*dev
)
3332 struct ucc_geth_private
*ugeth
= netdev_priv(dev
);
3335 ugeth_vdbg("%s: IN", __func__
);
3337 /* Test station address */
3338 if (dev
->dev_addr
[0] & ENET_GROUP_ADDR
) {
3339 if (netif_msg_ifup(ugeth
))
3340 ugeth_err("%s: Multicast address used for station address"
3341 " - is this what you wanted?", __func__
);
3345 err
= init_phy(dev
);
3347 if (netif_msg_ifup(ugeth
))
3348 ugeth_err("%s: Cannot initialize PHY, aborting.",
3353 err
= ucc_struct_init(ugeth
);
3355 if (netif_msg_ifup(ugeth
))
3356 ugeth_err("%s: Cannot configure internal struct, aborting.", dev
->name
);
3360 napi_enable(&ugeth
->napi
);
3362 err
= ucc_geth_startup(ugeth
);
3364 if (netif_msg_ifup(ugeth
))
3365 ugeth_err("%s: Cannot configure net device, aborting.",
3370 err
= adjust_enet_interface(ugeth
);
3372 if (netif_msg_ifup(ugeth
))
3373 ugeth_err("%s: Cannot configure net device, aborting.",
3378 /* Set MACSTNADDR1, MACSTNADDR2 */
3379 /* For more details see the hardware spec. */
3380 init_mac_station_addr_regs(dev
->dev_addr
[0],
3386 &ugeth
->ug_regs
->macstnaddr1
,
3387 &ugeth
->ug_regs
->macstnaddr2
);
3389 phy_start(ugeth
->phydev
);
3391 err
= ugeth_enable(ugeth
, COMM_DIR_RX_AND_TX
);
3393 if (netif_msg_ifup(ugeth
))
3394 ugeth_err("%s: Cannot enable net device, aborting.", dev
->name
);
3398 err
= request_irq(ugeth
->ug_info
->uf_info
.irq
, ucc_geth_irq_handler
,
3399 0, "UCC Geth", dev
);
3401 if (netif_msg_ifup(ugeth
))
3402 ugeth_err("%s: Cannot get IRQ for net device, aborting.",
3407 netif_start_queue(dev
);
3412 napi_disable(&ugeth
->napi
);
3414 ucc_geth_stop(ugeth
);
3418 /* Stops the kernel queue, and halts the controller */
3419 static int ucc_geth_close(struct net_device
*dev
)
3421 struct ucc_geth_private
*ugeth
= netdev_priv(dev
);
3423 ugeth_vdbg("%s: IN", __func__
);
3425 napi_disable(&ugeth
->napi
);
3427 ucc_geth_stop(ugeth
);
3429 free_irq(ugeth
->ug_info
->uf_info
.irq
, ugeth
->ndev
);
3431 netif_stop_queue(dev
);
3436 /* Reopen device. This will reset the MAC and PHY. */
3437 static void ucc_geth_timeout_work(struct work_struct
*work
)
3439 struct ucc_geth_private
*ugeth
;
3440 struct net_device
*dev
;
3442 ugeth
= container_of(work
, struct ucc_geth_private
, timeout_work
);
3445 ugeth_vdbg("%s: IN", __func__
);
3447 dev
->stats
.tx_errors
++;
3449 ugeth_dump_regs(ugeth
);
3451 if (dev
->flags
& IFF_UP
) {
3453 * Must reset MAC *and* PHY. This is done by reopening
3456 ucc_geth_close(dev
);
3460 netif_tx_schedule_all(dev
);
3464 * ucc_geth_timeout gets called when a packet has not been
3465 * transmitted after a set amount of time.
3467 static void ucc_geth_timeout(struct net_device
*dev
)
3469 struct ucc_geth_private
*ugeth
= netdev_priv(dev
);
3471 netif_carrier_off(dev
);
3472 schedule_work(&ugeth
->timeout_work
);
3475 static phy_interface_t
to_phy_interface(const char *phy_connection_type
)
3477 if (strcasecmp(phy_connection_type
, "mii") == 0)
3478 return PHY_INTERFACE_MODE_MII
;
3479 if (strcasecmp(phy_connection_type
, "gmii") == 0)
3480 return PHY_INTERFACE_MODE_GMII
;
3481 if (strcasecmp(phy_connection_type
, "tbi") == 0)
3482 return PHY_INTERFACE_MODE_TBI
;
3483 if (strcasecmp(phy_connection_type
, "rmii") == 0)
3484 return PHY_INTERFACE_MODE_RMII
;
3485 if (strcasecmp(phy_connection_type
, "rgmii") == 0)
3486 return PHY_INTERFACE_MODE_RGMII
;
3487 if (strcasecmp(phy_connection_type
, "rgmii-id") == 0)
3488 return PHY_INTERFACE_MODE_RGMII_ID
;
3489 if (strcasecmp(phy_connection_type
, "rgmii-txid") == 0)
3490 return PHY_INTERFACE_MODE_RGMII_TXID
;
3491 if (strcasecmp(phy_connection_type
, "rgmii-rxid") == 0)
3492 return PHY_INTERFACE_MODE_RGMII_RXID
;
3493 if (strcasecmp(phy_connection_type
, "rtbi") == 0)
3494 return PHY_INTERFACE_MODE_RTBI
;
3496 return PHY_INTERFACE_MODE_MII
;
3499 static const struct net_device_ops ucc_geth_netdev_ops
= {
3500 .ndo_open
= ucc_geth_open
,
3501 .ndo_stop
= ucc_geth_close
,
3502 .ndo_start_xmit
= ucc_geth_start_xmit
,
3503 .ndo_validate_addr
= eth_validate_addr
,
3504 .ndo_set_mac_address
= eth_mac_addr
,
3505 .ndo_change_mtu
= eth_change_mtu
,
3506 .ndo_set_multicast_list
= ucc_geth_set_multi
,
3507 .ndo_tx_timeout
= ucc_geth_timeout
,
3508 #ifdef CONFIG_NET_POLL_CONTROLLER
3509 .ndo_poll_controller
= ucc_netpoll
,
3513 static int ucc_geth_probe(struct of_device
* ofdev
, const struct of_device_id
*match
)
3515 struct device
*device
= &ofdev
->dev
;
3516 struct device_node
*np
= ofdev
->node
;
3517 struct net_device
*dev
= NULL
;
3518 struct ucc_geth_private
*ugeth
= NULL
;
3519 struct ucc_geth_info
*ug_info
;
3520 struct resource res
;
3521 struct device_node
*phy
;
3522 int err
, ucc_num
, max_speed
= 0;
3523 const u32
*fixed_link
;
3524 const unsigned int *prop
;
3526 const void *mac_addr
;
3527 phy_interface_t phy_interface
;
3528 static const int enet_to_speed
[] = {
3529 SPEED_10
, SPEED_10
, SPEED_10
,
3530 SPEED_100
, SPEED_100
, SPEED_100
,
3531 SPEED_1000
, SPEED_1000
, SPEED_1000
, SPEED_1000
,
3533 static const phy_interface_t enet_to_phy_interface
[] = {
3534 PHY_INTERFACE_MODE_MII
, PHY_INTERFACE_MODE_RMII
,
3535 PHY_INTERFACE_MODE_RGMII
, PHY_INTERFACE_MODE_MII
,
3536 PHY_INTERFACE_MODE_RMII
, PHY_INTERFACE_MODE_RGMII
,
3537 PHY_INTERFACE_MODE_GMII
, PHY_INTERFACE_MODE_RGMII
,
3538 PHY_INTERFACE_MODE_TBI
, PHY_INTERFACE_MODE_RTBI
,
3541 ugeth_vdbg("%s: IN", __func__
);
3543 prop
= of_get_property(np
, "cell-index", NULL
);
3545 prop
= of_get_property(np
, "device-id", NULL
);
3550 ucc_num
= *prop
- 1;
3551 if ((ucc_num
< 0) || (ucc_num
> 7))
3554 ug_info
= &ugeth_info
[ucc_num
];
3555 if (ug_info
== NULL
) {
3556 if (netif_msg_probe(&debug
))
3557 ugeth_err("%s: [%d] Missing additional data!",
3562 ug_info
->uf_info
.ucc_num
= ucc_num
;
3564 sprop
= of_get_property(np
, "rx-clock-name", NULL
);
3566 ug_info
->uf_info
.rx_clock
= qe_clock_source(sprop
);
3567 if ((ug_info
->uf_info
.rx_clock
< QE_CLK_NONE
) ||
3568 (ug_info
->uf_info
.rx_clock
> QE_CLK24
)) {
3570 "ucc_geth: invalid rx-clock-name property\n");
3574 prop
= of_get_property(np
, "rx-clock", NULL
);
3576 /* If both rx-clock-name and rx-clock are missing,
3577 we want to tell people to use rx-clock-name. */
3579 "ucc_geth: missing rx-clock-name property\n");
3582 if ((*prop
< QE_CLK_NONE
) || (*prop
> QE_CLK24
)) {
3584 "ucc_geth: invalid rx-clock propperty\n");
3587 ug_info
->uf_info
.rx_clock
= *prop
;
3590 sprop
= of_get_property(np
, "tx-clock-name", NULL
);
3592 ug_info
->uf_info
.tx_clock
= qe_clock_source(sprop
);
3593 if ((ug_info
->uf_info
.tx_clock
< QE_CLK_NONE
) ||
3594 (ug_info
->uf_info
.tx_clock
> QE_CLK24
)) {
3596 "ucc_geth: invalid tx-clock-name property\n");
3600 prop
= of_get_property(np
, "tx-clock", NULL
);
3603 "ucc_geth: mising tx-clock-name property\n");
3606 if ((*prop
< QE_CLK_NONE
) || (*prop
> QE_CLK24
)) {
3608 "ucc_geth: invalid tx-clock property\n");
3611 ug_info
->uf_info
.tx_clock
= *prop
;
3614 err
= of_address_to_resource(np
, 0, &res
);
3618 ug_info
->uf_info
.regs
= res
.start
;
3619 ug_info
->uf_info
.irq
= irq_of_parse_and_map(np
, 0);
3620 fixed_link
= of_get_property(np
, "fixed-link", NULL
);
3624 phy
= of_parse_phandle(np
, "phy-handle", 0);
3628 ug_info
->phy_node
= phy
;
3630 /* get the phy interface type, or default to MII */
3631 prop
= of_get_property(np
, "phy-connection-type", NULL
);
3633 /* handle interface property present in old trees */
3634 prop
= of_get_property(phy
, "interface", NULL
);
3636 phy_interface
= enet_to_phy_interface
[*prop
];
3637 max_speed
= enet_to_speed
[*prop
];
3639 phy_interface
= PHY_INTERFACE_MODE_MII
;
3641 phy_interface
= to_phy_interface((const char *)prop
);
3644 /* get speed, or derive from PHY interface */
3646 switch (phy_interface
) {
3647 case PHY_INTERFACE_MODE_GMII
:
3648 case PHY_INTERFACE_MODE_RGMII
:
3649 case PHY_INTERFACE_MODE_RGMII_ID
:
3650 case PHY_INTERFACE_MODE_RGMII_RXID
:
3651 case PHY_INTERFACE_MODE_RGMII_TXID
:
3652 case PHY_INTERFACE_MODE_TBI
:
3653 case PHY_INTERFACE_MODE_RTBI
:
3654 max_speed
= SPEED_1000
;
3657 max_speed
= SPEED_100
;
3661 if (max_speed
== SPEED_1000
) {
3662 /* configure muram FIFOs for gigabit operation */
3663 ug_info
->uf_info
.urfs
= UCC_GETH_URFS_GIGA_INIT
;
3664 ug_info
->uf_info
.urfet
= UCC_GETH_URFET_GIGA_INIT
;
3665 ug_info
->uf_info
.urfset
= UCC_GETH_URFSET_GIGA_INIT
;
3666 ug_info
->uf_info
.utfs
= UCC_GETH_UTFS_GIGA_INIT
;
3667 ug_info
->uf_info
.utfet
= UCC_GETH_UTFET_GIGA_INIT
;
3668 ug_info
->uf_info
.utftt
= UCC_GETH_UTFTT_GIGA_INIT
;
3669 ug_info
->numThreadsTx
= UCC_GETH_NUM_OF_THREADS_4
;
3670 ug_info
->numThreadsRx
= UCC_GETH_NUM_OF_THREADS_4
;
3673 if (netif_msg_probe(&debug
))
3674 printk(KERN_INFO
"ucc_geth: UCC%1d at 0x%8x (irq = %d) \n",
3675 ug_info
->uf_info
.ucc_num
+ 1, ug_info
->uf_info
.regs
,
3676 ug_info
->uf_info
.irq
);
3678 /* Create an ethernet device instance */
3679 dev
= alloc_etherdev(sizeof(*ugeth
));
3684 ugeth
= netdev_priv(dev
);
3685 spin_lock_init(&ugeth
->lock
);
3687 /* Create CQs for hash tables */
3688 INIT_LIST_HEAD(&ugeth
->group_hash_q
);
3689 INIT_LIST_HEAD(&ugeth
->ind_hash_q
);
3691 dev_set_drvdata(device
, dev
);
3693 /* Set the dev->base_addr to the gfar reg region */
3694 dev
->base_addr
= (unsigned long)(ug_info
->uf_info
.regs
);
3696 SET_NETDEV_DEV(dev
, device
);
3698 /* Fill in the dev structure */
3699 uec_set_ethtool_ops(dev
);
3700 dev
->netdev_ops
= &ucc_geth_netdev_ops
;
3701 dev
->watchdog_timeo
= TX_TIMEOUT
;
3702 INIT_WORK(&ugeth
->timeout_work
, ucc_geth_timeout_work
);
3703 netif_napi_add(dev
, &ugeth
->napi
, ucc_geth_poll
, 64);
3706 ugeth
->msg_enable
= netif_msg_init(debug
.msg_enable
, UGETH_MSG_DEFAULT
);
3707 ugeth
->phy_interface
= phy_interface
;
3708 ugeth
->max_speed
= max_speed
;
3710 err
= register_netdev(dev
);
3712 if (netif_msg_probe(ugeth
))
3713 ugeth_err("%s: Cannot register net device, aborting.",
3719 mac_addr
= of_get_mac_address(np
);
3721 memcpy(dev
->dev_addr
, mac_addr
, 6);
3723 ugeth
->ug_info
= ug_info
;
3724 ugeth
->dev
= device
;
3731 static int ucc_geth_remove(struct of_device
* ofdev
)
3733 struct device
*device
= &ofdev
->dev
;
3734 struct net_device
*dev
= dev_get_drvdata(device
);
3735 struct ucc_geth_private
*ugeth
= netdev_priv(dev
);
3737 unregister_netdev(dev
);
3739 ucc_geth_memclean(ugeth
);
3740 dev_set_drvdata(device
, NULL
);
3745 static struct of_device_id ucc_geth_match
[] = {
3748 .compatible
= "ucc_geth",
3753 MODULE_DEVICE_TABLE(of
, ucc_geth_match
);
3755 static struct of_platform_driver ucc_geth_driver
= {
3757 .match_table
= ucc_geth_match
,
3758 .probe
= ucc_geth_probe
,
3759 .remove
= ucc_geth_remove
,
3762 static int __init
ucc_geth_init(void)
3766 if (netif_msg_drv(&debug
))
3767 printk(KERN_INFO
"ucc_geth: " DRV_DESC
"\n");
3768 for (i
= 0; i
< 8; i
++)
3769 memcpy(&(ugeth_info
[i
]), &ugeth_primary_info
,
3770 sizeof(ugeth_primary_info
));
3772 ret
= of_register_platform_driver(&ucc_geth_driver
);
3777 static void __exit
ucc_geth_exit(void)
3779 of_unregister_platform_driver(&ucc_geth_driver
);
3782 module_init(ucc_geth_init
);
3783 module_exit(ucc_geth_exit
);
3785 MODULE_AUTHOR("Freescale Semiconductor, Inc");
3786 MODULE_DESCRIPTION(DRV_DESC
);
3787 MODULE_VERSION(DRV_VERSION
);
3788 MODULE_LICENSE("GPL");